TWI680677B - Displayer and clock generator thereof - Google Patents

Abstract

This case discloses a clock generator for generating a plurality of clock signals to control the gate driver. The gate driver outputs gate signals through a plurality of gate lines to turn on a plurality of sub-pixels of a plurality of pixels of the display device. When the clock generator receives the first mode signal, the clock generator sequentially outputs a plurality of high-level clock signals to the gate driver. When the clock generator receives the second mode signal, the clock generator outputs the enabled clock signal to the gate driver during the first period, and the clock generator outputs the enabled clock signal to the gate during the second period. Pole driver.

Description

   Display device and its clock generator   

This case relates to an image processing device, and more particularly to a display device and its clock generator.

With the rapid development of display technology, display devices are widely used in human life and play an increasingly important role. The panel of the existing display device often uses Panel Self Refresh (PSR) technology. Once the PSR technology of the display device is activated, its clock generator reduces the refresh rate to output the stored image. However, because the panel uses the original The resolution output causes the overall power consumption of the display device to increase.

It can be seen that the above existing methods obviously still have inconveniences and defects, and need to be improved. In order to solve the above-mentioned problems, the related fields have made every effort to find a solution, but a suitable solution has not been developed for a long time.

One aspect disclosed in this case relates to a clock generator for generating a plurality of clock signals to control the gate driver. The gate driver outputs gate signals through a plurality of gate lines to turn on a plurality of sub-pixels of a plurality of pixels of the display device. When the clock generator receives the first mode signal, the clock generator sequentially outputs a plurality of high-level clock signals to the gate driver. When the clock generator receives the second mode signal, the clock generator outputs the enabled clock signal to the gate driver during the first period, and the clock generator outputs the enabled clock signal to the gate during the second period. Pole driver.

Another aspect disclosed in this application relates to a display device. The display device includes a panel, a panel, a gate driver, and a source driver. The panel includes a plurality of pixels, wherein each of the pixels includes a plurality of sub-pixels. The clock generator is used for generating a first clock signal, a second clock signal, a third clock signal and a fourth clock signal. When the clock generator receives the first mode signal, the clock generator operates in the first mode, and the clock generator sequentially outputs the first to fourth clock signals in the first mode. When the clock generator receives the second mode signal, the clock generator operates in the second mode. In the second mode, the clock generator outputs the enabled first and second clock signals during the first period, and The enabled third and fourth clock signals are output during the second period. The gate driver is respectively coupled to the sub-pixels arranged in the first row and the second row of the gates through the first gate line, the second gate line, the third gate line, and the fourth gate line. The sub-pixels, the sub-pixels arranged in the third column, and the sub-pixels arranged in the fourth column. The source driver is respectively coupled to the sub-pixels through a plurality of data lines. The source driver outputs data signals to the pixels arranged in the first and second columns during the first period, and outputs data signals to the pixels arranged in the third and fourth columns during the second period.

Therefore, according to the technical content of the present case, an embodiment of the present case provides a display device and its clock generator, so as to reduce the switching frequency of the gate driver and even the source driver to achieve the purpose of energy saving.

100‧‧‧ display device

110‧‧‧clock generator

120‧‧‧Gate driver

130‧‧‧Source Driver

140‧‧‧ panel

D1 ~ D12‧‧‧Data line

DS1 ~ DS12‧‧‧Data signal

G1 ~ G6‧‧‧Gate line

GS1 ~ GS6‧‧‧Gate signal

HC1 ~ HC6‧‧‧ clock signal

M1, M2‧‧‧ mode signals

SP11 ~ SP46 ‧‧‧ times pixels

SR1 ~ SR6‧‧‧Shift register

T1 ~ T4‧‧‧‧

VST‧‧‧Start signal

FIG. 1 is a schematic diagram of a display device according to an embodiment disclosed in this application.

FIG. 2 is a waveform diagram drawn according to the embodiment disclosed in the present application.

FIG. 3 is a schematic diagram of a clock generator and a gate driver of the display device shown in FIG. 1 according to the embodiment disclosed in this case.

FIG. 4 is a schematic diagram of a panel of the display device shown in FIG. 1 according to the embodiment disclosed in this case.

FIG. 5 is a schematic diagram of a panel of the display device shown in FIG. 1 according to the embodiment disclosed in the present invention.

The following is a detailed description with examples and drawings to better understand the aspect of the case, but the examples provided are not intended to limit the scope covered by this disclosure, and the description of structural operations is not intended to limit The order of execution, any structure with recombination of components, and a device with equal efficacy are all covered by the present disclosure. In addition, according to industry standards and common practices, the drawings are only for the purpose of assisting the description, and are not drawn according to the original dimensions. In fact, the dimensions of various features can be arbitrarily increased or decreased for ease of explanation. In the following description, the same elements will be described with the same symbols to facilitate understanding.

The terms used throughout the specification and the scope of patent applications, unless otherwise specified, usually have the ordinary meaning of each term used in this field, the content disclosed here, and the special content. Certain terms used to describe the present disclosure are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art on the description of the present disclosure.

In addition, the terms "including", "including", "having", "containing", etc. used in this case are all open-ended terms, meaning "including but not limited to."

FIG. 1 is a schematic diagram of a display device 100 according to an embodiment disclosed in this application. As shown, the display device 100 includes a clock generator 110, a gate driver 120, a source driver 130, and a panel 140. The above clock generator 110 is used to generate a plurality of clock signals HC1 to HC6 to control the gate driver 120, and the gate driver 120 can output the gate signals through the plurality of gate lines G1 to G6 to turn on the display device 100. Among the plurality of pixels, a plurality of sub-pixels SP11 ~ SP16, SP21 ~ SP26, SP31 ~ SP36, SP41 ~ SP46, etc. In addition, the clock generator 110 is further configured to receive mode signals (such as the mode signals M1 and M2).

In order to make the operation of the clock generator 110 in this case easy to understand, please refer to FIG. 2 together, which is a waveform diagram drawn according to the embodiment disclosed in this case. When the clock generator 110 receives the first mode signal (for example, the mode signals M1 and M2 are both low level), the clock generator 110 sequentially outputs a plurality of high-level clock signals HC1 ~ HC6 to the gate during the period T1. Drive 120. Furthermore, when the clock generator 110 receives the second mode signal (for example, the mode signals M1 and M2 are both at a high level), the clock generator 110 outputs the enabled clock signals HC1 and HC2 to the gate driver during the period T2. 120, and the clock generator 110 outputs the enabled clock signals HC3 and HC4 to the gate driver 120 during the period T3.

As described above, the gate driver 120 simultaneously outputs the gate signals GS1 and GS2 as shown in FIG. 1 according to the enabled clock signals HC1 and HC2 received during the period T2. In other words, the gate driver 120 performs The clock signals HC1 and HC2 output the gate signals GS1 and GS2 through the first and second gate lines G1 and G2 to the pixels SP11 to SP16 and SP21 to SP26 arranged in the first and second columns. Since the pixels SP11 ~ SP16 and SP21 ~ SP26 of the first and second columns are turned on at the same time, the source driver 130 can charge the two columns of pixels at the same time, thereby reducing the gate driver 120. Even the switching frequency of the source driver 130 to reduce power consumption. Similarly, during the period T3, the gate driver 120 outputs the gate signals GS3 and GS4 as shown in FIG. 1 through the third and fourth gate lines G3 and G4 according to the clock signals HC3 and HC4, and is arranged in the third and fourth gate lines. The pixels in the fourth column are SP31 ~ SP36, SP41 ~ SP46, so as to reduce the switching frequency of the gate driver 120 and even the source driver 130.

In an embodiment, please refer to FIG. 1. The panel 140 includes a plurality of pixels, each of which includes a plurality of sub-pixels SP11 ~ SP16, SP21 ~ SP26, SP31 ~ SP36, SP41 ~ SP46 .. .Wait. In some embodiments, the pixels of the panel 140 may be composed of SP11 to SP16 and SP21 to SP26, and the other pixels of the panel 140 may be composed of SP31 to SP36 and SP41 to SP46. In addition, the gate driver 120 is coupled to the sub-pixels SP11 arranged in the first column through the first gate line G1, the second gate line G2, the third gate line G3, and the fourth gate line G4, respectively. ~ SP16, the pixels SP21 ~ SP26 arranged in the second column, the pixels SP31 ~ SP36 arranged in the third column, and the pixels SP41 ~ SP46 arranged in the fourth column. Furthermore, the source driver 130 is coupled to the pixels SP11 to SP16, SP21 to SP26, SP31 to SP36, SP41 to SP46, etc. through a plurality of data lines D1 to D12, respectively. However, this case is not limited to the structure shown in the above embodiments, and it is only used to exemplarily illustrate one of the implementation manners of this case.

In another embodiment, please refer to FIG. 1 and FIG. 2 together. The clock generator 110 is configured to generate a first clock signal HC1, a second clock signal HC2, a third clock signal HC3, and a fourth clock. The clock signal HC4, the fifth clock signal HC5, and the sixth clock signal HC6. When the clock generator 110 receives the first mode signal (for example, the mode signals M1 and M2 are both at a low level), the clock generator 110 sequentially outputs the first to sixth clock signals HC1 to HC6 during the period T1. Subsequently, during the period T1, the gate driver 120 sequentially outputs the gate signals GS1 to GS6 to the first to sixth gate lines G1 to G6 according to the first to sixth clock signals HC1 to HC6 to sequentially open the coupling. The pixels of the first to sixth gate lines G1 to G6.

In yet another embodiment, please refer to FIG. 1 and FIG. 2 together. When the clock generator 110 receives the second mode signal (for example, the mode signals M1 and M2 are both high level), the clock generator 110 is at During the period T2, the first and second clock signals HC1 and HC2 with high levels are output to the gate driver 120. Subsequently, during the period T2, the gate driver 120 outputs the gate signals GS1 and GS2 through the first gate line G1 and the second gate line G2 according to the first and second clock signals HC1 and HC2 to the first and second clock signals HC1 and HC2. The sub-pixels SP11-SP16, SP21-SP26 of one column and the second column, and the above-mentioned sub-pixels SP11-SP16, SP21-SP26 are turned on. Furthermore, the source driver 130 outputs data signals to the pixels SP11 to SP16 and SP21 to SP26 arranged in the first and second columns during the period T2.

In another embodiment, please refer to FIG. 1 and FIG. 2 together. When the clock generator 110 receives the second mode signal (for example, the mode signals M1 and M2 are both high level), the clock generator 110 is at During the period T3, the third and fourth clock signals HC3 and HC4 at a high level are output to the gate driver 120. Subsequently, during the period T3, the gate driver 120 outputs the gate signals GS3 and GS4 through the third gate line G3 and the fourth gate line G4 according to the third and fourth clock signals HC3 and HC4, and is arranged in the first row of the panel 140. The sub-pixels SP31-SP36, SP41-SP46 of the three columns and the fourth column, and the above-mentioned sub-pixels SP31-SP36, SP41-SP46 are turned on. Furthermore, the source driver 130 outputs data signals to the pixels SP31 to SP36 and SP41 to SP46 arranged in the third and fourth columns during the period T3. In addition, the operation mode of the clock generator 110 during the period T4 is similar to that of the clock generator 110 during the period T2 or T3. The pixels arranged in the fifth and sixth columns of the panel 140 will be The gate driver 120 is turned on, and the source driver 130 outputs data signals to the pixels. However, this case is not limited to the operation modes described in the above embodiments, and is only used to exemplarily illustrate one of the implementation modes of this case.

Referring to FIG. 2, in one embodiment, the period T2 and the period T3 occur sequentially. Please also refer to the periods T2 and T3. The pulse widths of the first and second clock signals HC1 and HC2 at the high level are the same as the pulse widths of the third and fourth clock signals HC3 and HC4 at the high level. In yet another embodiment, periods T2, T3, and T4 occur sequentially. During periods T2 ~ T4, the pulse widths of the first and second clock signals HC1, HC2 at the high level, the pulse widths of the third and fourth clock signals HC3, HC4 at the high level, and the fifth and sixth of the high level The pulse widths of the clock signals HC5 and HC6 are the same. However, this case is not limited to the waveform shown in the embodiment in FIG. 2, and is only used to exemplarily illustrate one of the implementation manners of this case.

In another embodiment, in a state where the clock generator 110 receives the second mode signal (for example, the mode signals M1 and M2 are both at a high level), the clock generator 110 outputs a start signal VST to the gate driver 120. Then, the gate driver 120 is configured to output the gate signals GS1 to GS2 according to the start signal VST and the high-level clock signals HC1 and HC2.

FIG. 3 is a schematic diagram of the clock generator 110 and the gate driver 120 of the display device 100 shown in FIG. 1 according to the embodiment disclosed in this case. Please refer to Figure 2 and Figure 3 together. LC1 / LC2 series control shift registers SR1 ~ SR6 keep low voltage output, so that the gate signals GS1 ~ GS6 output by each gate line G1 ~ G6 are low. Voltage.

Referring to FIG. 3, the gate driver 120 includes a first shift register SR1, a second shift register SR2, a third shift register SR3, and a fourth shift register SR4. When the clock generator 110 receives the second mode signal, the clock generator 110 outputs a start signal VST, and the first shift register SR1 is used to receive the first clock signal HC1, and according to the start signal VST and the first The clock signal HC1 determines whether to output the gate signal GS1 through the first gate line G1. The second shift register SR2 is used for receiving the second clock signal HC2, and determines whether to output the gate signal GS2 through the second gate line G2 according to the start signal VST and the second clock signal HC2.

In another embodiment, the third shift register SR3 is configured to receive the third clock signal HC3, and according to the first clock signal HC1 and the third clock signal transmitted from the first shift register SR1. HC3 determines whether to output the gate signal GS3 through the third gate line G3. The fourth shift register SR4 is used to receive the fourth clock signal HC4, and determines whether to pass the fourth clock signal HC4 and the fourth clock signal HC4 according to the second clock register SR2. The gate line G4 outputs a gate signal GS4. In still another embodiment, the driving methods of the fifth shift register SR5, the sixth shift register SR6, and the subsequent shift registers are similar to the third shift register SR3 and the first shift register. The driving method of the four-shift register SR4 is not described in detail here in order to make the description of this case concise.

FIG. 4 is a schematic diagram of a panel of the display device 100 shown in FIG. 1 according to the embodiment disclosed in this case. FIG. 5 is a schematic diagram of a panel of the display device 100 shown in FIG. 1 according to the embodiment disclosed in this case. It should be noted that the structure of panel 140A shown in FIG. 4 is basically the same as that of panel 140 shown in FIG. 1, and the pixel structure of panel 140B shown in FIG. 5 uses interlaced coupling (Zig-Zag ) The structure is different from the panel 140 shown in FIG. 1, and details are as follows.

Please refer to Fig. 4. When the sub pixels SP11 ~ SP16 and SP21 ~ SP26 arranged in the first and second columns are turned on by the gate signals GS1 and GS2 at the same time, the first data line D1 and the fourth data line D4 are respectively turned on. Provide data signals DS1, DS4 to sub-pixels SP11, SP21 and SP14, SP24 of the same voltage; second data line D2 and fifth data line D5 provide data signals DS2, DS5 to sub-pixels SP12, SP22 and SP15, SP25; the third data line D3 and the sixth data line D6 respectively provide data signals DS3, DS6 to sub-pixels SP13, SP23, SP16, SP26 of the same voltage. In another embodiment, the driving methods of the sub-pixels SP31-SP36, SP41-SP46, and even the other sub-pixels are similar to the driving methods of the sub-pixels SP11-SP16 and SP21-SP26. In order to make the description of this case concise, I won't go into details here.

Please refer to FIG. 5. The source driver 130 shown in FIG. 1 passes through each of the data lines D1 to D12 and the pixels 140B of the panel 140B, SP11 to SP16, SP21 to SP26, SP31 to SP36, SP41 to SP46. ... interleaved coupling (Zig-Zag) so that the color of light emitted by the second pixel coupled to the same data line of the data lines D1 to D12 is the same. For example, the data line D1 is alternately coupled to the sub-pixel SP11 (to the left of the data line D1), the sub-pixel SP22 (to the right of the data line D1), the sub-pixel SP31 (to the left of the data line D1), and the sub-pixel SP42 (located to the right of the data line D1) ... etc., and it can be seen from the figure that the sub-pixels SP11, SP22, SP31, SP42 are all the same color sub-pixels (it should be noted that the same dots are used to mark the Secondary pixels are secondary pixels of the same color). In an embodiment, the interleaving method between the data lines D2 to D12 and the sub-pixels is similar to the interleaving method between the data line D1 and the sub-pixels.

In yet another embodiment, please refer to FIG. 5. When the sub-pixels SP11 ~ SP16 and SP21 ~ SP26 arranged in the first column and the second column are turned on by the gate signals GS1 and GS2 at the same time, the first data line D1 And the fourth data line D4 respectively provide data signals DS1, DS4 to sub-pixels SP11, SP22 and SP14, SP25 of the same voltage; the second data line D2 and fifth data line D5 provide data signals DS2, DS5 to Secondary pixels SP12, SP23 and SP15, SP26; the third data line D3 and sixth data line D6 respectively provide data signals DS3, DS6 to the secondary pixels SP13, SP24 and SP16, SP26 on the right side of the secondary voltage. In addition, the driving methods of the sub-pixels SP31-SP36, SP41-SP46, and even the other sub-pixels are similar to the driving methods of the sub-pixels SP11-SP16 and SP21-SP26.

It can be known from the foregoing embodiments of the present application that the application of the present application has the following advantages. The embodiment of the present invention provides a display device and its clock generator, thereby reducing the switching frequency of the gate driver and even the source driver to achieve the purpose of energy saving.

Those skilled in the art can readily understand that the disclosed embodiments achieve the advantages of one or more of the foregoing examples. After reading the foregoing description, one of ordinary skill in the art will be able to make various types of changes, substitutions, equivalents, and various other embodiments as disclosed herein. Therefore, the scope of protection in this case shall be determined mainly by the scope defined by the scope of patent application and its equivalent scope.

Claims (9)

A clock generator is used to generate a plurality of clock signals to control a gate driver, wherein the gate driver turns on a plurality of pixels in a display device through a plurality of gate lines to output a gate signal. A plurality of sub-pixels; wherein when the clock generator receives a first mode signal, the clock generator sequentially outputs the high-level clock signals to the gate driver, so that the gate driver The gate signals are sequentially output through the plurality of gate lines, and when the clock generator receives a second mode signal, the clock generator outputs the enabled clocks in a first period. Signal to the gate driver, so that the gate driver simultaneously outputs the gate signal through at least two of the plurality of gate lines, and the clock generator outputs the enabled clocks in a second period Signal to the gate driver, so that the gate driver simultaneously outputs the gate signal through at least two of the plurality of gate lines. The clock generator according to claim 1, wherein the clock generator is used to generate a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal, wherein when When the clock generator receives the second mode signal, the clock generator outputs the first and second clock signals of high level to the gate driver during the first period, and the gate driver according to the The first and the second clock signals output the gate signals to a plurality of pixels arranged in the first and second columns of the display device through a first gate line and a second gate line simultaneously. . The clock generator according to claim 2, wherein the clock generator is used to generate the third clock signal and the fourth clock signal, and when the clock generator receives the second mode signal, The clock generator outputs the third and fourth clock signals of high level to the gate driver during the second period, and the gate driver transmits a third signal according to the third and fourth clock signals through a third The gate line and a fourth gate line simultaneously output the gate signals to the sub-pixels arranged in the third and fourth columns of the display device. The clock generator as described in claim 3, wherein the first period and the second period occur sequentially, and the pulse widths of the first and second clock signals of the high level are the same as the third period of the high level And the pulse width of the fourth clock signal. The clock generator according to any one of claims 1 to 4, wherein in a state where the clock generator receives the second mode signal, the clock generator outputs a start signal to the gate driver, The gate driver is configured to output the gate signal according to the start signal and the high-level clock signals. A display device includes: a panel including a plurality of pixels, wherein each of the pixels includes a plurality of sub-pixels; a clock generator for generating a first clock signal, a second clock A clock signal, a third clock signal, and a fourth clock signal, wherein when the clock generator receives a first mode signal, the clock generator operates in a first mode, and the clock generator The first to the fourth clock signals are sequentially output in the first mode; wherein when the clock generator receives a second mode signal, the clock generator operates in a second mode. In the second mode, the clock generator simultaneously outputs the first and second clock signals that are enabled in a first period, and simultaneously outputs the third and fourth clock signals that are enabled in a second period. Pulse signal; a gate driver, coupled to the first and second gate lines through a first gate line, a second gate line, a third gate line, and a fourth gate line, respectively Pixels, the pixels arranged in the second column, the pixels arranged in the third column, and the arrangement The pixels in the fourth column; and a source driver, respectively coupled to the pixels through a plurality of data lines, wherein the source driver outputs a data signal to the first pixel in the first period; And the pixels in the second column, and outputting the data signal to the pixels in the third and fourth columns during the second period, in the first mode, when the gate driver When the first to the fourth clock signals are sequentially received, the gate driver sequentially outputs a gate signal to the first to the fourth gate lines to sequentially open and couple the first to the fourth clock lines. The sub-pixels of the fourth gate line, wherein in the second mode, the gate driver passes the first and the second clock signals according to the first and the second clock signals during the first period The polar line outputs the gate signal to the pixels arranged in the first and second columns at the same time, and transmits the third and fourth clock signals according to the third and fourth clock signals during the second period. The gate line simultaneously outputs the gate signal to the sub-pixels arranged in the third and fourth columns. The display device according to claim 6, wherein when the clock generator receives the second mode signal, the clock generator outputs a start signal during the first period, wherein the gate driver includes: a first A shift register for receiving the first clock signal and determining whether to output the gate signal through the first gate line according to the start signal and the first clock signal; and a second shift A bit register is used for receiving the second clock signal and determining whether to output the gate signal through the second gate line according to the start signal and the second clock signal. The display device according to claim 7, wherein the gate driver further comprises: a third shift register for receiving the third clock signal, and according to the first clock signal and the third clock Pulse signal to determine whether to output the gate signal through the third gate line; and a fourth shift register for receiving the fourth clock signal, and based on the second clock signal and the fourth The clock signal determines whether to output the gate signal through the fourth gate line. The display device according to claim 8, wherein the source driver is coupled to the sub-pixel interleaving (Zig-Zag) of the panel through each of the data lines, and is the same as the data lines. The color of the light emitted by the pixels connected to one data line is the same.