TW202009915A - Display device and gate driving circuit - Google Patents

Display device and gate driving circuit Download PDF

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TW202009915A
TW202009915A TW108101701A TW108101701A TW202009915A TW 202009915 A TW202009915 A TW 202009915A TW 108101701 A TW108101701 A TW 108101701A TW 108101701 A TW108101701 A TW 108101701A TW 202009915 A TW202009915 A TW 202009915A
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transistor
terminal
scan
signal
coupled
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TW108101701A
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Chinese (zh)
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TWI680450B (en
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楊創丞
張哲嘉
李明賢
鍾俊甫
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友達光電股份有限公司
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Abstract

A display device includes multiple vertical driving lines, and further includes multiple switch circuits and multiple shift registers. The multiple switch circuits are correspondingly coupled with the multiple vertical driving lines, and are configured to receive at least one control signal. The multiple shift registers include a last-stage shift register, wherein the last-stage shift register is configured to output the at least one control signal. During a first time period, the multiple switch circuits are, according to the at least one control signal, configured to render a first part of the multiple vertical driving lines to have a first voltage level, and render a second part of the multiple vertical driving lines to have a second voltage level. During a second time period, the multiple switch circuits are, according to the at least one control signal, configured to render the second part of the multiple vertical driving lines to have the first voltage level, and render the first part of the multiple vertical driving lines to have the second voltage level.

Description

顯示裝置與閘極驅動器 Display device and gate driver

本揭示文件有關一種顯示裝置與閘極驅動器,尤指一種可防止畫素漏電的顯示裝置。 This disclosure relates to a display device and a gate driver, in particular to a display device capable of preventing pixel leakage.

當目前主流的行動裝置持續顯示靜止畫面(例如,持續顯示其中一個桌面分頁)時,行動裝置的顯示裝置會暫時停止更新顯示畫面以降低功率消耗。然而,當顯示裝置停止更新顯示畫面時,由於資料線具有低電壓,畫素電路與資料線之間會產生漏電流。此時,畫素電路所顯示的灰階亮度會因為漏電流而逐漸改變,使得顯示畫面產生人眼可察覺的閃爍。 When the current mainstream mobile devices continue to display still images (for example, one of the desktop pages is continuously displayed), the display device of the mobile device temporarily stops updating the display screen to reduce power consumption. However, when the display device stops updating the display image, since the data line has a low voltage, a leakage current may be generated between the pixel circuit and the data line. At this time, the gray scale brightness displayed by the pixel circuit will gradually change due to the leakage current, so that the display screen will generate a flicker that can be noticed by the human eye.

本揭示文件提供一種顯示裝置,顯示裝置包含多個縱向驅動線,且另包含多個切換電路與多個移位暫存器。多個切換電路對應耦接於多個縱向驅動線,用於接收至少一控制訊號。多個移位暫存器包含末級移位暫存器,其中末級移位暫存器用於輸出至少一控制訊號。多個切換電路用 於依據至少一控制訊號,於第一時段中將多個縱向驅動線中的第一部分縱向驅動線設置為具有第一電壓準位,將多個縱向驅動線中的第二部分縱向驅動線設置為具有第二電壓準位,並且於第二時段中將第二部分縱向驅動線設置為具有第一電壓準位,將第一部分縱向驅動線設置為具有第二電壓準位。 The present disclosure provides a display device. The display device includes a plurality of vertical drive lines, and further includes a plurality of switching circuits and a plurality of shift registers. The plurality of switching circuits are correspondingly coupled to the plurality of vertical drive lines, and are used to receive at least one control signal. The plurality of shift registers include a last-stage shift register, wherein the last-stage shift register is used to output at least one control signal. The plurality of switching circuits are used for setting the first part of the plurality of vertical drive lines to have the first voltage level in the first period according to at least one control signal, and setting the second part of the plurality of vertical drive lines The vertical drive line is set to have a second voltage level, and in the second period, the second partial vertical drive line is set to have a first voltage level, and the first partial vertical drive line is set to have a second voltage level.

本揭示文件另提供一種閘極驅動器,閘極驅動器適用於顯示裝置,其中顯示裝置包含多個縱向驅動線,閘極驅動器包含多個移位暫存器。多個移位暫存器包含末級移位暫存器,其中末級移位暫存器用於輸出第一控制訊號群組至多個切換電路,且多個切換電路對應耦接於多個縱向驅動線。多個切換電路用於依據第一控制訊號群組,於第一時段中將多個縱向驅動線中的第一部分縱向驅動線設置為具有第一電壓準位,將多個縱向驅動線中的第二部分縱向驅動線設置為具有第二電壓準位,並且於第二時段中將第二部分縱向驅動線設置為具有第一電壓準位,將第一部分縱向驅動線設置為具有第二電壓準位。 The disclosure also provides a gate driver suitable for a display device, wherein the display device includes a plurality of vertical drive lines, and the gate driver includes a plurality of shift registers. The plurality of shift registers include a last-stage shift register, wherein the last-stage shift register is used to output the first control signal group to a plurality of switching circuits, and the plurality of switching circuits are correspondingly coupled to the plurality of vertical drives line. The plurality of switching circuits are used to set the first part of the plurality of vertical drive lines to have the first voltage level in the first period according to the first control signal group, and set the first of the plurality of vertical drive lines to the first voltage level. The two-part longitudinal drive line is set to have the second voltage level, and in the second period, the second-part vertical drive line is set to have the first voltage level, and the first part of the vertical drive line is set to have the second voltage level .

上述的顯示裝置與閘極驅動器能防止畫素電路與垂直驅動線之間產生漏電流。 The above display device and gate driver can prevent leakage current between the pixel circuit and the vertical drive line.

100‧‧‧顯示裝置 100‧‧‧Display device

110‧‧‧控制電路 110‧‧‧Control circuit

120‧‧‧源極驅動器 120‧‧‧ source driver

130‧‧‧閘極驅動器 130‧‧‧Gate driver

140‧‧‧防漏電電路 140‧‧‧anti-leakage circuit

150‧‧‧畫素電路 150‧‧‧ pixel circuit

VL[1]~VL[x]‧‧‧垂直信號線 VL[1]~VL[x]‧‧‧Vertical signal line

HL[1]~HL[y]‧‧‧水平信號線 HL[1]~HL[y]‧‧‧horizontal signal line

210[1]~210[m]‧‧‧移位暫存器 210[1]~210[m]‧‧‧Shift register

210[1]‧‧‧移位暫存器 210[1]‧‧‧Shift register

210[m]‧‧‧移位暫存器 210[m]‧‧‧Shift register

210[m-1]‧‧‧移位暫存器 210[m-1]‧‧‧Shift register

710[1]~710[m]‧‧‧移位暫存器 710[1]~710[m]‧‧‧shift register

ODD‧‧‧第一防護信號 ODD‧‧‧The first protection signal

EVEN‧‧‧第二防護信號 EVEN‧‧‧Second protection signal

CTL1‧‧‧第一控制信號群組 CTL1‧‧‧First control signal group

CTL2‧‧‧第二控制信號群組 CTL2‧‧‧Second control signal group

CK‧‧‧時脈信號 CK‧‧‧clock signal

XCK‧‧‧反相時脈信號 XCK‧‧‧Inverted clock signal

ST‧‧‧起始信號 ST‧‧‧Start signal

SP‧‧‧起始脈衝 SP‧‧‧Start pulse

RS‧‧‧重置信號 RS‧‧‧Reset signal

RP‧‧‧重置脈衝 RP‧‧‧Reset pulse

PW‧‧‧電力輸入 PW‧‧‧Power input

Mu‧‧‧多工信號群組 Mu‧‧‧Multiplex signal group

Da‧‧‧資料信號 Da‧‧‧Data signal

710[1]‧‧‧移位暫存器 710[1]‧‧‧Shift register

710[m]‧‧‧移位暫存器 710[m]‧‧‧shift register

710[m-1]‧‧‧移位暫存器 710[m-1]‧‧‧shift register

1210[1]~1210[m]‧‧‧移位暫存器 1210[1]~1210[m]‧‧‧shift register

1210[1]‧‧‧移位暫存器 1210[1]‧‧‧Shift register

1210[m]‧‧‧移位暫存器 1210[m]‧‧‧Shift register

1210[m-1]‧‧‧移位暫存器 1210[m-1]‧‧‧shift register

1710[1]~1710[m]‧‧‧移位暫存器 1710[1]~1710[m]‧‧‧shift register

1710[1]‧‧‧移位暫存器 1710[1]‧‧‧Shift register

1710[m]‧‧‧移位暫存器 1710[m]‧‧‧Shift register

1710[m-1]‧‧‧移位暫存器 1710[m-1]‧‧‧Shift register

2200‧‧‧移位暫存器 2200‧‧‧Shift register

310[1]~310[n]‧‧‧切換電路 310[1]~310[n]‧‧‧switch circuit

810[1]~810[n]‧‧‧切換電路 810[1]~810[n]‧‧‧switch circuit

1310[1]~1310[n]‧‧‧切換電路 1310[1]~1310[n]‧‧‧switch circuit

1810[1]~1810[n]‧‧‧切換電路 1810[1]~1810[n]‧‧‧switch circuit

510‧‧‧驅動電路 510‧‧‧Drive circuit

1010‧‧‧驅動電路 1010‧‧‧Drive circuit

1510‧‧‧驅動電路 1510‧‧‧Drive circuit

2010‧‧‧驅動電路 2010‧‧‧Drive circuit

2210‧‧‧驅動電路 2210‧‧‧Drive circuit

R1‧‧‧電阻 R1‧‧‧Resistance

Tr1‧‧‧第一驅動電晶體 Tr1‧‧‧ First drive transistor

Tr2‧‧‧第二驅動電晶體 Tr2‧‧‧second drive transistor

Gn[1]~Gn[y]‧‧‧掃描信號 Gn[1]~Gn[y]‧‧‧scan signal

CP‧‧‧掃描脈衝 CP‧‧‧scan pulse

U1‧‧‧第一上掃信號 U1‧‧‧First sweep signal

U2‧‧‧第二上掃信號 U2‧‧‧second sweep signal

U3‧‧‧第三上掃信號 U3‧‧‧ Third sweep signal

D1‧‧‧第一下掃信號 D1‧‧‧First sweep signal

D2‧‧‧第二下掃信號 D2‧‧‧second sweep signal

D3‧‧‧第三下掃信號 D3‧‧‧ Third sweep signal

Vref1‧‧‧第一參考電壓 Vref1‧‧‧First reference voltage

Vref2‧‧‧第二參考電壓 Vref2‧‧‧second reference voltage

Vref3‧‧‧第三參考電壓 Vref3‧‧‧third reference voltage

Vref4‧‧‧第四參考電壓 Vref4‧‧‧ Fourth reference voltage

Vref5‧‧‧第五參考電壓 Vref5‧‧‧fifth reference voltage

Vref6‧‧‧第六參考電壓 Vref6 ‧‧‧ sixth reference voltage

In1‧‧‧第一電源端 In1‧‧‧First power terminal

In2‧‧‧第二電源端 In2‧‧‧second power terminal

O1‧‧‧第一輸出端 O1‧‧‧ First output

O2‧‧‧第二輸出端 O2‧‧‧Second output

O3‧‧‧第三輸出端 O3‧‧‧The third output

GND‧‧‧接地端 GND‧‧‧Ground terminal

N1‧‧‧第一節點 N1‧‧‧First node

N2‧‧‧第二節點 N2‧‧‧The second node

P1‧‧‧第一內部節點 P1‧‧‧First internal node

P2‧‧‧第二內部節點 P2‧‧‧Second internal node

Tr3‧‧‧第三驅動電晶體 Tr3‧‧‧third drive transistor

Tr4‧‧‧第四驅動電晶體 Tr4‧‧‧ fourth driving transistor

Tr5‧‧‧第五驅動電晶體 Tr5‧‧‧ fifth drive transistor

Tr6‧‧‧第六驅動電晶體 Tr6‧‧‧ sixth drive transistor

Tr7‧‧‧第七驅動電晶體 Tr7‧‧‧ seventh driving transistor

Tr8‧‧‧第八驅動電晶體 Tr8‧‧‧Eighth drive transistor

Tr9‧‧‧第九驅動電晶體 Tr9‧‧‧Ninth drive transistor

Tr10‧‧‧第十驅動電晶體 Tr10‧‧‧Tenth drive transistor

Tr11‧‧‧第十一驅動電晶體 Tr11‧‧‧Eleventh drive transistor

P3‧‧‧第三內部節點 P3‧‧‧The third internal node

P4‧‧‧第四內部節點 P4‧‧‧The fourth internal node

P5‧‧‧第五內部節點 P5‧‧‧Fifth internal node

P6‧‧‧第六內部節點 P6‧‧‧Sixth internal node

M1‧‧‧第一電晶體 M1‧‧‧ First transistor

M2‧‧‧第二電晶體 M2‧‧‧second transistor

M3‧‧‧第三電晶體 M3‧‧‧The third transistor

M4‧‧‧第四電晶體 M4‧‧‧ fourth transistor

M5‧‧‧第五電晶體 M5‧‧‧ fifth transistor

M6‧‧‧第六電晶體 M6‧‧‧The sixth transistor

M7‧‧‧第七電晶體 M7‧‧‧The seventh transistor

M8‧‧‧第八電晶體 M8‧‧‧Eighth transistor

為讓揭示文件之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附圖式之說明如下:第1圖為根據本揭示文件一實施例的顯示裝置簡化後 的功能方塊圖。 In order to make the above and other objects, features, advantages and embodiments of the disclosed document more obvious and understandable, the drawings are described as follows: FIG. 1 is a simplified functional block diagram of a display device according to an embodiment of the disclosed document .

第2圖為依據本揭示文件一實施例的閘極驅動器簡化後的功能方塊圖。 FIG. 2 is a simplified functional block diagram of a gate driver according to an embodiment of the present disclosure.

第3圖為依據本揭示文件一實施例的多個切換電路的電路示意圖。 FIG. 3 is a schematic circuit diagram of multiple switching circuits according to an embodiment of the present disclosure.

第4圖為依據本揭示文件一實施例的顯示裝置的運作方式示意圖。 FIG. 4 is a schematic diagram of an operation mode of a display device according to an embodiment of the present disclosure.

第5圖為依據本揭示文件一實施例的移位暫存器簡化後的功能方塊圖。 FIG. 5 is a simplified functional block diagram of a shift register according to an embodiment of the present disclosure.

第6圖為依據本揭示文件一實施例的第一級移位暫存器簡化後的功能方塊圖。 FIG. 6 is a simplified functional block diagram of the first-stage shift register according to an embodiment of the present disclosure.

第7圖為依據本揭示文件另一實施例的閘極驅動器簡化後的功能方塊圖。 FIG. 7 is a simplified functional block diagram of a gate driver according to another embodiment of the present disclosure.

第8圖為依據本揭示文件另一實施例的防漏電電路的電路示意圖。 FIG. 8 is a schematic circuit diagram of an anti-leakage circuit according to another embodiment of the present disclosure.

第9圖為依據本揭示文件另一實施例的顯示裝置的運作方式示意圖。 FIG. 9 is a schematic diagram of an operation mode of a display device according to another embodiment of the present disclosure.

第10圖為依據本揭示文件一實施例的末級移位暫存器簡化後的功能方塊圖。 FIG. 10 is a simplified functional block diagram of the last-stage shift register according to an embodiment of the present disclosure.

第11圖為依據本揭示文件一實施例的第一級移位暫存器簡化後的功能方塊圖。 FIG. 11 is a simplified functional block diagram of the first-stage shift register according to an embodiment of the present disclosure.

第12圖為依據本揭示文件又一實施例的閘極驅動器簡化後的功能方塊圖。 FIG. 12 is a simplified functional block diagram of a gate driver according to another embodiment of this disclosure.

第13圖為依據本揭示文件又一實施例的防漏電電路的 電路示意圖。 Fig. 13 is a schematic circuit diagram of an anti-leakage circuit according to another embodiment of the present disclosure.

第14圖為依據本揭示文件又一實施例的顯示裝置的運作方式示意圖。 FIG. 14 is a schematic diagram of an operation mode of a display device according to another embodiment of the present disclosure.

第15圖為依據本揭示文件一實施例的末級移位暫存器簡化後的功能方塊圖。 FIG. 15 is a simplified functional block diagram of the last-stage shift register according to an embodiment of the present disclosure.

第16圖為依據本揭示文件一實施例的第一級移位暫存器簡化後的功能方塊圖。 FIG. 16 is a simplified functional block diagram of the first-stage shift register according to an embodiment of the present disclosure.

第17圖為依據本揭示文件再一實施例的閘極驅動器簡化後的功能方塊圖。 FIG. 17 is a simplified functional block diagram of a gate driver according to another embodiment of this disclosure.

第18圖為依據本揭示文件再一實施例的防漏電電路的電路示意圖。 FIG. 18 is a schematic circuit diagram of an anti-leakage circuit according to yet another embodiment of the present disclosure.

第19圖為依據本揭示文件再一實施例的顯示裝置的運作方式示意圖。 FIG. 19 is a schematic diagram of an operation mode of a display device according to still another embodiment of the present disclosure.

第20圖為依據本揭示文件一實施例的末級移位暫存器簡化後的功能方塊圖。 FIG. 20 is a simplified functional block diagram of the last-stage shift register according to an embodiment of the present disclosure.

第21圖為依據本揭示文件一實施例的第一級移位暫存器簡化後的功能方塊圖。 FIG. 21 is a simplified functional block diagram of the first-stage shift register according to an embodiment of the present disclosure.

第22圖為依據本揭示文件一實施例的末級移位暫存器簡化後的功能方塊圖。 FIG. 22 is a simplified functional block diagram of the last-stage shift register according to an embodiment of the present disclosure.

以下將配合相關圖式來說明本揭示文件的實施例。在圖式中,相同的標號表示相同或類似的元件或方法流程。 The embodiments of the present disclosure will be described below in conjunction with related drawings. In the drawings, the same reference numerals indicate the same or similar elements or method flows.

第1圖為根據本揭示文件一實施例的顯示裝置100簡化後的功能方塊圖。顯示裝置100包含控制電路110、源極驅動器120、閘極驅動器130、防漏電電路140以及多個畫素電路150。顯示裝置100還包含多個垂直信號線VL[1]~VL[x]與多個水平信號線HL[1]~HL[y]。多個畫素電路150各自對應設置於垂直信號線VL[1]~VL[x]與水平信號線HL[1]~HL[y]的交叉處。源極驅動器120與閘極驅動器130用於透過垂直信號線VL[1]~VL[x]與水平信號線HL[1]~HL[y]驅動畫素電路150。控制電路110用於提供源極驅動器120與閘極驅動器130運作所需要的各種電源輸入與信號。顯示裝置100能暫時停止更新顯示畫面以節省電力消耗。並且,顯示裝置100於停止更新顯示畫面的過程中,能減輕多個畫素電路150與垂直信號線VL[1]~VL[x]之間的漏電流。為使圖面簡潔而易於說明,顯示裝置100中的其他元件與連接關係並未繪示於第1圖中。 FIG. 1 is a simplified functional block diagram of a display device 100 according to an embodiment of the present disclosure. The display device 100 includes a control circuit 110, a source driver 120, a gate driver 130, a leakage prevention circuit 140, and a plurality of pixel circuits 150. The display device 100 further includes a plurality of vertical signal lines VL[1] to VL[x] and a plurality of horizontal signal lines HL[1] to HL[y]. The plurality of pixel circuits 150 are respectively disposed at intersections of the vertical signal lines VL[1]~VL[x] and the horizontal signal lines HL[1]~HL[y]. The source driver 120 and the gate driver 130 are used to drive the pixel circuit 150 through the vertical signal lines VL[1]~VL[x] and the horizontal signal lines HL[1]~HL[y]. The control circuit 110 is used to provide various power input and signals required for the operation of the source driver 120 and the gate driver 130. The display device 100 can temporarily stop updating the display screen to save power consumption. In addition, the display device 100 can reduce the leakage current between the plurality of pixel circuits 150 and the vertical signal lines VL[1] to VL[x] while the updating of the display screen is stopped. In order to make the drawing simple and easy to explain, the other components and the connection relationship in the display device 100 are not shown in FIG. 1.

本案說明書和圖式中使用的元件編號和裝置編號中的索引[1]~[n]、[1]~[x]與[1]~[y]等等,只是為了方便指稱個別的元件和裝置,並非有意將前述元件和裝置的數量侷限在特定數目。在本案說明書和圖式中,若使用某一元件編號或裝置編號時沒有指明該元件編號或裝置編號的索引,則代表該元件編號或裝置編號是指稱所屬元件群組或裝置群組中不特定的任一元件或裝置。例如,元件編號VL[1]指稱的對象是垂直信號線VL[1],而元件編號VL指稱的對象則是垂直信號線VL[1]~VL[x]中不特定的任意垂直信號 線。 The index numbers [1]~[n], [1]~[x] and [1]~[y] in the component numbers and device numbers used in the specification and drawings of this case are just for the convenience of referring to individual components and The device is not intended to limit the number of the aforementioned elements and devices to a specific number. In the specification and drawings of this case, if an element number or device number is used without indicating the index of the element number or device number, it means that the element number or device number refers to the component group or device group to which it belongs Any element or device. For example, the part number VL[1] refers to the vertical signal line VL[1], and the part number VL refers to the vertical signal line VL[1]~VL[x], which is any unspecified vertical signal line.

如第1圖所示,控制電路110用於提供資料信號Da與多工信號群組Mu至源極驅動器120,以使源極驅動器120依據多工信號群組Mu將資料信號Da寫入畫素電路150。控制電路110還用於提供時脈信號CK、反相時脈信號XCK、起始信號ST、重置信號RS與電力輸入PW至閘極驅動器130,以使閘極驅動器130依據時脈信號CK、反相時脈信號XCK、起始信號ST與重置信號RS導通或斷開畫素電路150與對應的垂直信號線VL。 As shown in FIG. 1, the control circuit 110 is used to provide the data signal Da and the multiplex signal group Mu to the source driver 120, so that the source driver 120 writes the data signal Da into the pixels according to the multiplex signal group Mu Circuit 150. The control circuit 110 is also used to provide the clock signal CK, the inverted clock signal XCK, the start signal ST, the reset signal RS and the power input PW to the gate driver 130, so that the gate driver 130 is based on the clock signal CK, The inverted clock signal XCK, the start signal ST and the reset signal RS turn on or off the pixel circuit 150 and the corresponding vertical signal line VL.

控制電路110還用於提供第一防護信號ODD與第二防護信號EVEN至防漏電電路140。閘極驅動器130用於提供第一控制信號群組CTL1與第二控制信號群組CTL2至防漏電電路140。防漏電電路140會依據第一控制信號群組CTL1與第二控制信號群組CTL2,於顯示裝置100暫時停止更新顯示畫面的期間,將第一防護信號ODD傳遞至部分的垂直信號線VL,並將第二防護信號EVEN傳遞至另一部份的垂直信號線VL。第一防護信號ODD與第二防護信號EVEN的電壓準位被設置為接近於畫素電路150儲存的電壓值,使得畫素電路150與垂直信號線VL之間的漏電流得以減輕。 The control circuit 110 is also used to provide the first protection signal ODD and the second protection signal EVEN to the leakage prevention circuit 140. The gate driver 130 is used to provide the first control signal group CTL1 and the second control signal group CTL2 to the leakage prevention circuit 140. According to the first control signal group CTL1 and the second control signal group CTL2, the anti-leakage circuit 140 transmits the first protection signal ODD to some vertical signal lines VL while the display device 100 temporarily stops updating the display image, and The second guard signal EVEN is transmitted to another part of the vertical signal line VL. The voltage levels of the first guard signal ODD and the second guard signal EVEN are set to be close to the voltage value stored by the pixel circuit 150, so that the leakage current between the pixel circuit 150 and the vertical signal line VL can be reduced.

實作上,畫素電路150可以用各種合適的液晶畫素電路來實現。在一實施例中,畫素電路150產生128灰階的亮度所需儲存的電壓值,於正半周期為第一電壓值,於負半週期為第二電壓值。第一防護信號ODD與第二防護信 號EVEN被設置為分別等於第一電壓值與第二電壓值,以防止128灰階左右亮度的畫素電路150產生漏電流。由於人眼對於128灰階附近的亮度變化較為敏感,本實施例可以有效提升使用者感受到的畫面品質。 In practice, the pixel circuit 150 can be implemented with various suitable liquid crystal pixel circuits. In one embodiment, the pixel circuit 150 generates 128 gray levels of brightness to store the voltage value, which is the first voltage value in the positive half cycle and the second voltage value in the negative half cycle. The first guard signal ODD and the second guard signal EVEN are set to be equal to the first voltage value and the second voltage value, respectively, to prevent the pixel circuit 150 having a brightness of about 128 gray levels from generating a leakage current. Since the human eye is relatively sensitive to changes in brightness around 128 gray levels, this embodiment can effectively improve the picture quality felt by the user.

第2圖為依據本揭示文件一實施例的閘極驅動器130簡化後的功能方塊圖。閘極驅動器130包含多級依序連接的移位暫存器210[1]~210[m]。移位暫存器210[1]~210[m]用於接收時脈信號CK與反向時脈信號XCK。移位暫存器210[1]與移位暫存器210[m]還用於接收電力輸入PW,在本實施例中,電力輸入PW包含第一參考電壓Vref1、第二參考電壓Vref2、第三參考電壓Vref3與第四參考電壓Vref4。 FIG. 2 is a simplified functional block diagram of the gate driver 130 according to an embodiment of the present disclosure. The gate driver 130 includes multiple stages of shift registers 210[1] to 210[m] connected in sequence. The shift registers 210[1]~210[m] are used to receive the clock signal CK and the reverse clock signal XCK. The shift register 210[1] and the shift register 210[m] are also used to receive the power input PW. In this embodiment, the power input PW includes the first reference voltage Vref1, the second reference voltage Vref2, the first The three reference voltage Vref3 and the fourth reference voltage Vref4.

另外,移位暫存器210[1]用於輸出第一控制信號群組CTL1,移位暫存器210[m]用於輸出第二控制信號群組CTL2。在本實施例中,第一控制信號群組CTL1包含第一上掃信號U1,第二控制信號群組CTL2包含第一下掃信號D1。移位暫存器210[1]與移位暫存器210[m]還分別用於接收起始信號ST與重置信號RS,並用於依據起始信號ST與重置信號RS控制移位暫存器210[2]~210[m-1]對應輸出多個掃描信號Gn[1]~Gn[y]至水平驅動線HL[1]~HL[y]。 In addition, the shift register 210[1] is used to output the first control signal group CTL1, and the shift register 210[m] is used to output the second control signal group CTL2. In this embodiment, the first control signal group CTL1 includes the first up-scan signal U1, and the second control signal group CTL2 includes the first down-scan signal D1. The shift register 210[1] and the shift register 210[m] are also used to receive the start signal ST and the reset signal RS, respectively, and to control the shift temporary according to the start signal ST and the reset signal RS The memories 210[2]~210[m-1] correspondingly output a plurality of scan signals Gn[1]~Gn[y] to the horizontal driving lines HL[1]~HL[y].

第3圖為依據本揭示文件一實施例的防漏電電路140的電路示意圖。防漏電電路140包含多個切換電路310[1]~310[n]。每個切換電路310耦接於兩條對應的垂直信號線VL,例如,切換電路310[1]耦接於垂直信號線VL[1] 與垂直信號線VL[2],切換電路310[2]耦接於垂直信號線VL[3]與垂直信號線VL[4],依此類推。為方便理解,以下以切換電路310[1]為例進行說明。 FIG. 3 is a schematic circuit diagram of the anti-leakage circuit 140 according to an embodiment of the present disclosure. The leakage prevention circuit 140 includes a plurality of switching circuits 310[1] to 310[n]. Each switching circuit 310 is coupled to two corresponding vertical signal lines VL, for example, the switching circuit 310[1] is coupled to the vertical signal line VL[1] and the vertical signal line VL[2], the switching circuit 310[2] It is coupled to the vertical signal line VL[3] and the vertical signal line VL[4], and so on. For ease of understanding, the following uses the switching circuit 310 [1] as an example.

切換電路310[1]包含第一下掃開關Td1、第二下掃開關Td2、第一上掃開關Tu1與第二上掃開關Tu2。第一下掃開關Td1的第一端用於接收第一防護信號ODD。第一下掃開關Td1的第二端耦接於縱向驅動線VL[1]。第一下掃開關Td1的控制端用於接收第一下掃信號D1。第二下掃開關Td2的第一端用於接收第二防護信號EVEN。第二下掃開關Td2的第二端耦接於縱向驅動線VL[2]。第二下掃開關Td2的控制端用於接收第一下掃信號D1。 The switching circuit 310[1] includes a first down-scan switch Td1, a second down-scan switch Td2, a first up-scan switch Tu1, and a second up-scan switch Tu2. The first end of the first down-scan switch Td1 is used to receive the first guard signal ODD. The second end of the first down-scan switch Td1 is coupled to the vertical drive line VL[1]. The control terminal of the first down-scan switch Td1 is used to receive the first down-scan signal D1. The first end of the second down-scan switch Td2 is used to receive the second guard signal EVEN. The second end of the second down-scan switch Td2 is coupled to the vertical drive line VL[2]. The control terminal of the second down-scan switch Td2 is used to receive the first down-scan signal D1.

第一上掃開關Tu1的第一端用於接收第一防護信號ODD。第一上掃開關Tu1的第二端耦接於縱向驅動線VL[1]。第一上掃開關Tu1的控制端用於接收第一上掃信號U1。第二上掃開關Tu2的第一端用於接收第二防護信號EVEN。第二上掃開關Tu2的第二端耦接於縱向驅動線VL[2]。第二上掃開關Tu2的控制端用於接收第一上掃信號U1。 The first end of the first up-scan switch Tu1 is used to receive the first guard signal ODD. The second end of the first up-sweep switch Tu1 is coupled to the longitudinal drive line VL[1]. The control terminal of the first up-scan switch Tu1 is used to receive the first up-scan signal U1. The first end of the second up-sweep switch Tu2 is used to receive the second guard signal EVEN. The second end of the second up-scan switch Tu2 is coupled to the longitudinal drive line VL[2]. The control terminal of the second up-scan switch Tu2 is used to receive the first up-scan signal U1.

前述切換電路310[1]的連接方式、元件、實施方式以及優點,皆適用於切換電路310[2]~310[n],為簡潔起見,在此不重複贅述。 The connection methods, components, embodiments, and advantages of the aforementioned switching circuit 310[1] are all applicable to the switching circuits 310[2] to 310[n]. For the sake of brevity, they are not repeated here.

第4圖為依據本揭示文件一實施例的顯示裝置100的運作方式示意圖。以下將以第2圖、第3圖與第4圖來說明顯示裝置100的運作。於第一掃描階段中,移位暫存器 210[1]輸出的第一上掃信號U1與移位暫存器210[m]輸出的第一下掃信號D1具有禁能準位(例如,-8V)。多工信號群組Mu則具有致能準位(例如,8.5V)。當移位暫存器210[1]接收到起始信號ST提供的起始脈衝SP時,移位暫存器210[2]~210[m-1]會依序輸出掃描脈衝CP。 FIG. 4 is a schematic diagram of the operation mode of the display device 100 according to an embodiment of the present disclosure. The operation of the display device 100 will be described below with reference to FIG. 2, FIG. 3 and FIG. 4. In the first scanning stage, the first up-scan signal U1 output from the shift register 210[1] and the first down-scan signal D1 output from the shift register 210[m] have a disabled level (for example, -8V). The multiplex signal group Mu has an enable level (for example, 8.5V). When the shift register 210[1] receives the start pulse SP provided by the start signal ST, the shift registers 210[2]~210[m-1] sequentially output the scan pulse CP.

換言之,當第一下掃信號D1與第一上掃信號U1都具有禁能準位,且移位暫存器210[1]接收到起始脈衝SP時,移位暫存器210[2]~210[m-1]會依序輸出掃描脈衝CP。 In other words, when both the first down-scan signal D1 and the first up-scan signal U1 have disabled levels, and the shift register 210[1] receives the start pulse SP, the shift register 210[2] ~210[m-1] will output the scan pulse CP in sequence.

因此,於第一掃描階段中,第一下掃開關Td1、第二下掃開關Td2、第一上掃開關Tu1與第二上掃開關Tu2皆被關斷。源極驅動器120會依據多工信號群組Mu將資料信號Da依序傳遞至垂直信號線VL[1]~VL[x]。此時,索引為奇數的垂直信號線VL(例如,垂直信號線VL[1]與垂直信號線VL[3]等等)會接收到正極性的電壓,索引為偶數的垂直信號線VL(例如,垂直信號線VL[2]與垂直信號線VL[4]等等)則會接收到負極性的電壓。 Therefore, in the first scanning stage, the first down-scan switch Td1, the second down-scan switch Td2, the first up-scan switch Tu1, and the second up-scan switch Tu2 are all turned off. The source driver 120 sequentially transmits the data signal Da to the vertical signal lines VL[1]~VL[x] according to the multiplex signal group Mu. At this time, the vertical signal line VL with an odd index (for example, the vertical signal line VL[1] and the vertical signal line VL[3], etc.) receives a positive voltage, and the vertical signal line with an even index (for example , The vertical signal line VL[2] and the vertical signal line VL[4], etc.) will receive a negative voltage.

另外,與索引為奇數的垂直信號線VL耦接的畫素電路150,會儲存有正極性的電壓,與索引為偶數的垂直信號線VL耦接的畫素電路150,則會儲存有負極性的電壓。 In addition, the pixel circuit 150 coupled to the vertical signal line VL with an odd index will store a positive voltage, and the pixel circuit 150 coupled to the vertical signal line VL with an even index will store a negative polarity. The voltage.

接著,於第一維持階段中,第一上掃信號U1與多工信號群組Mu具有禁能準位。第一防護信號ODD會具有正極性的電壓(例如,2.5V),而第二防護信號EVEN會具有負極性的電壓(例如,-2.5V)。當移位暫存器210[m]接收到 移位暫存器210[m-1]輸出的掃描脈衝CP時,移位暫存器210[m]會將第一下掃信號D1自禁能準位切換至致能準位。此時,移位暫存器210[2]~210[m-1]會停止輸出掃描脈衝CP。 Then, in the first maintenance stage, the first up-scan signal U1 and the multiplex signal group Mu have a disabled level. The first guard signal ODD will have a positive voltage (for example, 2.5V), and the second guard signal EVEN will have a negative voltage (for example, -2.5V). When the shift register 210[m] receives the scan pulse CP output from the shift register 210[m-1], the shift register 210[m] disables the first down-scan signal D1 from itself The level is switched to the enable level. At this time, the shift registers 210[2]~210[m-1] will stop outputting the scan pulse CP.

因此,第一下掃開關Td1與第二下掃開關Td2會被導通,而第一上掃開關Tu1與第二上掃開關Tu2維持於關斷狀態。第一防護信號ODD會經由第一下掃開關Td1傳遞至索引為奇數的垂直信號線VL,使得索引為奇數的垂直信號線VL具有正極性的電壓。由於與索引為奇數的垂直信號線VL耦接的畫素電路150亦儲存有正極性的電壓,所以索引為奇數的垂直信號線VL與對應的畫素電路150之間的漏電流得以減輕。 Therefore, the first down scan switch Td1 and the second down scan switch Td2 are turned on, and the first up scan switch Tu1 and the second up scan switch Tu2 are maintained in the off state. The first guard signal ODD is transmitted to the vertical signal line VL with an odd index through the first down-scan switch Td1, so that the vertical signal line VL with an odd index has a positive voltage. Since the pixel circuit 150 coupled to the vertical signal line VL with an odd index also stores a positive voltage, the leakage current between the vertical signal line VL with an odd index and the corresponding pixel circuit 150 is reduced.

另一方面,第二防護信號EVEN會經由第二下掃開關Td2傳遞至索引為偶數的垂直信號線VL,使得索引為偶數的垂直信號線VL具有負極性的電壓。由於與索引為偶數的垂直信號線VL耦接的畫素電路150亦儲存有負極性的電壓,所以索引為偶數的垂直信號線VL與對應的畫素電路150之間的漏電流得以減輕。 On the other hand, the second guard signal EVEN is transmitted to the even-numbered vertical signal line VL through the second down-scan switch Td2, so that the even-numbered vertical signal line VL has a negative voltage. Since the pixel circuit 150 coupled to the vertical signal line VL with an even index also stores a negative voltage, the leakage current between the vertical signal line VL with an even index and the corresponding pixel circuit 150 is reduced.

於第二掃描階段中,當移位暫存器210[m]接收到重置信號RS提供的重置脈衝RP時,移位暫存器210[m]將第一下掃信號D1自致能準位切換至禁能準位。接著,當移位暫存器210[1]再度接收到起始脈衝SP時,移位暫存器210[2]~210[m-1]會再度依序輸出掃描脈衝CP。重置脈衝RP於時序上早於起始脈衝SP。亦即,於第一掃描階段或第 二掃描階段中,移位暫存器210[m]會先接收到重置脈衝RP,然後移位暫存器210[1]才接收到起始脈衝SP。 In the second scanning stage, when the shift register 210[m] receives the reset pulse RP provided by the reset signal RS, the shift register 210[m] automatically enables the first down-scan signal D1 The level is switched to the disabled level. Then, when the shift register 210[1] receives the start pulse SP again, the shift registers 210[2]~210[m-1] will output the scan pulse CP in sequence again. The reset pulse RP is earlier than the start pulse SP in timing. That is, during the first scanning stage or the second scanning stage, the shift register 210[m] will receive the reset pulse RP first, and then the shift register 210[1] will receive the start pulse SP .

此時,為了實現極性反轉,索引為奇數的垂直信號線VL會改為接收到負極性的電壓,而索引為偶數的垂直信號線VL則會改為接收到正極性的電壓。顯示裝置100於第二掃描階段的運作方式,相似於顯示裝置100於第一掃描階段的運作方式,為簡潔起見,在此不重複贅述。 At this time, in order to achieve polarity inversion, the vertical signal line VL with an odd index will change to receive a voltage of negative polarity, and the vertical signal line VL with an even index will change to receive a voltage of positive polarity. The operation mode of the display device 100 in the second scanning stage is similar to the operation mode of the display device 100 in the first scanning stage. For the sake of brevity, the details will not be repeated here.

於第二維持階段中,第一防護信號ODD會切換至負極性的電壓(例如,-2.5V),而第二防護信號EVEN會切換至正極性的電壓(例如,2.5V)。當移位暫存器210[m]接收到移位暫存器210[m-1]輸出的掃描脈衝CP時,移位暫存器210[m]會將第一下掃信號D1自禁能準位切換至致能準位。 In the second sustain phase, the first protection signal ODD will switch to a negative voltage (for example, -2.5V), and the second protection signal EVEN will switch to a positive voltage (for example, 2.5V). When the shift register 210[m] receives the scan pulse CP output from the shift register 210[m-1], the shift register 210[m] disables the first down-scan signal D1 from itself The level is switched to the enable level.

因此,第一下掃開關Td1與第二下掃開關Td2會被導通,而第一上掃開關Tu1與第二上掃開關Tu2維持於關斷狀態。第一防護信號ODD會經由第一下掃開關Td1傳遞至索引為奇數的垂直信號線VL,使得索引為奇數的垂直信號線VL具有負極性的電壓。由於與索引為奇數的垂直信號線VL耦接的畫素電路150亦儲存有負極性的電壓,所以索引為奇數的垂直信號線VL與對應的畫素電路150之間的漏電流得以減輕。 Therefore, the first down scan switch Td1 and the second down scan switch Td2 are turned on, and the first up scan switch Tu1 and the second up scan switch Tu2 are maintained in the off state. The first guard signal ODD is transmitted to the vertical signal line VL having an odd index through the first down-scan switch Td1, so that the vertical signal line VL having an odd index has a negative voltage. Since the pixel circuit 150 coupled to the vertical signal line VL with an odd index also stores a negative voltage, the leakage current between the vertical signal line VL with an odd index and the corresponding pixel circuit 150 is reduced.

另一方面,第二防護信號EVEN會經由第二下掃開關Td2傳遞至索引為偶數的垂直信號線VL,使得索引為偶數的垂直信號線VL具有正極性的電壓。由於與索引為 偶數的垂直信號線VL耦接的畫素電路150亦儲存有正極性的電壓,所以索引為偶數的垂直信號線VL與對應的畫素電路150之間的漏電流得以減輕。 On the other hand, the second guard signal EVEN is transmitted to the vertical signal line VL with an even index through the second down-scan switch Td2, so that the vertical signal line VL with an even index has a positive voltage. Since the pixel circuit 150 coupled to the vertical signal line VL with an even index also stores a positive voltage, the leakage current between the vertical signal line VL with an even index and the corresponding pixel circuit 150 is reduced.

另外,由上述可知,於第一維持階段與第二維持階段中,第一防護信號ODD與第二防護信號EVEN的波形彼此相反。 In addition, as can be seen from the above, in the first sustain stage and the second sustain stage, the waveforms of the first guard signal ODD and the second guard signal EVEN are opposite to each other.

在某一實施例中,移位暫存器210[2]~210[m-1]是自第2圖的下方往上方依序輸出掃描脈衝CP。亦即,移位暫存器210[m-1]會第一個輸出掃描脈衝CP,而移位暫存器210[2]會最後一個輸出掃描脈衝CP。此時,移位暫存器210[1]會由接收起始信號ST改為接收重置信號RS,並執行相似於第2圖至第4圖的實施例中移位暫存器210[m]的運作。移位暫存器210[m]會由接收重置信號RS改為接收起始信號ST,並執行相似於第2圖至第4圖的實施例中移位暫存器210[1]的運作。 In one embodiment, the shift registers 210[2] to 210[m-1] sequentially output the scan pulse CP from the bottom to the top in FIG. 2. That is, the shift register 210[m-1] will output the scan pulse CP first, and the shift register 210[2] will output the scan pulse CP last. At this time, the shift register 210[1] will change from receiving the start signal ST to receiving the reset signal RS, and perform the shift register 210[m in the embodiment similar to FIGS. 2 to 4 ] Operation. The shift register 210[m] is changed from receiving the reset signal RS to receiving the start signal ST, and performs operations similar to the shift register 210[1] in the embodiment of FIGS. 2 to 4 .

在此情況下,第一下掃開關Td1與第二下掃開關Td2會維持於關斷狀態。第一上掃開關Tu1與第二上掃開關Tu2於第一掃描階段與第二掃描階段會被關斷,並於第一維持階段與第二維持階段被導通。因此,於第一維持階段與第二維持階段中,第一防護信號ODD會經由第一上掃開關Tu1傳遞至索引為奇數的垂直驅動線VL,第二防護信號EVEN會經由第二上掃開關Tu2傳遞至索引為偶數的垂直驅動線VL。前述第2圖至第4圖的實施例的其他連接方式、元件、實施方式以及優點,皆適用於本實施例,為簡潔起見, 在此不重複贅述。 In this case, the first down-scan switch Td1 and the second down-scan switch Td2 are maintained in the off state. The first up-scan switch Tu1 and the second up-scan switch Tu2 are turned off during the first scan stage and the second scan stage, and are turned on during the first sustain stage and the second sustain stage. Therefore, in the first sustain stage and the second sustain stage, the first guard signal ODD is transmitted to the vertical drive line VL with an odd index through the first up-scan switch Tu1, and the second guard signal EVEN is passed through the second up-scan switch Tu2 passes to the vertical drive line VL with an even index. The other connection methods, components, embodiments, and advantages of the foregoing embodiments of FIGS. 2 to 4 are applicable to this embodiment, and for the sake of brevity, they are not repeated here.

第5圖為依據本揭示文件一實施例的移位暫存器210[m]簡化後的功能方塊圖。移位暫存器210[m]包含第一電晶體M1、第二電晶體M2、第三電晶體M3、第四電晶體M4與驅動電路510。驅動電路510用於接收移位暫存器210[m]的前一級移位暫存器(亦即,移位暫存器210[m-1])輸出的掃描脈衝CP,以及接收重置信號RS、第一參考電壓Vref1、第二參考電壓Vref2、第三參考電壓Vref3與第四參考電壓Vref4。 FIG. 5 is a simplified functional block diagram of the shift register 210 [m] according to an embodiment of the present disclosure. The shift register 210 [m] includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a driving circuit 510. The driving circuit 510 is used to receive the scan pulse CP output by the shift register of the previous stage of the shift register 210 [m] (that is, the shift register 210 [m-1]), and receive the reset signal RS, first reference voltage Vref1, second reference voltage Vref2, third reference voltage Vref3 and fourth reference voltage Vref4.

第一電晶體M1耦接於第一電源端In1與第一節點N1之間,用於透過第一電源端In1接收第三參考電壓Vref3。第二電晶體M2耦接於第一節點N1與接地端GND之間,其中第一電晶體M1與第二電晶體M2的控制端都耦接於驅動電路510。第三電晶體M3耦接於第一節點N1與第一輸出端O1之間,且第三電晶體M3的控制端用於接收第一參考電壓Vref1。第四電晶體M4耦接於第一輸出端O1與接地端GND之間,且第四電晶體M4的控制端用於接收第二參考電壓Vref2。 The first transistor M1 is coupled between the first power terminal In1 and the first node N1 for receiving the third reference voltage Vref3 through the first power terminal In1. The second transistor M2 is coupled between the first node N1 and the ground GND. The control terminals of the first transistor M1 and the second transistor M2 are coupled to the driving circuit 510. The third transistor M3 is coupled between the first node N1 and the first output terminal O1, and the control terminal of the third transistor M3 is used to receive the first reference voltage Vref1. The fourth transistor M4 is coupled between the first output terminal O1 and the ground terminal GND, and the control terminal of the fourth transistor M4 is used to receive the second reference voltage Vref2.

當移位暫存器210[2]~210[m-1]具有第一掃描順序(例如,由第2圖的上方至下方依序輸出掃描脈衝CP)時,第一參考電壓Vref1會具有高電壓準位且第二參考電壓Vref2會具有低電壓準位。因此,第三電晶體M3會維持於導通狀態,第四電晶體M4會維持於關斷狀態。 When the shift registers 210[2]~210[m-1] have the first scanning order (for example, the scanning pulse CP is sequentially output from the top to the bottom of FIG. 2), the first reference voltage Vref1 will have a high The voltage level and the second reference voltage Vref2 will have a low voltage level. Therefore, the third transistor M3 is maintained in the on state, and the fourth transistor M4 is maintained in the off state.

當移位暫存器210[m-1]輸出掃描脈衝CP時, 驅動電路510會導通第一電晶體M1並關斷第二電晶體M2,以導通第一電源端In1與第一節點N1。此時,第三參考電壓Vref3便會自第一電源端In1傳遞至第一輸出端O1,並作為具有致能準位的第一下掃信號D1輸出。 When the shift register 210 [m-1] outputs the scan pulse CP, the driving circuit 510 turns on the first transistor M1 and turns off the second transistor M2 to turn on the first power terminal In1 and the first node N1. At this time, the third reference voltage Vref3 is transferred from the first power supply terminal In1 to the first output terminal O1, and is output as the first down-scan signal D1 with the enable level.

另一方面,當驅動電路510接收到重置信號RS的重置脈衝RP時,驅動電路510會關斷第一電晶體M1並導通第二電晶體M2,以導通第一節點N1與接地端GND。此時,接地電壓便會自接地端GND傳遞至第一輸出端O1,並作為具有禁能準位的第一下掃信號D1輸出。 On the other hand, when the driving circuit 510 receives the reset pulse RP of the reset signal RS, the driving circuit 510 turns off the first transistor M1 and turns on the second transistor M2 to turn on the first node N1 and the ground GND . At this time, the ground voltage is transmitted from the ground terminal GND to the first output terminal O1, and is output as the first down-scan signal D1 with the disabled level.

詳細而言,驅動電路510包含第一驅動電晶體Tr1、第二驅動電晶體Tr2、第三驅動電晶體Tr3、第四驅動電晶體Tr4、第五驅動電晶體Tr5、第六驅動電晶體Tr6、第七驅動電晶體Tr7、第八驅動電晶體Tr8、第九驅動電晶體Tr9、第十驅動電晶體Tr10與第十一驅動電晶體Tr11。 In detail, the driving circuit 510 includes a first driving transistor Tr1, a second driving transistor Tr2, a third driving transistor Tr3, a fourth driving transistor Tr4, a fifth driving transistor Tr5, a sixth driving transistor Tr6, The seventh driving transistor Tr7, the eighth driving transistor Tr8, the ninth driving transistor Tr9, the tenth driving transistor Tr10, and the eleventh driving transistor Tr11.

第一驅動電晶體Tr1的第一端用於接收時脈信號CK,第二端與控制端分別耦接於第一內部節點P1與第二內部節點P2。第二驅動電晶體Tr2的第一端、第二端與控制端分別耦接於第一內部節點P1、第三內部節點P3與第二內部節點P2,且第二驅動電晶體Tr2的第一端和第二端互相耦接。第三驅動電晶體Tr3的第一端、第二端與控制端分別耦接於第三內部節點P3、接地端GND與第四內部節點P4。第四驅動電晶體Tr4的第一端、第二端分別耦接於第二內部節點P2與第五內部節點P5,控制端用於接收第四參考電壓Vref4。 The first terminal of the first driving transistor Tr1 is used to receive the clock signal CK, and the second terminal and the control terminal are respectively coupled to the first internal node P1 and the second internal node P2. The first end, the second end, and the control end of the second driving transistor Tr2 are respectively coupled to the first internal node P1, the third internal node P3, and the second internal node P2, and the first end of the second driving transistor Tr2 And the second end are coupled to each other. The first end, the second end, and the control end of the third driving transistor Tr3 are respectively coupled to the third internal node P3, the ground terminal GND, and the fourth internal node P4. The first terminal and the second terminal of the fourth driving transistor Tr4 are respectively coupled to the second internal node P2 and the fifth internal node P5, and the control terminal is used to receive the fourth reference voltage Vref4.

第五驅動電晶體Tr5的第一端與控制端耦接於第三內部節點P3,第二端耦接於第五內部節點P5。第六驅動電晶體Tr6的第一端、第二端與控制端分別耦接於第五內部節點P5、接地端GND與第四內部節點P4。第七驅動電晶體Tr7的第一端與控制端用於接收重置信號RS,第二端耦接於第四內部節點P4。第八驅動電晶體Tr8的第一端用於接收第四參考電壓Vref4,第二端耦接於電阻R1的第一端,控制端用於接收反相時脈信號XCK。 The first end and the control end of the fifth driving transistor Tr5 are coupled to the third internal node P3, and the second end is coupled to the fifth internal node P5. The first end, the second end, and the control end of the sixth driving transistor Tr6 are respectively coupled to the fifth internal node P5, the ground terminal GND, and the fourth internal node P4. The first terminal and the control terminal of the seventh driving transistor Tr7 are used to receive the reset signal RS, and the second terminal is coupled to the fourth internal node P4. The first terminal of the eighth driving transistor Tr8 is used to receive the fourth reference voltage Vref4, the second terminal is coupled to the first terminal of the resistor R1, and the control terminal is used to receive the inverted clock signal XCK.

第九驅動電晶體Tr9的第一端、第二端與控制端分別耦接於電阻R1的第二端、接地端GND與第五內部節點P5。第十驅動電晶體Tr10的第一端用於接收第一參考電壓Vref1,第二端耦接於第五內部節點P5,控制端用於接收移位暫存器210[m-1]輸出的掃描脈衝CP。第十一驅動電晶體Tr11的第一端耦接於第五內部節點P5,第二端用於接收第二參考電壓Vref2,控制端用於接收重置信號RS。 The first terminal, the second terminal and the control terminal of the ninth driving transistor Tr9 are respectively coupled to the second terminal of the resistor R1, the ground terminal GND and the fifth internal node P5. The first terminal of the tenth driving transistor Tr10 is used to receive the first reference voltage Vref1, the second terminal is coupled to the fifth internal node P5, and the control terminal is used to receive the scan output from the shift register 210[m-1] Pulse CP. The first end of the eleventh driving transistor Tr11 is coupled to the fifth internal node P5, the second end is used to receive the second reference voltage Vref2, and the control end is used to receive the reset signal RS.

第6圖為依據本揭示文件一實施例的第一級移位暫存器210[1]簡化後的功能方塊圖。移位暫存器210[1]與移位暫存器210[m]相似。差異在於,移位暫存器210[1]的第三電晶體M3與第四電晶體M4的控制端分別用於接收第二參考電壓Vref2與第一參考電壓Vref1,且移位暫存器210[1]的第十驅動電晶體Tr10與第十一驅動電晶體Tr11的控制端分別用於接收起始信號ST與移位暫存器210[2]輸出的掃描脈衝CP。因此,當移位暫存器210[2]~210[m-1]具有前述的第一掃描順序時,移位暫存器210[1]的第三電 晶體M3會關斷而第四電晶體M4會導通,以將第一上掃信號U1維持於禁能準位。 FIG. 6 is a simplified functional block diagram of the first-stage shift register 210[1] according to an embodiment of the present disclosure. The shift register 210[1] is similar to the shift register 210[m]. The difference is that the control terminals of the third transistor M3 and the fourth transistor M4 of the shift register 210[1] are used to receive the second reference voltage Vref2 and the first reference voltage Vref1, respectively, and the shift register 210 The control terminals of the tenth driving transistor Tr10 and the eleventh driving transistor Tr11 of [1] are used to receive the start signal ST and the scan pulse CP output by the shift register 210 [2], respectively. Therefore, when the shift registers 210[2]~210[m-1] have the aforementioned first scanning sequence, the third transistor M3 of the shift register 210[1] is turned off and the fourth power The crystal M4 will be turned on to maintain the first up-scan signal U1 at the disabled level.

在一實施例中,移位暫存器210[2]~210[m-1]具有第二掃描順序(例如,由第2圖的下方至上方依序輸出掃描脈衝CP)。此時,第一參考電壓Vref1會具有低電壓準位且第二參考電壓Vref2會具有高電壓準位。因此,移位暫存器210[1]的第三電晶體M3會導通而第四電晶體M4會關斷,以使移位暫存器210[1]能夠輸出具有致能準位的第一上掃信號U1。另一方面,移位暫存器210[m]的第三電晶體M3會關斷而第四電晶體M4會導通,以使移位暫存器210[m]輸出的第一下掃信號D1維持於禁能準位。 In one embodiment, the shift registers 210[2]-210[m-1] have a second scan order (for example, the scan pulse CP is sequentially output from the bottom to the top of FIG. 2). At this time, the first reference voltage Vref1 will have a low voltage level and the second reference voltage Vref2 will have a high voltage level. Therefore, the third transistor M3 of the shift register 210[1] will be turned on and the fourth transistor M4 will be turned off, so that the shift register 210[1] can output the first with the enable level Up signal U1. On the other hand, the third transistor M3 of the shift register 210 [m] will be turned off and the fourth transistor M4 will be turned on, so that the first down-scan signal D1 output by the shift register 210 [m] Maintain at the disabled level.

在一無需雙向掃描的實施例中,可以省略第2圖的移位暫存器210[1],並將移位暫存器210[2]由接收移位暫存器210[1]的掃描脈衝CP改為接收起始信號ST。另外,還可以省略切換電路310中的第一上掃開關Tu1與第二上掃開關Tu2。 In an embodiment that does not require bidirectional scanning, the shift register 210[1] of FIG. 2 can be omitted, and the shift register 210[2] can be scanned by the receiving shift register 210[1]. The pulse CP receives the start signal ST instead. In addition, the first up-scan switch Tu1 and the second up-scan switch Tu2 in the switching circuit 310 may also be omitted.

此外,還可以省略第5圖的第一電晶體M1、第二電晶體M2、第三電晶體M3與第四電晶體M4,並將第一驅動電晶體Tr1的第一端改為接收第三參考電壓Vref3。在此情況下,第一下掃信號D1會改由移位暫存器210[m]的第三內部節點P3輸出。 In addition, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 of FIG. 5 may also be omitted, and the first end of the first driving transistor Tr1 may be changed to receive the third Reference voltage Vref3. In this case, the first down-scan signal D1 will be output by the third internal node P3 of the shift register 210 [m] instead.

第7圖為依據本揭示文件另一實施例的閘極驅動器130簡化後的功能方塊圖。在本實施例中,閘極驅動器130包含依序連接的移位暫存器710[1]~710[m]。移位暫存 器710[1]~710[m]相似於第2圖的移位暫存器210[1]~210[m]。差異在於,本實施例的電力輸入PW包含第一參考電壓Vref1、第二參考電壓Vref2、第三參考電壓Vref3、第四參考電壓Vref4與第五參考電壓Vref5,所以移位暫存器710[1]與710[m]除了用於接收第一參考電壓Vref1至第四參考電壓Vref4,還用於接收第五參考電壓Vref5。 FIG. 7 is a simplified functional block diagram of the gate driver 130 according to another embodiment of the present disclosure. In this embodiment, the gate driver 130 includes shift registers 710[1] to 710[m] connected in sequence. The shift registers 710[1]~710[m] are similar to the shift registers 210[1]~210[m] in FIG. The difference is that the power input PW of this embodiment includes a first reference voltage Vref1, a second reference voltage Vref2, a third reference voltage Vref3, a fourth reference voltage Vref4 and a fifth reference voltage Vref5, so the shift register 710[1 ] And 710 [m] are used to receive the fifth reference voltage Vref5 in addition to the first to fourth reference voltages Vref1 to Vref4.

另外,在本實施例中,第一控制信號群組CTL1包含第一上掃信號U1與第二上掃信號U2,第二控制信號群組CTL2包含第一下掃信號D1與第二下掃信號D2。 In addition, in this embodiment, the first control signal group CTL1 includes a first up-scan signal U1 and a second up-scan signal U2, and the second control signal group CTL2 includes a first down-scan signal D1 and a second down-scan signal D2.

第8圖為依據本揭示文件另一實施例的防漏電電路140的電路示意圖。在本實施例中,防漏電電路140包含多個切換電路810[1]~810[n]。每個切換電路810耦接於兩條對應的垂直信號線VL,例如,切換電路810[1]耦接於垂直信號線VL[1]與垂直信號線VL[2],切換電路810[2]耦接於垂直信號線VL[3]與垂直信號線VL[4],依此類推,為簡潔起見,在此不重複贅述。為方便理解,以下以切換電路810[1]為例進行說明。 FIG. 8 is a schematic circuit diagram of the anti-leakage circuit 140 according to another embodiment of the present disclosure. In this embodiment, the leakage prevention circuit 140 includes a plurality of switching circuits 810[1] to 810[n]. Each switching circuit 810 is coupled to two corresponding vertical signal lines VL, for example, the switching circuit 810[1] is coupled to the vertical signal line VL[1] and the vertical signal line VL[2], the switching circuit 810[2] It is coupled to the vertical signal line VL[3] and the vertical signal line VL[4], and so on. For the sake of brevity, they are not repeated here. To facilitate understanding, the following uses the switching circuit 810 [1] as an example for description.

切換電路810[1]包含第一下掃開關Td1、第二下掃開關Td2、第三下掃開關Td3與第四下掃開關Td4。切換電路810[1]還包含第一上掃開關Tu1、第二上掃開關Tu2、第三上掃開關Tu3與第四上掃開關Tu4。第一下掃開關Td1的第一端用於接收第一防護信號ODD。第一下掃開關Td1的第二端耦接於縱向信號線VL[1]。第一下掃開關 Td1的控制端用於接收第一下掃信號D1。第二下掃開關Td2的第一端用於接收第二防護信號EVEN。第二下掃開關Td2的第二端耦接於縱向信號線VL[1]。第二下掃開關Td2的控制端用於接收第二下掃信號D2。 The switching circuit 810 [1] includes a first down-scan switch Td1, a second down-scan switch Td2, a third down-scan switch Td3, and a fourth down-scan switch Td4. The switching circuit 810 [1] further includes a first up-sweep switch Tu1, a second up-sweep switch Tu2, a third up-sweep switch Tu3, and a fourth up-sweep switch Tu4. The first end of the first down-scan switch Td1 is used to receive the first guard signal ODD. The second end of the first down-scan switch Td1 is coupled to the longitudinal signal line VL[1]. The control terminal of the first down-scan switch Td1 is used to receive the first down-scan signal D1. The first end of the second down-scan switch Td2 is used to receive the second guard signal EVEN. The second end of the second down-scan switch Td2 is coupled to the longitudinal signal line VL[1]. The control terminal of the second down-scan switch Td2 is used to receive the second down-scan signal D2.

第三下掃開關Td3的第一端用於接收第二防護信號EVEN。第三下掃開關Td3的第二端耦接於第二縱向信號線VL[2]。第三下掃開關Td3的控制端用於接收第一下掃信號D1。第四下掃開關Td4的第一端用於接收第一防護信號ODD。第四下掃開關Td4的第二端耦接於縱向信號線VL[2]。第四下掃開關Td4的控制端用於接收第二下掃信號D2。 The first end of the third down-scan switch Td3 is used to receive the second guard signal EVEN. The second end of the third down-scan switch Td3 is coupled to the second longitudinal signal line VL[2]. The control terminal of the third down-scan switch Td3 is used to receive the first down-scan signal D1. The first end of the fourth down-scan switch Td4 is used to receive the first guard signal ODD. The second end of the fourth down-scan switch Td4 is coupled to the longitudinal signal line VL[2]. The control terminal of the fourth down-scan switch Td4 is used to receive the second down-scan signal D2.

第一上掃開關Tu1的第一端用於接收第一防護信號ODD。第一上掃開關Tu1的第二端耦接於縱向信號線VL[1]。第一上掃開關Tu1的控制端用於接收第一上掃信號U1。第二上掃開關Tu2的第一端用於接收第二防護信號EVEN。第二上掃開關Tu2的第二端耦接於縱向信號線VL[1]。第二上掃開關的控制端用於接收第二上掃信號U2。 The first end of the first up-scan switch Tu1 is used to receive the first guard signal ODD. The second end of the first up-scan switch Tu1 is coupled to the longitudinal signal line VL[1]. The control terminal of the first up-scan switch Tu1 is used to receive the first up-scan signal U1. The first end of the second up-sweep switch Tu2 is used to receive the second guard signal EVEN. The second end of the second up-sweep switch Tu2 is coupled to the longitudinal signal line VL[1]. The control end of the second upsweep switch is used to receive the second upsweep signal U2.

第三上掃開關Tu3的第一端用於接收第二防護信號EVEN。第三上掃開關Tu3的第二端耦接於縱向信號線VL[2]。第三上掃開關Tu3的控制端用於接收第一上掃信號U1。第四上掃開關Tu4的第一端用於接收第一防護信號ODD。第四上掃開關Tu4的第二端耦接於縱向信號線VL[2]。第四上掃開關Tu4的控制端用於接收第二上掃信號U2。 The first end of the third up-scan switch Tu3 is used to receive the second guard signal EVEN. The second end of the third up-scan switch Tu3 is coupled to the longitudinal signal line VL[2]. The control terminal of the third up-scan switch Tu3 is used to receive the first up-scan signal U1. The first end of the fourth up-scan switch Tu4 is used to receive the first guard signal ODD. The second end of the fourth up-scan switch Tu4 is coupled to the longitudinal signal line VL[2]. The control terminal of the fourth up-scan switch Tu4 is used to receive the second up-scan signal U2.

前述切換電路810[1]的連接方式、元件、實施方式以及優點,皆適用於切換電路810[2]~810[n],為簡潔起見,在此不重複贅述。 The connection methods, components, implementations, and advantages of the aforementioned switching circuit 810[1] are all applicable to the switching circuits 810[2]~810[n]. For the sake of brevity, they are not repeated here.

第9圖為依據本揭示文件另一實施例的顯示裝置100的運作方式示意圖。以下將以第7圖、第8圖與第9圖來說明顯示裝置100的運作。在本實施例中,第一防護信號ODD維持於正極性的電壓(例如,2.5V),而第二防護信號EVEN維持於負極性的電壓(例如,-2.5V)。 FIG. 9 is a schematic diagram of the operation of the display device 100 according to another embodiment of the present disclosure. The operation of the display device 100 will be described below with reference to FIGS. 7, 8 and 9. In this embodiment, the first protection signal ODD is maintained at a positive voltage (for example, 2.5V), and the second protection signal EVEN is maintained at a negative voltage (for example, -2.5V).

在第一掃描階段中,第一上掃信號U1、第二上掃信號U2、第一下掃信號D1與第二下掃信號D2具有禁能準位。因此,第一下掃開關Td1、第二下掃開關Td2、第三下掃開關Td3、第四下掃開關Td4、第一上掃開關Tu1、第二上掃開關Tu2、第三上掃開關Tu3與第四上掃開關Tu4被關斷。 In the first scanning stage, the first up-scan signal U1, the second up-scan signal U2, the first down-scan signal D1, and the second down-scan signal D2 have disable levels. Therefore, the first down sweep switch Td1, the second down sweep switch Td2, the third down sweep switch Td3, the fourth down sweep switch Td4, the first up sweep switch Tu1, the second up sweep switch Tu2, the third up sweep switch Tu3 The fourth sweep switch Tu4 is turned off.

此時,索引為奇數的垂直信號線VL會接收到正極性的電壓,而索引為偶數的垂直信號線VL則會接收到負極性的電壓。 At this time, the vertical signal line VL with an odd index will receive a positive voltage, and the vertical signal line VL with an even index will receive a negative voltage.

在第一維持階段中,第一下掃信號D1具有致能準位,而第一上掃信號U1、第二上掃信號U2與第二下掃信號D2維持於禁能準位。因此,第一下掃開關Td1與第三下掃開關Td3被導通,而第二下掃開關Td2、第四下掃開關Td4、第一上掃開關Tu1、第二上掃開關Tu2、第三上掃開關Tu3與第四下掃開關Tu4被關斷。 In the first sustain stage, the first down-scan signal D1 has an enable level, and the first up-scan signal U1, the second up-scan signal U2, and the second down-scan signal D2 are maintained at the disabled level. Therefore, the first down sweep switch Td1 and the third down sweep switch Td3 are turned on, and the second down sweep switch Td2, the fourth down sweep switch Td4, the first up sweep switch Tu1, the second up sweep switch Tu2, the third up sweep switch The sweep switch Tu3 and the fourth down sweep switch Tu4 are turned off.

此時,第一防護信號ODD會經由第一下掃開關 Td1傳遞至索引為奇數的垂直信號線VL,使得索引為奇數的垂直信號線VL具有正極性的電壓。第二防護信號EVEN會經由第三下掃開關Td3傳遞至索引為偶數的垂直信號線VL,使得索引為偶數的垂直信號線VL具有負極性的電壓。因此,垂直信號線VL與對應的畫素電路150之間的漏電流得以減輕。 At this time, the first guard signal ODD is transmitted to the vertical signal line VL having an odd index through the first down-scan switch Td1, so that the vertical signal line VL having an odd index has a positive voltage. The second guard signal EVEN is transmitted to the vertical signal line VL with an even index through the third down-scan switch Td3, so that the vertical signal line VL with an even index has a negative voltage. Therefore, the leakage current between the vertical signal line VL and the corresponding pixel circuit 150 is reduced.

在第二掃描階段中,第一上掃信號U1、第二上掃信號U2、第一下掃信號D1與第二下掃信號D2具有禁能準位。因此,第一下掃開關Td1、第二下掃開關Td2、第三下掃開關Td3、第四下掃開關Td4、第一上掃開關Tu1、第二上掃開關Tu2、第三上掃開關Tu3與第四上掃開關Tu4會再度被關斷。 In the second scanning stage, the first up-scan signal U1, the second up-scan signal U2, the first down-scan signal D1, and the second down-scan signal D2 have disabled levels. Therefore, the first down sweep switch Td1, the second down sweep switch Td2, the third down sweep switch Td3, the fourth down sweep switch Td4, the first up sweep switch Tu1, the second up sweep switch Tu2, the third up sweep switch Tu3 The fourth sweep switch Tu4 will be turned off again.

此時,索引為奇數的垂直信號線VL會接收到負極性的電壓,而索引為偶數的垂直信號線VL則會接收到正極性的電壓。 At this time, the vertical signal line VL with an odd index will receive a negative voltage, and the vertical signal line VL with an even index will receive a positive voltage.

接著,在第二維持階段中,第二下掃信號D2具有致能準位,而第一上掃信號U1、第二上掃信號U2與第一下掃信號D1維持於禁能準位。因此,第二下掃開關Td2與第四下掃開關Td4被導通,而第一下掃開關Td1、第三下掃開關Td3、第一上掃開關Tu1、第二上掃開關Tu2、第三上掃開關Tu3與第四下掃開關Tu4被關斷。 Then, in the second sustain stage, the second down-scan signal D2 has an enable level, and the first up-scan signal U1, the second up-scan signal U2, and the first down-scan signal D1 are maintained at the disabled level. Therefore, the second down scan switch Td2 and the fourth down scan switch Td4 are turned on, and the first down scan switch Td1, the third down scan switch Td3, the first up scan switch Tu1, the second up scan switch Tu2, the third up The sweep switch Tu3 and the fourth down sweep switch Tu4 are turned off.

此時,第二防護訊號EVEN會經由第二下掃開關Td2傳遞至索引為奇數的垂直信號線VL,使得索引為奇數的垂直信號線VL具有負極性的電壓。第一防護信號ODD 會經由第四下掃開關Td4傳遞至索引為偶數的垂直信號線VL,使得索引為偶數的垂直信號線VL具有正極性的電壓。因此,垂直信號線VL與對應的畫素電路150之間的漏電流得以減輕。 At this time, the second guard signal EVEN is transmitted to the vertical signal line VL with an odd index through the second down-scan switch Td2, so that the vertical signal line VL with an odd index has a negative voltage. The first guard signal ODD is transmitted to the vertical signal line VL with an even index through the fourth down-scan switch Td4, so that the vertical signal line VL with an even index has a positive voltage. Therefore, the leakage current between the vertical signal line VL and the corresponding pixel circuit 150 is reduced.

由於在第7圖至第9圖的實施例中第一防護信號ODD與第二防護信號EVEN為直流信號,所以控制電路110的設計複雜度得以降低。 Since the first protection signal ODD and the second protection signal EVEN are DC signals in the embodiments of FIGS. 7 to 9, the design complexity of the control circuit 110 is reduced.

前述第2圖至第4圖的實施例的其餘連接方式、元件、實施方式以及優點,皆適用於第7圖至第9圖的實施例,為簡潔起見,在此不重複贅述。 The remaining connection methods, components, embodiments, and advantages of the foregoing embodiments of FIGS. 2 to 4 are applicable to the embodiments of FIGS. 7 to 9. For the sake of brevity, they are not repeated here.

在某一實施例中,移位暫存器710[2]~710[m-1]是自第7圖的下方往上方依序輸出掃描脈衝CP。移位暫存器710[m-1]是第一個輸出掃描脈衝CP,移位暫存器710[2]是最後一個輸出掃描脈衝CP。此時,移位暫存器710[1]會由接收起始信號ST改為接收重置信號RS,並執行相似於第7圖至第9圖的實施例中移位暫存器710[m]的運作。移位暫存器710[m]會由接收重置信號RS改為接收起始信號ST,並執行相似於第7圖至第9圖的實施例中移位暫存器710[1]的運作。 In an embodiment, the shift registers 710[2] to 710[m-1] sequentially output the scan pulse CP from the bottom to the top in FIG. 7. The shift register 710[m-1] is the first output scan pulse CP, and the shift register 710[2] is the last output scan pulse CP. At this time, the shift register 710[1] will change from receiving the start signal ST to receiving the reset signal RS, and perform the shift register 710[m in the embodiment similar to FIGS. 7-9 ] Operation. The shift register 710[m] is changed from receiving the reset signal RS to receiving the start signal ST, and performs operations similar to those of the shift register 710[1] in the embodiment of FIGS. 7-9 .

在此情況下,第一下掃開關Td1、第二下掃開關Td2、第三下掃開關Td3與第四下掃開關Td4會維持於關斷狀態。第一上掃開關Tu1與第三上掃開關Tu3會於第一掃描階段與第二掃描階段被關斷,並於第一維持階段被導通。第二上掃開關Tu2與第四上掃開關Tu4會於第一掃描階段 與第二掃描階段被關斷,並於第二維持階段被導通。前述第7圖至第9圖的實施例的其他連接方式、元件、實施方式以及優點,皆適用於本實施例,為簡潔起見,在此不重複贅述。 In this case, the first down sweep switch Td1, the second down sweep switch Td2, the third down sweep switch Td3, and the fourth down sweep switch Td4 are maintained in the off state. The first up-scan switch Tu1 and the third up-scan switch Tu3 are turned off during the first scan stage and the second scan stage, and turned on during the first sustain stage. The second up-scan switch Tu2 and the fourth up-scan switch Tu4 are turned off in the first scan stage and the second scan stage, and turned on in the second sustain stage. The other connection methods, components, embodiments, and advantages of the foregoing embodiments of FIGS. 7 to 9 are applicable to this embodiment, and for the sake of brevity, they are not repeated here.

第10圖為依據本揭示文件一實施例的移位暫存器710[m]簡化後的功能方塊圖。移位暫存器710[m]包含第一電晶體M1、第二電晶體M2、第三電晶體M3、第四電晶體M4、第五電晶體M5、第六電晶體M6、第七電晶體M7、第八電晶體M8與驅動電路1010。 FIG. 10 is a simplified functional block diagram of the shift register 710 [m] according to an embodiment of the present disclosure. The shift register 710 [m] includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, the eighth transistor M8 and the driving circuit 1010.

第一電晶體M1耦接於第一電源端In1與第一節點N1之間,用於透過第一電源端In1接收第三參考電壓Vref3。第二電晶體M2耦接於第一節點N1與接地端GND之間,其中第一電晶體M1與第二電晶體M2的控制端都耦接於驅動電路1010。第三電晶體M3耦接於第一節點N1與第一輸出端O1之間,且第三電晶體M3的控制端用於接收第一參考電壓Vref1。第四電晶體M4耦接於第一輸出端O1與接地端GND之間,且第四電晶體M4的控制端用於接收第二參考電壓Vref2。 The first transistor M1 is coupled between the first power terminal In1 and the first node N1 for receiving the third reference voltage Vref3 through the first power terminal In1. The second transistor M2 is coupled between the first node N1 and the ground GND. The control terminals of the first transistor M1 and the second transistor M2 are coupled to the driving circuit 1010. The third transistor M3 is coupled between the first node N1 and the first output terminal O1, and the control terminal of the third transistor M3 is used to receive the first reference voltage Vref1. The fourth transistor M4 is coupled between the first output terminal O1 and the ground terminal GND, and the control terminal of the fourth transistor M4 is used to receive the second reference voltage Vref2.

第五電晶體M5耦接於第二電源端In2與第二節點N2之間,用於透過第二電源端In2接收第五參考電壓Vref5。第六電晶體M6耦接於第二節點N2與接地端GND之間,其中第五電晶體M5與第六電晶體M6的控制端都耦接於驅動電路1010。第七電晶體M7耦接於第二節點N2與第二輸出端O2之間,且第七電晶體M7的控制端用於接收第一參考電壓Vref1。第八電晶體M8耦接於第二輸出端O2與接地 端GND之間,且第八電晶體M8的控制端用於接收第二參考電壓Vref2。 The fifth transistor M5 is coupled between the second power terminal In2 and the second node N2 for receiving the fifth reference voltage Vref5 through the second power terminal In2. The sixth transistor M6 is coupled between the second node N2 and the ground GND. The control terminals of the fifth transistor M5 and the sixth transistor M6 are coupled to the driving circuit 1010. The seventh transistor M7 is coupled between the second node N2 and the second output terminal O2, and the control terminal of the seventh transistor M7 is used to receive the first reference voltage Vref1. The eighth transistor M8 is coupled between the second output terminal O2 and the ground terminal GND, and the control terminal of the eighth transistor M8 is used to receive the second reference voltage Vref2.

驅動電路1010用於接收移位暫存器710[m]的前一級移位暫存器(亦即,移位暫存器710[m-1])輸出的掃描脈衝CP,以及接收重置信號RS。第5圖的驅動電路510的其他連接方式、元件、實施方式以及優點,皆適用於驅動電路1010,為簡潔起見,在此不重複贅述。 The driving circuit 1010 is used to receive the scan pulse CP output by the shift register of the previous stage of the shift register 710 [m] (that is, the shift register 710 [m-1]) and receive the reset signal RS. The other connection methods, components, embodiments, and advantages of the driving circuit 510 in FIG. 5 are all applicable to the driving circuit 1010. For the sake of brevity, they are not repeated here.

當移位暫存器710[2]~710[m-1]具有第一掃描順序(例如,由第7圖的上方至下方依序輸出掃描脈衝CP)時,第一參考電壓Vref1會具有高電壓準位且第二參考電壓Vref2會具有低電壓準位。因此,第三電晶體M3與第七電晶體M7會維持於導通狀態,且第四電晶體M4與第八電晶體M8會維持於關斷狀態。 When the shift registers 710[2]~710[m-1] have the first scan order (for example, the scan pulse CP is sequentially output from the top to the bottom of FIG. 7), the first reference voltage Vref1 will have a high The voltage level and the second reference voltage Vref2 will have a low voltage level. Therefore, the third transistor M3 and the seventh transistor M7 are maintained in the on state, and the fourth transistor M4 and the eighth transistor M8 are maintained in the off state.

當移位暫存器710[m-1]輸出掃描脈衝CP時,驅動電路1010會導通第一電晶體M1與第五電晶體M5,且關斷第二電晶體M2與第六電晶體M6,以導通第一電源端In1與第一節點N1,以及導通第二電源端In2與第二節點N2。此時,第三參考電壓Vref3會自第一電源端In1傳遞至第一輸出端O1,並作為具有致能準位的第一下掃信號D1輸出。第五參考電壓Vref5會自第二電源端In2傳遞至第二輸出端O2,並作為具有致能準位的第二下掃信號D2輸出。 When the shift register 710 [m-1] outputs the scan pulse CP, the driving circuit 1010 turns on the first transistor M1 and the fifth transistor M5, and turns off the second transistor M2 and the sixth transistor M6, To turn on the first power terminal In1 and the first node N1, and turn on the second power terminal In2 and the second node N2. At this time, the third reference voltage Vref3 is transmitted from the first power terminal In1 to the first output terminal O1, and is output as the first down-scan signal D1 with the enable level. The fifth reference voltage Vref5 is transmitted from the second power supply terminal In2 to the second output terminal O2, and is output as the second down-scan signal D2 with the enable level.

另一方面,當驅動電路1010接收到重置信號RS的重置脈衝RP時,驅動電路1010會關斷第一電晶體M1與第五電晶體M5,且導通第二電晶體M2與第六電晶體 M6,以導通接地端GND與第一節點N1和第二節點N2。此時,接地電壓便會自接地端GND傳遞至第一輸出端O1和第二輸出端O2,並作為具有禁能準位的第一下掃信號D1與第二下掃信號D2輸出。 On the other hand, when the driving circuit 1010 receives the reset pulse RP of the reset signal RS, the driving circuit 1010 turns off the first transistor M1 and the fifth transistor M5, and turns on the second transistor M2 and the sixth transistor The crystal M6 turns on the ground GND and the first node N1 and the second node N2. At this time, the ground voltage is transferred from the ground terminal GND to the first output terminal O1 and the second output terminal O2, and is output as the first down-scan signal D1 and the second down-scan signal D2 with the disabled level.

第11圖為依據本揭示文件一實施例的移位暫存器710[1]簡化後的功能方塊圖。移位暫存器710[1]與移位暫存器710[m]相似。差異在於,移位暫存器710[1]的第三電晶體M3與第七電晶體M7的控制端用於接收第二參考電壓Vref2,第四電晶體M4與第八電晶體M8的控制端用於接收第一參考電壓Vref1。另外,移位暫存器710[1]的第十驅動電晶體Tr10與第十一驅動電晶體Tr11的控制端分別用於接收起始信號ST與移位暫存器710[2]輸出的掃描脈衝CP。因此,當移位暫存器710[2]~710[m-1]具有前述的第一掃描順序時,移位暫存器710[1]的第三電晶體M3與第七電晶體M7會關斷,而第四電晶體M4與第八電晶體M8會導通,以將第一上掃信號U1與第二上掃信號U2維持於禁能準位。 FIG. 11 is a simplified functional block diagram of the shift register 710 [1] according to an embodiment of the present disclosure. The shift register 710[1] is similar to the shift register 710[m]. The difference is that the control terminals of the third transistor M3 and the seventh transistor M7 of the shift register 710[1] are used to receive the second reference voltage Vref2, and the control terminals of the fourth transistor M4 and the eighth transistor M8 It is used to receive the first reference voltage Vref1. In addition, the control terminals of the tenth driving transistor Tr10 and the eleventh driving transistor Tr11 of the shift register 710[1] are used to receive the start signal ST and the scan output from the shift register 710[2], respectively. Pulse CP. Therefore, when the shift registers 710[2]~710[m-1] have the aforementioned first scanning order, the third transistor M3 and the seventh transistor M7 of the shift register 710[1] will It is turned off, and the fourth transistor M4 and the eighth transistor M8 are turned on to maintain the first up-scan signal U1 and the second up-scan signal U2 at the disabled level.

在一實施例中,移位暫存器710[2]~710[m-1]具有第二掃描順序(例如,由第7圖的下方至上方依序輸出掃描脈衝CP)。此時,第一參考電壓Vref1會具有低電壓準位且第二參考電壓Vref2會具有高電壓準位。因此,移位暫存器210[1]的第三電晶體M3與第七電晶體M7會導通,而第四電晶體M4與第八電晶體M8會關斷,以使移位暫存器210[1]能輸出具有致能準位的第一上掃信號U1與第二上掃 信號U2。另一方面,移位暫存器210[m]的第三電晶體M3與第七電晶體M7會關斷,而第四電晶體M4與第八電晶體M8會導通,以使移位暫存器210[m]輸出的第一下掃信號D1與第二下掃信號D2維持於禁能準位。 In one embodiment, the shift registers 710[2]~710[m-1] have a second scan order (for example, the scan pulse CP is sequentially output from the bottom to the top of FIG. 7). At this time, the first reference voltage Vref1 will have a low voltage level and the second reference voltage Vref2 will have a high voltage level. Therefore, the third transistor M3 and the seventh transistor M7 of the shift register 210[1] will be turned on, and the fourth transistor M4 and the eighth transistor M8 will be turned off, so that the shift register 210 [1] The first up-scan signal U1 and the second up-scan signal U2 with the enable level can be output. On the other hand, the third transistor M3 and the seventh transistor M7 of the shift register 210 [m] will be turned off, and the fourth transistor M4 and the eighth transistor M8 will be turned on to temporarily store the shift The first down-scan signal D1 and the second down-scan signal D2 output by the device 210[m] are maintained at the disabled level.

在一無需雙向掃描的實施例中,可以省略第7圖的移位暫存器710[1],並將移位暫存器710[2]由接收移位暫存器710[1]的掃描脈衝CP改為接收起始信號ST。另外,還可以省略切換電路810的第一上掃開關Tu1、第二上掃開關Tu2、第三上掃開關Tu3與第四上掃開關Tu4。 In an embodiment that does not require bidirectional scanning, the shift register 710[1] of FIG. 7 can be omitted, and the shift register 710[2] can be scanned by the receiving shift register 710[1] The pulse CP receives the start signal ST instead. In addition, the first upsweep switch Tu1, the second upswap switch Tu2, the third upswap switch Tu3, and the fourth upswap switch Tu4 of the switching circuit 810 may also be omitted.

此外,還可以省略第10圖的第三電晶體M3、第四電晶體M4、第七電晶體M7與第八電晶體M8。在此情況下,第一下掃信號D1會改由移位暫存器710[m]的第一節點N1輸出,而第二下掃信號D2會改由移位暫存器710[m]的第二節點N2輸出。 In addition, the third transistor M3, the fourth transistor M4, the seventh transistor M7, and the eighth transistor M8 of FIG. 10 may also be omitted. In this case, the first down-scan signal D1 will be output by the first node N1 of the shift register 710[m], and the second down-scan signal D2 will be changed by the shift register 710[m]. The second node N2 is output.

第12圖為依據本揭示文件又一實施例的閘極驅動器130簡化後的功能方塊圖。在本實施例中,閘極驅動器130包含依序連接的移位暫存器1210[1]~1210[m]。移位暫存器1210[1]~1210[m]相似於第7圖的移位暫存器710[1]~710[m]。差異在於,本實施例的電力輸入PW包含第一參考電壓Vref1、第二參考電壓Vref2與第四參考電壓Vref4,移位暫存器1210[1]與移位暫存器1210[m]以接收第一防護信號ODD取代接收第三參考電壓Vref3,且以接收第二防護信號EVEN取代接收第五參考電壓Vref5。 FIG. 12 is a simplified functional block diagram of the gate driver 130 according to another embodiment of the present disclosure. In this embodiment, the gate driver 130 includes shift registers 1210[1] to 1210[m] connected in sequence. The shift registers 1210[1]~1210[m] are similar to the shift registers 710[1]~710[m] of FIG. The difference is that the power input PW of this embodiment includes a first reference voltage Vref1, a second reference voltage Vref2 and a fourth reference voltage Vref4, a shift register 1210[1] and a shift register 1210[m] to receive The first guard signal ODD replaces receiving the third reference voltage Vref3, and the second guard signal EVEN replaces receiving the fifth reference voltage Vref5.

因此,在本實施例中,第一上掃信號U1、第二 上掃信號U2、第一下掃信號D1與第二下掃信號D2的致能準位,會相同於第一防護信號ODD與第二防護信號EVEN的正極性電壓或負極性電壓。 Therefore, in this embodiment, the enable levels of the first up-scan signal U1, the second up-scan signal U2, the first down-scan signal D1 and the second down-scan signal D2 will be the same as the first guard signal ODD and The positive voltage or negative voltage of the second guard signal EVEN.

第13圖為依據本揭示文件又一實施例的防漏電電路140的電路示意圖。在本實施例中,防漏電電路140包含多個切換電路1310[1]~1310[n]。每個切換電路1310耦接於兩條對應的垂直信號線VL,例如,切換電路1310[1]耦接於垂直信號線VL[1]與垂直信號線VL[2],切換電路1310[2]耦接於垂直信號線VL[3]與垂直信號線VL[4],依此類推,為簡潔起見,在此不重複贅述。為方便理解,以下以切換電路1310[1]為例進行說明。 FIG. 13 is a schematic circuit diagram of a leakage prevention circuit 140 according to another embodiment of the present disclosure. In this embodiment, the leakage prevention circuit 140 includes a plurality of switching circuits 1310[1] to 1310[n]. Each switching circuit 1310 is coupled to two corresponding vertical signal lines VL. For example, the switching circuit 1310[1] is coupled to the vertical signal line VL[1] and the vertical signal line VL[2], and the switching circuit 1310[2] It is coupled to the vertical signal line VL[3] and the vertical signal line VL[4], and so on. For the sake of brevity, they are not repeated here. For ease of understanding, the following uses the switching circuit 1310 [1] as an example.

切換電路1310[1]包含第一下掃開關Td1、第二下掃開關Td2、第一上掃開關Tu1與第二上掃開關Tu2。第一下掃開關Td1的第一端用於接收第一防護信號ODD。第一下掃開關Td1的第二端耦接於縱向驅動線VL[1]。第一下掃開關Td1的控制端用於接收第一下掃信號D1。第二下掃開關Td2的第一端用於接收第二防護信號EVEN。第二下掃開關Td2的第二端耦接於第二縱向驅動線VL[2]。第二下掃開關的控制端用於接收第二下掃信號D2。 The switching circuit 1310 [1] includes a first down-scan switch Td1, a second down-scan switch Td2, a first up-scan switch Tu1, and a second up-scan switch Tu2. The first end of the first down-scan switch Td1 is used to receive the first guard signal ODD. The second end of the first down-scan switch Td1 is coupled to the vertical drive line VL[1]. The control terminal of the first down-scan switch Td1 is used to receive the first down-scan signal D1. The first end of the second down-scan switch Td2 is used to receive the second guard signal EVEN. The second end of the second down-scan switch Td2 is coupled to the second longitudinal drive line VL[2]. The control end of the second down-scan switch is used to receive the second down-scan signal D2.

第一上掃開關Tu1的第一端用於接收第一防護信號ODD。第一上掃開關Tu1的第二端耦接於縱向驅動線VL[1]。第一上掃開關Tu1的控制端用於接收第一上掃信號U1。第二上掃開關Tu2的第一端用於接收第二防護信號EVEN。第二上掃開關Tu2的第二端耦接於縱向驅動線 VL[2]。第二上掃開關Tu2的控制端用於接收第二上掃信號U2。 The first end of the first up-scan switch Tu1 is used to receive the first guard signal ODD. The second end of the first up-sweep switch Tu1 is coupled to the longitudinal drive line VL[1]. The control terminal of the first up-scan switch Tu1 is used to receive the first up-scan signal U1. The first end of the second up-sweep switch Tu2 is used to receive the second guard signal EVEN. The second end of the second up-sweep switch Tu2 is coupled to the longitudinal drive line VL[2]. The control terminal of the second up-scan switch Tu2 is used to receive the second up-scan signal U2.

前述切換電路1310[1]的連接方式、元件、實施方式以及優點,皆適用於切換電路1310[2]~1310[n],為簡潔起見,在此不重複贅述。 The connection methods, components, embodiments, and advantages of the aforementioned switching circuit 1310[1] are all applicable to the switching circuits 1310[2]~1310[n]. For the sake of brevity, they are not repeated here.

第14圖為依據本揭示文件又一實施例的顯示裝置100的運作方式示意圖。以下將以第12圖、第13圖與第14圖來說明顯示裝置100的運作。在第一掃描階段中,第一上掃信號U1、第二上掃信號U2、第一下掃信號D1與第二下掃信號D2具有禁能準位。因此,第一上掃開關Tu1、第二上掃開關Tu2、第一下掃開關Td1與第二下掃開關Td2被關斷。 FIG. 14 is a schematic diagram of the operation mode of the display device 100 according to another embodiment of the present disclosure. The operation of the display device 100 will be described below with reference to FIGS. 12, 13 and 14. In the first scanning stage, the first up-scan signal U1, the second up-scan signal U2, the first down-scan signal D1, and the second down-scan signal D2 have disable levels. Therefore, the first up scan switch Tu1, the second up scan switch Tu2, the first down scan switch Td1, and the second down scan switch Td2 are turned off.

此時,索引為奇數的垂直信號線VL會接收到正極性的電壓,而索引為偶數的垂直信號線VL則會接收到負極性的電壓。 At this time, the vertical signal line VL with an odd index will receive a positive voltage, and the vertical signal line VL with an even index will receive a negative voltage.

在第一維持階段中,第一防護信號ODD具有正極性的電壓(例如,2.5V),第二防護信號EVEN具有負極性的電壓(例如,-2.5V)。第一下掃信號D1會切換至第一致能準位,其中第一致能準位相同於第一防護信號ODD的正極性電壓。第二下掃信號D2會切換至第二致能準位,其中第二致能準位相同於第二防護信號EVEN的負極性電壓。因此,第一下掃開關Td1與第二下掃開關Td2會被導通,而第一上掃開關Tu1與第二上掃開關Tu2會被關斷。 In the first sustain phase, the first protection signal ODD has a positive voltage (eg, 2.5V), and the second protection signal EVEN has a negative voltage (eg, -2.5V). The first down-scan signal D1 will switch to the first enable level, where the first enable level is the same as the positive voltage of the first protection signal ODD. The second down-scan signal D2 will switch to the second enable level, where the second enable level is the same as the negative voltage of the second guard signal EVEN. Therefore, the first down scan switch Td1 and the second down scan switch Td2 are turned on, and the first up scan switch Tu1 and the second up scan switch Tu2 are turned off.

此時,第一防護信號ODD會經由第一下掃開關 Td1傳遞至索引為奇數的垂直信號線VL,使得索引為奇數的垂直信號線VL具有正極性的電壓。第二防護信號EVEN會經由第二下掃開關Td2傳遞至索引為偶數的垂直信號線VL,使得索引為偶數的垂直信號線VL具有負極性的電壓。因此,垂直信號線VL與對應的畫素電路150之間的漏電流得以減輕。 At this time, the first guard signal ODD is transmitted to the vertical signal line VL having an odd index through the first down-scan switch Td1, so that the vertical signal line VL having an odd index has a positive voltage. The second guard signal EVEN is transmitted to the vertical signal line VL with an even index through the second down-scan switch Td2, so that the vertical signal line VL with an even index has a negative voltage. Therefore, the leakage current between the vertical signal line VL and the corresponding pixel circuit 150 is reduced.

在第二掃描階段中,第一上掃信號U1、第二上掃信號U2、第一下掃信號D1與第二下掃信號D2具有禁能準位。因此,第一上掃開關Tu1、第二上掃開關Tu2、第一下掃開關Td1與第二下掃開關Td2會再度被關斷。 In the second scanning stage, the first up-scan signal U1, the second up-scan signal U2, the first down-scan signal D1, and the second down-scan signal D2 have disabled levels. Therefore, the first up-sweep switch Tu1, the second up-sweep switch Tu2, the first down-sweep switch Td1 and the second down-sweep switch Td2 will be turned off again.

此時,索引為奇數的垂直信號線VL會接收到負極性的電壓,而索引為偶數的垂直信號線VL則會接收到正極性的電壓。 At this time, the vertical signal line VL with an odd index will receive a negative voltage, and the vertical signal line VL with an even index will receive a positive voltage.

在第二維持階段中,第一防護信號ODD具有負極性的電壓,第二防護信號EVEN具有正極性的電壓。第一下掃信號D1會切換至第二致能準位,其中第致二能準位相同於第一防護信號ODD的負極性電壓。第二下掃信號D2會切換至第一致能準位,其中第一致能準位相同於第二防護信號EVEN的正極性電壓。因此,第一下掃開關Td1與第二下掃開關Td2會被導通,而第一上掃開關Tu1與第二上掃開關Tu2會被關斷。 In the second sustain phase, the first guard signal ODD has a negative voltage, and the second guard signal EVEN has a positive voltage. The first down-scan signal D1 will switch to the second enable level, where the second enable level is the same as the negative voltage of the first protection signal ODD. The second down-scan signal D2 is switched to the first enable level, where the first enable level is the same as the positive voltage of the second guard signal EVEN. Therefore, the first down scan switch Td1 and the second down scan switch Td2 are turned on, and the first up scan switch Tu1 and the second up scan switch Tu2 are turned off.

此時,第一防護信號ODD會經由第一下掃開關Td1傳遞至索引為奇數的垂直信號線VL,使得索引為奇數的垂直信號線VL具有負極性的電壓。第二防護信號EVEN 會經由第二下掃開關Td2傳遞至索引為偶數的垂直信號線VL,使得索引為偶數的垂直信號線VL具有正極性的電壓。因此,垂直信號線VL與對應的畫素電路150之間的漏電流得以減輕。 At this time, the first guard signal ODD is transmitted to the vertical signal line VL having an odd index through the first down-scan switch Td1, so that the vertical signal line VL having an odd index has a negative voltage. The second guard signal EVEN is transmitted to the vertical signal line VL with an even index through the second down-scan switch Td2, so that the vertical signal line VL with an even index has a positive voltage. Therefore, the leakage current between the vertical signal line VL and the corresponding pixel circuit 150 is reduced.

第15圖為依據本揭示文件一實施例的移位暫存器1210[m]簡化後的功能方塊圖。移位暫存器1210[m]似於第10圖的移位暫存器710[m],差異在於,移位暫存器1210[m]的第一電晶體M1的第一端與第五電晶體M5的第一端分別用於接收第一防護信號ODD與第二防護信號EVEN。 FIG. 15 is a simplified functional block diagram of the shift register 1210 [m] according to an embodiment of the present disclosure. The shift register 1210 [m] is similar to the shift register 710 [m] of FIG. 10, the difference is that the first end of the first transistor M1 of the shift register 1210 [m] and the fifth The first ends of the transistor M5 are used to receive the first guard signal ODD and the second guard signal EVEN, respectively.

當移位暫存器1210[1]~1210[m]具有第一掃描順序(例如,由第12圖的上方往下方輸出掃描脈衝CP)時,第一參考電壓Vref1具有高電壓準位,而第二參考電壓Vref2具有低電壓準位。因此,第一防護信號ODD會做為具有第一致能準位或第二致能準位的第一下掃信號D1輸出,而第二防護信號EVEN會作為具有第一致能準位或第二致能準位的第二下掃信號D2輸出。 When the shift registers 1210[1]~1210[m] have the first scanning order (for example, the scanning pulse CP is output from the top to the bottom of FIG. 12), the first reference voltage Vref1 has a high voltage level, and The second reference voltage Vref2 has a low voltage level. Therefore, the first guard signal ODD will be output as the first down-scan signal D1 with the first enable level or the second enable level, and the second guard signal EVEN will be used as the first enable level or the second enable level. The second down-scan signal D2 of the two enable level is output.

由上述可知,在第一維持階段與第二維持階段中,第一防護信號ODD與第二防護信號EVEN的波形彼此相反,第一下掃信號D1與第一防護信號ODD的電壓準位相同,第二下掃信號D2與第二防護信號EVEN的電壓準位相同。前述移位暫存器710[m]的其餘連接方式、元件、實施方式以及優點,皆適用於移位暫存器1210[m],為簡潔起見,在此不重複贅述。 As can be seen from the above, in the first sustain stage and the second sustain stage, the waveforms of the first guard signal ODD and the second guard signal EVEN are opposite to each other, and the voltage levels of the first down-scan signal D1 and the first guard signal ODD are the same. The voltage level of the second down-scan signal D2 and the second guard signal EVEN are the same. The remaining connection methods, components, implementations, and advantages of the aforementioned shift register 710 [m] are all applicable to the shift register 1210 [m]. For brevity, they are not repeated here.

第16圖為依據本揭示文件一實施例的移位暫存器1210[1]簡化後的功能方塊圖。移位暫存器1210[1]相似於第11圖的移位暫存器710[1],差異在於,移位暫存器1210[1]的第一電晶體M15的第一端與第五電晶體M5的第一端分別用於接收第一防護信號ODD與第二防護信號EVEN。前述移位暫存器710[1]的其餘連接方式、元件、實施方式以及優點,皆適用於移位暫存器1210[1],為簡潔起見,在此不重複贅述。 FIG. 16 is a simplified functional block diagram of the shift register 1210 [1] according to an embodiment of the present disclosure. The shift register 1210[1] is similar to the shift register 710[1] of FIG. 11 except that the first end of the first transistor M15 of the shift register 1210[1] and the fifth The first ends of the transistor M5 are used to receive the first guard signal ODD and the second guard signal EVEN, respectively. The remaining connection methods, components, implementations, and advantages of the aforementioned shift register 710[1] are all applicable to the shift register 1210[1]. For brevity, they are not repeated here.

在一實施例中,移位暫存器1210[1]~1210[m]具有第二掃描順序(例如,由第12圖的下方往上方輸出掃描脈衝CP),且第一參考電壓Vref1具有低電壓準位,而第二參考電壓Vref2具有高電壓準位。因此,第一防護信號ODD會做為具有第一致能準位或第二致能準位的第一上拉信號U1被輸出,第二防護信號EVEN會作為具有第一致能準位或第二致能準位的第二上拉信號U2被輸出。此時,於第一維持階段與第二維持階段中,第一上拉開關Tu1與第二上拉開關Tu2會被導通,而第一下拉開關Td1與第二下拉開關Td2會被關斷。 In one embodiment, the shift registers 1210[1]~1210[m] have a second scan order (for example, the scan pulse CP is output from the bottom to the top in FIG. 12), and the first reference voltage Vref1 has a low The voltage level, and the second reference voltage Vref2 has a high voltage level. Therefore, the first guard signal ODD will be output as the first pull-up signal U1 having the first enable level or the second enable level, and the second guard signal EVEN will be used as the first enable level or the second enable level. The second pull-up signal U2 of the two enable level is output. At this time, in the first sustain stage and the second sustain stage, the first pull-up switch Tu1 and the second pull-up switch Tu2 are turned on, and the first pull-down switch Td1 and the second pull-down switch Td2 are turned off.

在此情況下,在第一維持階段與第二維持階段中,第一防護信號ODD與第二防護信號EVEN的波形彼此相反,第一上掃信號U1與第一防護信號ODD的電壓準位相同,第二上掃信號U2與第二防護信號EVEN的電壓準位相同。 In this case, in the first sustain stage and the second sustain stage, the waveforms of the first guard signal ODD and the second guard signal EVEN are opposite to each other, and the voltage levels of the first up-scan signal U1 and the first guard signal ODD are the same The voltage level of the second up-scan signal U2 and the second guard signal EVEN are the same.

由上述可知,由於使用第一防護信號ODD與第 二防護信號EVEN取代第三參考電壓Vref3與第五參考電壓Vref5,第12圖的閘極驅動器130具有走線簡單的優點。 As can be seen from the above, since the first guard signal ODD and the second guard signal EVEN are used instead of the third reference voltage Vref3 and the fifth reference voltage Vref5, the gate driver 130 of FIG. 12 has the advantage of simple wiring.

在一實施例中,為了抵銷第一下拉開關Td1、第二下拉開關Td2、第一上拉開關Tu1與第二上拉開關Tu2的臨界電壓的影響,第一防護信號ODD與第二防護信號EVEN被設置為原本的電壓準位再加上前述的臨界電壓。 In an embodiment, in order to offset the influence of the threshold voltages of the first pull-down switch Td1, the second pull-down switch Td2, the first pull-up switch Tu1 and the second pull-up switch Tu2, the first protection signal ODD and the second protection The signal EVEN is set to the original voltage level plus the aforementioned threshold voltage.

例如,第一防護信號ODD與第二防護信號EVEN的正極性電壓被設置為2.5V+Vth,負極性電壓被設置為-2.5V+Vth,其中Vth表示第一下拉開關Td1、第二下拉開關Td2、第一上拉開關Tu1或第二上拉開關Tu2的臨界電壓。 For example, the positive polarity voltage of the first protection signal ODD and the second protection signal EVEN is set to 2.5V+Vth, and the negative polarity voltage is set to -2.5V+Vth, where Vth represents the first pull-down switch Td1, the second pull-down The threshold voltage of the switch Td2, the first pull-up switch Tu1, or the second pull-up switch Tu2.

在一無需雙向掃描的實施例中,可以省略第12圖的移位暫存器1210[1],並將移位暫存器1210[2]由接收移位暫存器1210[1]的掃描脈衝CP改為接收起始信號ST。另外,還可以省略切換電路1310的第一上掃開關Tu1與第二上掃開關Tu2。 In an embodiment that does not require bidirectional scanning, the shift register 1210[1] of FIG. 12 may be omitted, and the shift register 1210[2] may be scanned by the receive shift register 1210[1]. The pulse CP receives the start signal ST instead. In addition, the first up-scan switch Tu1 and the second up-scan switch Tu2 of the switching circuit 1310 may also be omitted.

此外,還可以省略第15圖的第三電晶體M3、第四電晶體M4、第七電晶體M7與第八電晶體M8。在此情況下,第一下掃信號D1會改由移位暫存器1210[m]的第一節點N1輸出,而第二下掃信號D2會改由移位暫存器1210[m]的第二節點N2輸出。 In addition, the third transistor M3, the fourth transistor M4, the seventh transistor M7, and the eighth transistor M8 of FIG. 15 may also be omitted. In this case, the first down-scan signal D1 will be output by the first node N1 of the shift register 1210[m], and the second down-scan signal D2 will be changed by the shift register 1210[m]. The second node N2 is output.

第17圖為依據本揭示文件再一實施例的閘極驅動器130簡化後的功能方塊圖。閘極驅動器130包含多級依序連接的移位暫存器1710[1]~1710[m]。移位暫存器 1710[1]~1710[m]用於接收時脈信號CK、反向時脈信號XCK。移位暫存器1710[1]與移位暫存器1710[m]還用於接收電力輸入PW,在本實施例中,電力輸入PW包含第一參考電壓Vref1、第二參考電壓Vref2、第三參考電壓Vref3與第四參考電壓Vref4。 FIG. 17 is a simplified functional block diagram of the gate driver 130 according to another embodiment of the present disclosure. The gate driver 130 includes multiple levels of shift registers 1710[1] to 1710[m] connected in sequence. The shift registers 1710[1]~1710[m] are used to receive the clock signal CK and the reverse clock signal XCK. The shift register 1710[1] and the shift register 1710[m] are also used to receive the power input PW. In this embodiment, the power input PW includes the first reference voltage Vref1, the second reference voltage Vref2, the first The three reference voltage Vref3 and the fourth reference voltage Vref4.

另外,移位暫存器1710[1]用於接收起始信號ST,並用於輸出第一控制信號群組CTL1。移位暫存器1710[m]用於接收重置信號RS,並用於輸出第二控制信號群組CTL2。在本實施例中,第一控制信號群組CTL1包含第一上掃信號U1、第二上掃信號U2與第三上掃信號U3,第二控制信號群組CTL2包含第一下掃信號D1、第二下掃信號D2與第三下掃信號D3。移位暫存器1710[2]~1720[m-1]則用於對應輸出多個掃描信號Gn[1]~Gn[y]至水平驅動線HL[1]~HL[y]。 In addition, the shift register 1710[1] is used to receive the start signal ST and to output the first control signal group CTL1. The shift register 1710 [m] is used to receive the reset signal RS and used to output the second control signal group CTL2. In this embodiment, the first control signal group CTL1 includes a first up-scan signal U1, a second up-scan signal U2 and a third up-scan signal U3, and the second control signal group CTL2 includes a first down-scan signal D1. The second down-scan signal D2 and the third down-scan signal D3. The shift registers 1710[2]~1720[m-1] are used to correspondingly output a plurality of scan signals Gn[1]~Gn[y] to the horizontal driving lines HL[1]~HL[y].

第18圖為依據本揭示文件再一實施例的防漏電電路140的電路示意圖。防漏電電路140包含多個切換電路1810[1]~1810[n]。每個切換電路1810耦接於兩條對應的垂直信號線VL,例如,切換電路1810[1]耦接於垂直信號線VL[1]與垂直信號線VL[2],切換電路1810[2]耦接於垂直信號線VL[3]與垂直信號線VL[4],依此類推,為簡潔起見,在此不重複贅述。 FIG. 18 is a schematic circuit diagram of a leakage prevention circuit 140 according to yet another embodiment of the present disclosure. The leakage prevention circuit 140 includes a plurality of switching circuits 1810[1] to 1810[n]. Each switching circuit 1810 is coupled to two corresponding vertical signal lines VL, for example, the switching circuit 1810[1] is coupled to the vertical signal line VL[1] and the vertical signal line VL[2], and the switching circuit 1810[2] It is coupled to the vertical signal line VL[3] and the vertical signal line VL[4], and so on. For the sake of brevity, they are not repeated here.

在本實施例中,為了減輕信號線上的負載,相鄰的切換電路1810是由不同的信號線控制,且信號線的分佈是以三個切換電路1810為一循環。例如,切換電路 1810[1]是由第一上掃信號U1與第一下掃信號D1控制,切換電路1810[2]是由第二上掃信號U2與第二下掃信號D2控制,切換電路1810[3]是由第三上掃信號U3與第三下掃信號D3控制,而切換電路1810[4]又再度由第一上掃信號U1與第一下掃信號D1控制,以此類推。為方便理解,以下以切換電路1810[1]、切換電路1810[2]與切換電路1810[3]為例進行說明。 In this embodiment, in order to reduce the load on the signal lines, adjacent switching circuits 1810 are controlled by different signal lines, and the distribution of the signal lines is a cycle of three switching circuits 1810. For example, the switching circuit 1810[1] is controlled by the first up-scan signal U1 and the first down-scan signal D1, the switching circuit 1810[2] is controlled by the second up-scan signal U2 and the second down-scan signal D2, and the switching circuit 1810[3] is controlled by the third up-scan signal U3 and the third down-scan signal D3, and the switching circuit 1810[4] is again controlled by the first up-scan signal U1 and the first down-scan signal D1, and so on. For ease of understanding, the following uses the switching circuit 1810 [1], the switching circuit 1810 [2], and the switching circuit 1810 [3] as examples.

針對切換電路1810[1]而言,切換電路1810[1]包含第一下掃開關Td1、第二下掃開關Td2、第一上掃開關Tu1與第二上掃開關Tu2。第一下掃開關Td1的第一端用於接收第一防護信號ODD。第一下掃開關Td1的第二端耦接於第一縱向驅動線VL[1]。第一下掃開關Td1的控制端用於接收第一下掃信號D1。第二下掃開關Td2的第一端用於接收第二防護信號EVEN。第二下掃開關Td2的第二端耦接於第二縱向驅動線VL[2]。第二下掃開關Td2的控制端用於接收第一下掃信號D1。第一上掃開關Tu1的第一端用於接收第一防護信號ODD。第一上掃開關Tu1的第二端耦接於第一縱向驅動線VL[1]。第一上掃開關Tu1的控制端用於接收第一上掃信號U1。第二上掃開關Tu2的第一端用於接收第二防護信號EVEN。第二上掃開關Tu2的第二端耦接於第二縱向驅動線VL[2]。第二上掃開關Tu2的控制端用於接收第一上掃信號U1。 With respect to the switching circuit 1810[1], the switching circuit 1810[1] includes a first down-scan switch Td1, a second down-scan switch Td2, a first up-scan switch Tu1, and a second up-scan switch Tu2. The first end of the first down-scan switch Td1 is used to receive the first guard signal ODD. The second end of the first down-scan switch Td1 is coupled to the first vertical drive line VL[1]. The control terminal of the first down-scan switch Td1 is used to receive the first down-scan signal D1. The first end of the second down-scan switch Td2 is used to receive the second guard signal EVEN. The second end of the second down-scan switch Td2 is coupled to the second longitudinal drive line VL[2]. The control terminal of the second down-scan switch Td2 is used to receive the first down-scan signal D1. The first end of the first up-scan switch Tu1 is used to receive the first guard signal ODD. The second end of the first up-scan switch Tu1 is coupled to the first longitudinal drive line VL[1]. The control terminal of the first up-scan switch Tu1 is used to receive the first up-scan signal U1. The first end of the second up-sweep switch Tu2 is used to receive the second guard signal EVEN. The second end of the second up-scan switch Tu2 is coupled to the second longitudinal drive line VL[2]. The control terminal of the second up-scan switch Tu2 is used to receive the first up-scan signal U1.

如第18圖所示,於切換電路1810[2]和切換電路1810[3]中,第一下掃開關Td1、第二下掃開關Td2、第 一上掃開關Tu1與第二上掃開關Tu2的連接方式相似於切換電路1810[1]。差異在於,針對切換電路1810[2]而言,第一下掃開關Td1與第二下掃開關Td2是由第二下掃信號D2控制,且分別耦接於縱向驅動線VL[3]與縱向驅動線VL[4],第一上掃開關Tu1與第二上掃開關Tu2是由第二上掃信號U2控制,且分別耦接於縱向驅動線VL[3]與縱向驅動線VL[4]。 As shown in FIG. 18, in the switching circuit 1810[2] and the switching circuit 1810[3], the first down sweep switch Td1, the second down sweep switch Td2, the first up sweep switch Tu1, and the second up sweep switch Tu2 The connection method is similar to the switching circuit 1810 [1]. The difference is that for the switching circuit 1810[2], the first down-scan switch Td1 and the second down-scan switch Td2 are controlled by the second down-scan signal D2, and are respectively coupled to the vertical drive line VL[3] and the vertical Drive line VL[4], the first up-scan switch Tu1 and the second up-scan switch Tu2 are controlled by the second up-scan signal U2, and are respectively coupled to the vertical drive line VL[3] and the vertical drive line VL[4] .

另一項差異在於,針對切換電路1810[3]而言,第一下掃開關Td1與第二下掃開關Td2是由第三下掃信號D3控制,且分別耦接於縱向驅動線VL[5]與縱向驅動線VL[6],第一上掃開關Tu1與第二上掃開關Tu2是由第三上掃信號U3控制,且分別耦接於縱向驅動線VL[5]與縱向驅動線VL[6]。 Another difference is that for the switching circuit 1810[3], the first down-scan switch Td1 and the second down-scan switch Td2 are controlled by the third down-scan signal D3, and are respectively coupled to the vertical drive lines VL[5 ] And the vertical drive line VL[6], the first up-scan switch Tu1 and the second up-scan switch Tu2 are controlled by the third up-scan signal U3, and are respectively coupled to the vertical drive line VL[5] and the vertical drive line VL [6].

前述以切換電路1810[1]、切換電路1810[2]與切換電路1810[3]為一循環的連接方式,亦適用於切換電路1810[4]~1810[n],為簡潔起見,在此不重複贅述。 The aforementioned connection method of switching circuit 1810[1], switching circuit 1810[2] and switching circuit 1810[3] is also applicable to switching circuit 1810[4]~1810[n]. This is not repeated here.

第19圖為依據本揭示文件再一實施例的顯示裝置100的運作方式示意圖。以下將以第17圖、第18圖與第19圖來說明顯示裝置100的運作。於第一掃描階段中,第一上掃信號U1、第二上掃信號2、第三上掃信號U3、第一下掃信號D1、第二下掃信號D2與第三下掃信號D3具有禁能準位。多工信號群組Mu具有致能準位。當移位暫存器1710[1]接收到觸發信號ST提供的起始脈衝SP時,移位暫存器1710[2]~1710[m-1]會依序輸出掃描脈衝CP。 FIG. 19 is a schematic diagram of the operation of the display device 100 according to another embodiment of the present disclosure. The operation of the display device 100 will be described below with reference to FIGS. 17, 18 and 19. In the first scanning stage, the first up-scan signal U1, the second up-scan signal 2, the third up-scan signal U3, the first down-scan signal D1, the second down-scan signal D2 and the third down-scan signal D3 have Can level. The multiplex signal group Mu has an enabling level. When the shift register 1710[1] receives the start pulse SP provided by the trigger signal ST, the shift register 1710[2]~1710[m-1] will sequentially output the scan pulse CP.

因此,第一下掃開關Td1、第二下掃開關Td2、第一上掃開關Tu1與第二上掃開關Tu2會被關斷。此時,索引為奇數的垂直信號線VL會接收到正極性的電壓,索引為偶數的垂直信號線VL則會接收到負極性的電壓。 Therefore, the first down scan switch Td1, the second down scan switch Td2, the first up scan switch Tu1, and the second up scan switch Tu2 are turned off. At this time, the vertical signal line VL with an odd index will receive a positive voltage, and the vertical signal line VL with an even index will receive a negative voltage.

於第一維持階段中,第一上掃信號U1、第二上掃信號U2與第三上掃信號U3具有禁能準位,第一下掃信號D1、第二下掃信號D2與第三下掃信號D3則切換至致能準位。多工信號群組Mu具有禁能準位。第一防護信號ODD具有正極性的電壓,而第二防護信號EVEN具有負極性的電壓。 In the first maintenance phase, the first up-scan signal U1, the second up-scan signal U2 and the third up-scan signal U3 have disabled levels, the first down-scan signal D1, the second down-scan signal D2 and the third down The scanning signal D3 is switched to the enable level. The multiplex signal group Mu has a disabled level. The first guard signal ODD has a positive voltage, and the second guard signal EVEN has a negative voltage.

因此,第一下掃開關Td1與第二下掃開關Td2會被導通,而第一上掃開關Tu1與第二上掃開關Tu2會維持於關斷狀態。此時,第一防護信號ODD會經由第一下掃開關Td1傳遞至索引為奇數的垂直信號線VL,使得索引為奇數的垂直信號線VL具有正極性的電壓。第二防護信號EVEN會經由第二下掃開關Td2傳遞至索引為偶數的垂直信號線VL,使得索引為偶數的垂直信號線VL具有負極性的電壓。因此,垂直信號線VL與對應的畫素電路150之間的漏電流得以減輕。 Therefore, the first down scan switch Td1 and the second down scan switch Td2 are turned on, and the first up scan switch Tu1 and the second up scan switch Tu2 are maintained in the off state. At this time, the first guard signal ODD is transmitted to the vertical signal line VL with an odd index through the first down-scan switch Td1, so that the vertical signal line VL with an odd index has a positive voltage. The second guard signal EVEN is transmitted to the vertical signal line VL with an even index through the second down-scan switch Td2, so that the vertical signal line VL with an even index has a negative voltage. Therefore, the leakage current between the vertical signal line VL and the corresponding pixel circuit 150 is reduced.

於第二掃描階段中,第一上掃信號U1、第二上掃信號2、第三上掃信號U3、第一下掃信號D1、第二下掃信號D2與第三下掃信號D3具有禁能準位。多工信號群組Mu具有致能準位。當移位暫存器1710[1]再度接收到觸發信號ST提供的起始脈衝SP時,移位暫存器 1710[2]~1710[m-1]會再度依序輸出掃描脈衝CP。 In the second scanning stage, the first up-scan signal U1, the second up-scan signal 2, the third up-scan signal U3, the first down-scan signal D1, the second down-scan signal D2 and the third down-scan signal D3 have Can level. The multiplex signal group Mu has an enabling level. When the shift register 1710[1] receives the start pulse SP provided by the trigger signal ST again, the shift register 1710[2]~1710[m-1] will sequentially output the scan pulse CP again.

因此,第一下掃開關Td1、第二下掃開關Td2、第一上掃開關Tu1與第二上掃開關Tu2會再度被關斷。此時,索引為奇數的垂直信號線VL會接收到負極性的電壓,索引為偶數的垂直信號線VL則會接收到正極性的電壓。 Therefore, the first down scan switch Td1, the second down scan switch Td2, the first up scan switch Tu1, and the second up scan switch Tu2 are turned off again. At this time, the vertical signal line VL with an odd index will receive a negative voltage, and the vertical signal line VL with an even index will receive a positive voltage.

於第二維持階段中,第一上掃信號U1、第二上掃信號2與第三上掃信號U3具有禁能準位,第一下掃信號D1、第二下掃信號D2與第三下掃信號D3則切換至致能準位。多工信號群組Mu具有禁能準位。第一防護信號ODD具有負極性的電壓,而第二防護信號EVEN具有正極性的電壓。 In the second maintenance phase, the first up-scan signal U1, the second up-scan signal 2 and the third up-scan signal U3 have disabled levels, the first down-scan signal D1, the second down-scan signal D2 and the third down The scanning signal D3 is switched to the enable level. The multiplex signal group Mu has a disabled level. The first guard signal ODD has a negative voltage, and the second guard signal EVEN has a positive voltage.

因此,第一下掃開關Td1與第二下掃開關Td2會被導通,而第一上掃開關Tu1與第二上掃開關Tu2會維持於關斷狀態。此時,第一防護信號ODD會經由第一下掃開關Td1傳遞至索引為奇數的垂直信號線VL,使得索引為奇數的垂直信號線VL具有負極性的電壓。第二防護信號EVEN會經由第二下掃開關Td2傳遞至索引為偶數的垂直信號線VL,使得索引為偶數的垂直信號線VL具有正極性的電壓。因此,垂直信號線VL與對應的畫素電路150之間的漏電流得以減輕。 Therefore, the first down scan switch Td1 and the second down scan switch Td2 are turned on, and the first up scan switch Tu1 and the second up scan switch Tu2 are maintained in the off state. At this time, the first guard signal ODD is transmitted to the vertical signal line VL having an odd index through the first down-scan switch Td1, so that the vertical signal line VL having an odd index has a negative voltage. The second guard signal EVEN is transmitted to the vertical signal line VL with an even index through the second down-scan switch Td2, so that the vertical signal line VL with an even index has a positive voltage. Therefore, the leakage current between the vertical signal line VL and the corresponding pixel circuit 150 is reduced.

第20圖為依據本揭示文件一實施例的移位暫存器1710[m]簡化後的功能方塊圖。移位暫存器1710[m]包含第一電晶體M1、第二電晶體M2、第三電晶體M3、第四電晶體M4、第五電晶體M5、第六電晶體M6、第七電晶 體M7、第八電晶體M8與驅動電路2010。驅動電路2010用於接收移位暫存器1710[m]的前一級移位暫存器(亦即,移位暫存器1710[m-1])輸出的掃描脈衝CP,以及接收重置信號RS、第一參考電壓Vref1、第二參考電壓Vref2、第三參考電壓Vref3與第四參考電壓Vref4。 FIG. 20 is a simplified functional block diagram of the shift register 1710 [m] according to an embodiment of the present disclosure. The shift register 1710 [m] includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, the eighth transistor M8 and the drive circuit 2010. The driving circuit 2010 is used to receive the scan pulse CP output by the shift register of the previous stage of the shift register 1710 [m] (that is, the shift register 1710 [m-1]), and receive the reset signal RS, first reference voltage Vref1, second reference voltage Vref2, third reference voltage Vref3 and fourth reference voltage Vref4.

前述驅動電路510的其餘連接方式、元件、實施方式以及優點,皆適用於驅動電路2010,為簡潔起見,在此不重複贅述。 The remaining connection methods, components, embodiments, and advantages of the foregoing driving circuit 510 are all applicable to the driving circuit 2010. For the sake of brevity, they are not repeated here.

第一電晶體M1耦接於第一電源端In1與第一節點N1之間,其中第一電晶體M1透過第一電源端In1接收第三參考電壓Vref3。第二電晶體M2耦接於該第一節點N1與接地端GND之間,其中第一電晶體M1與第二電晶體M2的控制端皆耦接於驅動電路2010。第三電晶體M3耦接於第一節點N1與第一輸出端O1之間。第四電晶體M4耦接於第一節點N1與第二輸出端O2之間。第五電晶體M5耦接於第一節點N1與第三輸出端O3之間,其中第三電晶體M3、第四電晶體M4與第五電晶體M5的控制端皆用於接收第一參考電壓Vref1。 The first transistor M1 is coupled between the first power terminal In1 and the first node N1, wherein the first transistor M1 receives the third reference voltage Vref3 through the first power terminal In1. The second transistor M2 is coupled between the first node N1 and the ground GND. The control terminals of the first transistor M1 and the second transistor M2 are coupled to the driving circuit 2010. The third transistor M3 is coupled between the first node N1 and the first output terminal O1. The fourth transistor M4 is coupled between the first node N1 and the second output terminal O2. The fifth transistor M5 is coupled between the first node N1 and the third output terminal O3, wherein the control terminals of the third transistor M3, the fourth transistor M4, and the fifth transistor M5 are used to receive the first reference voltage Vref1.

第六電晶體M6耦接於第一輸出端O1與接地端GND之間。第七電晶體M7耦接於第二輸出端O2與接地端GND之間。第八電晶體M8耦接於第三輸出端O3與接地端GND之間,其中第六電晶體M6、第七電晶體M7與第八電晶體M8的控制端皆用於接收第二參考電壓Vref2。 The sixth transistor M6 is coupled between the first output terminal O1 and the ground terminal GND. The seventh transistor M7 is coupled between the second output terminal O2 and the ground terminal GND. The eighth transistor M8 is coupled between the third output terminal O3 and the ground terminal GND, wherein the control terminals of the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are used to receive the second reference voltage Vref2 .

當移位暫存器1710[2]~210[m-1]具有第一掃 描順序(例如,由第17圖的上方至下方依序輸出掃描脈衝CP)時,第一參考電壓Vref1會具有高電壓準位且第二參考電壓Vref2會具有低電壓準位。因此,第三電晶體M3、第四電晶體M4與第五電晶體M5會維持於導通狀態,第六電晶體M6、第七電晶體M7與第八電晶體M8會維持於關斷狀態。 When the shift registers 1710[2]~210[m-1] have the first scanning order (for example, the scanning pulse CP is sequentially output from the top to the bottom of FIG. 17), the first reference voltage Vref1 will have a high The voltage level and the second reference voltage Vref2 will have a low voltage level. Therefore, the third transistor M3, the fourth transistor M4, and the fifth transistor M5 are maintained in the on state, and the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are maintained in the off state.

當移位暫存器1710[m-1]輸出掃描脈衝CP時,驅動電路2010會導通第一電晶體M1並關斷第二電晶體M2,以導通第一電源端In1與第一節點N1。此時,第三參考電壓Vref3便會自第一電源端In1傳遞至第一輸出端O1、第二輸出端O2與第三輸出端O3,並作為具有致能準位的第一下掃信號D1、第二下掃信號D2與第三下掃信號D3輸出。 When the shift register 1710 [m-1] outputs the scan pulse CP, the driving circuit 2010 turns on the first transistor M1 and turns off the second transistor M2 to turn on the first power terminal In1 and the first node N1. At this time, the third reference voltage Vref3 is transferred from the first power supply terminal In1 to the first output terminal O1, the second output terminal O2, and the third output terminal O3, and serves as the first down-scan signal D1 with the enable level 2. The second down-scan signal D2 and the third down-scan signal D3 are output.

另一方面,當驅動電路2010接收到重置脈衝RP時,驅動電路2010會關斷第一電晶體M1並導通第二電晶體M2,以導通第一節點N1與接地端GND。此時,接地電壓便會自接地端GND傳遞至第一輸出端O1、第二輸出端O2與第三輸出端O3,並作為具有禁能準位的第一下掃信號D1、第二下掃信號D2與第三下掃信號D3輸出。 On the other hand, when the driving circuit 2010 receives the reset pulse RP, the driving circuit 2010 turns off the first transistor M1 and turns on the second transistor M2 to turn on the first node N1 and the ground GND. At this time, the ground voltage will be transmitted from the ground terminal GND to the first output terminal O1, the second output terminal O2 and the third output terminal O3, and serve as the first down-scan signal D1 with the disabled level and the second down-scan The signal D2 and the third down-scan signal D3 are output.

第21圖為依據本揭示文件一實施例的第一級移位暫存器1710[1]簡化後的功能方塊圖。移位暫存器1710[1]與移位暫存器1710[m]相似。差異在於,移位暫存器1710[1]的第三電晶體M3、第四電晶體M4與第五電晶體M5的控制端用於接收第二參考電壓Vref2,且第六電晶體M6、第七電晶體M7與第八電晶體M8的控制端用於接收第 一參考電壓Vref1。另外,移位暫存器1710[1]的第十四電晶體M14與第十五電晶體M15的控制端分別用於接收起始信號ST與移位暫存器1710[2]輸出的掃描脈衝CP。 FIG. 21 is a simplified functional block diagram of the first-stage shift register 1710 [1] according to an embodiment of the present disclosure. The shift register 1710[1] is similar to the shift register 1710[m]. The difference is that the control terminals of the third transistor M3, the fourth transistor M4, and the fifth transistor M5 of the shift register 1710[1] are used to receive the second reference voltage Vref2, and the sixth transistor M6, the first The control terminals of the seventh transistor M7 and the eighth transistor M8 are used to receive the first reference voltage Vref1. In addition, the control terminals of the fourteenth transistor M14 and the fifteenth transistor M15 of the shift register 1710[1] are used to receive the start signal ST and the scan pulse output by the shift register 1710[2], respectively. CP.

因此,當移位暫存器1710[2]~1710[m-1]具有前述的第一掃描順序時,移位暫存器1710[1]的第三電晶體M3、第四電晶體M4與第五電晶體M5會被關斷,而第六電晶體M6、第七電晶體M7與第八電晶體M8會被導通,以將第一上掃信號U1、第二上掃信號U2與第三上掃信號U3維持於禁能準位。 Therefore, when the shift registers 1710[2]~1710[m-1] have the aforementioned first scanning order, the third transistor M3, the fourth transistor M4 of the shift register 1710[1] and The fifth transistor M5 will be turned off, and the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 will be turned on to convert the first up-scan signal U1, the second up-scan signal U2 and the third The up-scan signal U3 is maintained at the disabled level.

在一實施例中,移位暫存器1710[2]~1710[m-1]具有第二掃描順序(例如,由第17圖的下方至上方依序輸出掃描脈衝CP)。此時,第一參考電壓Vref1會具有低電壓準位,且第二參考電壓Vref2會具有高電壓準位。因此,移位暫存器1710[1]的第三電晶體M3、第四電晶體M4與第五電晶體M5會被導通,而第六電晶體M6、第七電晶體M7與第八電晶體M8會被關斷,以使移位暫存器210[1]能夠輸出具有致能準位的第一上掃信號U1、第二上掃信號U2與第三上掃信號U3。另一方面,移位暫存器1710[m]的第三電晶體M3、第四電晶體M4與第五電晶體M5會被關斷,而第六電晶體M6、第七電晶體M7與第八電晶體M8則會被導通,以使移位暫存器1710[m]輸出的第一下掃信號D1、第二下掃信號D2與第三下掃信號D3維持於禁能準位。 In one embodiment, the shift registers 1710[2]~1710[m-1] have a second scan order (for example, the scan pulse CP is sequentially output from the bottom to the top of FIG. 17). At this time, the first reference voltage Vref1 will have a low voltage level, and the second reference voltage Vref2 will have a high voltage level. Therefore, the third transistor M3, the fourth transistor M4, and the fifth transistor M5 of the shift register 1710[1] will be turned on, and the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 is turned off, so that the shift register 210[1] can output the first up-scan signal U1, the second up-scan signal U2, and the third up-scan signal U3 with the enable level. On the other hand, the third transistor M3, the fourth transistor M4, and the fifth transistor M5 of the shift register 1710 [m] are turned off, and the sixth transistor M6, the seventh transistor M7, and the first transistor The eight transistor M8 is turned on, so that the first down-scan signal D1, the second down-scan signal D2 and the third down-scan signal D3 output from the shift register 1710 [m] are maintained at the disabled level.

在一無需雙向掃描的實施例中,可以省略第17 圖的移位暫存器1710[1],並將移位暫存器1710[2]由接收移位暫存器1710[1]的掃描脈衝CP改為接收起始信號ST。另外,還可以省略切換電路1810的第一上掃開關Tu1與第二上掃開關Tu2。 In an embodiment that does not require bidirectional scanning, the shift register 1710[1] of FIG. 17 may be omitted, and the shift register 1710[2] may be scanned by the receive shift register 1710[1]. The pulse CP receives the start signal ST instead. In addition, the first up-scan switch Tu1 and the second up-scan switch Tu2 of the switching circuit 1810 may also be omitted.

此外,還可以將移位暫存器1710[m]替換為第22圖所示的移位暫存器2200。移位暫存器2200包含第一電晶體M1、第二電晶體M2、第三電晶體M3、第四電晶體M4與驅動電路2210。第一電晶體M1耦接於第一電源端In1與第一輸出端O1之間,且第一電晶體M1透過第一電源端In1接收第三參考電壓Vref3。第二電晶體M2耦接於第一輸出端O1與接地端GND之間。第三電晶體M3耦接於第二電源端In2與第二輸出端O2之間,且第三電晶體M3透過第二電源端In2接收第五參考電壓Vref5。第四電晶體M4耦接於第二輸出端O2與接地端GND之間。其中,第一電晶體M1、第二電晶體M2、第三電晶體M3、第四電晶體M4的控制端皆耦接於驅動電路2210。 In addition, the shift register 1710 [m] may be replaced with the shift register 2200 shown in FIG. 22. The shift register 2200 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a drive circuit 2210. The first transistor M1 is coupled between the first power terminal In1 and the first output terminal O1, and the first transistor M1 receives the third reference voltage Vref3 through the first power terminal In1. The second transistor M2 is coupled between the first output terminal O1 and the ground terminal GND. The third transistor M3 is coupled between the second power terminal In2 and the second output terminal O2, and the third transistor M3 receives the fifth reference voltage Vref5 through the second power terminal In2. The fourth transistor M4 is coupled between the second output terminal O2 and the ground terminal GND. The control terminals of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all coupled to the driving circuit 2210.

驅動電路2110相似於第20圖的的驅動電路2010,差異在於驅動電路2210的第一驅動電晶體Tr1的第一端用於接收第六參考電壓Vref6。當移位暫存器1710[m-1]輸出掃描脈衝CP時,驅動電路2110會導通第一驅動電晶體Tr1、第一電晶體M1、第三電晶體M3,並關斷第三驅動電晶體Tr3、第二電晶體M2與第四電晶體M4。 The driving circuit 2110 is similar to the driving circuit 2010 of FIG. 20, except that the first terminal of the first driving transistor Tr1 of the driving circuit 2210 is used to receive the sixth reference voltage Vref6. When the shift register 1710[m-1] outputs the scan pulse CP, the driving circuit 2110 turns on the first driving transistor Tr1, the first transistor M1, the third transistor M3, and turns off the third driving transistor Tr3, the second transistor M2 and the fourth transistor M4.

此時,第三參考電壓Vref3會傳遞至第三內部節點P3,並作為具有致能準位的第一下掃信號D1輸出。第 第六參考電壓Vref6會傳遞至第一輸出端O1,並作為具有致能準位的第二下掃信號D2輸出。第五參考電壓Vref5會傳遞至第二輸出端O2,並作為具有致能準位的第三下掃信號D3輸出。 At this time, the third reference voltage Vref3 is transferred to the third internal node P3 and is output as the first down-scan signal D1 with the enable level. The sixth reference voltage Vref6 is transmitted to the first output terminal O1, and is output as the second down-scan signal D2 with the enable level. The fifth reference voltage Vref5 is transmitted to the second output terminal O2 and is output as the third down-scan signal D3 with the enable level.

另一方面,當驅動電路2210接收到重置脈衝RP時,驅動電路2210會關斷第一驅動電晶體Tr1、第一電晶體M1、第三電晶體M3,並導通第三驅動電晶體Tr3、第二電晶體M2與第四電晶體M4。此時,接地電壓便會作為具有禁能準位的第一下掃信號D1、第二下掃信號D2與第三下掃信號D3輸出。 On the other hand, when the driving circuit 2210 receives the reset pulse RP, the driving circuit 2210 turns off the first driving transistor Tr1, the first transistor M1, the third transistor M3, and turns on the third driving transistor Tr3, The second transistor M2 and the fourth transistor M4. At this time, the ground voltage is output as the first down-scan signal D1, the second down-scan signal D2, and the third down-scan signal D3 with the disabled level.

由上述可知,當顯示裝置100暫停更新顯示畫面時,顯示裝置100可防止畫素電路150與垂直驅動線VL之間產生漏電流。因此,顯示裝置100可提供高品質的顯示畫面。 As can be seen from the above, when the display device 100 pauses to update the display screen, the display device 100 can prevent the leakage current between the pixel circuit 150 and the vertical drive line VL. Therefore, the display device 100 can provide a high-quality display screen.

在說明書及申請專利範圍中使用了某些詞彙來指稱特定的元件。然而,所屬技術領域中具有通常知識者應可理解,同樣的元件可能會用不同的名詞來稱呼。說明書及申請專利範圍並不以名稱的差異做為區分元件的方式,而是以元件在功能上的差異來做為區分的基準。在說明書及申請專利範圍所提及的「包含」為開放式的用語,故應解釋成「包含但不限定於」。另外,「耦接」在此包含任何直接及間接的連接手段。因此,若文中描述第一元件耦接於第二元件,則代表第一元件可通過電性連接或無線傳輸、光學傳輸等信號連接方式而直接地連接於第二元件,或者通過其他元件或 連接手段間接地電性或信號連接至該第二元件。 Certain words are used in the specification and patent application scope to refer to specific elements. However, those of ordinary skill in the art should understand that the same elements may be referred to by different nouns. The specification and the scope of patent application do not use the difference in names as a way to distinguish the components, but the difference in the functions of the components as the basis for distinguishing. "Inclusion" mentioned in the description and the scope of patent application is an open term, so it should be interpreted as "including but not limited to." In addition, "coupling" here includes any direct and indirect connection means. Therefore, if it is described that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection, wireless transmission, optical transmission, or other signal connection, or through other elements or connections The means is indirectly electrically or signally connected to the second element.

在此所使用的「及/或」的描述方式,包含所列舉的其中之一或多個項目的任意組合。另外,除非說明書中特別指明,否則任何單數格的用語都同時包含複數格的涵義。 The description method of "and/or" used herein includes any combination of one or more of the listed items. In addition, unless otherwise specified in the description, any singular case also includes the meaning of the plural case.

以上僅為本揭示文件的較佳實施例,凡依本揭示文件請求項所做的均等變化與修飾,皆應屬本揭示文件的涵蓋範圍。 The above are only the preferred embodiments of the disclosed document, and any changes and modifications made according to the requested items of the disclosed document shall fall within the scope of the disclosed document.

100‧‧‧顯示裝置 100‧‧‧Display device

110‧‧‧控制電路 110‧‧‧Control circuit

120‧‧‧源極驅動器 120‧‧‧ source driver

130‧‧‧閘極驅動器 130‧‧‧Gate driver

140‧‧‧防漏電電路 140‧‧‧anti-leakage circuit

150‧‧‧畫素電路 150‧‧‧ pixel circuit

VL[1]~VL[x]‧‧‧垂直信號線 VL[1]~VL[x]‧‧‧Vertical signal line

HL[1]~HL[y]‧‧‧水平信號線 HL[1]~HL[y]‧‧‧horizontal signal line

ODD‧‧‧第一防護信號 ODD‧‧‧The first protection signal

EVEN‧‧‧第二防護信號 EVEN‧‧‧Second protection signal

CTL1‧‧‧第一控制信號群組 CTL1‧‧‧First control signal group

CTL2‧‧‧第二控制信號群組 CTL2‧‧‧Second control signal group

CK‧‧‧時脈信號 CK‧‧‧clock signal

XCK‧‧‧反相時脈信號 XCK‧‧‧Inverted clock signal

ST‧‧‧起始信號 ST‧‧‧Start signal

RS‧‧‧重置信號 RS‧‧‧Reset signal

PW‧‧‧電力輸入 PW‧‧‧Power input

Mu‧‧‧多工信號群組 Mu‧‧‧Multiplex signal group

Da‧‧‧資料信號 Da‧‧‧Data signal

Claims (24)

一種顯示裝置,包含多個縱向驅動線,且該顯示裝置另包含:多個切換電路,對應耦接於該多個縱向驅動線,用於接收至少一控制訊號;以及多個移位暫存器,包含一末級移位暫存器,其中該末級移位暫存器用於輸出該至少一控制訊號;其中該多個切換電路用於依據該至少一控制訊號,於一第一時段中將該多個縱向驅動線中的一第一部分縱向驅動線設置為具有一第一電壓準位,將該多個縱向驅動線中的一第二部分縱向驅動線設置為具有一第二電壓準位,並且於一第二時段中將該第二部分縱向驅動線設置為具有該第一電壓準位,將該第一部分縱向驅動線設置為具有該第二電壓準位。 A display device includes a plurality of vertical drive lines, and the display device further includes: a plurality of switching circuits corresponding to the plurality of vertical drive lines for receiving at least one control signal; and a plurality of shift registers , Including a last-stage shift register, wherein the last-stage shift register is used to output the at least one control signal; wherein the plurality of switching circuits are used to convert the at least one control signal in a first period A first portion of the longitudinal drive lines of the plurality of longitudinal drive lines is set to have a first voltage level, and a second portion of the longitudinal drive lines of the plurality of vertical drive lines is set to have a second voltage level, In a second period, the second partial vertical driving line is set to have the first voltage level, and the first partial vertical driving line is set to have the second voltage level. 如請求項1的顯示裝置,其中,當該第一控制訊號群組具有一禁能準位時,該其他移位暫存器依序輸出一掃描脈衝,當該第一控制訊號群組具有一致能準位時,該其他移位暫存器不輸出該掃描脈衝。 The display device of claim 1, wherein when the first control signal group has a disabled level, the other shift registers sequentially output a scan pulse when the first control signal group has the same When the level can be set, the other shift register does not output the scan pulse. 如請求項2的顯示裝置,其中,當該末級移位暫存器接收到一重置脈衝時,該末級移位暫存器將該 該第一控制訊號群組自該致能準位切換至該禁能準位,當該第一控制訊號群組具有該禁能準位,且該其他移位暫存器接收到一起始脈衝時,該其他移位暫存器才依序輸出一掃描脈衝,該重置脈衝於時序上早於該起始脈衝。 The display device of claim 2, wherein, when the last-stage shift register receives a reset pulse, the last-stage shift register removes the first control signal group from the enable level Switch to the disabled level. When the first control signal group has the disabled level and the other shift register receives a start pulse, the other shift register outputs a Scan pulse, the reset pulse is earlier than the start pulse in timing. 如請求項2的顯示裝置,其中,當該末級移位暫存器的前一級移位暫存器輸出該掃描脈衝時,該末級移位暫存器將該第一控制訊號群組自該禁能準位切換至該致能準位。 The display device of claim 2, wherein, when the previous stage shift register of the last stage shift register outputs the scan pulse, the last stage shift register groups the first control signal from The disabled level is switched to the enabled level. 如請求項4的顯示裝置,其中,該第一控制訊號群組包含一第一下掃訊號,每個切換電路包含:一第一下掃開關,包含一第一端、一第二端和一控制端,其中該第一下掃開關的該第一端用於接收一第一防護訊號,該第一下掃開關的該第二端耦接於該多個縱向驅動線中的一第一縱向驅動線,該第一下掃開關的該控制端用於接收該第一下掃訊號;以及一第二下掃開關,包含一第一端、一第二端和一控制端,其中該第二下掃開關的該第一端用於接收一第二防護訊號,該第二下掃開關的該第二端耦接於該多個縱向驅動線中的一第二縱向驅動線,該第二下掃開關的該控制端用於接收該第一下掃訊號;其中該第一縱向驅動線和該第二縱向驅動線為相鄰設 置,於該第一時段與該第二時段中,該第一防護訊號與該第二防護訊號的波形彼此相反。 The display device according to claim 4, wherein the first control signal group includes a first down-scan signal, and each switching circuit includes: a first down-scan switch, including a first terminal, a second terminal, and a The control terminal, wherein the first end of the first down-sweep switch is used to receive a first protection signal, and the second end of the first down-sweep switch is coupled to a first longitudinal direction of the plurality of longitudinal drive lines Drive line, the control end of the first down-scan switch is used to receive the first down-scan signal; and a second down-scan switch, including a first end, a second end and a control end, wherein the second The first end of the down-sweep switch is used to receive a second protection signal. The second end of the second down-sweep switch is coupled to a second longitudinal drive line of the plurality of longitudinal drive lines. The control end of the scan switch is used to receive the first down-scan signal; wherein the first longitudinal drive line and the second longitudinal drive line are arranged adjacently, and in the first period and the second period, the first The waveforms of the guard signal and the second guard signal are opposite to each other. 如請求項5的顯示裝置,其中,每個切換電路另包含:一第一上掃開關,包含一第一端、一第二端和一控制端,其中該第一上掃開關的該第一端用於接收該第一防護訊號,該第一上掃開關的該第二端耦接於該第一縱向驅動線,該第一上掃開關的該控制端用於接收一第一上掃訊號;以及一第二上掃開關,包含一第一端、一第二端和一控制端,其中該第二上掃開關的該第一端用於接收該第二防護訊號,該第二上掃開關的該第二端耦接於該第二縱向驅動線,該第二上掃開關的該控制端用於接收該第一上掃訊號。 The display device according to claim 5, wherein each switching circuit further includes: a first up-sweep switch, including a first end, a second end, and a control end, wherein the first The terminal is used to receive the first protection signal, the second end of the first up-sweep switch is coupled to the first longitudinal drive line, and the control end of the first up-sweep switch is used to receive a first up-sweep signal ; And a second up-sweep switch, including a first end, a second end and a control end, wherein the first end of the second up-sweep switch is used to receive the second protection signal, the second up-sweep The second end of the switch is coupled to the second longitudinal drive line, and the control end of the second up-sweep switch is used to receive the first up-sweep signal. 如請求項6的顯示裝置,其中,該末級移位暫存器包含:一第一電晶體,耦接於一第一電源端與一第一節點之間,當該末級移位暫存器的前一級移位暫存器輸出該掃描脈衝時,該第一電晶體導通該第一電源端與該第一節點;一第二電晶體,耦接於該第一節點與一接地端之間,當該末級移位暫存器接收到一重置脈衝時,該第二電晶體導通該第一節點與該接地端; 一第三電晶體,耦接於該第一節點與一第一輸出端之間,當該其他移位暫存器具有一第一掃描順序時,該第三電晶體導通該第一節點與該第一輸出端,當該其他移位暫存器具有一第二掃描順序時,該第三電晶體斷開該第一節點與該第一輸出端;以及一第四電晶體,耦接於該第一輸出端與該接地端之間,當該其他移位暫存器具有該第一掃描順序時,該第四電晶體斷開該第一輸出端與該接地端,當該其他移位暫存器具有該第二掃描順序時,該第四電晶體導通該第一輸出端與該接地端。 The display device according to claim 6, wherein the last-stage shift register includes: a first transistor, coupled between a first power terminal and a first node, when the last-stage shift register When the previous stage of the shift register outputs the scan pulse, the first transistor turns on the first power terminal and the first node; a second transistor is coupled between the first node and a ground terminal In the meantime, when the last-stage shift register receives a reset pulse, the second transistor turns on the first node and the ground terminal; a third transistor is coupled to the first node and a first Between an output terminal, when the other shift register has a first scan sequence, the third transistor turns on the first node and the first output terminal, and when the other shift register has a second scan In sequence, the third transistor disconnects the first node and the first output terminal; and a fourth transistor, coupled between the first output terminal and the ground terminal, when the other shift is temporarily stored When the device has the first scanning sequence, the fourth transistor disconnects the first output terminal and the ground terminal, and when the other shift register has the second scanning sequence, the fourth transistor turns on the first An output terminal and the ground terminal. 如請求項4的顯示裝置,其中,該第一控制訊號群組包含一第一下掃訊號和一第二下掃訊號,每個切換電路包含:一第一下掃開關,包含一第一端、一第二端和一控制端,其中該第一下掃開關的該第一端用於接收一第一防護訊號,該第一下掃開關的該第二端耦接於該多個縱向驅動線中的一第一縱向訊號線,該第一下掃開關的該控制端用於接收該第一下掃訊號;一第二下掃開關,包含一第一端、一第二端和一控制端,其中該第二下掃開關的該第一端用於接收一第二防護訊號,該第二下掃開關的該第二端耦接於該第一縱向訊號線,該第二下掃開關的該控制端用於接收該第二下掃訊號; 一第三下掃開關,包含一第一端、一第二端和一控制端,其中該第三下掃開關的該第一端用於接收該第二防護訊號,該第三下掃開關的該第二端耦接於該多個縱向驅動線中的一第二縱向訊號線,該第三下掃開關的該控制端用於接收該第一下掃訊號;以及一第四下掃開關,包含一第一端、一第二端和一控制端,其中該第四下掃開關的該第一端用於接收該第一防護訊號,該第四下掃開關的該第二端耦接於該第二縱向訊號線,該第四下掃開關的該控制端用於接收該第二下掃訊號;其中該第一防護訊號與該第二防護訊號為直流訊號。 The display device according to claim 4, wherein the first control signal group includes a first down-scan signal and a second down-scan signal, and each switching circuit includes: a first down-scan switch, including a first terminal , A second end and a control end, wherein the first end of the first down-scan switch is used to receive a first protection signal, and the second end of the first down-scan switch is coupled to the plurality of longitudinal drives A first longitudinal signal line in the line, the control end of the first down-sweep switch is used to receive the first down-sweep signal; a second down-sweep switch includes a first end, a second end and a control Terminal, wherein the first end of the second down-scan switch is used to receive a second protection signal, the second end of the second down-scan switch is coupled to the first longitudinal signal line, and the second down-scan switch The control terminal is used to receive the second down-scan signal; a third down-scan switch includes a first terminal, a second terminal and a control terminal, wherein the first end of the third down-scan switch is used for Receiving the second protection signal, the second end of the third down-scan switch is coupled to a second longitudinal signal line of the plurality of vertical drive lines, and the control end of the third down-scan switch is used to receive the A first down-scan signal; and a fourth down-scan switch, including a first end, a second end and a control terminal, wherein the first end of the fourth down-scan switch is used to receive the first protection signal, The second end of the fourth down-scan switch is coupled to the second longitudinal signal line, and the control end of the fourth down-scan switch is used to receive the second down-scan signal; wherein the first protection signal and the first The second protection signal is a DC signal. 如請求項8的顯示裝置,其中,每個切換電路另包含:一第一上掃開關,包含一第一端、一第二端和一控制端,其中該第一上掃開關的該第一端用於接收該第一防護訊號,該第一上掃開關的該第二端耦接於該第一縱向訊號線,該第一上掃開關的該控制端用於接收一第一上掃訊號;一第二上掃開關,包含一第一端、一第二端和一控制端,其中該第二上掃開關的該第一端用於接收該第二防護訊號,該第二上掃開關的該第二端耦接於該第一縱向訊號線,該第二上掃開關的該控制端用於接收一第二上掃訊號; 一第三上掃開關,包含一第一端、一第二端和一控制端,其中該第三上掃開關的該第一端用於接收該第二防護訊號,該第三上掃開關的該第二端耦接於該第二縱向訊號線,該第三上掃開關的該控制端用於接收該第一上掃訊號;以及一第四上掃開關,包含一第一端、一第二端和一控制端,其中該第四上掃開關的該第一端用於接收該第一防護訊號,該第四上掃開關的該第二端耦接於該第二縱向訊號線,該第四上掃開關的該控制端用於接收該第二上掃訊號。 The display device according to claim 8, wherein each switching circuit further includes: a first up-sweep switch, including a first end, a second end, and a control end, wherein the first The terminal is used to receive the first protection signal, the second end of the first up-sweep switch is coupled to the first longitudinal signal line, and the control end of the first up-sweep switch is used to receive a first up-sweep signal A second up-sweep switch, including a first end, a second end and a control end, wherein the first end of the second up-sweep switch is used to receive the second protection signal, the second up-sweep switch The second end is coupled to the first longitudinal signal line, and the control end of the second up-sweep switch is used to receive a second up-sweep signal; a third up-sweep switch includes a first end, a first Two terminals and a control terminal, wherein the first end of the third up-sweep switch is used to receive the second protection signal, the second end of the third up-sweep switch is coupled to the second longitudinal signal line, the The control terminal of the third upsweep switch is used to receive the first upsweep signal; and a fourth upsweep switch includes a first end, a second end, and a control end, wherein the fourth upswap switch The first end is used to receive the first protection signal, the second end of the fourth up-sweep switch is coupled to the second longitudinal signal line, and the control end of the fourth up-sweep switch is used to receive the second Scan the signal. 如請求項4的顯示裝置,其中,該第一控制訊號群組包含一第一下掃訊號和一第二下掃訊號,且每個切換電路包含:一第一下掃開關,包含一第一端、一第二端和一控制端,其中該第一下掃開關的該第一端用於接收一第一防護訊號,該第一下掃開關的該第二端耦接於該多個縱向驅動線中的一第一縱向驅動線,該第一下掃開關的該控制端用於接收該第一下掃訊號;以及一第二下掃開關,包含一第一端、一第二端和一控制端,其中該第二下掃開關的該第一端用於接收一第二防護訊號,該第二下掃開關的該第二端耦接於該多個縱向驅動線中的一第二縱向驅動線,該第二下掃開關的該控制端用於接收該第二下掃訊號; 其中該第一縱向驅動線和該第二縱向驅動線為相鄰設置,該第一下掃訊號與該第一防護訊號的電壓準位相同,且該第二下掃訊號與該第二防護訊號的電壓準位相同。 The display device according to claim 4, wherein the first control signal group includes a first down-scan signal and a second down-scan signal, and each switching circuit includes: a first down-scan switch, including a first End, a second end and a control end, wherein the first end of the first down-scan switch is used to receive a first protection signal, and the second end of the first down-scan switch is coupled to the plurality of longitudinal directions A first vertical drive line in the drive line, the control end of the first down-scan switch is used to receive the first down-scan signal; and a second down-scan switch, including a first end, a second end and A control terminal, wherein the first end of the second down-scan switch is used to receive a second protection signal, and the second end of the second down-scan switch is coupled to a second of the plurality of longitudinal drive lines A vertical drive line, the control end of the second down-scan switch is used to receive the second down-scan signal; wherein the first vertical drive line and the second vertical drive line are arranged adjacently, and the first down-scan signal is The voltage level of the first protection signal is the same, and the voltage level of the second down-scan signal and the second protection signal are the same. 如請求項10的顯示裝置,其中,每個切換電路另包含:一第一上掃開關,包含一第一端、一第二端和一控制端,其中該第一上掃開關的該第一端用於接收該第一防護訊號,該第一上掃開關的該第二端耦接於該第一縱向驅動線,該第一上掃開關的該控制端用於接收一第一上掃訊號;以及一第二上掃開關,包含一第一端、一第二端和一控制端,其中該第二上掃開關的該第一端用於接收該第二防護訊號,該第二上掃開關的該第二端耦接於該第二縱向驅動線,該第二上掃開關的該控制端用於接收一第二上掃訊號。 The display device according to claim 10, wherein each switching circuit further includes: a first up-sweep switch, including a first end, a second end, and a control end, wherein the first The terminal is used to receive the first protection signal, the second end of the first up-sweep switch is coupled to the first longitudinal drive line, and the control end of the first up-sweep switch is used to receive a first up-sweep signal ; And a second up-sweep switch, including a first end, a second end and a control end, wherein the first end of the second up-sweep switch is used to receive the second protection signal, the second up-sweep The second end of the switch is coupled to the second longitudinal drive line, and the control end of the second up-sweep switch is used to receive a second up-sweep signal. 如請求項9或11的顯示裝置,其中,該末級移位暫存器包含:一第一電晶體,耦接於一第一電源端與一第一節點之間;一第二電晶體,耦接於該第一節點與一接地端之間;一第三電晶體,耦接於該第一節點與一第一輸出端之間; 一第四電晶體,耦接於該第一輸出端與該接地端之間;一第五電晶體,耦接於一第二電源端與一第二節點之間,其中當該末級移位暫存器的前一級移位暫存器輸出該掃描脈衝時,該第一電晶體導通該第一電源端與該第一節點,該第五電晶體導通該第二電源端與該第二節點;一第六電晶體,耦接於該第二節點與該接地端之間,其中當該末級移位暫存器接收到一重置脈衝時,該第二電晶體導通該第一節點與該接地端,該第六電晶體導通該第二節點與該接地端;一第七電晶體,耦接於該第二節點與一第二輸出端之間,其中當該其他移位暫存器具有一第一掃描順序時,該第三電晶體導通該第一節點與該第一輸出端且該第七電晶體導通該第二節點與該第二輸出端,當該其他移位暫存器具有一第二掃描順序時,該第三電晶體斷開該第一節點與該第一輸出端且該第七電晶體斷開該第二節點與該第二輸出端;以及一第八電晶體,耦接於該第二輸出端與該接地端之間,其中當該其他移位暫存器具有該第一掃描順序時,該第四電晶體斷開該第一輸出端與該接地端且該第八電晶體斷開該第二輸出端與該接地端,當該其他移位暫存器具有該第二掃描順序時,該第四電晶體導通該第一輸出端與該接地端且該第八電晶體導通該第二輸出端與該接地端。 The display device according to claim 9 or 11, wherein the last-stage shift register includes: a first transistor coupled between a first power terminal and a first node; a second transistor, Is coupled between the first node and a ground terminal; a third transistor is coupled between the first node and a first output terminal; a fourth transistor is coupled to the first output terminal And the ground terminal; a fifth transistor, coupled between a second power terminal and a second node, wherein when the last-stage shift register of the last-stage shift register outputs the scan When pulsed, the first transistor turns on the first power terminal and the first node, the fifth transistor turns on the second power terminal and the second node; a sixth transistor is coupled to the second node And the ground terminal, wherein when the last-stage shift register receives a reset pulse, the second transistor turns on the first node and the ground terminal, and the sixth transistor turns on the second node And the ground terminal; a seventh transistor, coupled between the second node and a second output terminal, wherein when the other shift register has a first scan sequence, the third transistor turns on the The first node and the first output terminal and the seventh transistor turn on the second node and the second output terminal. When the other shift register has a second scanning sequence, the third transistor turns off the A first node and the first output terminal and the seventh transistor disconnects the second node and the second output terminal; and an eighth transistor, coupled between the second output terminal and the ground terminal, When the other shift register has the first scanning sequence, the fourth transistor disconnects the first output terminal and the ground terminal and the eighth transistor disconnects the second output terminal and the ground terminal When the other shift register has the second scan sequence, the fourth transistor turns on the first output terminal and the ground terminal and the eighth transistor turns on the second output terminal and the ground terminal. 如請求項12的顯示裝置,其中,在該第一下掃訊號與該第一防護訊號的電壓準位相同,且該第二下掃訊號與該第二防護訊號的電壓準位相同的情況下,該第一電晶體透過該第一電源端接收該第一防護訊號,該第二電晶體透過該第二電源端接收該第二防護訊號。 The display device according to claim 12, wherein, when the voltage level of the first down-scan signal and the first protection signal are the same, and the voltage level of the second down-scan signal and the second protection signal are the same , The first transistor receives the first protection signal through the first power terminal, and the second transistor receives the second protection signal through the second power terminal. 如請求項4的顯示裝置,其中,該第一控制訊號群組包含一第一下掃訊號與一第二下掃訊號,該多個切換電路包含一第一切換電路和一第二切換電路,該第一切換電路包含:一第一下掃開關,包含一第一端、一第二端和一控制端,其中該第一下掃開關的該第一端用於接收一第一防護訊號,該第一下掃開關的該第二端耦接於該多個縱向驅動線中的一第一縱向驅動線,該第一下掃開關的該控制端用於接收該第一下掃訊號;以及一第二下掃開關,包含一第一端、一第二端和一控制端,其中該第二下掃開關的該第一端用於接收一第二防護訊號,該第二下掃開關的該第二端耦接於該多個縱向驅動線中的一第二縱向驅動線,該第二下掃開關的該控制端用於接收該第一下掃訊號;其中,該第二切換電路包含:一第三下掃開關,包含一第一端、一第二端和一控制端,其中該第三下掃開關的該第一端用於接收該第一防護訊號,該第三下掃開關的該第二端耦接於該 多個縱向驅動線中的一第三縱向驅動線,該第三下掃開關的該控制端用於接收該第二下掃訊號;以及一第四下掃開關,包含一第一端、一第二端和一控制端,其中該第四下掃開關的該第一端用於接收該第二防護訊號,該第四下掃開關的該第二端耦接於該多個縱向驅動線中的一第四縱向驅動線,該第四下掃開關的該控制端用於接收該第二下掃訊號;其中該第一縱向驅動線、該第二縱向驅動線、該第三縱向驅動線與該第四縱向驅動線依序相鄰設置,於該第一時段與該第二時段中,該第一防護訊號與該第二防護訊號的波形彼此相反。 The display device according to claim 4, wherein the first control signal group includes a first down-scan signal and a second down-scan signal, and the plurality of switching circuits include a first switching circuit and a second switching circuit, The first switching circuit includes: a first down-scan switch, including a first end, a second end, and a control terminal, wherein the first end of the first down-scan switch is used to receive a first protection signal, The second end of the first down-scan switch is coupled to a first longitudinal drive line among the plurality of vertical drive lines, and the control end of the first down-scan switch is used to receive the first down-scan signal; and A second down sweep switch includes a first end, a second end and a control end, wherein the first end of the second down sweep switch is used to receive a second protection signal, and the second down sweep switch The second end is coupled to a second vertical drive line among the plurality of vertical drive lines, and the control end of the second down-scan switch is used to receive the first down-scan signal; wherein, the second switching circuit includes : A third sweep-down switch, including a first end, a second end, and a control end, wherein the first end of the third sweep-down switch is used to receive the first protection signal, and the third sweep-down switch The second end is coupled to a third longitudinal drive line among the plurality of longitudinal drive lines, the control end of the third down-scan switch is used to receive the second down-scan signal; and a fourth down-scan switch Including a first end, a second end and a control end, wherein the first end of the fourth down-scan switch is used to receive the second protection signal, and the second end of the fourth down-scan switch is coupled A fourth longitudinal drive line among the plurality of longitudinal drive lines, the control end of the fourth down-scan switch is used to receive the second down-scan signal; wherein the first vertical drive line and the second vertical drive line 3. The third vertical drive line and the fourth vertical drive line are sequentially arranged adjacently. In the first period and the second period, the waveforms of the first protection signal and the second protection signal are opposite to each other. 如請求項14的顯示裝置,其中,該第一切換電路另包含:一第一上掃開關,包含一第一端、一第二端和一控制端,其中該第一上掃開關的該第一端用於接收該第一防護訊號,該第一上掃開關的該第二端耦接於該第一縱向驅動線,該第一上掃開關的該控制端用於接收一第一上掃訊號;以及一第二上掃開關,包含一第一端、一第二端和一控制端,其中該第二上掃開關的該第一端用於接收該第二防護訊號,該第二上掃開關的該第二端耦接於該第二縱向驅動線,該第二上掃開關的該控制端用於接收該第一上掃訊號; 其中,該第二切換電路另包含:一第三上掃開關,包含一第一端、一第二端和一控制端,其中該第三上掃開關的該第一端用於接收該第一防護訊號,該第三上掃開關的該第二端耦接於該第三縱向驅動線,該第三上掃開關的該控制端用於接收一第二上掃訊號;以及一第四上掃開關,包含一第一端、一第二端和一控制端,其中該第四上掃開關的該第一端用於接收該第二防護訊號,該第四上掃開關的該第二端耦接於該第四縱向驅動線,該第四上掃開關的該控制端用於接收該第二上掃訊號。 The display device according to claim 14, wherein the first switching circuit further includes: a first up-sweep switch, including a first end, a second end, and a control end, wherein the first One end is used to receive the first protection signal, the second end of the first up-sweep switch is coupled to the first longitudinal drive line, and the control end of the first up-sweep switch is used to receive a first up-sweep Signal; and a second up-sweep switch, including a first end, a second end and a control end, wherein the first end of the second up-sweep switch is used to receive the second protection signal, the second up The second end of the scan switch is coupled to the second longitudinal drive line, and the control end of the second up-scan switch is used to receive the first up-scan signal; wherein, the second switching circuit further includes: a third The up-sweep switch includes a first end, a second end and a control end, wherein the first end of the third up-sweep switch is used to receive the first protection signal, and the second end of the third up-sweep switch The terminal is coupled to the third longitudinal drive line. The control terminal of the third up-sweep switch is used to receive a second up-sweep signal; and a fourth up-sweep switch includes a first end, a second end and A control terminal, wherein the first end of the fourth up-sweep switch is used to receive the second guard signal, the second end of the fourth up-sweep switch is coupled to the fourth longitudinal drive line, the fourth up The control end of the scan switch is used to receive the second up-scan signal. 如請求項15的顯示裝置,其中,該末級移位暫存器包含:一第一電晶體,耦接於一第一電源端與一第一節點之間,其中當該末級移位暫存器的前一級移位暫存器輸出該掃描脈衝時,該第一電晶體導通該第一電源端與該第一節點;一第二電晶體,耦接於該第一節點與一接地端之間,其中當該末級移位暫存器接收到一重置脈衝時,該第二電晶體導通該第一節點與該接地端;一第三電晶體,耦接於該第一節點與一第一輸出端之間;一第四電晶體,耦接於該第一節點與一第二輸出端之 間;一第五電晶體,耦接於該第一節點與一第三輸出端之間,其中當該其他移位暫存器具有一第一掃描順序時,該第三電晶體導通該第一節點與該第一輸出端,該第四電晶體導通該第一節點與該第二輸出端,且該第五電晶體導通該第一節點與該第三輸出端,當該其他移位暫存器具有一第二掃描順序時,該第三電晶體斷開該第一節點與該第一輸出端,該第四電晶體斷開該第一節點與該第二輸出端,且該第五電晶體斷開該第一節點與該第三輸出端;一第六電晶體,耦接於該第一輸出端與該接地端之間;一第七電晶體,耦接於該第二輸出端與該接地端之間;以及一第八電晶體,耦接於該第三輸出端與該接地端之間,其中當該其他移位暫存器具有該第一掃描順序時,該第六電晶體斷開該第一輸出端與該接地端,該第七電晶體斷開該第二輸出端與該接地端,且該第八電晶體斷開該第三輸出端與該接地端,當該其他移位暫存器具有該第二掃描順序時,該第六電晶體導通該第一輸出端與該接地端,該第七電晶體導通該第二輸出端與該接地端,且該第八電晶體導通該第三輸出端與該接地端。 The display device according to claim 15, wherein the last-stage shift register includes: a first transistor, coupled between a first power terminal and a first node, wherein when the last-stage shift register When the previous-stage shift register of the register outputs the scan pulse, the first transistor turns on the first power terminal and the first node; a second transistor is coupled to the first node and a ground terminal In between, when the last-stage shift register receives a reset pulse, the second transistor turns on the first node and the ground terminal; a third transistor is coupled to the first node and Between a first output terminal; a fourth transistor, coupled between the first node and a second output terminal; a fifth transistor, coupled between the first node and a third output terminal When the other shift registers have a first scan sequence, the third transistor turns on the first node and the first output terminal, and the fourth transistor turns on the first node and the second output Terminal, and the fifth transistor turns on the first node and the third output terminal, and when the other shift register has a second scan sequence, the third transistor disconnects the first node and the first At the output terminal, the fourth transistor disconnects the first node and the second output terminal, and the fifth transistor disconnects the first node and the third output terminal; a sixth transistor is coupled to the Between the first output and the ground; a seventh transistor, coupled between the second output and the ground; and an eighth transistor, coupled between the third output and the ground Between the terminals, wherein when the other shift register has the first scan sequence, the sixth transistor disconnects the first output terminal and the ground terminal, and the seventh transistor disconnects the second output terminal And the ground terminal, and the eighth transistor disconnects the third output terminal and the ground terminal, and when the other shift register has the second scan sequence, the sixth transistor turns on the first output terminal With the ground terminal, the seventh transistor turns on the second output terminal and the ground terminal, and the eighth transistor turns on the third output terminal and the ground terminal. 一種閘極驅動器,適用於一顯示裝置,其中該顯示裝置包含多個縱向驅動線,該閘極驅動器包 含:多個移位暫存器,包含一末級移位暫存器,其中該末級移位暫存器用於輸出第一控制訊號群組至多個切換電路,且該多個切換電路對應耦接於該多個縱向驅動線;其中該多個切換電路用於依據該第一控制訊號群組,於一第一時段中將該多個縱向驅動線中的一第一部分縱向驅動線設置為具有一第一電壓準位,將該多個縱向驅動線中的一第二部分縱向驅動線設置為具有一第二電壓準位,並且於一第二時段中將該第二部分縱向驅動線設置為具有該第一電壓準位,將該第一部分縱向驅動線設置為具有該第二電壓準位。 A gate driver suitable for a display device, wherein the display device includes a plurality of vertical drive lines, the gate driver includes: a plurality of shift registers, including a last-stage shift register, wherein the last stage The shift register is used for outputting the first control signal group to a plurality of switching circuits, and the plurality of switching circuits are correspondingly coupled to the plurality of vertical drive lines; wherein the plurality of switching circuits are used to control the first control signal group Group, set a first portion of the longitudinal drive lines of the plurality of longitudinal drive lines to have a first voltage level in a first period, and set a second portion of the longitudinal drive lines of the plurality of vertical drive lines To have a second voltage level, and set the second partial vertical drive line to have the first voltage level in a second period, and set the first partial vertical drive line to have the second voltage level . 如請求項17的閘極驅動器,其中,當該第一控制訊號群組具有一禁能準位時,該其他移位暫存器依序輸出一掃描脈衝,當該第一控制訊號群組具有一致能準位時,該其他移位暫存器不輸出該掃描脈衝。 The gate driver of claim 17, wherein, when the first control signal group has a disabled level, the other shift registers sequentially output a scan pulse, and when the first control signal group has When the energy level is consistent, the other shift register does not output the scan pulse. 如請求項18的閘極驅動器,其中,當該末級移位暫存器接收到一重置脈衝時,該末級移位暫存器將該第一控制訊號群組自該致能準位切換至該禁能準位,當該第一控制訊號群組具有該禁能準位,且該其他移位暫存器接收到一起始脈衝時,該其他移位暫存器才依序 輸出一掃描脈衝,該重置脈衝於時序上早於該起始脈衝。 The gate driver of claim 18, wherein, when the last-stage shift register receives a reset pulse, the last-stage shift register removes the first control signal group from the enable level Switch to the disabled level. When the first control signal group has the disabled level and the other shift register receives a start pulse, the other shift register outputs a Scan pulse, the reset pulse is earlier than the start pulse in timing. 如請求項18的閘極驅動器,其中,當該末級移位暫存器的前一級移位暫存器輸出該掃描脈衝時,該末級移位暫存器將該第一控制訊號群組自該禁能準位切換至該致能準位。 The gate driver of claim 18, wherein when the previous stage shift register of the last stage shift register outputs the scan pulse, the last stage shift register groups the first control signal Switch from the disabled level to the enabled level. 如請求項19的閘極驅動器,其中,該末級移位暫存器包含:一驅動電路,用於接收該末級移位暫存器的前一級移位暫存器輸出的該掃描脈衝、該重置脈衝、一第一參考電壓、一第二參考電壓,以及用於接收一第三參考電壓或一時脈信號;一第一電晶體,耦接於一第一電源端與一第一節點之間,且該第一電晶體的一控制端耦接於該驅動電路;一第二電晶體,耦接於該第一節點與一接地端之間,且該第二電晶體的一控制端耦接於該驅動電路;一第三電晶體,耦接於該第一節點與一第一輸出端之間,且該第三電晶體的一控制端用於接收該第一參考電壓;以及一第四電晶體,耦接於該第一輸出端與該接地端之間,且該第四電晶體的一控制端用於接收該第二參考電壓。 The gate driver of claim 19, wherein the last-stage shift register includes: a driving circuit for receiving the scan pulse output by the previous-stage shift register of the last-stage shift register, The reset pulse, a first reference voltage, and a second reference voltage are used to receive a third reference voltage or a clock signal; a first transistor is coupled to a first power terminal and a first node And a control terminal of the first transistor is coupled to the driving circuit; a second transistor is coupled between the first node and a ground terminal, and a control terminal of the second transistor A third transistor coupled between the first node and a first output terminal, and a control terminal of the third transistor for receiving the first reference voltage; and a The fourth transistor is coupled between the first output terminal and the ground terminal, and a control terminal of the fourth transistor is used to receive the second reference voltage. 如請求項19的閘極驅動器,其中,該末級移位暫存器包含:一驅動電路,用於接收該末級移位暫存器的前一級移位暫存器輸出的該掃描脈衝、該重置脈衝、一第一參考電壓、一第二參考電壓,以及用於接收一第三參考電壓或一時脈信號;一第一電晶體,耦接於一第一電源端與一第一節點之間,且該第一電晶體的一控制端耦接於該驅動電路;一第二電晶體,耦接於該第一節點與一接地端之間,且該第二電晶體的一控制端耦接於該驅動電路;一第三電晶體,耦接於該第一節點與一第一輸出端之間,且該第三電晶體的一控制端用於接收該第一參考電壓;一第四電晶體,耦接於該第一輸出端與該接地端之間,且該第四電晶體的一控制端用於接收該第二參考電壓;一第五電晶體,耦接於一第二電源端與一第二節點之間,且該第五電晶體的一控制端耦接於該驅動電路;一第六電晶體,耦接於該第二節點與該接地端之間,且該第六電晶體的一控制端耦接於該驅動電路;一第七電晶體,耦接於該第二節點與一第二輸出端之間,且該第七電晶體的一控制端用於接收該第一參考電壓;以及一第八電晶體,耦接於該第二輸出端與該接地端之間,且該第八電晶體的一控制端用於接收該第二參考電壓。 The gate driver of claim 19, wherein the last-stage shift register includes: a driving circuit for receiving the scan pulse output by the previous-stage shift register of the last-stage shift register, The reset pulse, a first reference voltage, and a second reference voltage are used to receive a third reference voltage or a clock signal; a first transistor is coupled to a first power terminal and a first node And a control terminal of the first transistor is coupled to the driving circuit; a second transistor is coupled between the first node and a ground terminal, and a control terminal of the second transistor Coupled to the driving circuit; a third transistor coupled between the first node and a first output terminal, and a control terminal of the third transistor for receiving the first reference voltage; a first Four transistors are coupled between the first output terminal and the ground terminal, and a control terminal of the fourth transistor is used to receive the second reference voltage; a fifth transistor is coupled to a second Between the power supply terminal and a second node, and a control terminal of the fifth transistor is coupled to the driving circuit; a sixth transistor is coupled between the second node and the ground terminal, and the first A control terminal of the six transistors is coupled to the driving circuit; a seventh transistor is coupled between the second node and a second output terminal, and a control terminal of the seventh transistor is used to receive the A first reference voltage; and an eighth transistor, coupled between the second output terminal and the ground terminal, and a control terminal of the eighth transistor is used to receive the second reference voltage. 如請求項19的閘極驅動器,其中,該末級移位暫存器包含:一驅動電路,用於接收該末級移位暫存器的前一級移位暫存器輸出的該掃描脈衝、該重置脈衝、一第一參考電壓、一第二參考電壓,以及用於接收一第三參考電壓或一時脈信號;一第一電晶體,耦接於一第一電源端與一第一節點之間,且該第一電晶體的一控制端耦接於該驅動電路;一第二電晶體,耦接於該第一節點與一接地端之間,且該第二電晶體的一控制端耦接於該驅動電路;一第三電晶體,耦接於該第一節點與一第一輸出端之間,且該第三電晶體的一控制端用於接收該第一參考電壓;一第四電晶體,耦接於該第一節點與一第二輸出端之間,且該第四電晶體的一控制端用於接收該第一參考電壓;一第五電晶體,耦接於該第一節點與一第三輸出端之間,且該第五電晶體的一控制端用於接收該第一參考電壓;一第六電晶體,耦接於該第一輸出端與該接地端之間,且該第六電晶體的一控制端用於接收該第二參考電壓;一第七電晶體,耦接於該第二輸出端與該接地端之間,且該第三電晶體的一控制端用於接收該第二參考電壓;以 及一第八電晶體,耦接於該第三輸出端與該接地端之間,且該第三電晶體的一控制端用於接收該第二參考電壓。 The gate driver of claim 19, wherein the last-stage shift register includes: a driving circuit for receiving the scan pulse output by the previous-stage shift register of the last-stage shift register, The reset pulse, a first reference voltage, and a second reference voltage are used to receive a third reference voltage or a clock signal; a first transistor is coupled to a first power terminal and a first node And a control terminal of the first transistor is coupled to the driving circuit; a second transistor is coupled between the first node and a ground terminal, and a control terminal of the second transistor Coupled to the driving circuit; a third transistor coupled between the first node and a first output terminal, and a control terminal of the third transistor for receiving the first reference voltage; a first Four transistors are coupled between the first node and a second output terminal, and a control terminal of the fourth transistor is used to receive the first reference voltage; a fifth transistor is coupled to the first transistor Between a node and a third output terminal, and a control terminal of the fifth transistor is used to receive the first reference voltage; a sixth transistor is coupled between the first output terminal and the ground terminal And a control terminal of the sixth transistor is used to receive the second reference voltage; a seventh transistor is coupled between the second output terminal and the ground terminal, and a control terminal of the third transistor A terminal for receiving the second reference voltage; and an eighth transistor, coupled between the third output terminal and the ground terminal, and a control terminal of the third transistor for receiving the second reference voltage . 如請求項21至23任一項的閘極驅動器,其中,該驅動電路包含:第一驅動電晶體,包含一第一端、一第二端與一控制端,其中該第一驅動電晶體的該第一端用於接收該時脈信號或該第三參考電壓,該第一驅動電晶體的該第二端耦接於一第一內部節點,該第一驅動電晶體的該控制端耦接於一第二內部節點;第二驅動電晶體,包含一第一端、一第二端與一控制端,其中該第二驅動電晶體的該第一端耦接於該第一內部節點,該第二驅動電晶體的該第二端耦接於一第三內部節點,該第二驅動電晶體的該控制端耦接於該第二內部節點;第三驅動電晶體,包含一第一端、一第二端與一控制端,其中該第三驅動電晶體的該第一端耦接於該第三內部節點,該第三驅動電晶體的該第二端耦接於該接地端,該第三驅動電晶體的該控制端耦接於一第四內部節點;第四驅動電晶體,包含一第一端、一第二端與一控制端,其中該第四驅動電晶體的該第一端耦接於該第二內部節點,該第四驅動電晶體的該第二端耦接於該第五內部節點,該第四驅動電晶體的該控制端用於接收一第四參考電 壓;第五驅動電晶體,包含一第一端、一第二端與一控制端,其中該第五驅動電晶體的該第一端與該控制端耦接於該第三內部節點,第五驅動電晶體的該第二端接於一第五內部節點;第六驅動電晶體,包含一第一端、一第二端與一控制端,其中該第六電晶體的該第一端耦接於該第五內部節點、該第六電晶體的該第二端耦接於該接地端,該第六電晶體的該控制端耦接於該第四內部節點;第七驅動電晶體,包含一第一端、一第二端與一控制端,其中該第七驅動電晶體的該第一端與該控制端用於接收該重置信號,該第七電晶體的該第二端耦接於該第四內部節點;第八驅動電晶體,包含一第一端、一第二端與一控制端,其中該第八驅動電晶體的該第一端用於接收該第四參考電壓,該第八驅動電晶體的該第二端耦接於一電阻的第一端,該第八驅動電晶體的該控制端用於接收一反相時脈信號;第九驅動電晶體,包含一第一端、一第二端與一控制端,其中該第九驅動電晶體的該第一端耦接於該電阻的第二端、該第九驅動電晶體的該第二端耦接於該接地端,該第九驅動電晶體的該控制端耦接於該第五內部節點;第十驅動電晶體,包含一第一端、一第二端與一控制端,其中該第十驅動電晶體的該第一端用於接收該第一參 考電壓,該第十驅動電晶體的該第二端耦接於該第五內部節點,該第十驅動電晶體的該控制端用於接收該末級移位暫存器的前一級移位暫存器輸出的該掃描脈衝;以及第十一驅動電晶體,包含一第一端、一第二端與一控制端,其中該第十一驅動電晶體的該第一端耦接於該第六節點,該第十一驅動電晶體的該第二端用於接收該第二參考電壓,該第十一驅動電晶體的該控制端用於接收該重置信號。 The gate driver according to any one of claims 21 to 23, wherein the driving circuit includes: a first driving transistor including a first terminal, a second terminal and a control terminal, wherein the first driving transistor The first terminal is used to receive the clock signal or the third reference voltage, the second terminal of the first driving transistor is coupled to a first internal node, and the control terminal of the first driving transistor is coupled At a second internal node; the second driving transistor includes a first end, a second end and a control end, wherein the first end of the second driving transistor is coupled to the first internal node, the The second end of the second driving transistor is coupled to a third internal node, the control end of the second driving transistor is coupled to the second internal node; the third driving transistor includes a first end, A second terminal and a control terminal, wherein the first terminal of the third driving transistor is coupled to the third internal node, the second terminal of the third driving transistor is coupled to the ground terminal, the first The control end of the three driving transistors is coupled to a fourth internal node; the fourth driving transistor includes a first end, a second end and a control end, wherein the first end of the fourth driving transistor Coupled to the second internal node, the second terminal of the fourth driving transistor is coupled to the fifth internal node, the control terminal of the fourth driving transistor is used to receive a fourth reference voltage; fifth The driving transistor includes a first end, a second end and a control end, wherein the first end and the control end of the fifth driving transistor are coupled to the third internal node, and the fifth driving transistor The second terminal is connected to a fifth internal node; the sixth driving transistor includes a first terminal, a second terminal and a control terminal, wherein the first terminal of the sixth transistor is coupled to the fifth The internal node and the second terminal of the sixth transistor are coupled to the ground terminal, and the control terminal of the sixth transistor is coupled to the fourth internal node; the seventh driving transistor includes a first terminal, A second terminal and a control terminal, wherein the first terminal and the control terminal of the seventh driving transistor are used to receive the reset signal, and the second terminal of the seventh transistor is coupled to the fourth interior Node; an eighth drive transistor, including a first end, a second end and a control end, wherein the first end of the eighth drive transistor is used to receive the fourth reference voltage, the eighth drive transistor The second end is coupled to the first end of a resistor, the control end of the eighth driving transistor is used to receive an inverted clock signal; the ninth driving transistor includes a first end, a second And a control terminal, wherein the first end of the ninth driving transistor is coupled to the second end of the resistor, the second end of the ninth driving transistor is coupled to the ground terminal, and the ninth driving The control end of the transistor is coupled to the fifth internal node; the tenth driving transistor includes a first end, a second end and a control end, wherein the first end of the tenth driving transistor is used for Receiving the first reference voltage, the second terminal of the tenth driving transistor is coupled to the fifth internal node, and the control terminal of the tenth driving transistor is used to receive the front of the last-stage shift register The scan pulse output by the first-level shift register; and the eleventh drive The dynamic transistor includes a first end, a second end and a control end, wherein the first end of the eleventh driving transistor is coupled to the sixth node, and the first end of the eleventh driving transistor The two terminals are used to receive the second reference voltage, and the control terminal of the eleventh driving transistor is used to receive the reset signal.
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TW202009565A (en) 2020-03-01

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