CN107833550A - Display device and its clock pulse generator - Google Patents
Display device and its clock pulse generator Download PDFInfo
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- CN107833550A CN107833550A CN201711019628.6A CN201711019628A CN107833550A CN 107833550 A CN107833550 A CN 107833550A CN 201711019628 A CN201711019628 A CN 201711019628A CN 107833550 A CN107833550 A CN 107833550A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The present invention discloses a clock pulse generator, and it is producing multiple clock signals with control gate driver.Gate drivers are by a plurality of gate line to export signal come multiple sub-pixels in multiple pixels of opening display device.When clock pulse generator receives first mode signal, clock pulse generator sequentially exports the clock signals of multiple high level to gate drivers.When clock pulse generator receives second mode signal, clock pulse generator in first period output enable clock signal to gate drivers, and clock pulse generator in second phase output enable clock signal to gate drivers.
Description
Technical field
The present invention is on a kind of image processor, especially with regard to a kind of display device and its clock pulse generator.
Background technology
With the fast development of Display Technique, display device widely applies in the life of the mankind and played the part of increasingly heavier
The role wanted.Frequently with panel self-renewing (Panel Self Refresh, PSR) skill in the panel of existing display device
Art, once the PSR technologies of display device start, its clock pulse generator reduces refresh rate with by the image output of storage, however, by
Exported in panel with original resolution, cause the increase of display device overall power.
As can be seen here, above-mentioned existing mode, it is clear that still suffer from inconvenience and defect, and have much room for improvement.It is above-mentioned in order to solve
Problem, association area there's no one who doesn't or isn't painstakingly seeks solution, but does not develop appropriate solution yet for a long time.
The content of the invention
The aspect that the present invention discloses is on a kind of clock pulse generator, and it is producing multiple clock signals with control gate
Driver.Gate drivers are by a plurality of gate line to export signal come more in multiple pixels of opening display device
Individual sub-pixel.When clock pulse generator receives first mode signal, clock pulse generator sequentially exports the clock pulse letter of multiple high level
Number to gate drivers.When clock pulse generator receives second mode signal, clock pulse generator is in first period output enable
Clock signal to gate drivers, and clock pulse generator in second phase output enable clock signal to gate drivers.
Another aspect that the present invention discloses is on a kind of display device, and this display device includes panel, panel, grid and driven
Dynamic device and source electrode driver.Panel includes multiple pixels, and the wherein each of those pixels includes multiple sub-pixels.Clock pulse produces
Device is producing the first clock signal, the second clock signal, the 3rd clock signal and the 4th clock signal.Work as clock pulse generator
When receiving first mode signal, clock pulse generator operates in first mode, and clock pulse generator sequentially exports first in first mode
To the 4th clock signal.When clock pulse generator receives second mode signal, clock pulse generator operates in second mode, second
Under pattern, clock pulse generator exports enable in first and second clock signal of first period output enable, and in the second phase
The the 3rd and the 4th clock signal.Gate drivers pass through first grid polar curve, second gate line, the 3rd gate line and the 4th grid
Polar curve is respectively coupled to those sub-pixels for being arranged in the first row, those sub-pixels for being arranged in the second row, is arranged in the third line
Those sub-pixels and be arranged in those sub-pixels of fourth line.Source electrode driver is respectively coupled to this by a plurality of data lines
A little sub-pixels.Source electrode driver in first period outputting data signals to those sub-pixels for being arranged in first and second row, and
In second phase outputting data signals to those sub-pixels for being arranged in the 3rd and fourth line.
Therefore, technique according to the invention content, the embodiment of the present invention provide a kind of display device and its clock pulse generator,
Using reduces the switching frequency of gate drivers or even source electrode driver, to reach the purpose of energy-conservation.
Brief description of the drawings
Fig. 1 is the schematic diagram for the display device drawn according to embodiments of the disclosure of the present invention.
Fig. 2 is the waveform diagram drawn according to embodiments of the disclosure of the present invention.
Fig. 3 for the clock pulse generator of display device as shown in Figure 1 drawn according to embodiments of the disclosure of the present invention with
Gate drivers schematic diagram.
Fig. 4 is the panel schematic diagram for the display device as shown in Figure 1 drawn according to embodiments of the disclosure of the present invention.
Fig. 5 is the panel schematic diagram for the display device as shown in Figure 1 drawn according to embodiments of the disclosure of the present invention.
Wherein, reference：
100：Display device GS1~GS6：Signal
110：Clock pulse generator HC1~HC6：Clock signal
120：Gate drivers M1, M2：Mode signal
130：Source electrode driver SP11~SP46：Sub-pixel
140：Panel SR1~SR6：Shift registor
D1~D12：Data wire T1~T4：Period
DS1~DS12：Data-signal VST：Initial signal
G1~G6：Gate line
Embodiment
It is hereafter to coordinate institute's accompanying drawings to elaborate for embodiment, to more fully understand the aspect of the present invention, but is carried
The embodiment of confession simultaneously is not used to limit the scope that this announcement is covered, and the description of structure operation is not used to limit the suitable of its execution
Sequence, any structure reconfigured by element is produced to have equal and other effects device, is all the scope that this announcement is covered.
In addition, according to the standard and practice of industry, schema is mapped only for the purpose of aid illustration not according to full size, actual
The size of upper various features can be increased or decreased arbitrarily in order to illustrate.Similar elements will be with identical symbol in the description below
Indicate to illustrate in order to understand.
In word (terms) used in full piece specification and claim, in addition to having and especially indicating, generally have
Each word using in the content disclosed in this area, at this with the usual meaning in special content.It is some describing this
Invent disclose word by it is lower or this specification other places discuss, taken off with providing those skilled in the art in the relevant present invention
Extra guiding in the description shown.
In addition, used word "comprising", " comprising ", " having ", " containing " etc. in the present invention, are opening
Term, that is, mean " including but not limited to ".
Fig. 1 is the schematic diagram for the display device 100 drawn according to embodiments of the disclosure of the present invention.As illustrated, display
Device 100 includes clock pulse generator 110, gate drivers 120, source electrode driver 130 and panel 140.Above-mentioned clock pulse generator
110 to produce multiple clock signal HC1~HC6 with control gate driver 120, and gate drivers 120 can be by a plurality of
1~G6 of gate lines G with export multiple sub-pixel SP11 that signal is come in multiple pixels of opening display device 100~
SP16, SP21~SP26, SP31~SP36, SP41~SP46 ... etc..In addition, clock pulse generator 110 more with believing in a receiving mode
Number (such as mode signal M1, M2).
To make the operation of the clock pulse generator 110 of the present invention it can be readily appreciated that also referring to Fig. 2, it is according to the present invention
The waveform diagram that embodiments of the disclosure is drawn.When clock pulse generator 110 receive first mode signal (such as mode signal M1 and
M2 is low level) when, clock pulse generator 110 sequentially exports clock signal HC1~HC6 of multiple high level to grid in period T1
Driver 120.Furthermore when clock pulse generator 110 receives second mode signal (such as mode signal M1 and M2 is high level)
When, clock pulse generator 110 in period T2 output enables clock signal HC1, HC2 to gate drivers 120, and clock pulse generator
110 in period T3 output enables clock signal HC3, HC4 to gate drivers 120.
As described above, during the foundation of gate drivers 120 clock signal HC1, HC2 of the enable that T2 is received and it is simultaneously defeated
Go out signal GS1, GS2 as shown in Figure 1, in other words, gate drivers 120 are in period T2 according to clock signal HC1, HC2
To export signal GS1, GS2 to those picture for being arranged in first and second row by first and second gate lines G 1, G2
Plain SP11~SP16, SP21~SP26.Because those sub-pixels SP11~SP16, the SP21~SP26 of first and second row are same
Shi Kaiqi, therefore, source electrode driver 130 can charge to two places pixels simultaneously in same period, and then reduce grid and drive
The switching frequency of dynamic device 120 or even source electrode driver 130, to reduce power consumption.Similarly, gate drivers 120 are in period T3
According to clock signal HC3, HC4 to pass through the 3rd and the 4th gate lines G 3, G4 exports signal GS3, GS4 as shown in Figure 1
To those sub-pixels SP31~SP36, the SP41~SP46 for being arranged in the 3rd and fourth line, gate drivers 120 are reduced to reach
Or even the purpose of the switching frequency of source electrode driver 130.
In one embodiment, referring to Fig. 1, panel 140 includes multiple pixels, each of these pixels includes multiple times
Pixel SP11~SP16, SP21~SP26, SP31~SP36, SP41~SP46 ... etc..In certain embodiments, panel 140
Pixel can be made up of SP11~SP16, SP21~SP26, another pixel of panel 140 can by SP31~SP36, SP41~
SP46 is formed.In addition, gate drivers 120 pass through first grid polar curve G1, second gate line G2, the 3rd gate lines G 3 and
Four gate lines Gs 4 are respectively coupled to those sub-pixels SP11~SP16 for being arranged in the first row, those picture for being arranged in the second row
Plain SP21~SP26, those sub-pixels SP31~SP36 for being arranged in the third line and those sub-pixels for being arranged in fourth line
SP41~SP46.Furthermore source electrode driver 130 by a plurality of data lines D1~D12 be respectively coupled to those sub-pixels SP11~
SP16, SP21~SP26, SP31~SP36, SP41~SP46 ... etc..So the present invention is not with the structure depicted in above-described embodiment
It is limited, it is only illustratively illustrating one of implementation of the present invention.
In another embodiment, also referring to Fig. 1 and Fig. 2, clock pulse generator 110 is producing the first clock signal
HC1, the second clock signal HC2, the 3rd clock signal HC3, the 4th clock signal HC4, the 5th clock signal HC5 and the 6th clock pulse
Signal HC6.When clock pulse generator 110 receives first mode signal (such as mode signal M1 and M2 is low level), clock pulse production
Raw device 110 sequentially exports first to the 6th clock signal HC1~HC6 in period T1.Then, gate drivers 120 are in period T1
Signal GS1~GS6 to first is sequentially exported to the 6th gate lines G 1 according to first to the 6th clock signal HC1~HC6
~G6, sequentially to open first to the 6th 1~G6 of gate lines G of coupling those sub-pixels.
In another embodiment, also referring to Fig. 1 and Fig. 2, when clock pulse generator 110 receives second mode signal (such as
Mode signal M1 and M2 are high level) when, clock pulse generator 110 is in first and second clock pulse letter of period T2 output high level
Number HC1, HC2 are to gate drivers 120.Then, gate drivers 120 in period T2 according to first and second clock signal HC1,
HC2 exports signal GS1, GS2 to the first row for being arranged in panel 140 to pass through first grid polar curve G1 and second gate line G2
With those sub-pixels SP11~SP16, the SP21~SP26 of the second row, and open above-mentioned sub-pixel SP11~SP16, SP21~
SP26.Furthermore source electrode driver 130 is in period T2 outputting data signals to those sub-pixels for being arranged in first and second row
SP11~SP16, SP21~SP26.
In another embodiment, also referring to Fig. 1 and Fig. 2, when clock pulse generator 110 receives second mode signal (such as
Mode signal M1 and M2 are high level) when, clock pulse generator 110 is in the 3rd and the 4th clock pulse letter of period T3 output high level
Number HC3, HC4 are to gate drivers 120.Then, gate drivers 120 in period T3 according to the 3rd and the 4th clock signal HC3,
HC4 by the 3rd gate lines G 3 and the 4th gate lines G 4 to export signal GS3, GS4 to the third line for being arranged in panel 140
With those sub-pixels SP31~SP36, the SP41~SP46 of fourth line, and open above-mentioned sub-pixel SP31~SP36, SP41~
SP46.Furthermore source electrode driver 130 is in period T3 outputting data signals to those sub-pixels for being arranged in the 3rd and fourth line
SP31~SP36, SP41~SP46.In addition, clock pulse generator 110 is similar to clock pulse generator 110 in period T4 mode of operation
In period T2 or period T3 mode of operation, those sub-pixels of the fifth line and the 6th row that are arranged in panel 140 can be by grid
Driver 120 is opened, then by the outputting data signals of source electrode driver 130 to those sub-pixels.So the present invention is not with above-mentioned implementation
Mode of operation described in example is limited, and it is only illustratively illustrating one of implementation of the present invention.
Referring to Fig. 2, in one embodiment, period T2 and period T3 sequentially occur.It is high also referring to period T2, T3
First and second clock signal HC1, HC2 of level pulse width be same as high level the 3rd and the 4th clock signal HC3,
HC4 pulse width.In another embodiment, period T2, period T3, period T4 sequentially occur.In period T2~T4, high level
First and second clock signal HC1, HC2 pulse width, high level the 3rd and the 4th clock signal HC3, HC4 pulse
The 5th of width and high level is identical with the 6th clock signal HC5, HC6 pulse width.So the present invention is not with Fig. 2 embodiments institute
The waveform illustrated is limited, and it is only illustratively illustrating one of implementation of the present invention.
In another embodiment, receive second mode signal in clock pulse generator 110 (such as mode signal M1 and M2 is height
Level) in the state of, clock pulse generator 110 exports initial signal VST to gate drivers 120, so that gate drivers 120
According to clock signal HC1, HC2 of initial signal VST and high level to export signal GS1~GS2.
Fig. 3 is the clock pulse generator for the display device 100 as shown in Figure 1 drawn according to embodiments of the disclosure of the present invention
110 with the schematic diagram of gate drivers 120.Also referring to Fig. 2 and Fig. 3, LC1/LC2 control shift registors SR1~SR6 is kept
Low-voltage output, the signal GS1~GS6 for making every 1~G6 of gate lines G outputs is low-voltage.
Referring to Fig. 3, gate drivers 120 include the first shift registor SR1, the second shift registor SR2, the 3rd shifting
Position buffer SR3 and the 4th shift registor SR4.When clock pulse generator 110 receives second mode signal, clock pulse generator
110 output enabling signal VST, the first shift registor SR1 believe to receive the first clock signal HC1 according to above-mentioned startup
Number VST and the first clock signal HC1 is to decide whether to export signal GS1 by first grid polar curve G1.Second shift register
Device SR2 is to receive the second clock signal HC2, and according to above-mentioned enabling signal VST and the second clock signal HC2 to decide whether
Signal GS2 is exported by second gate line G2.
In another embodiment, the 3rd shift registor SR3 is to receive the 3rd clock signal HC3, and is moved according to first
The the first clock signal HC1 and the 3rd clock signal HC3 that position buffer SR1 is transmitted are defeated by the 3rd gate lines G 3 to decide whether
Go out signal GS3.4th shift registor SR4 is to receive the 4th clock signal HC4, and according to the second shift registor
The the second clock signal HC2 and the 4th clock signal HC4 that SR2 is transmitted with decide whether by the 4th gate lines G 4 export grid believe
Number GS4.In another embodiment, the 5th shift registor SR5, the 6th shift registor SR6, or even remaining follow-up displacement are temporary
The type of drive of storage is similar to the 3rd shift registor SR3 and the 4th shift registor SR4 type of drive, to make this hair
It is clean to speak frankly bright letters, is not repeated in this.
Fig. 4 is the panel signal for the display device 100 as shown in Figure 1 drawn according to embodiments of the disclosure of the present invention
Figure.Fig. 5 is the panel schematic diagram for the display device 100 as shown in Figure 1 drawn according to embodiments of the disclosure of the present invention.It must say
Bright, the framework of the panel 140A shown in Fig. 4 is substantially identical with the panel 140 shown in Fig. 1, and the panel shown in Fig. 5
140B pixel structure is using staggeredly coupling (Zig-Zag) framework, with the difference of the panel 140 shown in Fig. 1, is described in detail such as
Afterwards.
Referring to Fig. 4, as the sub-pixel SP11~SP16 and SP21~SP26 while quilt that are arranged in the first row and the second row
When signal GS1, GS2 is opened, the first data wire D1 and the 4th data wire D4 provide the data-signal of identical voltage respectively
DS1, DS4 are to sub-pixel SP11, SP21 and SP14, SP24；Second data wire D2 and the 5th data wire D5 provide identical electricity respectively
Data-signal DS2, DS5 of pressure are to sub-pixel SP12, SP22 and SP15, SP25；D6 points of 3rd data wire D3 and the 6th data wire
Indescribably for identical voltage data-signal DS3, DS6 to sub-pixel SP13, SP23 and SP16, SP26.In another embodiment, it is secondary
Pixel SP31~SP36, SP41~SP46, so remaining sub-pixel type of drive be similar to sub-pixel SP11~SP16 and
SP21~SP26 type of drive, to make description of the invention succinct, do not repeated in this.
Referring to Fig. 5, source electrode driver 130 shown in Fig. 1 by data wire D1~D12 each with panel 140B's
Those sub-pixels SP11~SP16, SP21~SP26, SP31~SP36, SP41~SP46 ... staggeredly couple (Zig-Zag) so that
It is identical with the light color that the sub-pixel that those data wires D1~D12 same data line couples is sent.For example, data
Line D1 is staggeredly coupled to sub-pixel SP11 (on the left of data wire D1), sub-pixel SP22 (on the right side of data wire D1), secondary picture
Plain SP31 (on the left of data wire D1), sub-pixel SP42 (on the right side of data wire D1) ... etc., and it is secondary as can be seen from Figure
Pixel SP11, SP22, SP31, SP42 are all same color sub pixels (it should be noted that the secondary picture indicated in figure with identical site
Element is the sub-pixel of same color).In one embodiment, the staggeredly mode between data wire D2~D12 and sub-pixel is similar to
Staggeredly mode between data wire D1 and sub-pixel, to make description of the invention succinct, is not repeated in this.
In another embodiment, referring to Fig. 5, when be arranged in the first row and the second row sub-pixel SP11~SP16 and
SP21~SP26 is opened by signal GS1, GS2 simultaneously when, the first data wire D1 and the 4th data wire D4 provide identical respectively
Data-signal DS1, DS4 of voltage are to sub-pixel SP11, SP22 and SP14, SP25；Second data wire D2 and the 5th data wire D5
Data-signal DS2, DS5 of identical voltage are provided respectively to sub-pixel SP12, SP23 and SP15, SP26；3rd data wire D3 and
6th data wire D6 provides data-signal DS3, DS6 of identical voltage on the right side of sub-pixel SP13, SP24 and SP16, SP26 respectively
Sub-pixel.In addition, sub-pixel SP31~SP36, SP41~SP46, or even the type of drive of remaining sub-pixel are similar to time picture
Plain SP11~SP16 and SP21~SP26 type of drive, to make description of the invention succinct, do not repeated in this.
From the invention described above embodiment, there are following advantages using the present invention.The embodiment of the present invention is by offer
A kind of display device and its clock pulse generator, use the switching frequency for reducing gate drivers or even source electrode driver, with up to
To the purpose of energy-conservation.
The usual skill of technical field will be readily understood that embodiments of the disclosure realizes the excellent of one or more foregoing citings
Point.After reading aforementioned specification, the usual skill of technical field will be able to as disclosure herein makees multiple types
Change, displacement, equivalent and various other embodiments.Therefore protection scope of the present invention is worked as and defined depending on claim
Based on person and its equivalency range.
Claims (10)
1. a kind of clock pulse generator, it is characterised in that to produce multiple clock signals to control a gate drivers, wherein should
Gate drivers open multiple times in multiple pixels of a display device by a plurality of gate line to export a signal
Pixel；
Wherein when the clock pulse generator receives a first mode signal, the clock pulse generator sequentially export those high level when
Arteries and veins signal is to the gate drivers, wherein when the clock pulse generator receives a second mode signal, the clock pulse generator is in one
Those clock signals of first period output enable are to the gate drivers, and the clock pulse generator is exported in a second phase and caused
Can those clock signals to the gate drivers.
2. clock pulse generator as claimed in claim 1, it is characterised in that the clock pulse generator is believed to produce one first clock pulse
Number, one second clock signal, one the 3rd clock signal and one the 4th clock signal, wherein when the clock pulse generator receive this
During two modes signal, the clock pulse generator in first period output high level this first with second clock signal to the grid
Driver, the gate drivers according to this first with second clock signal to pass through a first grid polar curve and a second grid
Line exports the signal to the first row for being arranged in the display device and those sub-pixels of the second row.
3. clock pulse generator as claimed in claim 2, it is characterised in that the clock pulse generator is believed to produce the 3rd clock pulse
Number and the 4th clock signal, wherein when the clock pulse generator receives the second mode signal, the clock pulse generator is in this
The 3rd of second phase output high level with the 4th clock signal to the gate drivers, the gate drivers according to this
Three is aobvious to this is arranged in export the signal by one the 3rd gate line and one the 4th gate line with the 4th clock signal
The third line of showing device and those sub-pixels of fourth line.
4. clock pulse generator as claimed in claim 3, it is characterised in that the first period and the second phase sequentially occur,
This of high level first is same as the 3rd of high level and the 4th clock signal with the pulse width of second clock signal
Pulse width.
5. the clock pulse generator as described in any one of Claims 1-4, it is characterised in that the clock pulse generator receive this
In the state of two modes signal, the clock pulse generator exports an initial signal to the gate drivers, so that the gate drivers
According to those clock signals of the initial signal and high level to export signal.
6. a kind of display device, it is characterised in that include：
One panel, comprising multiple pixels, the wherein each of those pixels includes multiple sub-pixels；
One clock pulse generator, to produce one first clock signal, one second clock signal, one the 3rd clock signal and one
Four clock signals, wherein when the clock pulse generator receives a first mode signal, the clock pulse generator operates in one first mould
Formula, the clock pulse generator sequentially export first to the 4th clock signal in the first mode；Wherein when the clock pulse generator
When receiving a second mode signal, the clock pulse generator operates in a second mode, and in this second mode, the clock pulse produces
Device in a first period output enable this first with second clock signal, and in a second phase output enable the 3rd
With the 4th clock signal；
One gate drivers, pass through a first grid polar curve, a second gate line, one the 3rd gate line and one the 4th gate line point
Be not coupled to those sub-pixels for being arranged in the first row, those sub-pixels for being arranged in the second row, be arranged in the third line those
Sub-pixel and those sub-pixels for being arranged in fourth line；And
One source driver, those sub-pixels are respectively coupled to by a plurality of data lines, wherein the source electrode driver in this first
Period exports a data-signal to those sub-pixels for being arranged in first and second row, and data letter is exported in the second phase
Number to those sub-pixels for being arranged in the 3rd and fourth line.
7. display device as claimed in claim 6, it is characterised in that in the first mode, when the gate drivers sequentially
Receive this first to four clock signals when, the gate drivers sequentially export a signal to this first to the 4th
Gate line, sequentially to open those sub-pixels for coupling first to the 4th gate line, wherein in this second mode, the grid
Driver in the first period according to this first with second clock signal with by this first with the second gate line export
The signal to those sub-pixels for being arranged in first and second row, and in the second phase according to the 3rd with the 4th when
Arteries and veins signal with by the 3rd with the 4th gate line export the signal to those picture for being arranged in the 3rd and fourth line
Element.
8. display device as claimed in claim 7, it is characterised in that when the clock pulse generator receives the second mode signal
When, the clock pulse generator exports an enabling signal in the first period, and the wherein gate drivers include：
One first shift registor, to receive first clock signal, and according to the enabling signal and first clock signal
To decide whether to export the signal by the first grid polar curve；And
One second shift registor, to receive second clock signal, and according to the enabling signal and second clock signal
To decide whether to export the signal by the second gate line.
9. display device as claimed in claim 8, it is characterised in that the gate drivers further include：
One the 3rd shift registor, to receive the 3rd clock signal, and according to first clock signal and the 3rd clock pulse
Signal is to decide whether to export the signal by the 3rd gate line；And
One the 4th shift registor, to receive the 4th clock signal, and according to second clock signal and the 4th clock pulse
Signal is to decide whether to export the signal by the 4th gate line.
10. display device as claimed in claim 9, it is characterised in that the source electrode driver passes through each of those data wires
Person and those sub-pixels of the panel staggeredly couple, wherein those sub-pixels with the same data line coupling of those data wires
The light color sent is identical.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711019628.6A CN107833550A (en) | 2017-10-27 | 2017-10-27 | Display device and its clock pulse generator |
| TW107119528A TWI680677B (en) | 2017-10-27 | 2018-06-06 | Displayer and clock generator thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711019628.6A CN107833550A (en) | 2017-10-27 | 2017-10-27 | Display device and its clock pulse generator |
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| CN107833550A true CN107833550A (en) | 2018-03-23 |
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| CN201711019628.6A Pending CN107833550A (en) | 2017-10-27 | 2017-10-27 | Display device and its clock pulse generator |
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| TW (1) | TWI680677B (en) |
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| TW201918063A (en) | 2019-05-01 |
| TWI680677B (en) | 2019-12-21 |
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