TWI678061B - Digital linear regulator and a power mos array thereof - Google Patents

Abstract

A power metal oxide semiconductor array suitable for a digital linear regulator includes a plurality of metal oxide semiconductor circuits. Each metal oxide semiconductor circuit includes a first metal oxide semiconductor transistor and a second metal oxide semiconductor transistor. Electrically connected in series between the power supply and the output node of the digital linear regulator. The first metal oxide semiconductor transistor is used as a current source and is controlled by the output voltage of the output node.

Description

Digital linear regulator and power metal oxide semiconductor array

The invention relates to a linear regulator, in particular to a digital linear regulator with a dynamic current source power metal oxide semiconductor (MOS) array.

A linear voltage regulator, such as a low-dropout regulator, is a DC linear voltage regulator that can be adapted to regulate the output voltage. Because of its small size and simple design, it is commonly used in single-chip systems (system on chip) to provide individual voltages. Digital linear regulators are preferred for modern systems due to their low voltage operation.

When a traditional digital linear regulator is in an unstable transient state (such as overshoot or undershoot voltage), it must wait for the next clock cycle or / and the analog-to-digital conversion (ADC) conversion time. Therefore the reply is slower or consumes more power. Although some digital linear regulators have improved transient recovery or lower power consumption, digital linear regulators can interfere with other circuits with the same ground.

Therefore, a novel digital linear regulator is urgently needed to overcome the lack of traditional digital linear regulators.

In view of the foregoing, one object of the embodiments of the present invention is to provide a digital linear regulator with a dynamic current source power metal-oxide-semiconductor (MOS) array.

According to an embodiment of the present invention, a power metal oxide semiconductor array suitable for a digital linear regulator includes a plurality of metal oxide semiconductor circuits. Each metal oxide semiconductor circuit includes a first metal oxide semiconductor transistor and a second metal oxide semiconductor transistor, which are electrically connected in series between the power source and the output node of the digital linear regulator. The first metal oxide semiconductor transistor is used as a current source and is controlled by the output voltage of the output node.

FIG. 1A shows a block diagram of a digital linear regulator 100 with a dynamic current source power metal-oxide semiconductor (MOS) array according to an embodiment of the present invention. FIG. 1B illustrates a detailed block diagram of part 1A . The digital linear regulator 100 of this embodiment is applicable to a system on chip to provide individual voltages.

In this embodiment, the digital linear regulator 100 may include a fine-loop controller 11 and a fine-tuned power metal oxide semiconductor array (hereinafter referred to as a fine-tuned power array) 12. In a steady state, the regulated output voltage Vout of the digital linear regulator 100 is stable, and the trimming loop controller 11 can turn on the trimming power array 12, which includes a complex trimming power metal oxide semiconductor transistor to generate an output Voltage Vout. The load 10 is connected between the output voltage Vout and the ground to receive the output voltage Vout.

The digital linear regulator 100 may include a coarse-loop controller 13 and a coarse-tuned power metal oxide semiconductor array (hereinafter referred to as a coarse-tuned power array) 14. In the transient state (transient state or unstable state), the regulated output voltage Vout of the digital linear regulator 100 is unstable. The coarse adjustment loop controller 13 can turn on the coarse adjustment power array 14, which includes complex coarse adjustment power metal oxidation. A semiconductor transistor to generate an output voltage Vout. Generally, the size of the coarse-tuned power metal oxide semiconductor transistor of the coarse-tuned power array 14 is larger than that of the fine-tuned power metal-oxide semiconductor transistor of the fine-tuned power array 12.

The digital linear regulator 100 in this embodiment may include an analog-to-digital converter (ADC) and a state circuit 15 for performing analog-to-digital conversion, and determine the current state of the digital linear regulator 100 according to the output voltage Vout (that is, Steady state or transient).

The analog-to-digital converter and state circuit 15 of this embodiment may include a comparator 151 that receives the output voltage Vout of the digital linear regulator 100 and the (preset) reference voltage Vref to generate a comparison signal V _comp . The analog-to-digital converter and state circuit 15 may include an analog-to-digital converter (ADC) 152 for generating a (digital) analog-to-digital conversion output, which is the difference between the output voltage Vout and the reference voltage Vref. The analog-to-digital converter and status circuit 15 may include a status circuit 153 that generates an event signal ENT according to the analog-to-digital conversion output to represent the current status.

The trimming loop controller 11 of this embodiment mainly includes a trimming loop shift register 111 that receives a comparison signal V _comp and generates a trimming shift output F accordingly. The trimming loop shift register 111 may include a flip flop (not shown) connected in series, and is controlled by the first clock signal CLK_f. According to one of the features of this embodiment, the trimming loop shift register 111 can be turned on by the event signal ENT, which can save power during the steady state. When the event signal ENT is de-asserted, indicating that the output voltage Vout is stable and steady, the trimming loop shift register 111 is turned on.

The coarse-tuning _loop controller 13 in this embodiment mainly includes a coarse-tuning _loop shift register 131, which receives a comparison signal _Vcomp and generates a coarse-shift shift output C accordingly. The coarse-adjustment loop shift register 131 may receive an analog-to-digital conversion output to accelerate the shift. The coarse-tuning loop shift register 131 may include a flip flop (not shown) connected in series, and is controlled by the second clock signal CLK_c, which is faster than the first clock signal CLK_f. According to another feature of this embodiment, the coarse adjustment loop shift register 131 can be turned off by the event signal ENT, and power can be saved during the steady state. When the event signal ENT is asserted, indicating that the output voltage Vout is unstable, the coarse adjustment loop shift register 131 is turned on. On the other hand, when the event signal ENT is de-asserted, indicating that the output voltage Vout is stable and steady, the coarse-tuning loop shift register 131 is turned off.

The second A diagram shows a circuit diagram of the trimming power array 12 of the first A diagram. The trimming power array 12 (self-trimming loop shift register 111) receives the trimming shift output F, thereby generating an output voltage Vout. In this embodiment, the trimming power array 12 may include a plurality of metal oxide semiconductor transistors M0 in parallel, such as a P-type metal oxide semiconductor transistor (PMOS), whose sources are electrically connected to the power source Vdd and their drains, respectively. Each is electrically connected to an output node, which provides an output voltage Vout. The gates of the metal oxide semiconductor transistor M0 are respectively electrically connected to the bits of the trimming shift output F.

The second B diagram shows a circuit diagram of the coarse-tuned power array 14 of the first A diagram. The coarse adjustment power array 14 (from the coarse adjustment loop shift register 131) receives the coarse adjustment shift output C, and generates an output voltage Vout accordingly. In this embodiment, the coarse-tuned power array 14 may include a plurality of metal oxide semiconductor circuits 141. According to another feature of this embodiment, each metal oxide semiconductor circuit 141 may include a first metal oxide semiconductor transistor (such as a P-type metal oxide semiconductor transistor) M1 and a second metal oxide semiconductor transistor (such as P-type metal oxide semiconductor transistor) M2, which is electrically connected in series between the power source Vdd and the output node (which provides the output voltage Vout). The source of the first metal oxide semiconductor transistor M1 is electrically connected to the power source Vdd, the drain thereof is electrically connected to the source of the second metal oxide semiconductor transistor M2, and the gate thereof is electrically connected to the second The drain and output node of the metal oxide semiconductor transistor M2 (which provides the output voltage Vout). The gates of the second metal oxide semiconductor transistor M2 are respectively electrically connected to the bits of the coarse-adjustment shift output C. In another embodiment, the trimming power array 12 may also use the circuit architecture of the second B diagram.

FIG. 2C shows an equivalent circuit of the metal oxide semiconductor circuit 141 of FIG. 2B. In this embodiment, the first metal oxide semiconductor transistor M1 is used as a current source and is controlled by the output voltage Vout. The first metal-oxide-semiconductor transistor M1 provides a source-to-drain current I _{SD (M1)} and flows to an output node (which provides an output voltage Vout). The load 10 thus obtains a load current I _load , which includes the source-to-drain current I _{SD (M1)} provided by all the metal-oxide semiconductor circuits 141. In the up transient state (that is, the load current I _load changes from low to high), if the output voltage Vout decreases, the current source (that is, the first metal oxide semiconductor transistor M1) provides more resistance due to the decrease in impedance. With multiple source-to-drain currents I _{SD (M1)} , the undershoot of the output voltage Vout can be reduced. In addition, the output voltage Vout can be recovered from the unstable state in a short time. On the other hand, during the down transient state (that is, the load current I _load changes from high to low), if the output voltage Vout rises, the current source (that is, the first metal oxide semiconductor transistor M1) due to the impedance It increases to provide less source-to-drain current I _{SD (M1)} , and the overshoot of the output voltage Vout can be reduced. In addition, the output voltage Vout can be recovered from the unstable state in a short time.

The third figure shows the waveforms of the related signals of the digital linear regulator 100 in the first B figure. In state 1 (ie, steady state), the output voltage Vout is stable, and its amplitude is within the voltage window (Vref ± ΔV). In the steady state, the coarse-tuning loop shift register 131 is turned off, but the fine-tuning loop shift register 111 is turned on to enable the fine-tuning power array 12 to provide the output voltage Vout. In general, the fine-tuned power array 12 (and the fine-tuned loop shift register 111) is slower than the coarse-tuned power array 14 (and the coarse-tuned loop shift register 131), consumes less power, and generates higher power. Output voltage accuracy. Since the trimming power array 12 (and the trimming loop shift register 111) consumes less power, the digital linear regulator 100 can reduce long-term power consumption.

In state 2 (ie, transient state), the output voltage Vout is unstable, and its overshoot or undershoot voltage exceeds the voltage window (Vref ± ΔV). In the transient state, the fine-tuning loop shift register 111 is closed, but the coarse-tuning loop shift register 131 is turned on to activate the coarse-adjustment power array 14 to provide the output voltage Vout. Because the operation speed of the coarse adjustment power array 14 (and the coarse adjustment circuit shift register 131) is fast, the output voltage Vout can be recovered from an unstable situation in a short time.

According to the above embodiment, the digital linear regulator 100 provides a dual-loop control mechanism to generate the output voltage Vout. Among them, in the steady state, the trimming power array 12 and the trimming loop controller 11 form a trimming loop, which has lower power consumption and higher accuracy of output voltage. On the other hand, in the transient state, the coarse adjustment power array 14 and the coarse adjustment loop controller 13 form a coarse adjustment loop, which has a fast operating speed.

The fourth graph shows the waveforms of the relevant signals of the coarse-tuned power array 14 of the second B graph. According to one of the features of the coarse-tuned power array 14 of this embodiment, the first metal oxide semiconductor transistor M1 is used as a current source and is controlled by the output voltage Vout. The dotted line in the fourth figure shows a waveform of a signal related to the coarse adjustment power array 14 without using the first metal oxide semiconductor transistor M1. According to this embodiment, other circuits that are grounded the same as the digital linear regulator 100 are not interfered by the digital linear regulator 100.

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the invention should be included in the following Within the scope of patent application.

100‧‧‧ digital linear regulator

10‧‧‧ load

11‧‧‧Fine-tuning loop controller

111‧‧‧Fine-tuning loop shift register

12‧‧‧Fine-tuning power metal oxide semiconductor array

13‧‧‧Coarse adjustment loop controller

131‧‧‧Coarse adjustment loop shift register

14‧‧‧Coarse-tuned power metal oxide semiconductor array

141‧‧‧ metal oxide semiconductor circuit

15‧‧‧ Analog to Digital Converter and State Circuit

151‧‧‧ Comparator

152‧‧‧ Analog to Digital Converter

MOS‧‧‧ Metal Oxide Semiconductor

Vout‧‧‧Output voltage

Vref‧‧‧Reference voltage

V _comp ‧‧‧ comparison signal

ENT‧‧‧Event Signal

CLK_f‧‧‧ the first clock signal

CLK_c‧‧‧Second clock signal

F‧‧‧fine-tuning shift output

C‧‧‧Coarse adjustment shift output

M0‧‧‧ metal oxide semiconductor transistor

M1‧‧‧The first metal oxide semiconductor transistor

M2‧‧‧Second metal oxide semiconductor transistor

Vdd‧‧‧ Power

I _{SD (M1)} ‧‧‧Source-to-drain current

I _load ‧‧‧ load current

FIG. 1A shows a block diagram of a digital linear regulator with a dynamic current source power metal oxide semiconductor (MOS) array according to an embodiment of the present invention. The first B diagram illustrates a detailed block diagram of a part of the first A diagram. The second A diagram shows a circuit diagram of the fine-tuned power array of the first A diagram. The second diagram B shows a circuit diagram of the coarse-tuned power array of the first diagram A. Figure 2C shows the equivalent circuit of the metal oxide semiconductor circuit in Figure 2B. The third graph shows the waveforms of the related signals of the digital linear regulator of the first B graph. The fourth graph shows the waveforms of the relevant signals of the coarse-tuned power array of the second B graph.

Claims (13)

A power metal oxide semiconductor array suitable for a digital linear regulator, comprising: a plurality of metal oxide semiconductor circuits, each of which includes a first metal oxide semiconductor transistor and a second metal oxide semiconductor transistor , Which is electrically connected in series between the power source and the output node of the digital linear regulator; wherein the first metal oxide semiconductor transistor is used as a current source and is controlled by the output voltage of the output node. The power metal-oxide-semiconductor array according to item 1 of the patent application scope, wherein the first metal-oxide-semiconductor transistor comprises: a source electrode electrically connected to the power source; a drain electrode electrically connected to the second metal A source of the oxide semiconductor transistor; and a gate electrode, which is electrically connected to the drain of the second metal oxide semiconductor transistor and the output node. According to the power metal-oxide-semiconductor array according to item 2 of the patent application scope, wherein the second metal-oxide-semiconductor transistor includes a gate electrode, which is electrically connected to a corresponding bit of a shift output of the shift register. A digital linear regulator includes: a fine-tuned power metal oxide semiconductor array; a fine-tuning loop controller that turns on the fine-tuned power metal-oxide semiconductor array in a steady state to generate an output voltage of the digital linear regulator; Power-adjusted metal oxide semiconductor array; a coarse-tuned loop controller that turns on the coarse-tuned power metal-oxide semiconductor array in a transient state to generate the output voltage; wherein the coarse-tuned power metal-oxide semiconductor array includes a plurality of metal oxides Each of the metal oxide semiconductor circuits includes a first metal oxide semiconductor transistor and a second metal oxide semiconductor transistor, which are electrically connected in series between a power source and an output node providing the output voltage, and the The first metal oxide semiconductor transistor acts as a current source and is controlled by the output voltage. The digital linear regulator according to item 4 of the scope of patent application, wherein the first metal oxide semiconductor transistor comprises: a source electrode electrically connected to the power source; a drain electrode electrically connected to the second metal oxide A source of the semiconductor transistor; and a gate electrode, which is electrically connected to a drain of the second metal oxide semiconductor transistor and the output node. According to the digital linear regulator according to item 5 of the patent application scope, wherein the second metal oxide semiconductor transistor includes a gate electrode, which is electrically connected to a corresponding bit of the shift output of the coarse-tuning loop controller. According to the digital linear regulator described in item 4 of the scope of patent application, the digital linear regulator further includes: an analog-to-digital converter and state circuit for analog-to-digital conversion, and determines the current status of the digital linear regulator based on the output voltage. The state is steady state or transient. The digital linear regulator according to item 7 of the scope of the patent application, wherein the analog-to-digital converter and state circuit includes: a comparator that receives the output voltage and a preset reference voltage to generate a comparison signal; and an analog-to- A digital converter for generating an analog-to-digital conversion output, which is the difference between the output voltage and the reference voltage; and a state circuit, according to the analog-to-digital conversion output, to generate an event signal, which represents the current state. According to the digital linear regulator according to item 8 of the scope of patent application, wherein the trimming loop controller includes: a trimming loop shift register, receiving the comparison signal, and generating a trimming shift output for stable state The fine-tuned power metal-oxide-semiconductor array is activated at any time. According to the digital linear regulator according to item 8 of the scope of patent application, wherein the coarse adjustment loop controller includes: a coarse adjustment loop shift register, receiving the comparison signal, and generating a coarse adjustment shift output for The coarse-tuned power metal oxide semiconductor array is activated in a transient state. The digital linear regulator according to item 4 of the scope of patent application, wherein the coarse-tuned power metal oxide semiconductor array includes a plurality of coarse-tuned power metal oxide semiconductor transistors, and the fine-tuned power metal-oxide semiconductor array includes a complex fine-tuned power The metal oxide semiconductor transistor, wherein the size of the coarse-tuned power metal oxide semiconductor transistor is larger than that of the fine-tuned power metal oxide semiconductor transistor. According to the digital linear regulator according to item 4 of the patent application scope, wherein the coarse adjustment loop controller operates faster than the fine adjustment loop controller. The digital linear regulator according to item 4 of the scope of patent application, wherein the fine-tuned power metal-oxide-semiconductor array includes: a plurality of second metal-oxide-semiconductor circuits, each of the second metal-oxide-semiconductor circuits comprising a first metal oxide And a second metal oxide semiconductor transistor are electrically connected in series between the power source and the output node, and the first metal oxide semiconductor transistor of the second metal oxide semiconductor circuit is used as a current source, Controlled by this output voltage.