CN108140614A - Reference generator and current source transistor based on complementary current field effect transistor devices - Google Patents

Abstract

It is existing a kind of to accuracy and to the undesirable sensitivity error of temperature and humidity or the accurate device of the matched larger component count of variation progress and floor space with absolute temperature proportional (PTAT)/and absolute temperature complementarity (CTAT) reference voltage circuit needs.The present invention relates to a kind of novel method of the reference voltage circuit for this N-shaped and p-type electric current field-effect transistor based on the complementation of a pair of of automatic biasing, the method provides track PTAT, track CTAT and analog reference voltage.

Description

Reference generator and current source based on complementary current field effect transistor devices are brilliant Body pipe

Cross reference to related applications

This application claims No. 62/198960 U.S. Provisional Application submitted on July 30th, 2015 and December 17 in 2015 The priority for the 62/268th, No. 983 U.S. Provisional Application that day submits, the content of the application are incorporated in entirety by reference Herein.

Background technology

Technical field

It is described the present invention relates to reference generator and current source transistor based on novel and creative set composite structure Set composite structure realizes the method using subthreshold Value Operations based on charge, and the method is used for design simulation cmos circuit.

Description of related art

The demand of connection is just extremely fast being expanded as the new millennium arrives.To year ends 2015, global network connection number Amount is by beyond twice of world population, and it is more than that 30,000,000,000 devices will be connected wirelessly to high in the clouds and be formed to estimate in the year two thousand twenty Internet of Things (or " IoT ").Realize this new era is the mobile computing and wireless communication occurred in past 20 years Revolutionary development.According to Moore's Law (Moore's Law), high integration and cost-effective silicon complementary metal oxygen are developed Compound semiconductor (CMOS) device allows to merge for example large-scale number such as A/D converter or transceiver and simulation system element Into more cost effective one chip solution.

However, in the past few years, although digital circuit largely has followed predicted path, and from by CMOS Technology expands to sub-micro (sub--μm) and benefits, but analog circuit not yet realizes the same trend that follows, and is simulating It is designed without to realize forever in the case of transfer.Simulation and radio frequency (or " RF ") designer still are making great efforts to visit How rope manufactures high performance integrated circuit (or " IC ") to realize that ultra-deep Asia-μm feature sizes reduce the excellent of size without losing Point；It is reduced comprising power, covering surface is compact and operable frequency higher.The existing board design science of Gonna breakthrough is to meet new thousand The requirement of year system on chip (SoC), needs the transformation in real pattern.

The prior art：

The core structure block of analog circuit is amplifier.Discrete component amplifier freely uses resistor, capacitor, inductance Device, transformer and non-linear element and various types of transistors.It is undesirable between usually negligible various assemblies to post Coming into force should.However, in order to build amplifier in integrated circuit, normal artificial circuit component can not be obtained easily, and if Very will so, the special IC processes of generally use extend to obtain these circuit elements.Due to integrated amplifier extremely Close to and be coupled by the silicon wafer that it is integrated into, therefore the ghost effect on integrated amplifier is more serious. Moore's Law IC technique progress concentrates on number, microprocessor and memory process development.Due to needing a generation (about 18 months) Or two generation to extend IC techniques to be incorporated to simulated assembly, it is therefore general comprising simulation work(on most up-to-date techniques system-on-a-chip Energy.These " mixed mode " IC techniques are not easy to obtain, are limited by Parameters variation dependent on manufacturer and more expensive and height.It needs big It measures engineered in the analog functuion for becoming to include rareness specific on any IC of its IC manufacturer and process node.Due to needle Analog circuit, therefore this kind of analog circuit pole not Portable belt are designed with caution and particularly or arrange to each process node.Due to Repel this limitation, Analog Circuit Design engineer becomes rareness and waits a moment slow retired and substituted without enough.

Operational amplifier (or amplifier) is basic IC analogue gain blocks necessary to processing analog information.Amplifier utilizes crystal High matching is managed to form differential pair of transistors at control source.Matching is the parameter being easily obtained on the integrated, But for the matching for reaching required grade, many Considerations can be used：Identical barycenter layout, the isolation of multiple large-scale plants, trap Degree and physical layout technology and many other Considerations.The matched transistor group of large area is additionally operable to current mirror and load Device.Amplifier needs current source for biasing.Amplifier additionally needs resistor and capacitor (or RC) compensating pole to prevent from shaking It swings.Resistor is essential for " R ", and the value of RC time constants is relatively accurate.The value of resistor is excessive will to be made to put Big device is excessively slow and too small, so as to cause oscillation.Constant " biasing " electric current increases the power of consumption.In general, these are inclined Put peak point current required during electric current wants more than full signal operation.

Since IC techniques are shunk, threshold voltage keeps slightly constant.This is because metal-oxide semiconductor (MOS) (or MOS) threshold Value cut-off curve does not change, and total chip OFF leakage current must be kept small enough to not substantially with the contraction of IC techniques Influence full chip power leakage.The threshold value and saturation voltage often occupy entire supply voltage, so as to not be analog voltage The amplitude of oscillation retains sufficient space.Lack to adapt to this signal swing voltage, amplifier is provided with multigroup current mirror, so as to further Its design is made to become complicated, while consumes more power and uses additional physical layout area.This patent is introduced in power supply electricity Pressure even runs to obtain better Amplifier Design when shrinking far below 1 volt.

Conventional MOS amplifier gains formation is to drive the mutual conductance (g that input voltage is converted into output current_m) input electricity Pressure.This output current then drives output loading, and for the purpose for establishing high load resistance, the output loading is typically electric current The output in source.Output current is converted back to output voltage by this high-resistance load.Equivalent output load resistance is actually negative Carry the parallel combination of current source transistor and amplifier output transistor.In order to make this equivalent load resistance that a high position be kept to carry For required voltage gain, these load transistors must extremely be grown, but in order to drive enough electric currents, these transistors must also It is extremely wide, therefore greatly transistor is necessary.It also might be noted that it is to reduce electricity that amplifier, which exports driven load resistance, Press the additional parallel resistance of gain.It shall yet further be noted that load capacitance is interacted with amplifier output resistance, so as to change AC performances.It is real It is desirable that antipodal operation principle, this is the relevant content of the present invention on border.Fig. 1 a are as the high-quality of baseline reference The transistor level schematic diagram of amount MOS IC amplifiers (comes from Wiley textbooks：《The analysis of Analogous Integrated Electronic Circuits and design (Analysis and Design of Analog Integrated Circuits)》, the works such as Gray, the 4th edition, page 482), it is used for herein Comparison in the description of shown amplifier.

Baseline compares and (is carried out in 180nm IC techniques entirely) in performance curve diagram form, as Fig. 1 b are in V_dd=1.8 Volt and R_cmpBode Gain-Phase curve graphs based on frequency at=700 ohm.As long as possible, in these three comparative graphs All axis scales of each keep identical.The 180nm techniques being easily obtained are selected in this document with more all relatively more real Example is because conventional prior amplifier operates use that is best and having had top, and provides needed for conventional simulation Ripe mixed mode IC process spreads.And since the contraction of IC techniques and supply voltage reduce, this is also the present invention's Embodiment becomes in place of very beneficial.

In general, MOS amplifiers operate due to strong inversion MOS transistor square-law characteristics in square law relationship；These are special Property do not define fully or predictably stablize in the degree needed for analog circuit.As the operation of the exponential laws such as ambipolar transistor operation Then gain higher, stabilization and fully define.Under extremely weak operating condition, MOS transistor is converted into exponent arithmetic, but the crystal Pipe excessively slowly acts on few.In addition, " moderate inversion " transformation between both operation modes, which provides, reduces simulation MOS electricity The non-linarite of the quality on road.Under the threshold voltage about operated in MOS transistor, 50% electric current is square-law, and in addition 50% is exponential law.This is the definition of the threshold voltage in newest MOS simulation equations.Total index number MOS operations under at a high speed will carry For higher gain that is predictable, stablizing and fully define.This patent is in relation to the amplifier that is operated with exponential model.

In order to understand the prior art, we start to discuss weak transoid and strong inversion.With reference to figure 1e and 1f, weak transoid is most Number designer will be considered to the range that transistor is OFF state：

● drain-to-source voltage is small (about 100mV)；

● grid G (or 17s) is in similar small potential (usually less than 300mV)；

● this generates the surface conductive layer of the uniform depth from source S to drain D；

● the electric conductivity of this superficial layer is the index relative to grid G voltage；

● this allows the operation in multiple ten times of (about 6) dynamic ranges；

● raceway groove is rendered as medium value resistor (100⁺S kilohms)；And

● the conducting channel of uniform depth promotes gain higher in exponential law, but has lost speed and (be attributed to conduction Low charge density in raceway groove).

Strong inversion is characterized in that stagewise conducting channel (with reference to figure 1g and 1h), relatively deeply and close at close source electrode It is shallower at drain electrode：

● the threshold value V in gate source voltage Vg and Fig. 1 h of the drain-to-source voltage more than Fig. 1 g_{Threshold value}(usually more than 400mV)；

● grid 17u is higher than its threshold voltage V_{Threshold value}Lower operation；

● this generates at the source electrode relatively depth and gradually decreases at drain electrode 12u the almost conducting channel of pinch off；

● gained conductive layer shows to make square-law response to the grid voltage at grid 17u；

● compared with weak transoid, dynamic range is limited to about 3 ten times；

● raceway groove 12g is rendered as adjustable current source (high resistance resistor)；And

● the wedge-type shape of conducting channel 12g provides the speed higher than weak transoid due to the more high charge density in conducting channel Degree.

Now referring back to Fig. 1 e, the raceway groove 12e development under the conditions of weak transoid is shown.Conducting channel 12e is whole at its There is relatively uniform Carrier Profile in a length and width.It should be noted that on the right side of the conductive depth 10s and Fig. 1 g of entire raceway groove Pinch-off region 12u it is identical.This thin conductive layer is due to channel current is advanced along the surface that carrier defect trap is concentrated Facilitate much noise.Grid 17s in Fig. 1 e to the voltage V of raceway groove_gHave to the carrier density in this conductive layer and (refer to by force very much Number) it influences.

Fig. 1 g show the raceway groove 12u development under the conditions of strong inversion.Higher gesture between source electrode and drain electrode on grid 17u Difference causes " channel length modulation " (flat of raceway groove 12u), and so as to generate pinch off near drain diffusion, raceway groove is described The thin layer close to 12u is terminated at drain diffusion.Pinch-off region 12u (carrier is forced to go to channel top here) passes through surface Defect carrier traps transmit much noise.Drain voltage V_dHigher, pinch-off region is longer, and therefore generated noise is got over Height, it is therefore desirable for keeping low level relatively low to be provided to the noise of channel current this voltage.Thin saturation pinch-off region herein Notice that speed saturation and thermoelectron leap to other effects such as gate oxide, therefore by reducing voltage and semiconductor doping point Cloth is come to minimize this region will be very desirable.

Fig. 1 h show performance diagram, and drain current I is presented_dWith drain voltage V_dsBetween grid G fixation grid Voltage V_gIn the case of " constant current " relationship.It should be noted that the limited drain voltage range with Fig. 1 f on the contrary, drain voltage V_ds Across approximate supply voltage V_ddWide range, while maintain identical electric current.

Fig. 1 i to 1k diagrams are finally actually combined with the prior art MOS structure of two operation modes, commonly referred to as CMOS inverter.A pair has the MOSFET, i.e. PFET and NFET of opposite conductivities, connection complimentary to one another.For example, it inputs 10i, 10j, 10k are connected to the gate control terminal of PFET and the gate control terminal of NFET, and the source electrode of PFET is connected to power supply (+), and the source terminal of NFET is connected to power supply (-)；And PFET drain electrode and NFET drain electrode link together for V_Output19i。

Fig. 1 j show with the relevant structure of physical layout abstract graph shown in Fig. 1 k, be the prior art 2 dual intensities CMOS or two refers to phase inverter.As set forth above, the gate terminal of PFET and NFET link together to receive V_Input10j and 10k, and the drain terminal of PFET and NFET links together to generate V_Output19j and 19k.Layout shown in Fig. 1 k exists The structurally corresponding layout in Fig. 1 i.As can be seen, in order to minimize the various shortcomings in conventional FET layouts, such as minimize and post Raw output capacitance, for example, the source terminal of PFET is divided into two source terminals S+ and S+, and by drain terminal D+12k It shifts to form a pair of raceway groove 14k and 16k in parallel between S+ and D+12k therebetween；The p-channel region overlay of grid G is in parallel Raceway groove 14k and 16k.By the segmentation of trap boundary WB, also a pair of of source terminal S- and S- is provided for NFET, and by its drain terminal D-11k shifts to form a pair of raceway groove 13k and 15k in parallel between S- and D- therebetween；In addition it covers in the n-channel region of grid G Lid raceway groove 13k and 15k in parallel.Drain electrode 12k is connected therebetween by metal works 18k with 11k and is formed V_Output19k。

The 3 dimensions expected view of this MOS electric crystal structure is shown in Fig. 1 m, and the cross-sectional view at the section AA in Fig. 1 m exists It is shown in Fig. 1 n.This structure be 2 times as shown in Fig. 1 j and 1k or two refer in phase inverters it is intrinsic.As in the pfet and Join at raceway groove 14k and 16k and at raceway groove 13k and 15k in parallel as it can be seen that all these raceway grooves from drain D+, D- to source S+, S- It is gradually reduced.

Although there is similar MOS structure in the prior art, a large amount of of its many unique property are excavated and not well known Or it is announced.In addition, appropriate biasing is still a problem for its operation.The relatively deep understanding of internal mechanism is caused to being permitted The discovery (realizing superior operation so as to fulfill with deep-submicron scale) of mostly desirable application, comprising being reached using natural equilibrium To the method suitably biased.This natural equilibrium is equally effective under deep-submicron scale " band gap " Voltage Reference mechanism Result.

With reference to figure 1p and 1q, some reference substances show have " conduction type " it is identical by diffusion region 11p (in the prior art In be appointed as representing low-impedance Z) the MOS field-effect transistors dress of two same areas 13p/13q and 15p/15q separating It puts.The Bedabrata Pain/R Schober and Boise of jet propulsion laboratory (Jet Propulsion Lab) are state big The more papers of the Jacob Baker/Vishal Saxena of (Boise State University) are learned, include Caltech Institute (California Institute of Technology) space microelectric technique jet propulsion laboratory center (Center for Space Microelectronics Technology Jet Propulsion Laboratory's) Pain, Bedabrata's et al.《For itself cascade cmos circuit (A Self-Cascoding of low power applications CMOS Circuit for Low-Power Applications)》, wherein containing such reference member, but these reference members, especially It is in the case where of this sort compensation device is such as combined into single set composite by what is explained in the present invention, is not sent out Dig any chance as shown in this document.Such configuration is referred to as Self-cascading or separation length device.Two of such configuration Region is arranged between source electrode and drain diffusion, and is connected with the high impedance common gate connection to intermediate channel region and Low ESR It connects.What the control input of this Low ESR intermediate channel was summarized in such as this document realizes one group of completely new board design when being used Method.

Although can find cascade amplifier in the prior art, the prior art does not simultaneously contain the cascade connected as totem Transistor complementary pair.Using this simple composite structure, from the feedback for being output to input can be used for by gained phase inverter automatic biasing to In its linear model.As mentioned above, there are problems always for the biasing of amplifier；However, the novelty and creativeness of the present invention Automatic biasing structure can solve problems.The configuration (be known as complementation iFET or CiFET) of the present invention has many advantages, comprising but not It is limited to：

● one pass gain is maximum when output is in intermediate point (automatic biasing point)；

● high gain (close to 100) CiFET grades single, therefore, although final output may be swung close to rail, its is defeated Enter still near intermediate point.The intermediate point (" sweet spot ") that grade before this is maximized due to high-gain in gain is nearby grasped Make it to output and input.It is same for each grade in prior stage；

● the conversion rate of (near intermediate point) and symmetry maximize in place of channel current highest；

● the minimum of (near intermediate point) in place of channel current highest；And

● in the case where voltage swing is small, ghost effect can be neglected.

When grid input signal moves in one direction, output is moved in the opposite direction.For example, positive input It obtains negative output and not merely because N-channel device is more difficult to connect, and is actually because P channel is turned off. Thevenin/Norton analyses are shown, are had to be perfectly the same by the electric current of P and N devices, because of the drain electrode in a transistor Electric current except through do not have except the drain electrode of complementary transistor it is other ground can go；However, across those devices voltage drop without Must be impartial, but must amount to and reach supply voltage.Supersaturated source channel is attributed to, these voltages are bundled in one by exponential law It rises.This even becomes apparent in the case where voltage gain reaches the low supply voltage of peak value.This means that gate source voltage is by passing through two The same and unique drain current of transistor accurately limits.Index has similar time constant or the unique physical of " half-life period " Matter；No matter we are at given time point wherein, sometime after constant we by for from end value closer to fix hundred Divide ratio.This is " imagination " explanation of the main enabler of the output mobile to changing in response to input.This grid is grasped to source electrode The same current for making voltage balances the reason of " sweet spot " also indicated in self biased amplifier can be repeated so.In fact, this Differential pair class reference point of the point as amplifier input signal.

It should be noted that during the transformation from vacuum tube to bipolar transistor, the industry experienced to be turned in main pattern Become, thought deeply in terms of electric current rather than voltage so as to acquire.With the appearance of FET and MOSFET, pendulum model is swung to be returned again Thought deeply in terms of voltage, but lost or forgotten many knowledge.Contain herein to some old conceptions and some new think ofs Again the exploration on road, all suitable for upcoming " current " state of the art.It is believed that the intrinsic simplification of the present invention can be said The applicability and integrality of those bright designs.

First problem may be, and there are the needs to some analog functuions always, however with the simulation of bipolar transistor Performance indicator is compared, and nearly all simulated performance index of MOS transistors is evidently poor.One's own profession is already by using extensive " alternative " makes mos device work.Conventional analog design is constrained by following one or more situations：

● supply voltage is enough to bias stacking threshold value, and transistor is same large enough to supply necessary output driving current When the linearity and gain (g are still provided_m*R_L) needed for high output impedance.

● lack the analog IC process spread (unavailable in nanoscale) needed for linear signal, needless to say with herein The enhancing performance of displaying.

● resistor, inductor and larger capacitance device is not present in the board design in newer IC techniques mostly.

In contrast, it can make bipolar transistor that there is high-gain (β), broader bandwidth, more wide dynamic range (many ten Times, from close to rail until background noise), preferably matching (being present in differential pair) and bandgap reference.Utilize surface defect The junction type FET that the sub-surface channel conduction of lower section is operated has the noise lower than bipolar transistor.Equally, CiFET satiates With source channel mainly at the channel surface below gate oxide the defects of below operate.

MOS designs are poor at above-mentioned aspect, but have its own great advantage, including but not limited to：

√ mos devices are smaller and relatively easy

√ is highly scalable

√ is at a high speed

√ low-power

Ultra dense/high function series irrespective of size chips of √, and bipolar design can not realize this point (deep Asia-μm scale).

Therefore, there are problems always for structure analog circuit on IC.Since analog circuit has been integrated form, held around bad The engineered primary goal for having become analog IC designer that capable simulated assembly carries out.This is driven to algorithm development Digital Signal Processing needs, so as to generate digital magic.

In Analog Circuit Design real world of today, it is still necessary to carry out signal in the front-end and back-end of signal processing system Conversion.It is this to need to have become the advance obstacle under deep Asia-μm scale.

Another problem may be that solid-state amplifier is great from the beginning non-linear.In order to realize that it is linear, by using Closed loop (feedback) being got in return with increased open-loop gain (have and be significantly higher than final required level) to actual circuit gain and The control of the linearity.Closed loop amplifier needs negative-feedback.Most of amplifier stages are reverse phases, necessary negative anti-so as to provide Feedback.Single-stage phase inverter with closed loop is stable (nonoscillatory).Increased loop gain needs to add grade so that depositing always Odd number grade (symbol is negative), so as to provide necessary negative-feedback.Although one-stage amplifier is substantially stable, three Grade and the most clearly, five grades are unstable (they are being vibrated always -- because they be ring oscillator).

Then, problem is how properly to compensate multistage closed loop amplifier, while maintain rational gain band width product. This circuit-level design must simply on deep-submicron scale it is particularly difficult.The supply voltage of critical constraints is hampered to normal Advise the use of board design method.Additionally, it is desirable to avoid the dependence to simulation extension, but it is expected to come using all numerical portions Necessary analog functuion is realized to improve output and reduce cost.Allow do not having still and may be forever using all numerical portions Analog functuion is realized at the remote process node for not having simulation extension.

The long-term large capacity for needing integrated low cost/high performance system on a single chip for affording fills It puts, such as Internet of Things, intelligence sensor and other devices being seen everywhere.

Invention content

The present invention relates to the circuit by novel and creative set composite structure structure, the set composite structure realizes base It is described in the method for the exponential relationship of supersaturated source channel that the utilization of charge is described below with respect to Fig. 2 a, 2b, 2c and 2d Method during analog cmos circuit design for possessing subthreshold value generic operation.The present invention is the evolution of common CMOS inverter.Its Very high degree of precision, speed, the linearity, low noise and compact object are provided using digital nanoscale or deep Asia-μm IC techniques Removing the work office.In addition to expected digital inverter function, the analog circuit of five classifications is instantiated：Control source amplifier, electricity Flow input amplifier, the current inverters opposite with current mirror, adjustable delay circuit and voltage or current reference source.Especially It should be noted that analog functuion is realized using the Digital Logical Circuits unit of single optimization in digital IC techniques.

According to another aspect of the present invention, dopant profiles and ratio method are utilized.The electricity configuration of circuit need not be performed has Close the every operation of optimization circuit.Appropriate device size design and the magnitude relationship meeting especially between adjustment complementary transistor Considerable performance benefit is provided.IFET as composite construction provides extensive chance to match by the appropriate of physical unit parameter Than being controlled to establish impedance matching and gain.As other key properties such as noise, speed and power can pass through the physics of transistor Construction and the careful specification of doping are customized rather than rely solely in circuit configuration.

According to another aspect of the invention, certain noise advantages are provided.Finally, it is attributed to signal-to-noise ratio.Ultra-deep sub-micro The peak signal amplitude of oscillation is limited to smaller than what most of board designs teacher were accustomed to by the low supply voltage requirement in rice IC techniques More numerical value.Therefore in the case of compared with small-signal, it is necessary to use the low noise audio technology implemented herein to maintain desired letter It makes an uproar ratio.

The present invention can provide additional advantages.The major advantage that this technology is presented has been generated in the case where being extended without simulation The ability of simulation structure block constructed entirely from numerical portion.The situation of no less important is that the technology is actually in ultra-deep Asia It being operated under micro-meter scale, and operates preferably under the supply voltage of reduction, the supply voltage of the reduction is sub- less than ultra-deep-μm One volt needed for IC techniques.These three factors facilitate the unprecedented design portability across process node.It will be more because having Completely new circuit design is realized in the FET of a control input.The CiFET provides high impedance voltage control on grid, And low impedance current control is provided at iPort simultaneously.Both inputs operate, and only to them at output independently of one another Vertical response is summed.

According to another aspect of the invention, complementation iFET set composites are provided, can be configured to reference to generator and electric current Source transistor is joined with absolute temperature proportional (PTAT) reference voltage circuit and/or with absolute temperature complementarity (or CTAT) voltage Examine potential circuit.

Description of the drawings

Fig. 1 a are shown as prior art amplifier so that relatively high quality CMOS amplifier prior arts transistor is illustrated Figure, comes from Gray, Hurst Lewis and the written famous textbooks of Meyer《The analysis and design of Analogous Integrated Electronic Circuits (Analysis and Design of Analog Integrated Circuits)》4th edition page 482；

Fig. 1 b to 1d are the generations of the frequency domain performance of the prior art amplifier of pictorial image 1a and one group of benchmark of power supply dependence Table performance chart；

The cross-sectional view of the prior art MOSFET channel conduction in weak transoid and strong inversion is shown respectively in Fig. 1 e and 1g, and Fig. 1 f and 1h show to present exponential relationship between drain current and grid voltage when in weak transoid respectively and in strong The curve graph of secondary relationship during transoid；

Fig. 1 i show that two (2) of the prior art refer to the transistor schematic of phase inverter；

Fig. 1 j and 1k show that two (2) of the prior art refer to the physical layout abstract graph of phase inverter；

Fig. 1 m show that two (2) of the prior art refer to three (3) dimension perspective view of phase inverter；

Fig. 1 n show the cross-sectional view at the section AA shown in Fig. 1 m；

Fig. 1 p show the physical layout of the separate channels CMOS transistor of the prior art；

Fig. 1 q show the 3D perspective views of MOSFET that the simulation of the prior art is sized；

Fig. 1 r show that the simulation of the fin formula field effect transistor (FinFET) of the prior art is sized the physics cloth of array Office's plan view；

Fig. 1 s show the scaling perspective view inside the round Z shown in Fig. 1 r, show the prior art FinFET it is saturating View；

Fig. 1 t illustrate that the curve graph of the intrinsic gain scale of the nMOS transistor of the prior art；

Fig. 2 a show the MOS field-effect transistors of the new intermediate channel bidirectional current port (iPort) with the present invention The expected view of three (3) dimension of (or iFET)；

Fig. 2 b show the cross-sectional view of the iFET with the distribution of intuitive channel charge of the present invention；

Fig. 2 c are shown there is no drain voltage V during iPort Injection Currents_dsWith drain current I_sFigure, and Fig. 2 d show Go out another figure when providing maximum iPort Injection Currents；

Fig. 2 e show the various iFET symbols of the present invention；

The schematic diagram of the iFET complementary pairs of Fig. 3 a diagram present invention；

The physical layout abstract graph of complementary iFET (or CiFET) set composite of Fig. 3 b and 3c the diagram present invention；

Fig. 3 d show three (3) dimension perspective view of CiFET set composites；

Fig. 3 e show the cross-sectional view at the section AA of Fig. 3 d；

Fig. 3 f, 3g and 3h diagram CiFET operability modeling, automatic biasing schematic diagram and symbol wherein used；

The physical layout of the NOR gate of Fig. 3 i diagram prior arts；

The physical layout of Fig. 3 j (1) diagram initiatives CiFET, Fig. 3 j (2) illustrate its corresponding schematic diagram, and Fig. 3 j (3) Illustrate its corresponding symbol；

The physics of the FinFET of the iFET complementary pairs (being equivalent to the CiFET symbols shown in Fig. 3 j) of Fig. 3 k diagram present invention Layout；

Fig. 3 m illustrate the schematic diagram with absolute temperature proportional (PTAT) circuit of the prior art；

Fig. 4 a show the schematic diagram of automatic biasing CiFET reference voltage output generation circuits, comprising analog voltage around swing ~V_dd/ 2 simulation virtual grounds and with absolute temperature proportional (or PTAT) Voltage Reference output and and absolute temperature complementarity (or CTAT) Voltage Reference exports；

Fig. 4 b show the positive current reference based on automatic biasing CiFET and negative current according to the present invention showing with reference to generator It is intended to；

Fig. 4 c are that CiFET PTAT and CTAT reference voltage in limiting temperature is linear and tracking；

Fig. 4 d show that the PTAT according to the present invention based on automatic biasing CiFET stacks reference voltage and CTAT is stacked with reference to electricity Press generation circuit；And

Fig. 4 e show according to the present invention with simulating the relevant reference voltage generation of virtual ground (CiFET automatic biasings) voltage The schematic diagram of device.

Specific embodiment

MOS structure is herein referred to as iFET, wherein alphabetical " i " refers to electric current and " FET " refers to field effect transistor Pipe, MOS structure are several high-performance of the present invention and the realization element of novel designs.The present invention is to be based on to be directly connected to add To the intermediate point in field-effect transistor (or FET) raceway groove, and based on the recognition that be by Low ESR port (electric current port or Referred to herein as " iPort ") under low saturation voltage extremely low input impedance is provided for bidirectional current trap/source electrode intermediate channel, and And other connection has reciprocal iFET pairs of opposite " conduction type " (p-type and N-type), the reciprocal iFET is to interconnected with utilization Its complementary nature is as one group and symmetrically operates with automatic biasing near intermediate point between the power supplies.Furthermore it is possible to it adjusts The first raceway groove of iFET and the relative intensity (threshold value selection, relative size and dopant profiles) of the second raceway groove are with the adjustment present invention's Gain, speed, quiescent current and the input impedance of such complementation iFET (or CiFET) set composite.

The iPort of iFET provides unusual and unexpected solution to compensation problem, then proceedes to old ask to be other Topic provides new or replacement solution, has exceeded the expection of industry.With the advantages of " weak inversion " operation circuit already be people It is known, but there is also problems.CiFET is enabled the circuitry to using obtainable high-gain and more wide dynamic range in weak inversion, Without losing superior speed ability.CiFET equipment complexes provide the active IC gain equipments of standard, it is than common mould It is more advanced to intend MOSET so that digital IC has analog functuion.It is not traded off.

Some unusual aspects of the circuit based on CiFET are listed below, including but not limited to：

● it operates at low supply voltages；

● high-gain；

● it is great linear；

● hypervelocity (broadband)；

● automatic biasing；

● low noise；

● fast quick-recovery (DC)；

● use all digital units and process；

● iPort makes sound to charge (things in nature is based on charge) rather than the voltage at resistance both ends It should；And

● iPort has extensive dynamic range, has constant gain in openloop.

With reference to figure 2a and 2b, according to a preferred embodiment of the invention, a kind of electric current FET (or iFET) 200 is provided, by serving as a contrast Bottom 26a or 26b, source terminal 24a or 24b and drain terminal 29a or 29b composition, in the source on substrate 26a or 26b Two raceway groove 23a and 25a or 23b and 25b, usual first (source electrode ditch are defined respectively between extreme son and the drain terminal Road 23a or 23b) power supply (not shown) is connected to, and second (drain channel 25a or 25b) is connected to load (not shown).Lining Bottom 26a or 26b are N-type or p-type.As shown in figs. 2 a and 2b, two raceway grooves, i.e. respectively source channel 23a and drain channel 25a or source channel 23b and drain channel 25b is connected to each other at iPort control terminals 21a or 21b, and raceway groove 23a and 25a or 23b and 25b shares common grid control terminal 27a or 27b respectively.This configuration means that iFET 200 has and is more than One control input terminal.

The operation of gate control terminal 27a or 27b are similar to routine MOSFET insulated gates, have its high input impedance and spy Some mutual conductance (g_m) transmission function.(the g of small-signal mosfet transistor_m) representative value is each 1 to 30 milli Siemens (1 milli west gate Son=1/1K-ohm), this is the measurement unit of mutual conductance.

IPort control terminal 21a or 21b impedances for source terminal 24a or 24b are relatively low, and have and seem More like the transmission function of the beta (β) of bipolar transistor, but it is actually across resistance (or r_m) or more generally, especially in height It is the transimpedance measured with K-ohm under frequency, wherein output voltage is obtained by input current.Trench size depending on CiFET Than representative resistor values (or the r of, small-signal iFET transistors 200_mValue) be from 1K Ω to 4M Ω, M Ω be metering list across resistance Position.Electric current is input to the basis that voltage output (transimpedance) is following confirmation：The input of 1 μ A will generate under big signal level The output (or 100,000 of 100mV:1 gain) or 1pA input in low-noise amplifier (or LNA) will generate The output (or 100,000 of 100nanoV:1 gain) (the two results both are from same circuit and are in this dynamic range Linear).

In simulation using same circuit, it is still correct for the iFET of single minimal size to have shown these values , there is the input value from 1 micromicroampere to 10 micromicroampere.In the CMOS constructions of 180nm, background noise limits measured value Below about 10 micromicroamperes.IFET can be constructed with different length from width ratio with foreseeable extremely different knots Fruit.

The high-gain different from state of the art design, atypia or unexpected as a result, being with the height of Fig. 2 b The result of " weak inversion " characteristic of the source channel 23b of the iFET 200 of the supersaturated pattern operation of ionization.

Speed in this supersaturated source channel 23b is not limited by carrier along the transition time of raceway groove 23b, but is had The ionization electric charge carrier of high concentration in the raceway groove of source only must be added to raceway groove 23b in charge by means of iPort control terminals 21b Or the charge of surrounding is slightly pushed when being removed from raceway groove 23b, so as to generate dissufion current, dissufion current is by working as MOSFET with weak anti- The exponential relationship for turning just to have been carried out during operation defines.This is with causing the electric field of charge transition raceway groove to form comparison, the electricity Field is the square-law function of grid-control voltage.In this configuration, speed be faster than by identical base transistor structure and not by The logic that " weak transoid " grade with higher gain as bipolar transistor influences.Compared to bipolar transistor, electric current is controlled It can enter or leave iPort control terminals 21b and operated in the case of no iPort electric currents, this is conducive to create Build automatic biasing operating point.

Automatic biasing operating point is helped to realize compared with low noise.Herein, the potential at drain terminal 29a or 29b and grid control Potential at terminal 27a or 27b processed is identical, so as to greatly reduce pinchoff effect present in conventional simulation circuit design.

Since source channel 23a/23b is connected with the common gate on drain channel 25a/25b, iFET 200 is to source terminal The gate control terminal 27a/27b (or GS) of 24a/24b or source channel 23a/23b applies higher than expected voltage.This is higher than Expected voltage causes much thick and firmly gets more (more low resistance, highly ionized) conductive layers, so as to make most of carriers The trap in crystalline surface can be avoided, therefore noise is much lower, similar to junction field effect transistor (or j-FET) conduction position Mode below surface.

Across resistance (r_m) it is mutual conductance (g_m) " duality ".When searching across resistance, most of references are all related inductors And capacitor, this shows that iFET is likely to be suited for combination inductance device.

The operation principle of iFET is as follows：Low-noise amplifier needs Low ESR raceway groove.The voltage gain of Low ESR raceway groove is low But current gain is high.In order to establish voltage gain, the second level operated as current-to-voltage convertor is needed.Cascade is to providing this Class is configured.The offset requirements of cascade pair eliminate its use at low voltage, unless finding the method for solving biasing problem. IFET provides the method for solving the problems, such as this by the automatic biasing of complementary pair.The impedance of raceway groove may be designed to adapt to described in driving The impedance (seeing below the literary chapters and sections in relation to ratio) of the particular signal source of impedance.

Generally for FET, carrier is attached to surface by gate field, and low grid voltage forms thin surface on raceway groove Layer (place of electric conductivity occur), and higher gate voltage forms thicker bottom.The carrier of thin layer is lacked by uneven surface Blocking is fallen into, so as to generate electrical noise, and a smoother path is found under the surface compared with thick-layer carrier, it is whole so as to reduce Body electrical noise.This indicates that higher grid voltage can reduce noise.

With reference to figure 2b, in iFET 200, cause to carry by the electric fields formed of the grid voltage Vg on gate control terminal 27b Stream is risen to from substrate 26b in source channel 23b regions, so as to have when semi-conducting material is changed into every volume or saturation Thus the conductor of relatively great amount of carrier establishes a degree of electric conductivity.

The Injection Current I being introduced into iPort control terminals 21b_injIt increases on source channel 23b and in source electrode ditch Diffusion charge (the carrier number per volume) in road 23b, therefore source channel 23b is made to have more electric conductivity.Electric conductivity changes Rate be exponential, as being found in " weak transoid ".The electric conductivity variation of this exponential rate is by along source The low pressure gradient (source terminal 24b to iPort control terminal 21b voltage gradients) of pole raceway groove 23b causes.

IFET exponential relationships between the charge of source channel 23b and grid voltage 27b can provide functional to logarithm It accesses, the addition of two of which logarithmic function is equivalent to multiplication.Reversed antilogarithm operation or the operation of reversed index passes through Opposite complementary iFET raceway grooves restore simulation output.This exponential relationship can be used for various low-noise amplifier applications.Refer to Number relationship also causes the more wide dynamic range of these iFET circuits.

Again, with reference to the source area in figure 2a, electricity is removed from gate control terminal 27a or/and iPort control terminal 21a Lotus (carrier number per volume) causes the electric conductivity of the semi-conducting material in source channel 23a to reduce.In this regard, iPort The connection of control terminal 21a to source terminal 24a (it is index) in a manner of the base region for being similar to bipolar transistor Operation：Control electric current to iPort control terminals 21a is more, device electric conductivity (g_m) higher.

The operation of the drain channel 25a of the iFET 200 of Fig. 2 a is more closely similar to conventional FET, and similar part is, drain ditch The thickness of road 25a bigger (identical with source channel 23a thickness) near iPort control terminals 21a, and with drain channel It reaches its diffusion region around drain terminal 29a and is gradually reduced and (reduces between drain channel 25a and gate control terminal 27a Voltage differential reduce field), so as to be formed by grid voltage V_gThe output resistance of the transistor of setting.Relatively low drain voltage V_g (close to voltage present on grid) can reduce drain channel output resistance (the relatively thick-channel at drain diffusion).It is led together with thicker Electric layer, this relatively low drain channel resistance can be generated compared with low noise and height output driving force, so as to what is provided using thick conductive layer Low ESR driving forms wanted drain voltage at drain electrode 29a.

The diffusion region around 200 source area 24a of iFET operated at low voltage have low voltage gain but its also have There is low noise.Due to drain voltage and grid voltage V_gIt is identical, therefore around the drain terminal 29a operated at higher voltages Diffusion region provide want voltage gain and caused by noise minimum.This voltage isotropism is biased by the uniqueness being explained below Produced by construction.

Fig. 2 b further show iFET channel charges distribution according to the present invention, show its operating point or the feature of iFET, But illustrated iPort Injection Currents in Fig. 2 c are not shown, wherein the source electrode ditch that will not have input current at drain channel 25b Road current level 24c and voltage level 25c are applied to iPort control terminals 21b.Slope 26c represent the point of drain channel 25b across Hinder r_m, and slope 23c for the source channel 23b of over-saturation and is then iPort input resistances R_Input.Fig. 2 d, which are shown in, to be had The V-I features of iFET in the case of iPort Injection Currents, wherein slope 26d represent drain channel 25b and its across resistance r_m, and Slope 23d is for oversaturated source channel 23b and iPort input resistances R_Input.It should be noted that a small amount of iPort electric currents 21d How drain channel output voltage V is greatly interfered with_Output25d.As can be seen, V_OutputFull power confession can be nearly reached Answer (V_dd).Reverse or double, the wherein big variation of drain-to-source voltage that this is that the normal voltage-controlled current source of mos device uses So that the variation of drain current is minimum during saturation, as shown in fig. 2d.This enables analog IC designer to understand iFET As the serviceability of amplifier, do not need to typical large-scale, heavy simulation planar transistor and be used for required mutual conductance to be increased Benefit.On the contrary, the NiFET in current-controlled voltage source configuration use across resistance come by the gain of the device based on MOS promotion to new Highly.

Noninverting property

About iPort control terminals, in the case of N-channel and P-channel both devices, into iPort control terminals The equivalent current that will be entered by drain channel of positive current substitution, moved up so as to which drain electrode (output) be made to be connected to positive voltage direction It is dynamic, the noninverting property of iPort inputs is consequently formed.

IPort also serves as current inverter rather than conventional current mirror.

It is interesting that it is different from other semiconductor devices, negative current can be extracted from iPort, so as to cause in negative direction On drain electrode (output) displacement.Zero input current is equally effective.

Appropriate biasing

IFET 200 makes two grids link together and appropriate biased electrical is needed on grid (as shown in figure 2b) It presses to establish wanted operating point.

Symmetry

P channel can by with its N-channel corresponding part similar mode construct and run.

It is emphasized that although grid the input phase is reverse phase for drain electrode, iPort is not reverse phase.

CiFET amplifiers are to simulate structure block in basic number：

Although single iFET has characteristic of interest, a pair of complementary iFET (or CiFET) for itself It is proved to advantageously.The iFET of opposite semiconductor type is used as load device conveniently to provide it partially for opposite iFET It puts, but also has the advantages that MOSFET operations unintentional nonlinearity is made to offset (linearisation).For example, the mistake of source channel The high-gain indicial response of operated in saturation is in extremely wide dynamic range inner linearization.

Gained compensation device (having initiative CiFET units) may be considered most possible power gain bandwidth MOSFET amplifier stages.For example, any iPort is observed, supersaturated source channel input impedance is the constant of relative low value Resistance.Any input current is converted into small input voltage by this, is calculated through high level r_mIncrease across the extra-high voltage that resistance is implemented Beneficial transmission function.In addition, the sub-surface operation of supersaturated source channel can be for the possible lowest noise of any mos device Lower operation.For low noise, drain channel is also operated below its surface defect to the maximum extent.Finally, everything is all It is about signal-to-noise ratio.

Initiative CiFET symbols are presented in Fig. 3 a and Fig. 3 b show roughly similar physical layout abstract graph with 3c；Figure 3d shows three (3) dimension perspective view and the viewgraph of cross-section of the section AA in Fig. 3 e pictorial images 3d；And Fig. 3 f and 3g illustrate this hair The iPort control terminals behavior models of bright CiFET devices, the present invention the complementary iFET of a pair automatic biasing schematic diagram and Its corresponding symbol is to the thorough of state of the art in terms of high-gain, high-precision, small scale, the original structure block of simulation It improves at bottom.The iFET of the complementation is extended to being built completely by logic module without simulation, while realizes proportional zoom and just The property taken.The power consumption of covering surface and every gain/bandwidth is greatly reduced from state of the art, maintains excellent noise-induced Energy.

With reference to figure 3a, complementary iFET (or CiFET) 300 is included p-type iFET (or PiFET) 301 and N-type iFET (or NiFET) 302, the gate control terminal of the gate control terminal 37p and NiFET 302 including being connected to PiFET 301 simultaneously The input terminal 30a of 37n, as common grid terminal 30a.The reception electric power of CiFET 300, i.e. power supply-and power supply+, wherein electricity Source-source terminal and power supply that are connected to NiFET 302+is connected to the source terminal of PiFET 301.PiFET 301 and NiFET Each in 302 includes the iPort control terminals (31a and 32a) for receiving Injection Current.PiFET 301 and NiFET 302 drain terminal is combined to provide output 39a.

Fig. 3 b extend PiFET the and NiFET devices 301 and 302 of the CiFET 300 of Fig. 3 a so that its visually with figure The physical layout abstract graph of 3c is related.

With reference to figure 3c, CiFET 300 include along the WB' of trap boundary shown in figure similar to mirror image be arranged in substrate (or point Not in body B+ and B-) on PiFET 301 and NiFET 302；PiFET 301 include source terminal S+, drain terminal D+ and IPort control terminal Pi, so as to define source electrode+raceway groove between source terminal S+ and iPort control terminal Pi diffusion region 32c Drain channel 36c between 34c and drain terminal D+ and iPort control terminal Pi diffusion region 32c.NiFET 302 includes source Extremely sub- S-, drain terminal D- and iPort control terminal Ni spread so as to define source terminal S- and iPort control terminals Ni The drain electrode ditch between source-channel 33c and drain terminal D- and iPort control terminal Ni diffusion region 31c between area 31c Road 35c.CiFET 300 further comprises in source electrode+raceway groove 34c, drain electrode+raceway groove 36c, source-channel 33c and drain electrode-raceway groove Common grid terminal 30c on 35c.Therefore, common grid terminal 30c is capacitively coupled to raceway groove 34c, 36c, 35c and 33c.

Fig. 3 d are 3 dimension diagrams of the CiFET physical layouts of Fig. 3 c, and Fig. 3 e are the cross section AA of Fig. 3 d.It is corresponding accurate Number is related to the same characteristic features between each figure in Fig. 3 a, 3b, 3c, 3d, 3e, 3f and 3g, and wherein same characteristic features are by carrying The reference label of figure alpha code represents.Fig. 3 h show the graphical diagram of the CiFET devices of the present invention.Fig. 3 d and 3e are further pointed out It is described inclined for active channel charge-conduction area 34d, 34e, 36d, 36e, 33d, 33e, 35d and 35e existing for biasing CiFET Put about half of difference of the grid voltage of CiFET between the grid voltage on S+ and S- terminals.

In many analog circuits, biasing is a problem.Using as shown in fig. 3g in complementary pair (31g and 32g) IFET allows their " automatic biasing " (38g), thus eliminates drifting problem, in addition, amplifier finds maximum on its operating curve Gain point.

In " behavior model " as illustrated in figure 3f, the electricity at iPort control terminal NiPort 33f and PiPort 34f Stream passes through across resistance (r_m) voltage is converted to, value determines gain.To eliminate drifting problem, V is provided_InputThe automatic biasing road of 30f Diameter 38f.This " across resistance " (r_m) established by the ratio of " drain channel " and " source channel " intensity, and protected in the range of whole operation It holds constant.Herein, iFET operations are derived from current density different in source electrode and drain electrode raceway groove, are similarly to generate reference voltage Band gap method duality：Make parallel connection of the same current value operation by single transistor and multiple examples of identical transistor Combination.Analog result shows this resistance (r_m) usually in the range of 1K Ω to 4M Ω, representative value is 100K Ω, this is by opposite Trench size determines.r_mIt is g_mDuality.

Export (V_Output39f) it is low-impedance source follower common grid FET configurations, it can be defeated with necessary electric current Go out its voltage to drive subsequent conditioning circuit.

IPort inputs are constant low-resistance ends (with r_mIt is related but much lower), there is the pact from corresponding power rail Constant offset voltage CTAT Ref, the PTAT Ref of 1mV to 100mV.This offset voltage is by " drain channel " and " source electrode ditch " band gap " reference that the ratio of road " intensity is established.

Standard CiFET set composite units physically can construct and instantiate just as logic unit to set Meter simulation.In general, this is the active circuit component uniquely needed.Just as transistor, but CiFET units complete active block All required.

Then appropriate bias voltage how is generatedThe simplest mode for generating bias voltage is used in complementary pair IFET, NiFET 31g and PiFET 32g, so as to form reverse phase device as shown in fig. 3g, and then using output 39g to It inputs 30g and negative-feedback 38g is provided.CiFET set composites are by " automatic biasing " at certain point between the power supplies, at the point, Gain maximizes, and speed or the conversion rate held stationary for most of quick variation.In this self-bias voltage point, lead to The electric current for crossing complementation iFET devices 31g and 32g two is essentially equal, and there is no be directed to other than entering NiFET (31g) and draining Other DC electric current paths of PiFET (32g) drain electrodes form particular gate electricity thus directed towards this electric current equality (or electric conductivity) Pressure.In addition, since iFET 31g and 32g are respectively provided with identical electric current, pull-up ability is equal to pull-down capability, this is defined Maximum slew rate bias point.Then the electric current at iPort control terminals NiPort 33g and PiPort 34g passes through across resistance (r_m) (not shown) is converted to voltage, value determines gain.

Since complementary iFET 31g and 32g is to being automatic biasing, for the variation in operating environment, any parameter The factor all compensates automatically.The intrinsic matching being attributed between the adjacent part on IC, bias generator can be used near Other iFET be biased.Real-time auto bias circuit correction parameter variation (taking various forms).

Each transistor in the phase inverter of the present invention serves as " dynamic " load of its complement, so as to make grid voltage bright The aobvious conventional bias point higher than analog circuit grid.It is higher than normal grid voltage in the grid voltage of complementary iFET set composites In the case of, source conduction raceway groove is deeper, so as to generate compared with low noise.

Main Noise Sources in conventional analog circuits are related to " pinch off ".With the voltage (zero differential) identical with grid to leakage Pole (or output), which is biased, makes Drain Electrodes Conductive raceway groove avoid the raceway groove pinch off (shallow channel) usually encountered in analog circuit existing As.Another illustrative fashion is：As drain electrode is close to its design maximum voltage, transistor becomes more noisy, automatic biasing reverse phase Device operates its transistor, and grid is in the voltage (zero differential) identical with drain electrode with half of design maximum voltage or so, Therefore the quiet many of automatic biasing phase inverter.

The operation of CiFET amplifiers is different from the operation of conventional simulation amplifier loaded using current mirror, different Part is：

" source electrode " raceway groove has minimum (~100mv) voltage from source terminal to iPort control terminals, and " gate terminal Son " is in~1/2V_{Power supply}.This causes iFET source channels to enter " supersaturation " state, and this state is similar to weak transoid, but has There is higher gate overdrive.Gate overdrive generates abnormal thick conductive layer and relatively low source electrode to iPort voltages, so as to lead Conductive layer is caused to be always maintained at along raceway groove thicker.Pay attention between the conducting channel 23b in conducting channel 10s and Fig. 2 b in Fig. 1 e Thickness difference.

" drain electrode " raceway groove 25b runs its drain terminal 29b under~1/2Vmax, so as to greatly reduce pinch off (and DIBBL) Effect.The situation of this pinch off reduction is by " gate terminal " in~1/2V_{Power supply}Operated under (identical with 1/2Vmax) and into One step enhances, it means that does not have potential difference between the 29b and grid 27b that drains.

Another importance of CiFET set composites is the input of its electric current, and the electric current input can be from parasitic capacitance Speed rob effect in free.

This subtle and significant difference is to act weak transoid and to have complementary iFET amplifiers excellent low The supported feature of noise, more extensive dynamic range and speed advantage.

Compared to equivalent bipolar circuit, MOSFET can not form particularly preferred amplifier.Its gain is limited, it is noisy and And its high impedance makes its slack-off.

Ambipolar difference amplifier has developed to the fairly good degree of Input Offset Value, but to the development of CMOS but never The result really brought.

For a long time, it is known that excellent performance can be obtained, but because unpractical by knowing from the CMOS operated with weak transoid The complex situations as caused by high impedance caused by low current can be interfered (to be equivalent to bipolar using the fine gain seen in weak transoid The fine gain of transistor), the dynamic range dynamic range of bipolar transistor (be more than) and logarithm performance (allow tens times to put Greatly).Due to weak transoid, CiFET brings the noise benefit of the majority carrier in the deep trench seen in junction type FET into MOSFET In.

It is identical in the MOSFET in weak transoid by increasing current source load and when presenting to logarithmic transfer function MOSFET is non-linear to eliminate by increasing antilogarithm load, so as to generate fairly linear transmission function.The CiFET amplifiers It is such circuit, i.e.,：Logarithm input, antilogarithm load, fairly linear, wide dynamic range, low noise.Low noise is biasing As a result, wherein source channel grid potential is high, and the potential for crossing over source channel itself is maintained close at zero volt.Drain ditch Road is level shifter, and the extremely low voltage in source channel is maintained when delivering the high amplitude signals amplitude of oscillation at output.

The CiFET amplifiers implemented with closed loop sample data block are when its " flying capacitor " inputs in terms of biasing is inputted The performance of near perfect is presented.Even also can in the case of there are high level background with the CiFET amplifiers that open loop is implemented Unexpected sensitivity level (gain is presented>1 million), this is caused by extreme dynamic range.

Fig. 3 i, 3j (1) and 3k show the comparison between NOR2 physical layouts and CiFET physical layouts.Specifically, Fig. 3 i The physical layout of NOR2 devices with corresponding symbol is shown.

In the layout abstract figure of Fig. 3 i, 3j (1) and 3k, addition metal layer (not shown) is with by its source/drain diffusion Contact point (small square) links together.That is, in Fig. 3 j (1), drain terminal pout and nout interconnection, an iPort Ni Another iPort Ni being connected on NiFET 30n, and an iPort Pi is connected to other iPort on PiFET 30p Pi.Raceway groove in parallel is used to increase total channel width on demand.

Fig. 3 j (1) show the physical layout of initiative CiFET, and Fig. 3 j (2) show its corresponding schematic diagram, and Fig. 3 j (3) Its corresponding symbol is illustrated, and Fig. 3 k show the iFET complementary pairs (being equivalent to the CiFET symbols shown in Fig. 3 j) of the present invention The physical layout of FinFET.

With reference to figure 3j (1), layout 30j includes the layout for PiFET 30p and NiFET 30n, and PiFET 30p include grid Pole Gate, iPort Pi, drain terminal pout and source terminal pst.Source channel ps is formed in iPort Pi and source terminal Between pst, and drain channel pd is formed between drain terminal pout and iPort terminals P i；And source channel ps1 and ps2 shape Into between source terminal pst and iPort terminals P i.In a similar manner, NiFET 30n include iPort Ni, drain terminal Nout and source terminal nst.Source channel ns1 and ns2 are formed between iPort ni and source terminal nst, and drain channel Nd is formed between drain terminal nout and iPort terminal Ni.

With reference to figure 3k, layout 30k includes the layout for PiFET 30'p and NiFET 30'n, and PiFET 30'p include grid Pole Gate, iPort P'i, drain terminal p'out and source terminal p'st.Source channel p's1a, p's1b, p's1c and p' S2a, p's2b and p's2c are formed between iPort P'i and source terminal p'st, and drain channel p'd1a, p'd1b and p' D1c and p'd2a, p'd2b and p'd2c are formed between drain terminal p'out and iPort terminals P ' i.In a similar manner, NiFET 30'n include iPort N'i, drain terminal n'out and source terminal n'st.Source channel n's1 and n's2 are formed in Between iPort N'i and source terminal n'st, and drain channel n'd1 and n'd2 are formed in drain terminal n'out and iPort ends Between sub- N'i.

Utilize dopant profiles and ratio method：

Traditionally, engineer can be avoided in analog configuration using Digital Logic because this be considered to have it is unacceptable It is non-linear and be difficult to bias.Digital Logic can also sacrifice driving symmetry for compactedness.Pass through appropriate device Ratio expression (~3:1p:N width) recovery symmetry can improve the linearity, increase noise immunity and maximization dynamic range.From Biasing solves biasing problem.

Fig. 1 q describe the basic symbol and 3 dimensional views of the mos transistor structure of saturated mode.Universal plane is shown herein MOSFET, with longer/wider raceway groove typical used in usual simulation application.Shown FET symbols and structure are suitable for n Type or p-type planar transistor, the transistor optionally can be further about and suitable for package grid finFET structures.It should Note that there are four ports for FET tools, grid (g) 17q, drain electrode (d) 19q, source electrode (s) 14q and body (b) 16q are included.In general, voltage High resistive gate port 17q is applied to as input, and voltage or electric current can be applied to the leakage of physically similar (and interchangeable) Pole 19q and source electrode port 14q.Block/body end mouth 16q is commonly attached to minimum (or low) voltage potential for N-shaped FET and attached Being connected to highest (or high), voltage potential is for p-type FET, so as to control/prevent the forward bias of block-source junction and provide phase The minimum V for supply voltage_gsFor normal operating, (despite the presence of exception and the special method of block, but this will not It discusses here).In addition, showing that plane 3 ties up MOSFET structure in Fig. 1 q, there is the more wide degree for being usually used in analog circuit Raceway groove in W and long length L and pinch off saturation region.

In order to maintain higher intrinsic gain, MOSFET is needed compared with high output impedance.This passes through high r_o=R_OutputIt is necessary compared with Long channel length obtains.Due to g_mIt is directly proportional to the W/L ratios of MOSFET, in order to keep g when raceway groove is longer_mHigher, raceway groove is also It is wider necessarily to scale.Herein, gain is~g_mR_L/R_Output.As IC techniques are shunk, g_mIncrease, but R_OutputReduce faster, from And short channel length is prevented for simulating.Here it is newest Double-number (position) although IC techniques are shunk but simulated in CMOS technology The reason of transistor does not scale accordingly.Also, it should be mentioned that the surface of simulation channel current under the gate is nearby advanced, surface Defect carrier traps distinctive MOSFET 1/f noises formed here.

Fig. 1 r show the physical layout plan view of fin formula field effect transistor (FinFET) array of the prior art.Source electrode 14r and drain electrode 19r are stacked and are formed fin, and the array of grid 17r is arranged there between forming FinFET 12r.It is shown in Fig. 1 s The enlarged drawing of round Z in Fig. 1 r shows a prior art three (3) the dimension perspective view of FinFET 12r.

Fig. 1 t illustrate that the curve graph of the intrinsic gain scale of the nMOS transistor of the prior art.It can be seen that nMOS The continuous reduction warning board design Shi Qi of the intrinsic gain of transistor, which attempts bi-directional scaling, to be had under 65nm or 90nm Effect ground perform 14nmCMOS techniques amplifier design when by face of difficulty, will likely fail.Therefore, it is necessary to it visits Rope is different from other methods of conventional program, to find practical strategy to be driven in newer ultra-deep Asia-μm CMOS technology Drive intrinsic transistor gain.

FinFET has increase g_mThe shorter nanoscale ditch of the drain electrode output resistance of exposed field-effect transistor is reduced simultaneously Road length.Higher g_mMore preferable control to channel conductance is provided, but drains and close to source electrode they is talked to each other, so as to Make output resistance relatively low.This obtains the relatively low intrinsic gain of the MOSFET under nano-grade size.On the contrary, CiFET is low defeated Go out resistance device and improve depth.

According to a preferred embodiment of the invention, noise figure can be expressed especially excellent on front-end amplifier by proper proportion Change.The electrical characteristics of iFET can be by changing the combined and relative intensity of source electrode and drain electrode raceway groove without changing available IC processes (being extended without simulating) strengthens.In the presence of the several methods for realizing this optimization (adjustment length, width and especially threshold value).

Substantially any source electrode and drain electrode trench size will form effective iFET, but depending on target, change indivedual The opposite and accumulated size of iFET raceway grooves can increase iFET performances.

Fundamentally：

● realize lower iPort impedances using lower current density (wider) source channel compared with drain channel.

● higher voltage gain is obtained by more high resistance (longer) drain channel compared with source channel, this generation The more high output impedance (iFET voltage gains=drain channel resistance/source channel resistance) pried through into drain terminal.

● the compromise of power and speed by for make reactive current pass through complementation iFET amplifiers all raceway groove intensity Cusum control.This just establishes output conversion rate (or output driving ability).

It more clearly says, the intensity of iFET raceway grooves and its threshold value are with individual channels width and length change.IFET ditches Each threshold value relationship with size selected individually and/or with another raceway groove in road.

Fig. 2 e show various convention/symbols of the iFET devices of the present invention.Show to represent the symbol 22g and 24g of PiFET with And represent the symbol 21g and 23g of NiFET.For example, NiFET 21g or 23g represent there is shorter source as described earlier The N-shaped iFET (or NiFET) of pole raceway groove, and therefore, as can be seen, showing NiPort close to source electrode.For combining the drain electrode of iFET: The example size design that source electrode ratio is 4, NiFET devices 21g can be W_min/2xL_minDrain channel, and source channel is 2xW_min/L_min.This NiFET will allow for the relatively low input iPort terminal resistances using current gain target as target, this is suitable for High-gain current inputs transimpedance amplifier application.Similarly, show that PiFET 22g or 24g also make PiPort close to source electrode, this Represent wider source channel.Combination iFET for being still 4 drains:Source electrode ratio, the example size design of PiFET devices 22g Can be 3xW_min/2xL_minDrain channel, and source channel can be 6xW_min/L_min, but in order to which similar PiFET is arrived Ratio of the bulk strength of NiFET with 3x PiFET to NiFET adjusts, so as to generally balance the total channel conductions of P to N.

Although iFET amplifiers are in order to be exceedingly fast response and high accuracy can be configured with and can be provided at output really fully The minimum dimension device of electric current, but still care must be taken so that complementary iFET amplifiers do not transmit excessive electric current, in order to avoid there is machine Tool failure.Physical layout needs enough contact point and metal for required DC and transient current.

Noise advantage：

Finally, it is attributed to signal-to-noise ratio.Low supply voltage in μm IC techniques of ultra-deep Asia requires to limit the peak signal amplitude of oscillation It is formed on the numerical value more much smaller than what most of board designs teacher were accustomed to.Therefore in the case of compared with small-signal, noise must be same Etc. ground it is small to maintain wanted signal-to-noise ratio.It is imperative to reduce noise problem.This iFET amplifier techniques are not only as institute's necessity will Noise reduction is a certain amount of, but also shows far out of expectation, so as to which super quiet front end be presented.

1/f noise in source channel is reduced because automatic biasing scheme provided on the grid of source channel it is higher Field intensity so as to which the carrier in raceway groove be forced just to work under the surface, exists in the lower face than being lacked along lattice Fall into the smoother path (less obstacle) in the surface of interference.

1/f noise in drain channel is relatively low.Different from conventional analog design, grid is as drained between power rail Middle point automatic biasing, and iPort electric power rail~100 millivolts in.In the high electric field and grid along drain channel In the case that voltage is equal to drain terminal voltage, carrier is limited to mainly in channel surface flowing underneath.This makes drain channel From pinch off situation, non-required 1/f noise can be generated under pinch off situation.

Resistor noise is reduced, because automatic biasing configuration makes complementary pair be in its minimum channel resistance operation Point.Resistance is generated by the collision between the carrier and neighboring atom in conductor.Resistance is lower, and collision is fewer.

For high-frequency circuit, broadband noise (white noise) will be a problem always in terms of high-gain.Although conventional set Meter adjustment grid voltage is with the suitable operating point of establishment, but grid electricity is established in the design of the present invention at optimum point (" sweet spot ") Pressure, then adjustment load want operating point with establishment.This method establishes higher quiescent currents, wherein (for explained above Reason) higher current density circuit have relatively low broadband noise.

There are the inhibition of high common-mode current source in the complementary iFET circuits of the present invention.Signal is with reference to intermediate point rather than with reference to power rail In one the amplifier of its " virtual " ground connection (be similar to).Power supply noise is from a rail to another rail, phase relative to each other Deng and reverse phase；Therefore it is offset around intermediate point.

Ground connection-loop noise is weakened, because circuit ground is " virtual " (as in many operational amplifier circuits) Rather than as one or the ground connection of another mains connection.... under closed-loop case, using " flying capacitor " (or " input electricity Press sampling capacitor ").In the case of " flying capacitor ", it is not present between at different levels and is directly electrically connected, therefore there is no share Ground connection；It is virtual or other means.Similar transformer is provided between at different levels the use of " difference decoupling " (flying capacitor) Isolation, and integrated circuit component is compact.

Coupled noise from " parasitic inductive crosstalk " with signal amplitude square increase.By coefficient 100:1 (square-law effect Should), the unvested capacitive coupling in the case of 1 vor signal can generate many troubles more than the situation than 100mV signal.Simulate section The small voltage signal of middle use generally reduces this capacitive coupling interference.According to definition, neighbouring digital signal will be high-amplitude (track to track).Good layout practice is still the optimum defense to this digital noise source.

Additional advantage：

There are multiple additional advantages.For example, mean that electric current can be flowed into and be flowed out to the double-direction control of iPort This connection；Both direction all has notable control effect to entire channel current.The iPort has more than grid about five (5) The dynamic control range of a order of magnitude.

The iFET of the present invention generates the significantly faster model configuration of logic than using identical mos device.This speed Improve attribution on the fact that：Complementary structure at its natural automatic biasing point, embody it and most increase by the centre position between power supply Beneficial (and highest quiescent current).

Due toiPortVoltage does not significantly change, not by the R/C time constant effects of the ghost effect of surrounding, Therefore iPort (electric current) inputs respond than grid (voltage) input faster.

Due in most of applications of the CiFET set composites of the present invention, output voltage (drain junction) not pole The earth changes, so that output is not influenced by the R/C time constant effects of ghost effect around.Herein, logical signal ratio Simulation is slow, because logical signal must swing to rail from rail.

Drain-induced barrier reduction is avoided in the CiFET set composites operated with simulation model or (DIBL) threshold value subtracts It is small.It when gain and more important threshold voltage, drains and is operated with the approximately half of of supply voltage, thus eliminate DIBL effects Active higher drain voltage.

Bandgap reference circuit is of crucial importance for analog circuit.Analog IC is required to the steady of the key value of such as voltage Fixed reference, the key value can change with temperature change.Circuit performance depends entirely on correct biasing, and any fluctuation It may cause to design incorrect or even inoperable.Therefore, reference circuit can be used for checking and change so that necessary to correct To carry out that circuit is allowed to well perform.It has been found that compact automatic biasing CiFET can as is shown in fig. 4 a with it is absolute Temperature proportional (PTAT) circuit.

Circuit diagram shown in Fig. 3 m is that Christoffersen, C. et al. exists《Ultra low power CMOS PTAT current sources (An Ultra-Low Power CMOS PTAT Current Source)》, IEEE-EMATA 2010, page 35 to page 40 Proposed in the prior art with absolute temperature proportional (PTAT) circuit.As shown, this prior art circuits requirement Multiple component counts include at least 41 big transistor npn npns.The multiple bias currents of further requirement have this effect, and therefore pre- Phase, this previous circuit will be with much higher power dissipation.Large assemblies counting is attributed to, further contemplates that this prior art electricity Road would further require bigger region.In addition, further contemplate that this prior art circuits will be extremely sensitive to temperature and humidity.Also It would further require the accuracy of multiple coalignments.Accordingly, there exist at least one aspects to improving prior art circuits It is long-term to need.

Fig. 4 a show the schematic diagram of CiFET reference circuits 100 according to a preferred embodiment of the present invention.Fig. 4 b The schematic diagram of CiFET current source circuits 150 according to a preferred embodiment of the present invention is shown.

Fig. 4 a show the reference circuits with CiFET amplifier architectures, include NiFET Q104 and PiFET Q105.Electricity Source voltage Vss (negative supply voltage) is connected to the source terminal 104s of NiFET Q104, and Vdd (positive supply voltage) is connected to The source terminal 104s of PiFET Q105a.The respective drain terminals 104d and 105d of NiFET Q104a and PiFET Q105a connect It is connected together and provides analog zero offset with reference to 100bias and be provided to common grid 100cg, the common grid connection To the respective gate terminals 104g and 105g of NiFET Q104a and PiFET Q105a.With setting for~1mv to~100mV The stabilization of range repeat voltage be presented in iPort control terminals 104i (or lower tracks bandgap reference 100LR) and 105i (or Upper track bandgap reference 100UR) on.This is a type of band gap reference voltage by following generation：Force complete phase With electric current by the transistor channel of two difference MOS channel widths that is connected in series with, while these MOS transistor raceway grooves are total to Enjoy identical grid voltage.N-channel iPort (or iPort control terminals) 104i of NiFET Q104 is presented (or negative to be supplied higher than Vss Piezoelectric voltage) bandgap reference, and P-channel iPort (or iPort control terminals) 105i of PiFET Q105 present less than Vdd (or Positive supply voltage) its band gap reference voltage.

As can be seen that voltage output is linear in a very wide range of temperature range in Fig. 4 c.In addition, this curve graph figure Show：Lower tracks bandgap reference 100LR (with absolute temperature proportional or PTAT) and upper track bandgap reference 100UR (with it is exhausted The complementary or CTAT to temperature) voltage is with same magnitude --- accurately with opposite slope --- and can be set by iFET ratios It puts.Therefore, the circuit 100 in Fig. 4 a generates desired voltage reference --- since designer can be only by the W/L ratios of iFET Voltage is set.CiFET PTAT/CTAT be it is compact, low-power, good power supply rejection ratio (or PSSR) is shown, and can expand It opens up in the sub- μm CMOS technology of ultra-deep.

Fig. 4 c are shown in the mutual NiPort PTAT of tracking and PiPort CTAT voltages in limiting temperature limitation.NiPort PTAT voltage measures upwards from CiFET negative power source terminals voltage, and PiPort CTAT voltages are from CiFET positive power source terminals What sub- voltage measured downwards.Therefore, these reference voltages are the iPort voltages far from its corresponding iFET source terminal and are temperature Linear function.The reference voltage is set by various CiFET ratios and injects finishing using small iPort electric currents.It opens Powered-down appearance sampled data technology can be used for generating the various function of reference.The combination of these voltages can also be as shown in figure 4d heap It is folded.

Reference circuits 160 in Fig. 4 d are another examples of the serviceability of CiFET initiative units.Circuit 160 wraps Containing a CiFET in four (4), that is, include the first CiFET of NiFET Q104A and PiFET Q105A；Comprising NiFET Q104B and The 2nd CiFET of PiFET Q105B；Include the 3rd CiFET of NiFET Q104C and PiFET Q105C；And include NiFET The 4th CiFET of Q104D and PiFET Q105D.For each in CiFET, as described by previously for Fig. 4 a, gate terminal Sub- 104Ag and 105Ag；104Bg and 105Bg；104Cg and 105Cg and 104Dg and 105Dg links together to be respectively formed Common grid terminal 100Acg, 100Bcg, 100Ccg and 100Dcg.Similarly, for each CiFET, drain terminal 104Ad and 105Ad；104Bd and 105Bd；104Cd and 105Cd；104Dd and 105Dd link together be respectively formed output 100Ao, 100Bo, 100Co and 100Do, and each output 100Ao, 100Bo, 100Co or 100Do connects respectively due to being used for its biasing Take back corresponding common grid 100Acg, 100Bcg, 100Ccg and 100Dcg.In practice, the source electrode of PiFET Q105A Terminal 105As is connected to positive voltage source V_dd；And the source terminal 104As of NiFET Q104A is connected to negative voltage power supply V_ss。 As stated previously, the iPort 105Ai of PiFET Q105A provide CTAT reference voltages；The iPort of NiFET Q104A 104Ai provides PTAT reference voltages.

For follow-up CiFET, the source terminal 104Bs of NiFET Q104B receives the iPort from previous NiFET 104A The PTAT reference voltages that 104Ai is generated；The source terminal 105Bs of PiFET Q105B receives the iPort from previous PiFET 105A The CTAT reference voltages that 105Ai is generated；And common grid 100Bcg receives the NiFET Q104A and PiFET of previous CiFET The output 100Ao of Q105A.Similarly, for NiFET Q104C and PiFET Q105C, the NiFET Q104C's of follow-up CiFET Source terminal 104Cs receives the PTAT reference voltages generated from the iPort 104Bi of previous NiFET 104B；PiFET Q105C Source terminal 105Cs receive the CTAT reference voltages generated from the iPort 105Bi of previous PiFET 105B；And common grid 100Ccg receives the output 100Bo of NiFET Q104B and the PiFET Q105B of previous CiFET.This can further be repeated.Citing For, for follow-up CiFET NiFET Q104D and PiFET Q105D, NiFET Q104D source terminal 104Ds receive from The PTAT reference voltages that the iPort 104Ci of previous NiFET 104C are generated；The source terminal 105Ds of PiFET Q105D is received The CTAT reference voltages generated from the iPort 105Ci of previous PiFET 105C；And common grid 100Dcg receives previous CiFET NiFET Q104C and PiFET Q105C output 100Co.Herein, biasing and iPort reference voltages pass through the W/L in iFET The ratio expression setting of value.Circuit 160 is automatic biasing, compact, low-power, and in deep sub- μm comprising FinFET and nanoscale It can be operated under low suppling voltage in CMOS technology.

Fig. 4 b show the current source circuit for including being similar to the circuit of the Voltage Reference generator circuitry shown in Fig. 4 a 150 another example, the current source circuit include NiFET Q104a and PiFET Q105a and for generating electric current output Additional iFET the devices Q106 and Q107 of 150a and 150b.The drain terminal 104ad of NiFET Q104a and PiFET Q105a and 105ad link together for will bias Bias provide NiFET Q104a and PiFET Q105a and NiFET Q106 and The gate control terminal 104ag and 105ag and 106g and 107g of PiFET Q107.Upper track bandgap reference 100UR from The iPort terminals 105ai of PiFET Q105a is fed to the iPort terminals 107i of PiFET Q107 for generating electric current 150b, And lower tracks bandgap reference 150LR is fed to the iPort ends of NiFET Q106 from the iPort terminals 104ai of NiFET Q104a Sub- 106i is for generation electric current 150a.These electric currents can be useful for the offset sensors of such as photodiode.

Fig. 4 e show according to the present invention with simulating the relevant reference voltage generation of virtual ground (CiFET automatic biasings) voltage The schematic diagram of device 170.Generator 170 includes two couples of complementary CiFET, and first pair includes NiFET N150A and PiFET P150A, and second pair includes NiFET N150B and PiFET P150B.The source terminal P150Aa of PiFET P150A is coupled to Positive supply Vdd；The source terminal N150Ba of NiFET N150Ba is coupled to negative supply Vss；The leakage of first couple of P150A and N150A Extremely sub- P150Ac and N150Ac links together；Drain terminal P150Bc and N150Bc also link together；And source terminal N150Aa, source terminal P150Ba and gate terminal N150Ad, P150Ad, N150Bd and P150Bd are both connected to together. In this configuration, the first output 170a references+power supply or positive voltage Vdd；(it is PiFET P150A to second output 170b IPort P150Ab) generate it is relevant with absolute temperature complementarity (or CTAT) reference voltage with positive supply Vdd；Third exports 170c (it is the iPort N150Ab of NiFET N150A) generate with analogue ground voltage 170d it is relevant with absolute temperature into than Example (or PTAT) reference voltage；

4th output 170d generates analogue ground；(it is the iPort terminals of PiFET P150B to 5th output 170e P150Bb it) generates relevant with absolute temperature complementarity (or CTAT) analog reference voltage with analogue ground 170d；6th output 170f (it is the iPort terminal N150Bb of NiFET N150B) generate with power ground (Vss) it is relevant with absolute temperature into than Example (or PTAT) reference voltage；And the 7th exports 170g reference power sources ground connection or negative supply Vss.

The definition of term：

iFET：4 terminals (adding body) device, is pierced similar to field-effect transistor but with described device is made to input electric current Swash the additional control connection made a response.

Source channel：IPort spreads the semiconductor regions between source diffusion.Conduction in this region is by grid Suitable voltage realize.

Drain channel：Semiconductor regions between drain diffusion and iPort diffusions.Conduction in this region is by grid Suitable voltage realize.

CiFET：Single-stage complementation iFET set composites shown in Fig. 3 a.

Supersaturation：Index conductive condition, similar to weak transoid, but with high gate overdrive and along conducting channel Force low-voltage.Fig. 2 b#23b.

Feedforward：In early stage to predict that the technology of the signal in relation to exporting is presented in end value.

Automatic biasing：Different from fixed bias circuit, auto bias circuit is adapted to local condition, so as to establish optimal behaviour Make a little.

Duality：(in theorem, expression etc.) and related to another, such as is arrived in " mutual conductance " by the exchange of variable pair Electric current and voltage in " across resistance ".

Across resistance：It is the duality of mutual conductance, referred to as mutual resistance once in a while.The term is the contraction of transfer resistance.It refers to two Ratio between the change of voltage at a output point and the change of the relevant electric current by two input points, and use symbol table It is shown as r_m：

Across the SI units of resistance be exactly ohm, such as resistance.

For small signal communication electricity, this definition is simpler：

Transimpedance：Similar to across resistance, but further include the aleatory variable for high frequency applications.

Mutual conductance is the attribute of certain electronic building bricks.It is conductive reciprocal with resistance；Mutual conductance is the curent change and input at output The ratio of the voltage change at place.It writes g_m.For direct current, mutual conductance is defined as below：

For small signal communication electricity, this definition is simpler：

Mutual conductance is the contraction of transefer conductance.The old unit mou (ohm mirror writing) of conductance is replaced by SI units west gate Son, symbol are S (often lying prostrate 1 Siemens=1 ampere).

Translinear circuit：Translinear circuit is the circuit that its function is performed using Span Calculation.These are can Use the transistor for deferring to Exponential current-voltage characteristic --- this includes BJT and the CMOS transistor in weak transoid --- manufacture Current-mode circuit.

Sub-threshold-conducting or sub-threshold leakage or subthreshold value drain current are in crystal between the source electrode of MOSFET and drain electrode Electric current when pipe is in sub-threshold region or weak inversion regime (that is, gate source voltage is less than threshold voltage).It is described in Tsividis The term of various transoid degree.(Yannis Tsividis(1999)；《The operation of MOS transistors and modeling (Operation and Modeling of the MOS Transistor)》(second edition)；New York：McGraw-Hill；Page 99；ISBN0- 07-065523-5。)

Sub-threshold slope：In sub-threshold region, although drain current behavior --- being controlled by gate terminal --- is similar to Forward-biased diodes press the increased electric current of exponential law.Therefore, it is fixed in drain electrode, source electrode and bulk voltage, it is right Substantially logarithmic linear behavior will be presented in the curve graph of number drain current and grid voltage in this MOSFET mode of operation.Its slope It is sub-threshold slope.

Dissufion current：Dissufion current is the electricity generated in semiconductor by the diffusion of electric charge carrier (hole and/or electronics) Stream.Dissufion current can with because the direction of drift current formed during the electric field in semiconductor it is identical or opposite.It is equal in p-n junction Under weighing apparatus state, forward direction dissufion current and reverse excursion current balance type in depletion region so that net current zero.Dissufion current and drift Electric current is moved to be described by drift-diffusion equation together.

Drain-induced barrier reduces：Drain-induced barrier reduction or DIBL are the short-channel effects in MOSFET, are initially The threshold voltage for referring to transistor reduces under higher drain voltage.

As channel length reduces, the potential barrier to be crossed during it leads to drain electrode of the electronics from source electrodeSubtract It is small.

As channel length reduces, the DIBL effects in sub-threshold region (weak transoid) are initially with subthreshold current and gate bias The form that the simple translation and drain voltage of curve change occurs, this can be modeled as the threshold voltage letter under the bias conditions that drain It is single to change.However, under more short length, electric current reduces with gate bias slope of a curve, that is, it needs the larger change of gate bias To realize the identical change of drain current.Under extremely short length, grid completely can not cutoff device.These effects can not be made It is modeled for adjusting thresholds.

DIBL has an effect on electric current and drain electrode bias curve in active mode so that and electric current increases as drain electrode biases, So as to reduce MOSFET output resistances.This increase has exceeded the normal channel length modulation to output resistance, and can not be always It is modeled as adjusting thresholds.

The power supply rejection ratio that PSSR expressions are defined as below：

Wherein A is the gain of circuit.The basis of PSSR is placed on amplifier and is input on offset voltage by some manufacturers, and The basis of PSSR is placed in the voltage output as shown in example equation by other manufacturers.

Claims (4)

1. a kind of and absolute temperature proportional reference voltage circuit, including：

A pair of complementary N-shaped electric current field-effect transistor (NiFET) and p-type electric current field-effect transistor (PiFET), it is described Each include in NiFET and PiFET：

Each source terminal, drain terminal, gate terminal in the PiFET and NiFET and corresponding conduction type Terminal is spread, defines the source terminal and the source channel spread between terminal and the drain terminal and the expansion The drain channel between terminal is dissipated, the diffusion terminal causes the diffusion charge in the entire source electrode and drain electrode raceway groove close The change of degree, and the gate terminal is capacitively coupled to the source channel and the drain channel；

The gate terminal of wherein described PiFET and the gate terminal of the NiFET are joined together to form shared Gate terminal, the source terminal of the NiFET is connected to negative supply and the source terminal of the PiFET is connected to just Power supply, and the drain terminal of the NiFET and the PiFET are joined together to form output；And

The common grid of wherein described complementary pair links together to generate mould with the output of the complementary pair Intend zero reference voltage, positive rail at the diffusion terminal of the PiFET is provided and is referred to absolute temperature complementarity (or CTAT) Voltage output and offer negative rail and absolute temperature proportional (or PTAT) reference electricity at the diffusion terminal of the NiFET Pressure output.

2. a kind of positive current reference and negative current refer to generator, including：

A. first and second is to complementary N-shaped electric current field-effect transistor (NiFET) and p-type electric current field-effect transistor (PiFET), each include in the NiFET and PiFET：

The diffusion terminal of each correspondence conduction type in the PiFET and NiFET, source terminal, drain terminal and Gate terminal,

The drain terminal defines the source channel and the drain terminal between the source terminal and the diffusion terminal With the drain channel between the diffusion terminal, the diffusion terminal causes the expansion in the entire source electrode and drain electrode raceway groove The change of charge density is dissipated, and the gate terminal is capacitively coupled to the source channel and the drain channel；

Wherein, for each complementary pair, the gate terminal of the PiFET is connected with the gate terminal of the NiFET Together to form common grid terminal, the source terminal of the NiFET is connected to the described of negative supply and the PiFET Source terminal is connected to positive supply, and the drain terminal of the NiFET and PiFET be joined together to form it is defeated Go out；And

The common grid of first and second wherein described complementary pair and the output of first complementary pair are connected to one Rise, so as at the diffusion terminal of the PiFET of first complementary pair by positive rail and absolute temperature complementarity (or CTAT) reference voltage output provides the diffusion terminal to the PiFET of second complementary pair for described in generation Negative reference current；And at the diffusion terminal of the NiFET of first complementary pair by negative rail and absolute temperature into Ratio (or PTAT) reference voltage output provides the diffused channel to the NiFET of second complementary pair for production The raw positive reference current.

3. a kind of stack and absolute temperature proportional reference voltage circuit, including：

The N-shaped electric current field-effect transistor (NiFET) of multipair complementation and p-type electric current field-effect transistor (PiFET), it is described Each include in NiFET and PiFET：

Each source terminal, drain terminal, gate terminal in the PiFET and NiFET and corresponding conduction type Terminal is spread, defines the source terminal and the source channel spread between terminal and the drain terminal and the expansion The drain channel between terminal is dissipated, the diffusion terminal causes the diffusion charge in the entire source electrode and drain electrode raceway groove close The change of degree, and the gate terminal is capacitively coupled to the source channel and the drain channel；

The gate terminal of wherein described PiFET and the gate terminal of the NiFET are joined together to form shared Gate terminal, and the drain terminal of the NiFET and the PiFET are joined together to form output；And

The common grid of wherein described complementary pair links together to generate mould with the output of the complementary pair Intend zero reference voltage, positive rail at the diffusion terminal of the PiFET is provided and is referred to absolute temperature complementarity (or CTAT) Voltage output and offer negative rail and absolute temperature proportional (or PTAT) reference electricity at the diffusion terminal of the NiFET Pressure output；

The source terminal of the NiFET of first in the wherein the multiple complementary pair is connected to negative supply, and The source terminal of the PiFET of described first in the multiple complementary pair is connected to positive supply,

The source terminal of the NiFET of the latter in the multiple complementary pair receives the multiple complementation The previous PTAT reference voltage outputs of centering；The PiFET's of described the latter in the multiple complementary pair The source terminal receives the previous CTAT reference voltage outputs in the multiple complementary pair；It is and the multiple The common grid of described the latter in the complementary pair receives described previous in the multiple complementary pair The output.

4. it is a kind of with absolute temperature proportional reference voltage and with absolute temperature complementarity reference voltage generator circuit, including：

A. first pair of complementary N-shaped electric current field-effect transistor (NiFET) and p-type electric current field-effect transistor (PiFET)；

B. second couple of complementary NiFET and PiFET；

Each include in the NiFET and PiFET：

I. each source terminal in the PiFET and NiFET, drain terminal, gate terminal and corresponding conduction type Diffusion terminal, define the source terminal and it is described diffusion terminal between source channel and the drain terminal with it is described The drain channel between terminal is spread, the diffusion terminal causes the diffusion charge in the entire source electrode and drain electrode raceway groove The change of density, and the gate terminal is capacitively coupled to the source channel and the drain channel；

The drain terminal of the NiFET and the PiFET of wherein described first complementary pair are coupled；

The drain terminal of the NiFET and the PiFET of second complementary pair are coupled；

The source terminal of the PiFET of first complementary pair receives positive supply；

The source terminal of the NiFET of second complementary pair receives negative supply；

The gate terminal of the PiFET of wherein described first complementary pair and second complementary pair is complementary with described first Pair and the gate terminal of the NiFET of second complementary pair be joined together to form common grid, and receive institute State the source terminal of the source terminal of the NiFET of the first complementary pair and the PiFET of second complementary pair Son, for generating positive rail and absolute temperature complementarity at the diffusion terminal of the PiFET of first complementary pair (or CTAT) reference voltage output generates CTAT simulations at the diffusion terminal of the NiFET of first complementary pair Ground reference exports, and analogue ground reference voltage is generated at the common grid, described in second complementary pair Negative rail and absolute temperature proportional (or PTAT) reference voltage output are generated at the diffusion terminal of NiFET.