TW202017290A - Digital linear regulator and a power mos array thereof - Google Patents

Digital linear regulator and a power mos array thereof Download PDF

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TW202017290A
TW202017290A TW107136551A TW107136551A TW202017290A TW 202017290 A TW202017290 A TW 202017290A TW 107136551 A TW107136551 A TW 107136551A TW 107136551 A TW107136551 A TW 107136551A TW 202017290 A TW202017290 A TW 202017290A
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oxide semiconductor
metal oxide
power
coarse
semiconductor transistor
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TWI678061B (en
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張凱璿
蔡建泓
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財團法人成大研究發展基金會
奇景光電股份有限公司
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract

A power metal-oxide-semiconductor (MOS) array adaptable to a digital linear regulator includes a plurality of MOS circuits each including a first MOS transistor and a second MOS transistor that are electrically connected in series between a power supply and an output node of the digital linear regulator. The first MOS transistor acts as a current source controlled by an output voltage at the output node.

Description

數位線性調節器與功率金屬氧化物半導體陣列Digital linear regulator and power metal oxide semiconductor array

本發明係有關一種線性調節器，特別是關於一種具動態電流源功率金屬氧化物半導體(MOS)陣列的數位線性調節器。The invention relates to a linear regulator, in particular to a digital linear regulator with a dynamic current source power metal oxide semiconductor (MOS) array.

線性電壓調節器，例如低壓降(low-dropout)調節器為一種直流線性電壓調節器，可適用以調節輸出電壓。由於其尺寸小且設計簡單，因此普遍應用於單晶片系統(system on chip)以提供個別電壓。數位線性調節器由於其低壓操作，因此較佳應用於現代系統。Linear voltage regulators, such as low-dropout regulators, are a type of DC linear voltage regulators that can be adapted to regulate the output voltage. Due to its small size and simple design, it is commonly used in system on chip to provide individual voltages. Digital linear regulators are preferably used in modern systems due to their low voltage operation.

傳統數位線性調節器於非穩定的暫態(例如過衝(overshoot)或下衝(undershoot)電壓)時，由於其須等待下一時脈週期或/且類比至數位轉換(ADC)的轉換時間，因此回復較慢或消耗較大功率。一些數位線性調節器雖然具有改良的暫態回復或較小功耗，然而數位線性調節器會干擾相同接地的其他電路。Traditional digital linear regulators have to wait for the next clock cycle or/and analog-to-digital conversion (ADC) conversion time during unstable transients (such as overshoot or undershoot voltage), So the recovery is slower or consumes more power. Although some digital linear regulators have improved transient recovery or lower power consumption, digital linear regulators can interfere with other circuits that are grounded at the same time.

因此亟需提出一種新穎的數位線性調節器，以克服傳統數位線性調節器的缺失。Therefore, there is an urgent need to propose a novel digital linear regulator to overcome the lack of the traditional digital linear regulator.

鑑於上述，本發明實施例的目的之一在於提出一種具動態電流源功率金屬氧化物半導體(MOS)陣列的數位線性調節器。In view of the above, one of the objectives of the embodiments of the present invention is to provide a digital linear regulator with a dynamic current source power metal oxide semiconductor (MOS) array.

根據本發明實施例，適用於數位線性調節器的功率金屬氧化物半導體陣列包含複數金屬氧化物半導體電路。每一金屬氧化物半導體電路包含第一金屬氧化物半導體電晶體與第二金屬氧化物半導體電晶體，其電性串聯於電源與數位線性調節器的輸出節點之間。其中第一金屬氧化物半導體電晶體作為電流源，受控於輸出節點的輸出電壓。According to an embodiment of the present invention, a power metal oxide semiconductor array suitable for a digital linear regulator includes a plurality of metal oxide semiconductor circuits. Each metal oxide semiconductor circuit includes a first metal oxide semiconductor transistor and a second metal oxide semiconductor transistor, which are electrically connected in series between the power supply and the output node of the digital linear regulator. The first metal oxide semiconductor transistor as a current source is controlled by the output voltage of the output node.

第一A圖顯示本發明實施例之具動態電流源功率金屬氧化物半導體(MOS)陣列的數位線性調節器(regulator)100的方塊圖，第一B圖例示部分第一A圖的細部方塊圖。本實施例之數位線性調節器100可適用於單晶片系統(system on chip)以提供個別電壓。FIG. 1A shows a block diagram of a digital linear regulator 100 with a dynamic current source power metal oxide semiconductor (MOS) array according to an embodiment of the present invention. FIG. 1B shows a partial block diagram of part 1 of FIG. . The digital linear regulator 100 of this embodiment can be applied to a system on chip to provide individual voltages.

在本實施例中，數位線性調節器100可包含微調迴路(fine-loop)控制器11及微調功率金屬氧化物半導體陣列(以下簡稱微調功率陣列)12。於穩態(steady state)，數位線性調節器100的調節輸出電壓Vout為穩定的，微調迴路控制器11可開啟微調功率陣列12，其包含有複數微調功率金屬氧化物半導體電晶體，以產生輸出電壓Vout。負載10連接於輸出電壓Vout與地之間，以接收輸出電壓Vout。In this embodiment, the digital linear regulator 100 may include a fine-loop controller 11 and a fine-tune power metal oxide semiconductor array (hereinafter referred to as fine-tune power array) 12. In a steady state, the regulated output voltage Vout of the digital linear regulator 100 is stable, and the trimmer loop controller 11 can turn on the trimmer power array 12, which includes a complex trimmer power metal oxide semiconductor transistor to generate an output Voltage Vout. The load 10 is connected between the output voltage Vout and ground to receive the output voltage Vout.

數位線性調節器100可包含粗調迴路(coarse-loop)控制器13及粗調功率金屬氧化物半導體陣列(以下簡稱粗調功率陣列)14。於暫態(transient state或不穩態)，數位線性調節器100的調節輸出電壓Vout為不穩定的，粗調迴路控制器13可開啟粗調功率陣列14，其包含有複數粗調功率金屬氧化物半導體電晶體，以產生輸出電壓Vout。一般來說，粗調功率陣列14的粗調功率金屬氧化物半導體電晶體之尺寸大於微調功率陣列12的微調功率金屬氧化物半導體電晶體。The digital linear regulator 100 may include a coarse-loop controller 13 and a coarse-tune power metal oxide semiconductor array (hereinafter referred to as coarse-tune power array) 14. In the transient state (transient state or unstable state), the regulated output voltage Vout of the digital linear regulator 100 is unstable, and the coarse loop controller 13 can turn on the coarse power array 14, which includes the complex coarse power metal oxide Semiconductor transistor to generate the output voltage Vout. Generally speaking, the size of the coarse tuning power metal oxide semiconductor transistor of the coarse tuning power array 14 is larger than that of the fine tuning power metal oxide semiconductor transistor of the fine tuning power array 12.

本實施例之數位線性調節器100可包含類比至數位轉換器(ADC)暨狀態電路15，用以進行類比至數位轉換，且根據輸出電壓Vout以決定數位線性調節器100的目前狀態(亦即穩態或暫態)。The digital linear regulator 100 of this embodiment may include an analog-to-digital converter (ADC) and state circuit 15 for performing analog-to-digital conversion, and determining the current state of the digital linear regulator 100 according to the output voltage Vout (i.e. Steady or transient).

本實施例之類比至數位轉換器暨狀態電路15可包含比較器151，其接收數位線性調節器100的輸出電壓Vout與(預設)參考電壓Vref，據以產生比較信號Vcomp 。類比至數位轉換器暨狀態電路15可包含類比至數位轉換器(ADC)152，用以產生(數位)類比至數位轉換輸出，其為輸出電壓Vout與參考電壓Vref的差值。類比至數位轉換器暨狀態電路15可包含狀態電路153，其根據類比至數位轉換輸出以產生事件信號ENT，以代表目前狀態。The analog-to-digital converter and state circuit 15 of this embodiment may include a comparator 151 that receives the output voltage Vout of the digital linear regulator 100 and the (default) reference voltage Vref, and generates the comparison signal V comp . The analog-to-digital converter and status circuit 15 may include an analog-to-digital converter (ADC) 152 for generating (digital) analog-to-digital conversion output, which is the difference between the output voltage Vout and the reference voltage Vref. The analog-to-digital converter and status circuit 15 may include a status circuit 153 that generates an event signal ENT according to the analog-to-digital conversion output to represent the current status.

本實施例之微調迴路控制器11主要包含微調迴路移位暫存器111，其接收比較信號Vcomp ，據以產生微調移位輸出F。微調迴路移位暫存器111可包含串聯的正反器(flip flop)(未顯示於圖式)，受控於第一時脈信號CLK_f。根據本實施例的特徵之一，微調迴路移位暫存器111可被事件信號ENT開啟，於穩態期間可節省功率。當事件信號ENT為非主動(de-asserted)時，表示輸出電壓Vout為穩定的穩態，則開啟微調迴路移位暫存器111。The trimming loop controller 11 of this embodiment mainly includes a trimming loop shift register 111, which receives the comparison signal V comp and accordingly generates a trimming shift output F. The trimming loop shift register 111 may include a series flip flop (not shown in the figure), controlled by the first clock signal CLK_f. According to one of the features of this embodiment, the fine-tuning loop shift register 111 can be turned on by the event signal ENT, which can save power during the steady state. When the event signal ENT is inactive (de-asserted), indicating that the output voltage Vout is stable and stable, the trimming loop shift register 111 is turned on.

本實施例之粗調迴路控制器13主要包含粗調迴路移位暫存器131，其接收比較信號Vcomp ，據以產生粗調移位輸出C。粗調迴路移位暫存器131可接收類比至數位轉換輸出以加速位移。粗調迴路移位暫存器131可包含串聯的正反器(flip flop)(未顯示於圖式)，受控於第二時脈信號CLK_c，其快於第一時脈信號CLK_f。根據本實施例的另一特徵，粗調迴路移位暫存器131可被事件信號ENT關閉，於穩態期間可節省功率。當事件信號ENT為主動(asserted)時，表示輸出電壓Vout為不穩定的暫態，則開啟粗調迴路移位暫存器131。另一方面，當事件信號ENT為非主動(de-asserted)時，表示輸出電壓Vout為穩定的穩態，則關閉粗調迴路移位暫存器131。The coarse adjustment loop controller 13 of this embodiment mainly includes a coarse adjustment loop shift register 131, which receives the comparison signal V comp and accordingly generates a coarse adjustment shift output C. The coarse loop shift register 131 can receive the analog-to-digital conversion output to accelerate the displacement. The coarse loop shift register 131 may include a series flip flop (not shown in the figure), controlled by the second clock signal CLK_c, which is faster than the first clock signal CLK_f. According to another feature of this embodiment, the coarse loop shift register 131 can be turned off by the event signal ENT, which can save power during the steady state. When the event signal ENT is asserted, indicating that the output voltage Vout is an unstable transient state, the coarse adjustment loop shift register 131 is turned on. On the other hand, when the event signal ENT is de-asserted (de-asserted), indicating that the output voltage Vout is stable and stable, the coarse-tuning loop shift register 131 is closed.

第二A圖顯示第一A圖之微調功率陣列12的電路圖。微調功率陣列12(自微調迴路移位暫存器111)接收微調移位輸出F，據以產生輸出電壓Vout。在本實施例中，微調功率陣列12可包含複數併聯的金屬氧化物半導體電晶體M0，例如P型金屬氧化物半導體電晶體(PMOS)，其源極分別電性連接至電源Vdd，其汲極分別電性連接至輸出節點，其提供輸出電壓Vout。金屬氧化物半導體電晶體M0的閘極分別電性連接微調移位輸出F的位元。The second diagram A shows the circuit diagram of the fine-tuning power array 12 of the first diagram A. The trimming power array 12 (from the trimming loop shift register 111) receives the trimming shift output F, and accordingly generates the output voltage Vout. In this embodiment, the trimming power array 12 may include a plurality of metal oxide semiconductor transistors M0 connected in parallel, such as a P-type metal oxide semiconductor transistor (PMOS), the sources of which are electrically connected to the power supply Vdd, respectively, and the drain They are respectively electrically connected to the output node, which provides the output voltage Vout. The gates of the metal oxide semiconductor transistor M0 are electrically connected to the bits of the trimming shift output F, respectively.

第二B圖顯示第一A圖之粗調功率陣列14的電路圖。粗調功率陣列14(自粗調迴路移位暫存器131)接收粗調移位輸出C，據以產生輸出電壓Vout。在本實施例中，粗調功率陣列14可包含複數金屬氧化物半導體電路141。根據本實施例的另一特徵，每一金屬氧化物半導體電路141可包含第一金屬氧化物半導體電晶體(例如P型金屬氧化物半導體電晶體)M1與第二金屬氧化物半導體電晶體(例如P型金屬氧化物半導體電晶體)M2，其電性串聯於電源Vdd與輸出節點(其提供輸出電壓Vout)之間。其中，第一金屬氧化物半導體電晶體M1的源極電性連接至電源Vdd，其汲極電性連接至第二金屬氧化物半導體電晶體M2的源極，其閘極電性連接至第二金屬氧化物半導體電晶體M2的汲極與輸出節點(其提供輸出電壓Vout)。第二金屬氧化物半導體電晶體M2的閘極分別電性連接粗調移位輸出C的位元。在另一實施例中，微調功率陣列12也可使用第二B圖的電路架構。The second figure B shows the circuit diagram of the coarse adjustment power array 14 of the first figure A. The coarse adjustment power array 14 (from the coarse adjustment loop shift register 131) receives the coarse adjustment shift output C, and accordingly generates the output voltage Vout. In this embodiment, the coarse power array 14 may include a plurality of metal oxide semiconductor circuits 141. According to another feature of this embodiment, each metal oxide semiconductor circuit 141 may include a first metal oxide semiconductor transistor (such as a P-type metal oxide semiconductor transistor) M1 and a second metal oxide semiconductor transistor (such as The P-type metal oxide semiconductor transistor) M2 is electrically connected in series between the power supply Vdd and the output node (which provides the output voltage Vout). Wherein, the source electrode of the first metal oxide semiconductor transistor M1 is electrically connected to the power supply Vdd, the drain electrode thereof is electrically connected to the source electrode of the second metal oxide semiconductor transistor M2, and the gate electrode thereof is electrically connected to the second The drain and output node of the metal oxide semiconductor transistor M2 (which provides the output voltage Vout). The gates of the second metal oxide semiconductor transistor M2 are electrically connected to the bits of the coarse shift output C, respectively. In another embodiment, the fine-tuning power array 12 can also use the second B circuit architecture.

第二C圖顯示第二B圖之金屬氧化物半導體電路141的等效電路。在本實施例中，第一金屬氧化物半導體電晶體M1作為電流源，受控於輸出電壓Vout。第一金屬氧化物半導體電晶體M1提供源極至汲極電流ISD(M1) ，流向輸出節點(其提供輸出電壓Vout)。負載10因此得到負載電流I­load ，其包含所有金屬氧化物半導體電路141所提供的源極至汲極電流ISD(M1) 。於上升(up)暫態時(亦即負載電流Iload 從低變為高)，若輸出電壓Vout下降，則電流源(亦即第一金屬氧化物半導體電晶體M1)因阻抗減少而提供更多的源極至汲極電流ISD(M1) ，且輸出電壓Vout的下衝(undershoot)可減少。此外，輸出電壓Vout可因此於短時間從非穩定狀態回復。另一方面，於下降(down)暫態時(亦即負載電流Iload 從高變為低)，若輸出電壓Vout上升，則電流源(亦即第一金屬氧化物半導體電晶體M1)因阻抗增加而提供更少的源極至汲極電流ISD(M1) ，且輸出電壓Vout的過衝(overshoot)可減少。此外，輸出電壓Vout可因此於短時間從非穩定狀態回復。The second diagram C shows the equivalent circuit of the metal oxide semiconductor circuit 141 of the second diagram B. In this embodiment, the first metal oxide semiconductor transistor M1 as a current source is controlled by the output voltage Vout. The first metal oxide semiconductor transistor M1 provides a source-to-drain current I SD(M1) , which flows to an output node (which provides an output voltage Vout). The load 10 thus obtains the load current I load , which includes the source-to-drain current I SD(M1) provided by all the metal oxide semiconductor circuits 141. During the up transient (that is, the load current I load changes from low to high), if the output voltage Vout decreases, the current source (that is, the first metal oxide semiconductor transistor M1) provides more There is much source-to-drain current I SD(M1) , and the undershoot of the output voltage Vout can be reduced. In addition, the output voltage Vout can thus recover from an unstable state in a short time. On the other hand, during the down transient (that is, the load current I load changes from high to low), if the output voltage Vout rises, the current source (that is, the first metal oxide semiconductor transistor M1) has an impedance due to The increase provides less source-to-drain current I SD(M1) , and the overshoot of the output voltage Vout can be reduced. In addition, the output voltage Vout can thus recover from an unstable state in a short time.

第三圖顯示第一B圖之數位線性調節器100的相關信號的波形。於狀態1(亦即穩態)，輸出電壓Vout為穩定，其振幅位於電壓視窗(Vref±ΔV)內。於穩態，關閉粗調迴路移位暫存器131，但開啟微調迴路移位暫存器111以啟動微調功率陣列12，用以提供輸出電壓Vout。一般來說，微調功率陣列12(及微調迴路移位暫存器111)較粗調功率陣列14(及粗調迴路移位暫存器131)的操作速度慢、消耗較少功率且產生較高輸出電壓精準度。由於微調功率陣列12(及微調迴路移位暫存器111)消耗較少功率，數位線性調節器100因此可以降低長期的功率消耗。The third diagram shows the waveform of the related signal of the digital linear regulator 100 in the first diagram B. In state 1 (that is, steady state), the output voltage Vout is stable, and its amplitude is within the voltage window (Vref±ΔV). In the steady state, the coarse-tuning loop shift register 131 is closed, but the fine-tuning loop shift register 111 is turned on to activate the fine-tuning power array 12 to provide the output voltage Vout. Generally speaking, the fine-tuning power array 12 (and the fine-tuning loop shift register 111) is slower in operation, consumes less power, and generates higher than the coarse-tuning power array 14 (and the coarse-tune loop shift register 131) Output voltage accuracy. Since the trimming power array 12 (and the trimming loop shift register 111) consumes less power, the digital linear regulator 100 can thus reduce long-term power consumption.

於狀態2(亦即暫態)，輸出電壓Vout為不穩定，其過衝(overshoot)或下衝(undershoot)電壓超出電壓視窗(Vref±ΔV)。於暫態，關閉微調迴路移位暫存器111，但開啟粗調迴路移位暫存器131以啟動粗調功率陣列14，用以提供輸出電壓Vout。由於粗調功率陣列14(及粗調迴路移位暫存器131)的操作速度快，輸出電壓Vout因此可以於短時間從非穩定情況回復。In state 2 (that is, transient state), the output voltage Vout is unstable, and its overshoot or undershoot voltage exceeds the voltage window (Vref±ΔV). In the transient state, the fine-tuning loop shift register 111 is turned off, but the coarse-tuning loop shift register 131 is turned on to activate the coarse-tuning power array 14 to provide the output voltage Vout. Since the operation speed of the coarse adjustment power array 14 (and the coarse adjustment loop shift register 131) is fast, the output voltage Vout can be recovered from the unstable condition in a short time.

根據上述實施例，數位線性調節器100提供雙迴路控制機制以產生輸出電壓Vout。其中，於穩態，微調功率陣列12及微調迴路控制器11形成微調迴路，其具有較低的功耗與較高的輸出電壓精準度。另一方面，於暫態，粗調功率陣列14及粗調迴路控制器13形成粗調迴路，其具有較快的操作速度。According to the above embodiment, the digital linear regulator 100 provides a dual loop control mechanism to generate the output voltage Vout. Among them, in the steady state, the trimming power array 12 and the trimming loop controller 11 form a trimming loop, which has lower power consumption and higher output voltage accuracy. On the other hand, in the transient state, the coarse adjustment power array 14 and the coarse adjustment loop controller 13 form a coarse adjustment loop, which has a faster operating speed.

第四圖顯示第二B圖之粗調功率陣列14的相關信號的波形。根據本實施例之粗調功率陣列14的特徵之一，第一金屬氧化物半導體電晶體M1作為電流源，受控於輸出電壓Vout。第四圖的虛線顯示粗調功率陣列14未使用第一金屬氧化物半導體電晶體M1的相關信號的波形。根據本實施例，與數位線性調節器100相同接地的其他電路不會受到數位線性調節器100的干擾。The fourth diagram shows the waveforms of the related signals of the coarse adjustment power array 14 in the second diagram B. According to one of the features of the coarse tuning power array 14 of this embodiment, the first metal oxide semiconductor transistor M1 as a current source is controlled by the output voltage Vout. The dotted line in the fourth diagram shows the waveform of the related signal of the coarse adjustment power array 14 without using the first metal oxide semiconductor transistor M1. According to the present embodiment, other circuits grounded to the digital linear regulator 100 are not disturbed by the digital linear regulator 100.

以上所述僅為本發明之較佳實施例而已，並非用以限定本發明之申請專利範圍；凡其它未脫離發明所揭示之精神下所完成之等效改變或修飾，均應包含在下述之申請專利範圍內。The above are only the preferred embodiments of the present invention and are not intended to limit the scope of the patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit of the invention should be included in the following Within the scope of patent application.

100:數位線性調節器10:負載11:微調迴路控制器111:微調迴路移位暫存器12:微調功率金屬氧化物半導體陣列13:粗調迴路控制器131:粗調迴路移位暫存器14:粗調功率金屬氧化物半導體陣列141:金屬氧化物半導體電路15:類比至數位轉換器暨狀態電路151:比較器152:類比至數位轉換器MOS:金屬氧化物半導體Vout:輸出電壓Vref:參考電壓Vcomp:比較信號ENT:事件信號CLK_f:第一時脈信號CLK_c:第二時脈信號F:微調移位輸出C:粗調移位輸出M0:金屬氧化物半導體電晶體M1:第一金屬氧化物半導體電晶體M2:第二金屬氧化物半導體電晶體Vdd:電源ISD(M1):源極至汲極電流I­load:負載電流100: digital linear regulator 10: load 11: trimming loop controller 111: trimming loop shift register 12: trimming power metal oxide semiconductor array 13: coarse tuning loop controller 131: coarse tuning loop shift register 14: Coarse adjustment power metal oxide semiconductor array 141: metal oxide semiconductor circuit 15: analog to digital converter and state circuit 151: comparator 152: analog to digital converter MOS: metal oxide semiconductor Vout: output voltage Vref: Reference voltage V comp : comparison signal ENT: event signal CLK_f: first clock signal CLK_c: second clock signal F: fine-tuned shift output C: coarse-tuned shift output M0: metal oxide semiconductor transistor M1: first Metal oxide semiconductor transistor M2: second metal oxide semiconductor transistor Vdd: power supply I SD (M1) : source to drain current I load : load current

第一A圖顯示本發明實施例之具動態電流源功率金屬氧化物半導體(MOS)陣列的數位線性調節器的方塊圖。 第一B圖例示部分第一A圖的細部方塊圖。 第二A圖顯示第一A圖之微調功率陣列的電路圖。 第二B圖顯示第一A圖之粗調功率陣列的電路圖。 第二C圖顯示第二B圖之金屬氧化物半導體電路的等效電路。 第三圖顯示第一B圖之數位線性調節器的相關信號的波形。 第四圖顯示第二B圖之粗調功率陣列的相關信號的波形。FIG. 1A shows a block diagram of a digital linear regulator with a dynamic current source power metal oxide semiconductor (MOS) array according to an embodiment of the invention. The first figure B illustrates a detailed block diagram of part of the first figure A. The second figure A shows the circuit diagram of the fine-tuned power array of the first figure A. The second diagram B shows the circuit diagram of the coarse adjustment power array of the first diagram A. The second diagram C shows the equivalent circuit of the metal oxide semiconductor circuit of the second diagram B. The third diagram shows the waveform of the related signal of the digital linear regulator in the first diagram B. The fourth diagram shows the waveforms of the related signals of the coarse power array of the second diagram B.

10:負載 10: load

14:粗調功率金屬氧化物半導體陣列 14: Coarse tuning power metal oxide semiconductor array

141:金屬氧化物半導體電路 141: Metal oxide semiconductor circuit

Vout:輸出電壓 Vout: output voltage

C:粗調移位輸出 C: Coarse adjustment shift output

M1:第一金屬氧化物半導體電晶體 M1: the first metal oxide semiconductor transistor

M2:第二金屬氧化物半導體電晶體 M2: Second metal oxide semiconductor transistor

Vdd:電源 Vdd: power supply

ISD(M1):源極至汲極電流 I SD(M1) : source to drain current

Iload:負載電流 I load : load current

Claims (13)

一種適用於數位線性調節器的功率金屬氧化物半導體陣列，包含：        複數金屬氧化物半導體電路，每一該金屬氧化物半導體電路包含第一金屬氧化物半導體電晶體與第二金屬氧化物半導體電晶體，其電性串聯於電源與該數位線性調節器的輸出節點之間；        其中該第一金屬氧化物半導體電晶體作為電流源，受控於該輸出節點的輸出電壓。A power metal oxide semiconductor array suitable for digital linear regulators, including: a plurality of metal oxide semiconductor circuits, each of the metal oxide semiconductor circuits includes a first metal oxide semiconductor transistor and a second metal oxide semiconductor transistor , Which is electrically connected in series between the power supply and the output node of the digital linear regulator; where the first metal oxide semiconductor transistor serves as a current source and is controlled by the output voltage of the output node. 根據申請專利範圍第1項所述之功率金屬氧化物半導體陣列，其中該第一金屬氧化物半導體電晶體包含：        源極，電性連接至該電源；        汲極，電性連接至該第二金屬氧化物半導體電晶體的源極；及        閘極，電性連接該第二金屬氧化物半導體電晶體的汲極與該輸出節點。According to the power metal oxide semiconductor array described in item 1 of the patent application scope, wherein the first metal oxide semiconductor transistor includes: a source electrode electrically connected to the power supply; a drain electrode electrically connected to the second metal The source electrode of the oxide semiconductor transistor; and the gate electrode, which is electrically connected to the drain electrode of the second metal oxide semiconductor transistor and the output node. 根據申請專利範圍第2項所述之功率金屬氧化物半導體陣列，其中該第二金屬氧化物半導體電晶體包含閘極，電性連接至移位暫存器的移位輸出的相應位元。The power metal oxide semiconductor array according to item 2 of the patent application scope, wherein the second metal oxide semiconductor transistor includes a gate electrode, and is electrically connected to the corresponding bit of the shift output of the shift register. 一種數位線性調節器，包含：        一微調功率金屬氧化物半導體陣列；        一微調迴路控制器，於穩態時開啟該微調功率金屬氧化物半導體陣列，以產生該數位線性調節器的輸出電壓；        一粗調功率金屬氧化物半導體陣列；        一粗調迴路控制器，於暫態時開啟該粗調功率金屬氧化物半導體陣列，以產生該輸出電壓；        其中該粗調功率金屬氧化物半導體陣列包含複數金屬氧化物半導體電路，每一該金屬氧化物半導體電路包含第一金屬氧化物半導體電晶體與第二金屬氧化物半導體電晶體，其電性串聯於電源與提供該輸出電壓的輸出節點之間，且該第一金屬氧化物半導體電晶體作為電流源，受控於該輸出電壓。A digital linear regulator, including: a fine-tuning power metal oxide semiconductor array; a fine-tuning loop controller, turning on the fine-tuning power metal oxide semiconductor array at a steady state to generate the output voltage of the digital linear regulator; a coarse Power-tuned metal oxide semiconductor array; a coarse-tuned loop controller that turns on the coarse-tuned power metal-oxide-semiconductor array during transient to generate the output voltage; wherein the coarse-tuned power-metal-oxide semiconductor array includes a plurality of metal oxides Each of the metal oxide semiconductor circuits includes a first metal oxide semiconductor transistor and a second metal oxide semiconductor transistor, which are electrically connected in series between a power supply and an output node that provides the output voltage, and the The first metal oxide semiconductor transistor as a current source is controlled by the output voltage. 根據申請專利範圍第4項所述之數位線性調節器，其中該第一金屬氧化物半導體電晶體包含：        源極，電性連接至該電源；        汲極，電性連接至該第二金屬氧化物半導體電晶體的源極；及        閘極，電性連接該第二金屬氧化物半導體電晶體的汲極與該輸出節點。According to the digital linear regulator described in item 4 of the patent application scope, wherein the first metal oxide semiconductor transistor includes: a source electrode electrically connected to the power supply; a drain electrode electrically connected to the second metal oxide The source electrode of the semiconductor transistor; and the gate electrode, which is electrically connected to the drain electrode of the second metal oxide semiconductor transistor and the output node. 根據申請專利範圍第5項所述之數位線性調節器，其中該第二金屬氧化物半導體電晶體包含閘極，電性連接至該粗調迴路控制器的移位輸出的相應位元。The digital linear regulator according to item 5 of the patent application scope, wherein the second metal oxide semiconductor transistor includes a gate electrode, and is electrically connected to the corresponding bit of the shift output of the coarse loop controller. 根據申請專利範圍第4項所述之數位線性調節器，更包含：        一類比至數位轉換器暨狀態電路，用以進行類比至數位轉換，且根據該輸出電壓以決定該數位線性調節器的目前狀態為穩態或暫態。The digital linear regulator described in item 4 of the patent application scope further includes: an analog-to-digital converter and status circuit for analog-to-digital conversion, and the current status of the digital linear regulator is determined according to the output voltage The state is steady or transient. 根據申請專利範圍第7項所述之數位線性調節器，其中該類比至數位轉換器暨狀態電路包含：        一比較器，接收該輸出電壓與預設參考電壓，據以產生比較信號；        一類比至數位轉換器，用以產生類比至數位轉換輸出，其為該輸出電壓與該參考電壓的差值；及 一狀態電路，根據該類比至數位轉換輸出，以產生事件信號，其代表目前狀態。According to the digital linear regulator described in item 7 of the patent application scope, the analog-to-digital converter and status circuit include: a comparator that receives the output voltage and a preset reference voltage to generate a comparison signal; and an analog to The digital converter is used to generate an analog-to-digital conversion output, which is the difference between the output voltage and the reference voltage; and a state circuit to generate an event signal according to the analog-to-digital conversion output, which represents the current state. 根據申請專利範圍第8項所述之數位線性調節器，其中該微調迴路控制器包含：        一微調迴路移位暫存器，接收該比較信號，據以產生微調移位輸出，用以於穩態時啟動該微調功率金屬氧化物半導體陣列。According to the digital linear regulator described in item 8 of the patent application scope, wherein the fine-tuning loop controller includes: a fine-tuning loop shift register, which receives the comparison signal and generates a fine-tuning shift output for steady state Start the fine-tune power metal oxide semiconductor array. 根據申請專利範圍第8項所述之數位線性調節器，其中該粗調迴路控制器包含：        一粗調迴路移位暫存器，接收該比較信號，據以產生粗調移位輸出，用以於暫態時啟動該粗調功率金屬氧化物半導體陣列。According to the digital linear regulator described in item 8 of the patent application scope, wherein the coarse loop controller includes: a coarse loop shift register, which receives the comparison signal and generates a coarse shift output based on The coarse-tune power metal oxide semiconductor array is activated in the transient state. 根據申請專利範圍第4項所述之數位線性調節器，其中該粗調功率金屬氧化物半導體陣列包含複數粗調功率金屬氧化物半導體電晶體，且該微調功率金屬氧化物半導體陣列包含複數微調功率金屬氧化物半導體電晶體，其中該粗調功率金屬氧化物半導體電晶體之尺寸大於該微調功率金屬氧化物半導體電晶體。The digital linear regulator according to item 4 of the patent application range, wherein the coarse-tuning power metal oxide semiconductor array includes complex coarse-tuning power metal oxide semiconductor transistors, and the fine-tuning power metal oxide semiconductor array includes complex fine-tuning power A metal oxide semiconductor transistor, wherein the size of the coarse power metal oxide semiconductor transistor is larger than that of the fine power metal oxide semiconductor transistor. 根據申請專利範圍第4項所述之數位線性調節器，其中該粗調迴路控制器的操作快於該微調迴路控制器。According to the digital linear regulator described in item 4 of the patent application range, the coarse loop controller operates faster than the fine loop controller. 根據申請專利範圍第4項所述之數位線性調節器，其中該微調功率金屬氧化物半導體陣列包含： 複數第二金屬氧化物半導體電路，每一該第二金屬氧化物半導體電路包含第一金屬氧化物半導體電晶體與第二金屬氧化物半導體電晶體，其電性串聯於電源與該輸出節點之間，且該第二金屬氧化物半導體電路的該第一金屬氧化物半導體電晶體作為電流源，受控於該輸出電壓。The digital linear regulator according to item 4 of the patent application scope, wherein the trimming power metal oxide semiconductor array includes: a plurality of second metal oxide semiconductor circuits, each of the second metal oxide semiconductor circuits including a first metal oxide An object semiconductor transistor and a second metal oxide semiconductor transistor, which are electrically connected in series between the power supply and the output node, and the first metal oxide semiconductor transistor of the second metal oxide semiconductor circuit serves as a current source, Controlled by the output voltage.
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