JP2008270732A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device allowing an input voltage to have temperature characteristics, stepping up or stepping down the input voltage, and simplifying a circuit configuration. <P>SOLUTION: An input transistor section 11 includes a first transistor M1 having a control electrode to which a reference voltage is supplied. An output transistor section 12 includes a second transistor M11 that is diode-connected. At least either the input transistor section 11 or the output transistor section 12 further includes a third transistor that is diode-connected and series-connected to the first transistor M1 or the second transistor M11 corresponding thereto, so as to output current in the same direction as the corresponding transistor. The number of the transistors included in each of the input transistor section 11 and the output transistor section 12 is different. The size of the transistors included in the input transistor section 11 is different from the size of the transistors included in the output transistor section 12. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device that generates a voltage for temperature compensation.

  A flash memory having a circuit for generating a voltage different from an external voltage based on the external voltage for a write voltage, a read voltage, and an erase voltage for the memory cell has been developed.

  In general, since the characteristics of a memory cell change with temperature, in such a flash memory, the write voltage, read voltage, and erase voltage for the memory cell are changed corresponding to the temperature characteristic of the memory cell, that is, temperature compensation is performed. There is a need. As a circuit for performing such temperature compensation, for example, there is a temperature compensation voltage generation circuit that generates an output voltage in which a reference input voltage has a temperature characteristic. In such a temperature compensation voltage generation circuit, for example, a current mirror circuit is used.

  Here, as a voltage generation circuit using a current mirror circuit, for example, Patent Document 1 discloses the following configuration. That is, the first transistor and the second transistor constitute a current mirror circuit. The third transistor receives a comparison voltage, which is a predetermined constant voltage, via the inverting input terminal, and is connected in series with the first transistor. The fourth transistor receives a feedback voltage proportional to the output voltage of the third transistor via the non-inverting input terminal, and is connected in series with the second transistor. The current source supplies a predetermined current to the first transistor, the second transistor, the third transistor, and the fourth transistor. The offset circuit is connected in series with the third transistor, and has a predetermined input offset voltage between the inverting input terminal and the non-inverting input terminal.

  Patent Document 2 discloses the following configuration. That is, the oscillator includes a ring oscillator unit formed of a CMOS inverter and a voltage supply unit that supplies a voltage to the ring oscillator unit in the semiconductor integrated circuit device. In the first compensation means, the voltage supply unit cancels the temperature characteristic of the oscillation frequency of the ring oscillator unit. The second compensation means cancels the variation in the oscillation frequency due to the variation from the design value of the threshold voltage of the MOS transistors having different conductivity types constituting the CMOS inverter.

  Patent Document 3 discloses the following configuration. That is, the back bias circuit applies a back bias voltage for correcting the threshold voltage of a transistor to a semiconductor device including a plurality of transistors. The back bias generation circuit includes a charge pump circuit and outputs a back bias voltage. The detection circuit detects a back bias voltage from the back bias generation circuit and controls on / off of the operation of the back bias generation circuit in accordance with the voltage.

  Patent Document 4 discloses the following configuration. That is, the diode has a negative temperature coefficient for the output voltage. The gate of the temperature compensating MOS transistor is connected to one end of the diode. The current supply means is a drain current set so that the temperature compensating MOS transistor operates in a region where the gate-source voltage of the temperature compensating MOS transistor has a positive temperature coefficient that compensates for the negative temperature coefficient of the diode. Is supplied to the temperature compensating MOS transistor. A voltage obtained by adding the output voltage of the diode and the gate-source voltage of the temperature compensating MOS transistor is output as a reference voltage.

  Patent Document 5 discloses a circuit that generates a negative voltage by a charge pump inside a chip. That is, the negative voltage detection circuit detects whether the output voltage of the charge pump is a desired negative voltage and outputs a control signal. The negative voltage detection circuit detects a negative voltage depending on whether or not a voltage obtained by multiplying the output voltage of the charge pump by − (1 / n) (n is a natural number) matches a positive reference voltage. When the output voltage of the charge pump drops below a desired voltage, the charge pump operation is stopped, otherwise, a control signal for operating the charge pump is generated. By such feedback control, the output voltage of the charge pump is controlled to be a desired negative voltage.

  Patent Document 6 discloses a configuration for supplying a high voltage that is not affected by temperature changes to a control gate and a source of a memory transistor when data is written to and erased from a nonvolatile semiconductor memory. Yes. That is, the feedback voltage obtained by resistance-dividing the output high voltage is compared with the reference voltage generated by the reference voltage generation circuit. Based on the comparison result, the booster circuit for boosting the external power supply voltage is controlled to be turned on / off to control the value of the output high voltage. By giving a temperature coefficient to the reference voltage, the temperature coefficient of the threshold voltage of the MOS (Metal Oxide Semiconductor) switching transistor that turns ON / OFF the application of the high voltage to the memory transistor becomes equal to the temperature coefficient of the output high voltage. Thus, the circuit constants of the reference voltage generation circuit are determined.

  Patent Document 7 discloses a configuration for generating a temperature compensation voltage for stabilizing the oscillation frequency against temperature fluctuation.

Patent Document 8 discloses a configuration for generating an overcurrent detection reference voltage for compensating temperature characteristics of an output transistor in overcurrent detection of the output transistor.
JP 2001-298332 A JP 2001-68976 A JP 2000-163970 A JP 2000-75946 A JP 10-239357 A JP 2004-164746 A JP-A-9-83309 JP 2000-252804 A

  By the way, in the conventional temperature compensation voltage generation circuit as described above, the output voltage value may be largely deviated from the input voltage value. For example, when the output voltage becomes considerably smaller than the reference input voltage, it is conceivable to increase the reference input voltage in advance. However, this method requires a separate circuit for boosting or stepping down the reference input voltage, resulting in an increase in circuit scale.

  Moreover, since the configuration described in Patent Document 1 is a differential amplifier, the input voltage cannot be boosted or lowered. In addition, the input voltage cannot have temperature characteristics. In the configuration described in Patent Document 2, the input voltage cannot be boosted or lowered. In the configuration described in Patent Document 3 and the configuration described in Patent Document 4, the input voltage cannot be boosted or lowered, and the input voltage cannot have temperature characteristics.

  Furthermore, in the configuration described in Patent Document 5, the negative voltage detection level can be changed by changing the reference voltage. However, in the configuration described in Patent Document 5, in order to prevent the detection level of the negative voltage from depending on the power supply voltage or the like, a reference voltage having a low temperature dependency and power supply voltage dependency is generated by using a band gap reference circuit or the like. Is intended to be. Therefore, the configuration described in Patent Document 5 has a problem in that it cannot properly cope with the temperature characteristics of the negative voltage supply destination.

  In the configuration disclosed in Patent Document 6, a voltage obtained by dividing the output voltage is compared with a reference voltage having temperature characteristics, and the output voltage is generated by controlling the booster circuit based on the comparison result. Here, in the configuration described in Patent Document 6, when the configuration in which the output voltage is changed by changing the voltage dividing ratio of the output voltage is applied, it is possible to prevent variations in the output voltage value due to variations in internal elements. However, with such a configuration, the temperature characteristics of the output voltage change according to the voltage division ratio.

  The configurations described in Patent Documents 7 and 8 are not intended to correspond to the temperature characteristics of the output voltage supply destination.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device capable of stabilizing the internal voltage regardless of the operating environment.

  Another object of the present invention is to provide a semiconductor device in which the input voltage has temperature characteristics, the input voltage is stepped up or stepped down, and the circuit configuration can be simplified.

  Still another object of the present invention is to provide a semiconductor device capable of appropriately dealing with characteristics due to external factors of an output voltage supply destination and preventing variations in output voltage values and output voltage characteristics. That is.

  In summary, the semiconductor device according to one embodiment of the present invention includes a first transistor having a control electrode to which a reference voltage is supplied. The first output transistor section includes a diode-connected second transistor. The first output current control circuit causes a current corresponding to a current flowing between the conductive electrodes of the first transistor to flow between the conductive electrodes of the second transistor. At least one of the first input transistor portion and the first output transistor portion is further diode-connected and connected in series with the corresponding first transistor or second transistor, and the corresponding first transistor or It includes one or more third transistors that output current in the same direction as the output current of the second transistor. The total number of third transistors in the first transistor and the first input transistor portion is different from the total number of third transistors in the second transistor and the first output transistor portion. The size of the first transistor and the size of one or more third transistors in the first input transistor portion and the size of the second transistor and the size of one or more third in the first output transistor portion The transistor size is different. The semiconductor device uses the voltage at the control electrode of the second transistor as the output voltage.

  In summary, in the semiconductor device according to another embodiment of the present invention, the first reference voltage generation circuit generates a first reference voltage whose voltage value changes according to an external factor. The output voltage generation circuit compares the first reference voltage with the comparison target voltage, and generates an output voltage based on the comparison result. The second reference voltage generation circuit generates a plurality of voltages smaller than the first reference voltage based on the first reference voltage, selects one of the plurality of voltages, and selects the second reference voltage. Output as. The comparison target voltage generation circuit generates a comparison target voltage based on the output voltage and the second reference voltage.

  According to an embodiment of the present invention, the size of the first transistor, the size of one or more third transistors in the first input transistor section, the size of the second transistor, and the first output The size of one or a plurality of third transistors in the transistor portion is different. As a result, a voltage in which the reference voltage has temperature characteristics can be generated. The total number of third transistors in the first transistor and the first input transistor portion is different from the total number of third transistors in the second transistor and the first output transistor portion. Thereby, it is possible to generate a voltage obtained by stepping up or down the reference voltage. Further, it is not necessary to separately provide a circuit for stepping up or down the reference voltage, and the circuit configuration can be simplified.

  Therefore, the input voltage can have temperature characteristics, the input voltage can be boosted, and the circuit configuration can be simplified.

  According to another embodiment of the present invention, the first reference voltage generation circuit generates a first reference voltage whose voltage value changes according to an external factor. The output voltage generation circuit compares the first reference voltage received from the first reference voltage generation circuit with the comparison target voltage received from the comparison target voltage generation circuit, and generates an output voltage based on the comparison result. As a result, it is possible to appropriately cope with characteristics due to external factors of the output voltage supply destination.

  Further, the second reference voltage generation circuit generates a plurality of voltages smaller than the first reference voltage based on the first reference voltage, selects any one of the plurality of voltages, and selects the second voltage Output as reference voltage. The comparison target voltage generation circuit generates a comparison target voltage based on the output voltage received from the output voltage generation circuit and the second reference voltage received from the second reference voltage generation circuit. As a result, the output voltage can be finely adjusted in response to variations in internal elements. Further, the characteristics of the output voltage can be finely adjusted corresponding to the voltage value of the output voltage.

  Therefore, it is possible to appropriately cope with characteristics due to external factors of the output voltage supply destination and to prevent variations in output voltage value and output voltage characteristics.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<First Embodiment>
FIG. 1 is a functional block diagram showing a configuration of the semiconductor device 301 according to the first embodiment of the present invention.

  Referring to FIG. 1, a semiconductor device 301 includes a temperature compensation voltage generation circuit 51, a comparison target voltage generation circuit 3, an output voltage generation circuit 4, a reference voltage generation circuit 5, a decoder 6, and a memory cell array 7. Is provided.

  Based on the reference input voltage VREFIN received from the reference voltage generation circuit 5, the temperature compensation voltage generation circuit 51 generates a temperature compensation voltage VT whose voltage value changes according to the ambient temperature that is an external factor.

  The output voltage generation circuit 4 compares the temperature compensation voltage VT received from the temperature compensation voltage generation circuit 51 with the comparison target voltage VCOMP received from the comparison target voltage generation circuit 3, and generates an output voltage VOUT based on the comparison result. , Output to the decoder 6 and the comparison target voltage generation circuit 3. The output voltage generation circuit 4 may be a VDC (Voltage Down Converter), a regulator, or a configuration including a charge pump as will be described later.

  The comparison target voltage generation circuit 3 generates a comparison target voltage VCOMP having a voltage value smaller than the output voltage VOUT based on the output voltage VOUT received from the output voltage generation circuit 4. With such a configuration, the withstand voltage of the transistors and the like included in the output voltage generation circuit 4 can be reduced. For example, since the voltage received by the comparison circuit included in the output voltage generation circuit 4 can be made smaller than the output voltage VOUT, the transistor included in the comparison circuit can be prevented from being destroyed.

  Further, the comparison target voltage generation circuit 3 can change the voltage value of the comparison target voltage VCOMP by, for example, an internal switch. With such a configuration, the voltage value of the output voltage VOUT can be changed.

  The decoder 6 generates a write voltage, a read voltage, an erase voltage, and the like based on the output voltage VOUT received from the output voltage generation circuit 4 and outputs the generated voltage to the memory cell array 7. For example, the decoder 6 supplies a voltage to the word lines in the memory cell array 7 based on the output voltage VOUT received from the output voltage generation circuit 4.

  Memory cell array 7 includes, for example, a plurality of memory cells for storing data, and stores data, outputs stored data, and erases stored data based on the write voltage, read voltage, erase voltage, etc. received from decoder 6. .

  FIG. 2 is a circuit diagram showing a configuration of the temperature compensated voltage generation circuit 51 according to the first embodiment of the present invention.

  Referring to FIG. 2, the temperature compensation voltage generation circuit 51 includes an input transistor unit 11, an output transistor unit 12, a current mirror circuit (output current control circuit) 13, and a constant current source 14. The input transistor unit 11 includes an N-channel MOS (Metal Oxide Semiconductor) transistor (insulated gate field effect transistor) M1. Output transistor portion 12 includes N-channel MOS transistors M11 and M12. Current mirror circuit 13 includes P-channel MOS transistors M21 and M22.

  N-channel MOS transistor M1 has a gate supplied with reference input voltage VREFIN, a source connected to the first terminal of constant current source 14, and a drain connected to the drain of P-channel MOS transistor M21. The second terminal of the constant current source 14 is connected to the ground potential node N2 to which the ground voltage VSS is supplied.

  N channel MOS transistors M11 and M12 are each diode-connected. N-channel MOS transistor M12 outputs a current in the same direction as the output current of N-channel MOS transistor M11. More specifically, N channel MOS transistor M11 has a gate and a drain connected to each other, and a source connected to the gate and the drain of N channel MOS transistor M12. N-channel MOS transistor M12 has a gate and a drain connected to each other, and a source connected to the first terminal of constant current source 14.

  P channel MOS transistor M21 has a gate and a drain connected to each other, and a source connected to power supply potential node N1 to which power supply voltage VCC is supplied.

  P-channel MOS transistor M22 has a gate connected to the gate and drain of P-channel MOS transistor M21, a drain connected to the gate and drain of N-channel MOS transistor M11, and a source connected to power supply potential node N1. Have.

  P channel MOS transistors M21 and M22 in current mirror circuit 13 have substantially the same characteristics. With such a configuration, the output current of the N-channel MOS transistor M1, that is, the current from the drain to the source, and the output current of the P-channel MOS transistor M22 and the N-channel MOS transistors M11 and M12, that is, the current from the drain to the source are made substantially equal. be able to. The gate-source voltages of N channel MOS transistors M11 and M12 are equal to the gate-source voltage of N channel MOS transistor M1. Note that the mirror ratio of the current mirror circuit 13 may be other than 1: 1.

  Temperature compensation voltage generation circuit 51 outputs the voltage at the drain and gate of N-channel MOS transistor M11 as temperature compensation voltage VT. Here, since N-channel MOS transistor M11 is diode-connected, temperature compensation voltage VT is a gate voltage at the stable operation point of N-channel MOS transistor M11.

  The size of N channel MOS transistor M1, that is, L / W, is different from the sizes of N channel MOS transistors M11 and M12. Here, L represents the channel length, and W represents the channel width. Therefore, the temperature compensation voltage VT changes according to the temperature. By changing the size relationship between the size of the N-channel MOS transistor M1 and the sizes of the N-channel MOS transistors M11 and M12, the temperature characteristic, that is, the degree of change of the temperature compensation voltage VT with respect to temperature change can be adjusted.

  The sizes of N channel MOS transistors M11 and M12 are substantially equal. Therefore, by changing the number of transistors included in the output transistor unit 12, the voltage offset value of the temperature compensation voltage VT can be changed by the number of transistors included in the output transistor unit 12, that is, an integer multiple.

  FIG. 3 is a circuit diagram showing a configuration in which a part of the circuit configuration of the temperature compensation voltage generation circuit 51 is omitted.

  Referring to FIG. 3, the temperature compensated voltage generation circuit 71 includes an output transistor unit 32 instead of the output transistor unit 12. The output transistor portion 32 includes an N channel MOS transistor M11. That is, the temperature compensation voltage generation circuit 71 is configured not to include the N-channel MOS transistor M12 as compared with the temperature compensation voltage generation circuit 51.

FIG. 4 is a graph showing an example of temperature characteristics of the temperature compensation voltage VT.
Referring to FIG. 4, in temperature compensation voltage generation circuit 71, for example, when the size of N channel MOS transistor M1, that is, L / W is made smaller than the size of N channel MOS transistor M11, temperature compensation voltage VT is as shown by graph G1A. Has negative temperature characteristics.

  In this case, the temperature compensation voltage VT is considerably smaller than the reference input voltage VREFIN. Then, it becomes necessary to generate a temperature compensation voltage VT as shown in the graph G1B by separately preparing a circuit for boosting the reference input voltage VREFIN in addition to the temperature compensation voltage generation circuit 71, which increases the circuit scale. .

  Referring to FIG. 2 again, in the temperature compensation voltage generation circuit 51 according to the first embodiment of the present invention, the output transistor unit 12 further includes an N-channel MOS transistor M12 as compared with the temperature compensation voltage generation circuit 71. Including. N-channel MOS transistor M12 is diode-connected and connected in series with N-channel MOS transistor M11, and outputs a current in the same direction as the output current of N-channel MOS transistor M11. With such a configuration, the voltage at the drain and the gate of the N-channel MOS transistor M11 of the temperature compensation voltage generation circuit 51 is larger than the voltage between the gate and the source of the N-channel MOS transistor M12 as compared with the temperature compensation voltage generation circuit 71. . That is, temperature compensation voltage VT is twice the gate-source voltage of N-channel MOS transistor M1. Therefore, in the temperature compensation voltage generation circuit 51 according to the first embodiment of the present invention, the temperature compensation voltage VT greatly deviates from the reference input voltage VREFIN without separately providing a circuit for boosting the reference input voltage VREFIN. Can be prevented.

  By the way, in the conventional temperature compensation voltage generation circuit, in order to prevent the output voltage value from greatly deviating from the input voltage value, a circuit for stepping up or down the reference input voltage is necessary, and the circuit scale is increased. End up. In the configurations described in Patent Documents 1 to 4, the input voltage cannot be boosted or lowered, and the input voltage cannot have temperature characteristics.

  However, in the temperature compensation voltage generation circuit 51 according to the first embodiment of the present invention, the size of the N-channel MOS transistor M1 included in the input transistor unit 11 and the size of the N-channel MOS transistors M11 and M12 included in the output transistor unit 12 Is different. With such a configuration, it is possible to generate a voltage in which the reference input voltage VREFIN has temperature characteristics. In the temperature compensation voltage generation circuit 51 according to the first embodiment of the present invention, the number of transistors included in the output transistor unit 12 is larger than the number of transistors included in the input transistor unit 11. With such a configuration, a voltage obtained by boosting the reference input voltage VREFIN can be generated. Further, the temperature compensation voltage generation circuit 51 according to the first embodiment of the present invention has a configuration in which the N-channel MOS transistor M12 is simply added to the temperature compensation voltage generation circuit 71, so that the reference input voltage VREFIN is set. There is no need to separately provide a boosting circuit, and the circuit configuration can be simplified. Further, since the current flowing through the output transistor section 12 is the same as that of the temperature compensation voltage generation circuit 71, an increase in power consumption can be prevented.

  Therefore, in the temperature compensated voltage generation circuit 51 according to the first embodiment of the present invention, the input voltage has temperature characteristics, the input voltage is boosted, and the circuit configuration can be simplified.

  Although the temperature compensation voltage generation circuit 51 according to the first embodiment of the present invention is configured to include the current mirror circuit 13, the present invention is not limited thereto. By supplying a voltage to the gate of the N channel MOS transistor M11 based on the output current of the N channel MOS transistor M1, a current corresponding to the current flowing between the drain and source of the N channel MOS transistor M1 is supplied to the N channel MOS transistor M11. A configuration in which a circuit that flows between the drain and the source is provided as an output current control circuit instead of the current mirror circuit may be employed.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Second Embodiment>
The present embodiment relates to a temperature compensation voltage generation circuit in which the number of transistors included in the output transistor unit is increased as compared with the temperature compensation voltage generation circuit according to the first embodiment. The contents other than those described below are the same as those of the temperature compensation voltage generation circuit according to the first embodiment.

  FIG. 5 is a circuit diagram showing a configuration of the temperature compensated voltage generation circuit 52 according to the second embodiment of the present invention.

  Referring to FIG. 5, the temperature compensation voltage generation circuit 52 includes an output transistor unit 22 instead of the output transistor unit 12 as compared with the temperature compensation voltage generation circuit according to the first embodiment of the present invention. The output transistor portion 22 includes N channel MOS transistors M11 to M13.

  N channel MOS transistors M11 to M13 are diode-connected. N channel MOS transistors M12 and M13 output current in the same direction as the output current of N channel MOS transistor M11. More specifically, N channel MOS transistor M11 has a gate and a drain connected to each other, and a source connected to the gate and the drain of N channel MOS transistor M12. N channel MOS transistor M12 has a gate and a drain connected to each other, and a source connected to the gate and the drain of N channel MOS transistor M13. N-channel MOS transistor M13 has a gate and a drain connected to each other, and a source connected to the first terminal of constant current source 14.

  P channel MOS transistors M21 and M22 in current mirror circuit 13 have substantially the same characteristics. With such a configuration, the output current of the N-channel MOS transistor M1, that is, the current from the drain to the source, and the output current of the P-channel MOS transistor M22 and the N-channel MOS transistors M11 to M13, that is, the current from the drain to the source are made substantially equal. be able to. The gate-source voltage of each of N channel MOS transistors M11-M13 is equal to the gate-source voltage of N channel MOS transistor M1.

  The size of N channel MOS transistor M1, that is, L / W, is different from the sizes of N channel MOS transistors M11 to M13. Here, L represents the channel length, and W represents the channel width. Therefore, the temperature compensation voltage VT changes according to the temperature. By changing the size relationship between the size of the N-channel MOS transistor M1 and the sizes of the N-channel MOS transistors M11 to M13, it is possible to adjust the temperature characteristic, that is, the degree of change in the temperature compensation voltage VT with respect to temperature change.

  The sizes of the N channel MOS transistors M11 to M13 are substantially equal. Therefore, by changing the number of transistors included in the output transistor unit 22, the voltage offset value of the temperature compensation voltage VT can be changed by the number of transistors included in the output transistor unit 12, that is, an integer multiple.

  In the temperature compensation voltage generation circuit 52 according to the second embodiment of the present invention, the output transistor unit 22 further includes N-channel MOS transistors M12 and M13 as compared to the temperature compensation voltage generation circuit 71 shown in FIG. N-channel MOS transistors M12 and M13 are diode-connected and connected in series with N-channel MOS transistor M11, and output current in the same direction as the output current of N-channel MOS transistor M11. With such a configuration, the voltage at the drain and gate of the N-channel MOS transistor M11 of the temperature compensation voltage generation circuit 52 is equal to the voltage between the gate and source of the N-channel MOS transistors M12 and M13 as compared with the temperature compensation voltage generation circuit 71. Increases the total amount. That is, temperature compensation voltage VT is three times the gate-source voltage of N-channel MOS transistor M1. Therefore, in the temperature compensation voltage generation circuit 52 according to the second embodiment of the present invention, the temperature compensation voltage VT greatly deviates from the reference input voltage VREFIN without separately providing a circuit for boosting the reference input voltage VREFIN. Can be prevented.

  Since other configurations and operations are the same as those of the temperature compensation voltage generation circuit according to the first embodiment, detailed description thereof will not be repeated here.

  Therefore, in the temperature compensated voltage generation circuit 52 according to the second embodiment of the present invention, similarly to the temperature compensated voltage generation circuit according to the first embodiment of the present invention, the input voltage has temperature characteristics, In addition, the input voltage can be boosted and the circuit configuration can be simplified.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Third Embodiment>
In this embodiment, the temperature compensation voltage in which the magnitude relationship between the number of transistors included in the input transistor unit and the number of transistors included in the output transistor unit is reversed as compared with the temperature compensation voltage generation circuit according to the first embodiment. The present invention relates to a generation circuit. The contents other than those described below are the same as those of the temperature compensation voltage generation circuit according to the first embodiment.

  FIG. 6 is a circuit diagram showing a configuration of the temperature compensated voltage generation circuit 53 according to the third embodiment of the present invention.

  Referring to FIG. 6, the temperature compensation voltage generation circuit 53 includes an input transistor unit 31 instead of the input transistor unit 11 as compared with the temperature compensation voltage generation circuit according to the first embodiment of the present invention. An output transistor unit 32 is provided instead of the transistor unit 12. Input transistor portion 31 includes N-channel MOS transistors M1 and M2. The output transistor portion 32 includes an N channel MOS transistor M11.

  N-channel MOS transistor M1 has a gate supplied with reference input voltage VREFIN, a source connected to the gate and drain of N-channel MOS transistor M2, and a drain connected to the drain of P-channel MOS transistor M21.

  N-channel MOS transistor M2 is diode-connected. N-channel MOS transistor M2 outputs a current in the same direction as the output current of N-channel MOS transistor M1. More specifically, N channel MOS transistor M2 has a gate and a drain connected to each other, and a source connected to the first terminal of constant current source 14. The second terminal of the constant current source 14 is connected to the ground potential node N2 to which the ground voltage VSS is supplied.

  N-channel MOS transistor M11 is diode-connected. More specifically, N channel MOS transistor M11 has a gate and a drain connected to each other, and a source connected to the first terminal of constant current source 14.

  P channel MOS transistors M21 and M22 in current mirror circuit 13 have substantially the same characteristics. With such a configuration, the output current of the N channel MOS transistor M1, that is, the current from the drain to the source, and the output current of the P channel MOS transistor M22 and the N channel MOS transistor M11, that is, the current from the drain to the source can be made substantially equal. it can. The gate-source voltage of N channel MOS transistor M11 is equal to the gate-source voltage of N channel MOS transistors M1 and M2.

  Temperature compensation voltage generation circuit 51 outputs the voltage at the drain and gate of N-channel MOS transistor M11 as temperature compensation voltage VT. Here, since N-channel MOS transistor M11 is diode-connected, temperature compensation voltage VT is a gate voltage at the stable operation point of N-channel MOS transistor M11.

  The sizes of N channel MOS transistors M1 and M2, that is, L / W, are different from the size of N channel MOS transistor M11. Here, L represents the channel length, and W represents the channel width. Therefore, the temperature compensation voltage VT changes according to the temperature. By changing the size relationship between the sizes of the N channel MOS transistors M1 and M2 and the size of the N channel MOS transistor M11, it is possible to adjust the temperature characteristic, that is, the degree of change in the temperature compensation voltage VT with respect to the temperature change.

  The sizes of N channel MOS transistors M1 and M2 are substantially equal. Therefore, by changing the number of transistors included in the input transistor unit 31, the voltage offset value of the temperature compensation voltage VT can be changed by (1 / number of transistors included in the input transistor unit 31) times.

FIG. 7 is a graph showing an example of temperature characteristics of the temperature compensation voltage VT.
Referring to FIG. 7, in temperature compensated voltage generation circuit 71 shown in FIG. 3, for example, when the size of N channel MOS transistor M1, that is, L / W is made larger than the size of N channel MOS transistor M11, temperature compensated voltage VT is represented by graph G2A. As shown in FIG.

  In this case, the temperature compensation voltage VT is considerably larger than the reference input voltage VREFIN. In this case, for example, by separately preparing a circuit for stepping down the reference input voltage VREFIN in addition to the temperature compensation voltage generation circuit 71, it becomes necessary to generate the temperature compensation voltage VT as shown in the graph G2B, which increases the circuit scale. .

  Referring to FIG. 6 again, in the temperature compensation voltage generation circuit 53 according to the third embodiment of the present invention, the input transistor unit 31 further includes an N-channel MOS transistor M2 as compared with the temperature compensation voltage generation circuit 71. Including. N-channel MOS transistor M2 is diode-connected and connected in series with N-channel MOS transistor M1, and outputs a current in the same direction as the output current of N-channel MOS transistor M1. With such a configuration, the voltage at the drain and the gate of the N-channel MOS transistor M1 of the temperature compensation voltage generation circuit 53 is larger than the temperature-compensation voltage generation circuit 71 by the voltage between the gate and the source of the N-channel MOS transistor M2. . That is, temperature compensation voltage VT is ½ times the gate-source voltage of N-channel MOS transistor M1. Therefore, in the temperature compensation voltage generation circuit 53 according to the third embodiment of the present invention, the temperature compensation voltage VT greatly deviates from the reference input voltage VREFIN without separately providing a circuit for stepping down the reference input voltage VREFIN. Can be prevented.

  Since other configurations and operations are the same as those of the temperature compensation voltage generation circuit according to the first embodiment, detailed description thereof will not be repeated here.

  By the way, in the conventional temperature compensation voltage generation circuit, in order to prevent the output voltage value from greatly deviating from the input voltage value, a circuit for stepping up or down the reference input voltage is necessary, and the circuit scale is increased. End up. In the configurations described in Patent Documents 1 to 4, the input voltage cannot be boosted or lowered, and the input voltage cannot have temperature characteristics.

  However, in the temperature compensation voltage generation circuit 53 according to the third embodiment of the present invention, the size of the N-channel MOS transistor M1 included in the input transistor unit 11 and the size of the N-channel MOS transistors M11 and M12 included in the output transistor unit 12 Is different. With such a configuration, it is possible to generate a voltage in which the reference input voltage VREFIN has temperature characteristics. In the temperature compensated voltage generation circuit 53 according to the third embodiment of the present invention, the number of transistors included in the output transistor unit 12 is smaller than the number of transistors included in the input transistor unit 11. With such a configuration, a voltage obtained by stepping down the reference input voltage VREFIN can be generated. Further, the temperature compensation voltage generation circuit 53 according to the third embodiment of the present invention has a configuration in which an N-channel MOS transistor M2 is simply added to the temperature compensation voltage generation circuit 71, so that the reference input voltage VREFIN is There is no need to separately provide a boosting circuit, and the circuit configuration can be simplified. Further, since the current flowing through the input transistor unit 31 is the same as that of the temperature compensation voltage generation circuit 71, an increase in power consumption can be prevented.

  Therefore, in the temperature compensated voltage generation circuit 53 according to the third embodiment of the present invention, the input voltage has temperature characteristics, the input voltage is stepped down, and the circuit configuration can be simplified.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Fourth embodiment>
The present embodiment relates to a temperature compensation voltage generation circuit having a two-stage temperature compensation voltage generation circuit as compared with the temperature compensation voltage generation circuit according to the first embodiment. The contents other than those described below are the same as those of the temperature compensation voltage generation circuit according to the first embodiment.

  FIG. 8 is a circuit diagram showing a configuration of the temperature compensation voltage generation circuit 54 according to the fourth embodiment of the present invention.

  Referring to FIG. 8, the temperature compensation voltage generation circuit 54 further includes an input transistor unit 61 and a current mirror circuit (output current control) as compared with the temperature compensation voltage generation circuit according to the first embodiment of the present invention. Circuit) 63 and a constant current source 64. Input transistor portion 61 includes an N-channel MOS transistor M31. Output transistor portion 62 includes N-channel MOS transistors M41 and M42. Current mirror circuit 63 includes P channel MOS transistors M51 and M52.

  N-channel MOS transistor M31 has a gate supplied with reference input voltage VREFIN, a source connected to the first terminal of constant current source 64, and a drain connected to the drain of P-channel MOS transistor M51. The second terminal of the constant current source 64 is connected to the ground potential node N62 to which the ground voltage VSS is supplied.

  N-channel MOS transistors M41 and M42 are diode-connected. N-channel MOS transistor M42 outputs a current in the same direction as the output current of N-channel MOS transistor M41. More specifically, N channel MOS transistor M41 has a gate and a drain connected to each other, and a source connected to the gate and the drain of N channel MOS transistor M42. N-channel MOS transistor M42 has a gate and a drain connected to each other, and a source connected to the first terminal of constant current source 64.

  P channel MOS transistor M51 has a gate and a drain connected to each other, and a source connected to power supply potential node N61 to which power supply voltage VCC is supplied.

  P channel MOS transistor M52 has a gate connected to the gate and drain of P channel MOS transistor M51, a drain connected to the gate and drain of N channel MOS transistor M41, and a source connected to power supply potential node N61. Have.

  P channel MOS transistors M51 and M52 in current mirror circuit 63 have substantially the same characteristics. With such a configuration, the output current of the N-channel MOS transistor M31, that is, the current from the drain to the source, and the output current of the P-channel MOS transistor M52 and the N-channel MOS transistors M41 and M42, that is, the current from the drain to the source are made substantially equal. be able to. The gate-source voltage of each of N channel MOS transistors M41 and M42 is equal to the gate-source voltage of N channel MOS transistor M31. Note that the mirror ratio of the current mirror circuit 63 may be other than 1: 1.

  Temperature compensation voltage generation circuit 54 outputs the voltage at the drain and gate of N-channel MOS transistor M41 as temperature compensation voltage VT. Here, since N channel MOS transistor M41 is diode-connected, temperature compensation voltage VT is a gate voltage at the stable operation point of N channel MOS transistor M41.

  The size of N channel MOS transistor M31, that is, L / W, is different from the sizes of N channel MOS transistors M41 and M42. Here, L represents the channel length, and W represents the channel width. Therefore, the temperature compensation voltage VT changes according to the temperature. By changing the size relationship between the size of the N-channel MOS transistor M31 and the sizes of the N-channel MOS transistors M41 and M42, the temperature characteristic, that is, the degree of change of the temperature compensation voltage VT with respect to temperature change can be adjusted.

  The sizes of N channel MOS transistors M41 and M42 are substantially equal. Therefore, by changing the number of transistors included in the output transistor unit 62, the voltage offset value of the temperature compensation voltage VT can be changed by the number of transistors included in the output transistor unit 62, that is, an integer multiple.

  Here, in the temperature compensation voltage generation circuit 54, when the size of the N-channel MOS transistor M1 is smaller than the sizes of the N-channel MOS transistors M11 and M12, the size of the N-channel MOS transistor M31 is changed to that of the N-channel MOS transistors M41 and M42. Make it smaller than the size. With such a configuration, the negative temperature characteristic of the temperature compensation voltage VT can be further increased as compared with the temperature compensation voltage generation circuit 51 according to the first embodiment of the present invention.

  In temperature compensation voltage generation circuit 54, input transistor unit 11 includes one N-channel MOS transistor, and output transistor unit 12 includes two N-channel MOS transistors. Input transistor portion 61 includes one N-channel MOS transistor, and output transistor portion 62 includes two N-channel MOS transistors. With such a configuration, the temperature compensation voltage VT is four times the gate-source voltage of the N-channel MOS transistor M1, that is, compared with the temperature compensation voltage generation circuit 51 according to the first embodiment of the present invention. Thus, the boosting rate can be further increased.

  Since other configurations and operations are the same as those of the temperature compensation voltage generation circuit according to the first embodiment, detailed description thereof will not be repeated here.

  Therefore, in the temperature compensated voltage generation circuit 54 according to the fourth embodiment of the present invention, similarly to the temperature compensated voltage generation circuit according to the first embodiment of the present invention, the input voltage has temperature characteristics, In addition, the input voltage can be boosted and the circuit configuration can be simplified.

  The magnitude relationship between the size of the transistor included in the input transistor unit 61 and the size of the transistor included in the output transistor unit 62 is not limited to the above. The size relationship between the size of the transistor included in the input transistor unit 61 and the size of the transistor included in the output transistor unit 62 is the same as the size relationship between the size of the transistor included in the input transistor unit 11 and the size of the transistor included in the output transistor unit 12. If so, the temperature characteristics of the temperature compensation voltage VT can be further increased as compared with the temperature compensation voltage generation circuit 51 according to the first embodiment of the present invention.

  The magnitude relationship between the number of transistors included in the input transistor unit 61 and the number of transistors included in the output transistor unit 62 is not limited to the above. The magnitude relationship between the number of transistors included in the input transistor unit 61 and the number of transistors included in the output transistor unit 62 is the same as the size relationship between the number of transistors included in the input transistor unit 11 and the number of transistors included in the output transistor unit 12. Then, it is possible to further increase the step-up rate or the step-down rate as compared with the temperature compensation voltage generation circuit 51 according to the first embodiment of the present invention.

Next, another embodiment of the present invention will be described with reference to the drawings.
<Fifth embodiment>
FIG. 9 is a functional block diagram showing a configuration of a semiconductor device 401 according to the fifth embodiment of the present invention.

  Referring to FIG. 9, the semiconductor device 401 includes a first reference voltage generation circuit 101, a second reference voltage generation circuit 102, a comparison target voltage generation circuit 103, an output voltage generation circuit 104, and a voltage generation circuit 105. , A decoder 106 and a memory cell array 107 are provided.

  Based on the voltage VA received from the voltage generation circuit 105, the first reference voltage generation circuit 101 generates a reference voltage VREF1 whose voltage value changes according to an external factor. Here, the external factors are, for example, the ambient temperature of the first reference voltage generation circuit 101, the value of the power supply voltage supplied to the first reference voltage generation circuit 101, and the signal received by the first reference voltage generation circuit 101. Is the frequency.

  The output voltage generation circuit 104 compares the reference voltage VREF1 received from the first reference voltage generation circuit 101 with the comparison target voltage VCOMP received from the comparison target voltage generation circuit 103, and generates the output voltage VOUT based on the comparison result. And output to the decoder 106 and the comparison target voltage generation circuit 103. The output voltage generation circuit 104 may be a VDC (Voltage Down Converter), a regulator, or a configuration including a charge pump as described later.

  The second reference voltage generation circuit 102 generates a plurality of voltages smaller than the reference voltage VREF1 based on the reference voltage VREF1 received from the first reference voltage generation circuit 101, and selects any one of the plurality of voltages. And output as the reference voltage VREF2.

  The comparison target voltage generation circuit 103 is based on the output voltage VOUT received from the output voltage generation circuit 104 and the reference voltage VREF2 received from the second reference voltage generation circuit 102, and has a voltage value smaller than the output voltage VOUT. Is generated. With such a structure, the withstand voltage of the transistor or the like included in the output voltage generation circuit 104 can be reduced. For example, a voltage received by a comparison circuit 131 (to be described later) in the output voltage generation circuit 104 can be made smaller than the output voltage VOUT, so that a transistor included in the comparison circuit 131 can be prevented from being destroyed.

  Further, the comparison target voltage generation circuit 103 can change the voltage value of the comparison target voltage VCOMP by, for example, an internal switch. With such a configuration, the voltage value of the output voltage VOUT can be changed.

  Decoder 106 generates a write voltage, a read voltage, an erase voltage, and the like based on output voltage VOUT received from output voltage generation circuit 104 and outputs the generated voltage to memory cell array 107. For example, the decoder 106 supplies a voltage to the word lines in the memory cell array 107 based on the output voltage VOUT received from the output voltage generation circuit 104.

  Memory cell array 107 includes, for example, a plurality of memory cells for storing data, and stores data, outputs stored data, and erases stored data based on the write voltage, read voltage, erase voltage, etc. received from decoder 106. .

  FIG. 10 is a circuit diagram showing a configuration of the first reference voltage generation circuit 101 in the semiconductor device 401 according to the fifth embodiment of the present invention.

  Referring to FIG. 10, first reference voltage generating circuit 101 includes P channel MOS transistors (insulated gate field effect transistors) M101 and M102, and N channel MOS transistors M103 to M105.

  The sources of P-channel MOS transistors M101 and M102 are connected to power supply potential node N1 to which power supply voltage VCC is supplied. The gate of P channel MOS transistor M101 is connected to the drain of P channel MOS transistor M101, the drain of N channel MOS transistor M103, and the gate of P channel MOS transistor M102. The source of N channel MOS transistor M103 is connected to the drain of N channel MOS transistor M105 and the source of N channel MOS transistor M104. The drain of P channel MOS transistor M102 is connected to the drain and gate of N channel MOS transistor M104. The source of N channel MOS transistor M105 is connected to ground potential node N2 to which a ground voltage is supplied. Voltage VA from voltage generation circuit 105 is supplied to the gate of N channel MOS transistor M103. A control voltage CONT1 from a control unit (not shown) included in the semiconductor device 401 is supplied to the gate of the N-channel MOS transistor M105.

  First reference voltage generation circuit 101 outputs the voltage at the drain and gate of N-channel MOS transistor M104 as reference voltage VREF1. That is, since the N-channel MOS transistor M104 is diode-connected, the reference voltage VREF1 is a gate voltage at the stable operation point of the N-channel MOS transistor M104. The first reference voltage generation circuit 101 outputs the reference voltage VREF1 when the N-channel MOS transistor M105 is turned on by the control voltage CONT1.

  N channel MOS transistors M103 and M104 have different sizes, that is, L / W. Here, L represents the channel length, and W represents the channel width. Therefore, the voltage value of the reference voltage VREF1 changes according to the temperature. By changing the size relationship between the N-channel MOS transistors M103 and M104, the degree of change of the reference voltage VREF1 with respect to temperature change can be adjusted.

  FIG. 11 is a circuit diagram showing a configuration of the second reference voltage generation circuit 102 in the semiconductor device 401 according to the fifth embodiment of the present invention.

  Referring to FIG. 11, second reference voltage generation circuit 102 includes a comparison circuit 111, a VREF2 selection circuit 112, a resistance unit 113, and a P-channel MOS transistor M111.

  The reference voltage VREF1 from the first reference voltage generation circuit 101 is supplied to the inverting input terminal of the comparison circuit 111, and the non-inverting input terminal is connected to the drain of the P-channel MOS transistor M111 and the first end of the resistance unit 113. The source of P-channel MOS transistor M111 is connected to power supply potential node N11 to which power supply voltage VCC is supplied. A second end of resistor 113 is connected to ground potential node N12 to which ground voltage VSS is supplied.

  Comparison circuit 111 compares reference voltage VREF1 with the drain voltage of P channel MOS transistor M111, and supplies a voltage to the gate of P channel MOS transistor M111 based on the comparison result. That is, the first end of the resistance unit 113 converges to the reference voltage VREF1.

  The resistor 113 generates voltages sref0 to sref15 obtained by dividing the voltage at the first end, that is, the reference voltage VREF1, and outputs the voltages to the VREF2 selection circuit 112. For example, the voltage sref0 is the ground voltage VSS, the voltage sref1 is 1/16 of the reference voltage VREF1, the voltage sref2 is 2/16 of the reference voltage VREF1, and the voltage sref15 is 15/16 of the reference voltage VREF1. It becomes.

  For example, the VREF2 selection circuit 112 selects one of the voltages sref0 to sref15 based on a 4-bit selection control signal SELCONT received from a control unit (not shown) included in the semiconductor device 401, and uses the selected voltage as a reference. The voltage VREF2 is output to the comparison target voltage generation circuit 103.

  FIG. 12 is a circuit diagram showing configurations of the comparison target voltage generation circuit 103 and the output voltage generation circuit 104 in the semiconductor device 401 according to the fifth embodiment of the present invention.

  Referring to FIG. 12, comparison target voltage generation circuit 103 includes P channel MOS transistors M121 to M127, N channel MOS transistors M128 to M130, and switches SW1 to SW4.

  The gate of P channel MOS transistor M121 is connected to the drain of P channel MOS transistor M121, the gate of P channel MOS transistor M126, and the source of P channel MOS transistor M122. The gate of P channel MOS transistor M122 is connected to the drain of P channel MOS transistor M122, the gate of P channel MOS transistor M127, and the source of P channel MOS transistor M123. The gate and drain of P channel MOS transistor M123 are connected to the source of P channel MOS transistor M124. The gate and drain of P channel MOS transistor M124 are connected to the source of P channel MOS transistor M125. The drain of P channel MOS transistor M125 is connected to the drain of N channel MOS transistor M129. The drain of P channel MOS transistor M126 is connected to the source of P channel MOS transistor M129. The drain of P channel MOS transistor M127 and the source of P channel MOS transistor M128 are connected. The drain of P channel MOS transistor M128 and the drain of N channel MOS transistor M130 are connected. The gate of P channel MOS transistor M128, the source of N channel MOS transistor M129, and the source of N channel MOS transistor M130 are connected to ground potential node N21 to which ground voltage VSS is supplied.

  The first end of switch SW1 is connected to the source of P-channel MOS transistor M125, and the second end is connected to the source of P-channel MOS transistor M124. The first end of switch SW2 is connected to the source of P-channel MOS transistor M125, and the second end is connected to the source of P-channel MOS transistor M123. The first end of switch SW3 is connected to the source of P-channel MOS transistor M125, and the second end is connected to the source of P-channel MOS transistor M122. The first end of switch SW4 is connected to the source of P-channel MOS transistor M125, and the second end is connected to the source of P-channel MOS transistor M121.

  The output voltage VOUT from the output voltage generation circuit 104 is supplied to the source of the P-channel MOS transistor M121 and the source of the P-channel MOS transistor M126. The reference voltage VREF2 from the second reference voltage generation circuit 102 is supplied to the gate of the P-channel MOS transistor M125. A control voltage CONT2 from a control unit (not shown) included in the semiconductor device 401 is supplied to the gates of the N-channel MOS transistors M129 and M130.

  Comparison target voltage generation circuit 103 outputs the voltage at the source of P-channel MOS transistor M128 to output voltage generation circuit 104 as comparison target voltage VCOMP. Comparison target voltage generation circuit 103 outputs comparison target voltage VCOMP when N-channel MOS transistors M129 and M130 are turned on by control voltage CONT2.

  The switches SW1 to SW4 switch the voltage value of the comparison target voltage VCOMP. Any one of the switches SW1 to SW4 is controlled to be turned on and the other switches are turned off, or all of the switches SW1 to SW4 are controlled to be turned off.

  For example, when all switches SW1 to SW4 are in the off state, P channel MOS transistors M121 to M125 are enabled. That is, the number of P-channel MOS transistors at the input stage in the comparison target voltage generation circuit 103 is 5.

  When switch SW1 is on and switches SW2-SW4 are off, P-channel MOS transistors M121-M123 and M125 are valid. That is, the number of P-channel MOS transistors at the input stage in the comparison target voltage generation circuit 103 is four.

  When switch SW2 is on and switches SW1, SW3, and SW4 are off, P-channel MOS transistors M121, M122, and M125 are enabled. That is, the number of P-channel MOS transistors at the input stage in the comparison target voltage generation circuit 103 is three.

  When switch SW3 is on and switches SW1, SW2, and SW4 are off, P-channel MOS transistors M121 and M125 are enabled. That is, the number of P-channel MOS transistors at the input stage in the comparison target voltage generation circuit 103 is two.

  Further, when the switch SW4 is in the on state and the switches SW1 to SW3 are in the off state, the P-channel MOS transistor M125 is enabled. That is, the number of P-channel MOS transistors at the input stage in the comparison target voltage generation circuit 103 is 1.

  The comparison target voltage generation circuit 103 is not limited to a configuration including a plurality of MOS transistors, but may be configured to include a resistor instead of the MOS transistors. However, in order to increase the efficiency of the charge pump 132, it is necessary to reduce the output current of the charge pump 132. For this reason, when the comparison target voltage generation circuit 103 is configured by a resistor, it is necessary to increase the resistance value. As a result, the area of the resistor becomes large, and it becomes difficult to reduce the size of the circuit. Therefore, it is preferable that the comparison target voltage generation circuit 103 is composed of a MOS transistor.

  Output voltage generation circuit 104 includes a comparison circuit 131, a charge pump 132, and a capacitor 133. The first electrode of the capacitor 133 is connected to the output of the charge pump 132, and the second electrode is connected to the ground potential node N31 to which the ground voltage is supplied.

  The comparison circuit 131 compares the reference voltage VREF1 received from the first reference voltage generation circuit 101 at the non-inverting input terminal with the comparison target voltage VCOMP received from the comparison target voltage generation circuit 103 at the inverting input terminal, and based on the comparison result. The logic high level or logic low level voltage is output to the charge pump 132. More specifically, the comparison circuit 131 outputs a logic high level voltage to the charge pump 132 when the comparison target voltage VCOMP is smaller than the reference voltage VREF1. On the other hand, the comparison circuit 131 outputs a logic low level voltage to the charge pump 132 when the comparison target voltage VCOMP is larger than the reference voltage VREF1.

  The charge pump 132 stores electric charge in the capacitor 133 when receiving a logic high level voltage from the comparison circuit 131, and stops operating when receiving a logic low level voltage from the comparison circuit 131, that is, the capacitor 133. Stops charge accumulation in

  The output voltage generation circuit 104 outputs the voltage at the first electrode of the capacitor 133 as the output voltage VOUT.

  Here, when the voltage value of the reference voltage VREF1 is VREF1, the voltage value of the reference voltage VREF2 is VREF2, and the number of P channel MOS transistors in the input stage of the comparison target voltage generation circuit 103 is N, the output voltage VOUT is It is expressed by the following formula.

VOUT = VREF1 × N + VREF2
Next, the operation of the semiconductor device 401 will be described with specific numerical values. Here, to simplify the explanation, it is assumed that the reference voltage VREF2 is set to 0V. It is assumed that the number of P-channel MOS transistors at the input stage of the comparison target voltage generation circuit 103 is set to 5.

  When the output voltage VOUT needs to be 8V, the reference voltage VREF1 is set to 1.6V. In this case, the second reference voltage generation circuit 102 can select any one voltage from 0 V to 1.5 V in 100 mV increments and output it as the reference voltage VREF2.

  Here, when the output voltage VOUT is, for example, 5V, the gate-source voltages VGS1 to VGS5 of the P-channel MOS transistors M121 to M125 are each 1V. Then, the gate-source voltage VGS8 of the P-channel MOS transistor M128, that is, the comparison target voltage VCOMP becomes 1V.

  At this time, the comparison circuit 131 outputs a logic high level voltage to the charge pump 132 because the comparison target voltage VCOMP is smaller than the reference voltage VREF1.

  The charge pump 132 receives a logic high level voltage from the comparison circuit 131 and stores electric charge in the capacitor 133 to increase the output voltage VOUT.

  On the other hand, in the state where output voltage VOUT is 9 V, for example, gate-source voltages VGS1 to VGS5 of P channel MOS transistors M121 to M125 are 1.8 V, respectively. Then, the gate-source voltage VGS8 of the P-channel MOS transistor M128, that is, the comparison target voltage VCOMP is 1.8V.

  At this time, since the comparison target voltage VCOMP is higher than the reference voltage VREF1, the comparison circuit 131 outputs a logic low level voltage to the charge pump 132.

  The charge pump 132 receives a logic low level voltage from the comparison circuit 131 and stops the charge accumulation of the capacitor 133. As a result, the output voltage VOUT decreases.

  With the feedback operation as described above, in the semiconductor device 401 according to the fifth embodiment of the present invention, the output voltage VOUT can be converged to a desired voltage, here 8V.

  In the semiconductor device 401 according to the fifth embodiment of the present invention, the first reference voltage generation circuit 101 changes the voltage value according to an external factor based on the voltage VA received from the voltage generation circuit 105. A reference voltage VREF1 is generated. Then, the output voltage generation circuit 104 compares the reference voltage VREF1 received from the first reference voltage generation circuit 101 with the comparison target voltage VCOMP received from the comparison target voltage generation circuit 103, and determines the output voltage VOUT based on the comparison result. Generate. With such a configuration, it is possible to appropriately cope with characteristics due to external factors of the output voltage supply destination.

  FIG. 13 is a graph showing the relationship between the voltage value of the output voltage VOUT and the temperature characteristics of the semiconductor device 401 according to the fifth embodiment of the invention.

  As described above, the comparison target voltage generation circuit 103 increases or decreases the number of P-channel MOS transistors in the input stage in the comparison target voltage generation circuit 103 by changing the settings of the on and off states of the switches SW1 to SW4. As a result, the voltage value of the comparison target voltage VCOMP is increased or decreased. With such a configuration, the voltage value of the output voltage VOUT can be changed.

  Here, the graph G1 is generated based on only the output voltage VOUT and the number of P-channel MOS transistors at the input stage in the comparison target voltage generation circuit 103 because the semiconductor device 401 does not generate the reference voltage VREF2. The case is assumed to be The graph G2 shows that the comparison target voltage VCOMP is the output voltage VOUT, the number of P-channel MOS transistors in the input stage in the comparison target voltage generation circuit 103, and the reference voltage VREF1 as in the semiconductor device 401 according to the fifth embodiment of the present invention. The case where it produces | generates based on the reference voltage VREF2 which has the same temperature characteristic is shown.

  In the graph G1, the temperature characteristic of the output voltage VOUT changes stepwise according to the set value of the output voltage VOUT, that is, the number of P-channel MOS transistors at the input stage in the comparison target voltage generation circuit 103. For example, when the output voltage VOUT is set to 1.6 V to 3.1 V by setting the number of P-channel MOS transistors at the input stage in the comparison target voltage generation circuit 103 to 1, the temperature characteristic of the output voltage VOUT is − 3.8 mV / ° C. When the output voltage VOUT is set to 3.2 V to 4.7 V by setting the number of P-channel MOS transistors at the input stage in the comparison target voltage generation circuit 103 to 2, the temperature characteristic of the output voltage VOUT is − It becomes 7.6 mV / ° C.

  Here, the output voltage VOUT of one of the two semiconductor devices 401 is within the required voltage range due to variations in internal elements, etc., but the other output voltage VOUT is out of the required voltage range. Think if you are. Assuming that the number of P-channel MOS transistors in the input stage in the comparison target voltage generation circuit 103 of the semiconductor device 401 in which the output voltage VOUT is within the required voltage range is 1, the voltage range in which the output voltage VOUT is required. For example, the number of P-channel MOS transistors in the input stage in the comparison target voltage generation circuit 103 of the semiconductor device 401 that does not fall within the range needs to be set to 2, for example. As a result, the temperature characteristics of the output voltage VOUT are greatly different between the two semiconductor devices 401 as described above.

  However, in the semiconductor device 401 according to the fifth embodiment of the present invention, the second reference voltage generation circuit 102 generates a plurality of voltages smaller than the reference voltage VREF1 based on the reference voltage VREF1, and generates a plurality of voltages. One of them is selected and output as the reference voltage VREF2. The comparison target voltage generation circuit 103 generates the comparison target voltage VCOMP based on the output voltage VOUT received from the output voltage generation circuit 104 and the reference voltage VREF2 received from the second reference voltage generation circuit 102. In this way, by making the reference voltage VREF2 selectable from a plurality of voltages smaller than the reference voltage VREF1, the comparison target voltage VCOMP is output from the output voltage VOUT and the comparison target voltage generation circuit 103 as shown in the graph G1. The output voltage VOUT can be finely adjusted in response to variations in internal elements as compared with the case where it is assumed that the transistor is generated based only on the number of P-channel MOS transistors in the input stage.

  The reference voltage VREF2 is a voltage generated based on the reference voltage VREF1, that is, a voltage obtained by dividing the reference voltage VREF1, and thus has the same temperature characteristics as the reference voltage VREF1. Therefore, as shown in the graph G2, the temperature characteristic of the output voltage VOUT can be adjusted accurately according to the voltage value of the output voltage VOUT. Compared to the case where it is assumed that the comparison target voltage VCOMP is generated based only on the output voltage VOUT and the number of P-channel MOS transistors at the input stage in the comparison target voltage generation circuit 103 as shown in the graph G1, the graph G2 As shown, the temperature characteristic of the output voltage VOUT can be finely adjusted in accordance with the voltage value of the output voltage VOUT.

  As described above, in the semiconductor device 401 according to the fifth embodiment of the present invention, it is possible to appropriately cope with the characteristics due to the external factor of the output voltage supply destination and prevent variations in the output voltage value and the output voltage characteristics. Can do.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Sixth Embodiment>
The present embodiment relates to a semiconductor device configured to generate a plurality of types of output voltages as compared with the semiconductor device according to the fifth embodiment. The contents other than those described below are the same as those of the semiconductor device according to the fifth embodiment.

  FIG. 14 is a functional block diagram showing the configuration of the semiconductor device 402 according to the sixth embodiment of the present invention.

  Referring to FIG. 14, a semiconductor device 402 includes first reference voltage generation circuits 121A to 121C, a second reference voltage generation circuit 122, comparison target voltage generation circuits 123A to 123C, and output voltage generation circuits 124A to 124C. , A voltage generation circuit 125, decoders 126A to 126C, a memory cell array 127, a selection circuit 128, a switching circuit 129, and selection circuits 130A to 130C.

  First reference voltage generation circuits 121A to 121C generate reference voltages VREF1A, VREF1B, and VREF1C whose voltage values change according to external factors based on voltage VA received from voltage generation circuit 105, respectively. Here, the external factor is, for example, the ambient temperature of the first reference voltage generation circuits 121A to 121C, the value of the power supply voltage supplied to the first reference voltage generation circuits 121A to 121C, or the first reference voltage generation circuit 121A. It is the frequency of the signal which -121C receives.

  The output voltage generation circuits 124A to 124C respectively receive the reference voltages VREF1A, VREF1B, and VREF1C received from the first reference voltage generation circuits 121A to 121C, and the comparison target voltages VCOMPA and VCOMPB received from the comparison target voltage generation circuits 123A to 123C, respectively. VCOMPC is compared, output voltages VOUTA, VOUTB, and VOUTC are generated based on the comparison results, and output to decoders 126A to 126C and comparison target voltage generation circuits 123A to 123C, respectively. The output voltage generation circuits 124A to 124C may be VDCs (Voltage Down Converters), regulators, or charged as in the semiconductor device 401 according to the fifth embodiment of the present invention. The structure including a pump may be sufficient.

  The selection circuit 128 selects any one of the reference voltages VREF1A, VREF1B, and VREF1C received from the first reference voltage generation circuits 121A to 121C and outputs the selected reference voltage VREF1 to the second reference voltage generation circuit 122. .

  The second reference voltage generation circuit 122 generates a plurality of voltages smaller than the reference voltage VREF1 received from the selection circuit 128 based on the reference voltage received from the selection circuit 128, and outputs any one of the plurality of voltages. Select and output as reference voltage VREF2.

  The switching circuit 129 outputs the reference voltage VREF2 received from the second reference voltage generation circuit 122 to the selection circuit corresponding to the first reference voltage generation circuit that generated the selected reference voltage VREF1 among the selection circuits 130A to 130C. To do.

  The selection circuits 130A to 130C are compared with the reference voltage VREF2 received from the switching circuit 129 and the reference voltages CONSTA, CONSTB, CONSTC not having temperature characteristics received from the voltage generation circuit (not shown) as the reference voltage VREF2. The voltage is output to the voltage generation circuits 123A to 123C.

  The comparison target voltage generation circuits 123A to 123C respectively output the output voltages VOUTA, VOUTA, VOUTB, and VOUTC received from the output voltage generation circuits 124A to 124C and the reference voltage VREF2 received from the second reference voltage generation circuit 122, respectively. Comparison target voltages VCOMPA, VCOMPB, and VCOMPC having voltage values smaller than VOUTB and VOUTC are generated. With such a configuration, the breakdown voltage of the transistors and the like included in the output voltage generation circuits 124A to 124C can be reduced. For example, since the voltage received by the comparison circuit 131 in the output voltage generation circuits 124A to 124C can be made smaller than the output voltages VOUTA, VOUTB, and VOUTC, the transistors included in the comparison circuit 131 can be prevented from being destroyed.

  Further, the comparison target voltage generation circuits 123A to 123C can change the voltage values of the comparison target voltages VCOMPA, VCOMPB, and VCOMPC, for example, by an internal switch. With such a configuration, the voltage values of the output voltages VOUTA, VOUTB, and VOUTC can be changed.

  Decoders 126A-126C generate write voltages, read voltages, erase voltages, etc. based on output voltages VOUTA, VOUTB, VOUTC received from output voltage generation circuits 124A-124C, respectively, and output them to memory cell array 127. For example, decoders 126A to 126C supply voltages to word lines, source lines, and bit lines in memory cell array 127 based on output voltages VOUTA, VOUTB, and VOUTC received from output voltage generation circuits 124A to 124C, respectively.

  Memory cell array 127 includes, for example, a plurality of memory cells for storing data, and stores data, outputs stored data, and erases stored data based on write voltages, read voltages, erase voltages, etc. received from decoders 126A-126C. To do.

  Since other configurations and operations are the same as those of the semiconductor device according to the fifth embodiment, detailed description thereof will not be repeated here.

  Therefore, in the semiconductor device according to the sixth embodiment of the present invention, similarly to the semiconductor device according to the fifth embodiment of the present invention, the characteristics due to the external factor of the output voltage supply destination are appropriately handled. In addition, variations in output voltage value and output voltage characteristics can be prevented.

  Further, when it is sufficient that at least one of the voltages supplied to the word line, the source line, the bit line, and the like in the memory cell array 127 corresponds to the temperature characteristics of the memory cell, as described above. The chip area of the semiconductor device 401 can be reduced by adopting a configuration in which the two reference voltage generation circuits are shared by each system of the output voltages VOUTA to VOUTC.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a functional block diagram showing a configuration of a semiconductor device 301 according to a first embodiment of the present invention. FIG. 3 is a circuit diagram showing a configuration of a temperature compensation voltage generation circuit 51 according to the first embodiment of the present invention. 3 is a circuit diagram showing a configuration in which a part of the circuit configuration of a temperature compensation voltage generation circuit 51 is omitted. FIG. It is a graph which shows an example of the temperature characteristic of the temperature compensation voltage VT. It is a circuit diagram which shows the structure of the temperature compensation voltage generation circuit 52 which concerns on the 2nd Embodiment of this invention. FIG. 6 is a circuit diagram showing a configuration of a temperature compensation voltage generation circuit 53 according to a third embodiment of the present invention. It is a graph which shows an example of the temperature characteristic of the temperature compensation voltage VT. It is a circuit diagram which shows the structure of the temperature compensation voltage generation circuit 54 which concerns on the 4th Embodiment of this invention. It is a functional block diagram which shows the structure of the semiconductor device 401 which concerns on the 5th Embodiment of this invention. FIG. 10 is a circuit diagram showing a configuration of a first reference voltage generation circuit 101 in a semiconductor device 401 according to a fifth embodiment of the present invention. FIG. 10 is a circuit diagram showing a configuration of a second reference voltage generation circuit 102 in a semiconductor device 401 according to a fifth embodiment of the present invention. FIG. 10 is a circuit diagram showing configurations of a comparison target voltage generation circuit 103 and an output voltage generation circuit 104 in a semiconductor device 401 according to a fifth embodiment of the present invention. It is a graph which shows the relationship between the voltage value of the output voltage VOUT of the semiconductor device 401 which concerns on the 5th Embodiment of this invention, and a temperature characteristic. It is a functional block diagram which shows the structure of the semiconductor device 402 concerning the 6th Embodiment of this invention.

Explanation of symbols

  3 Comparison target voltage generation circuit, 4 Output voltage generation circuit, 5 Reference voltage generation circuit, 6 Decoder, 7 Memory cell array, 11, 21, 31, 61 Input transistor unit, 12, 22, 32, 62 Output transistor unit, 13, 63 current mirror circuit (output current control circuit), 14, 64 constant current source, 51-54, 71 temperature compensation voltage generation circuit, 301 semiconductor device, M1, M11-M13, M31, M41, M42 N-channel MOS transistor, M21 , M22, M51, M52 P-channel MOS transistors, 101, 121A to 121C, first reference voltage generation circuit, 102, 122, second reference voltage generation circuit, 103, 123A to 123C, comparison target voltage generation circuit, 104, 124A to 124C output Voltage generation circuit 105, 125 voltage generation circuit, 06, 126A to 126C decoder, 107, 127 memory cell array, 111 comparison circuit, 112 VREF2 selection circuit, 113 resistance unit, 128, 130A to 130C selection circuit, 129 switching circuit, 131 comparison circuit, 132 charge pump, 133 capacitor, 101 , 102 Semiconductor device, M101, M102, M111, M121 to M127 P-channel MOS transistors, M103 to M105, M128, M129, M130 N-channel MOS transistors, SW1 to SW4 switches.

Claims (12)

A first input transistor portion including a first transistor having a control electrode to which a reference voltage is supplied;
A first output transistor section including a diode-connected second transistor;
A first output current control circuit for causing a current corresponding to a current flowing between the conductive electrodes of the first transistor to flow between the conductive electrodes of the second transistor;
At least one of the first input transistor section and the first output transistor section is further diode-connected and connected in series with the corresponding first transistor or the second transistor, and the corresponding Including one or more third transistors that output a current in the same direction as the output current of the first transistor or the second transistor;
The total number of the third transistors in the first transistor and the first input transistor portion is different from the total number of the third transistors in the second transistor and the first output transistor portion,
The size of the first transistor, the size of the one or more third transistors in the first input transistor portion, the size of the second transistor, and the size of the one or more in the first output transistor portion. Unlike the size of the plurality of third transistors,
A semiconductor device in which a voltage at a control electrode of the second transistor is an output voltage. The total number of the third transistors in the first transistor and the first input transistor portion is less than the total number of the third transistors in the second transistor and the first output transistor portion,
The size of the first transistor and the size of the one or more third transistors in the first input transistor portion are the size of the second transistor and the size of the one transistor in the first output transistor portion. The semiconductor device according to claim 1, wherein the semiconductor device is smaller than a plurality of third transistors. The total number of the third transistors in the first transistor and the first input transistor portion is greater than the total number of the third transistors in the second transistor and the first output transistor portion,
The size of the first transistor and the size of the one or more third transistors in the first input transistor portion are the size of the second transistor and the size of the one transistor in the first output transistor portion. The semiconductor device according to claim 1, wherein the semiconductor device is larger than a plurality of third transistors.   2. The semiconductor device according to claim 1, wherein the first input transistor section includes the first transistor and the one or more third transistors that are substantially equal in size.   2. The semiconductor device according to claim 1, wherein the first output transistor section includes the second transistor and the one or more third transistors that are substantially equal in size. The semiconductor device further includes:
A second input transistor portion including a fourth transistor having a control electrode coupled to the control electrode of the second transistor;
A second output transistor section including a diode-connected fifth transistor;
A second output current control circuit for causing a current corresponding to a current flowing between the conductive electrodes of the fourth transistor to flow between the conductive electrodes of the fifth transistor;
At least one of the second input transistor portion and the second output transistor portion is further diode-connected and connected in series with the corresponding fourth transistor or the fifth transistor, and the corresponding Including one or more sixth transistors that output current in the same direction as the output current of the fourth transistor or the fifth transistor;
The magnitude relationship between the total number of the sixth transistors in the fourth transistor and the second input transistor portion and the total number of the sixth transistors in the fifth transistor and the second output transistor portion is as follows. The magnitude relationship between the total number of the third transistors in the first transistor and the first input transistor portion and the total number of the third transistors in the second transistor and the first output transistor portion is the same. ,
The size of the fourth transistor and the size of the one or more sixth transistors in the second input transistor portion and the size of the fifth transistor and the one or more in the second output transistor portion The size relationship between the sizes of the plurality of sixth transistors is such that the size of the first transistor, the size of the one or more third transistors in the first input transistor portion, and the second transistor. And the size relationship of the size of the one or more third transistors in the first output transistor section,
The semiconductor device according to claim 1, wherein a voltage at a control electrode of the fifth transistor is an output voltage. A first reference voltage generation circuit that generates a first reference voltage whose voltage value changes according to an external factor;
An output voltage generation circuit that compares the first reference voltage with a comparison target voltage and generates an output voltage based on the comparison result;
Based on the first reference voltage, a plurality of voltages smaller than the first reference voltage are generated, and any one of the plurality of voltages is selected and output as a second reference voltage. A reference voltage generation circuit;
A semiconductor device comprising: a comparison target voltage generation circuit that generates the comparison target voltage based on the output voltage and the second reference voltage.   8. The semiconductor device according to claim 7, wherein the comparison target voltage generation circuit generates the comparison target voltage having a voltage value smaller than the output voltage based on the output voltage and the second reference voltage. The comparison target voltage generation circuit includes:
A first transistor having a control electrode, a first conduction electrode to which the output voltage is supplied, and a second conduction electrode coupled to the control electrode;
A control electrode to which the second reference voltage is supplied, a first conduction electrode coupled to a second conduction electrode of the first transistor, and a first potential electrode coupled to a fixed potential node to which a fixed voltage is supplied. A second transistor having two conducting electrodes;
A third transistor having a control electrode coupled to the control electrode of the first transistor, a first conduction electrode to which the output voltage is supplied, and a second conduction electrode;
A fourth transistor having a first conduction electrode coupled to the second conduction electrode of the third transistor, a control electrode coupled to the fixed potential node and a second conduction electrode;
The semiconductor device according to claim 7, wherein the comparison target voltage generation circuit outputs a voltage at the first conduction electrode of the fourth transistor as the comparison target voltage. The comparison target voltage generation circuit further includes:
10. The semiconductor device according to claim 9, further comprising a switch having a first end coupled to a first conduction electrode of the first transistor and a second end coupled to a second conduction electrode of the first transistor.   The external factor is an ambient temperature of the first reference voltage generation circuit, a power supply voltage value supplied to the first reference voltage generation circuit, or a frequency of a signal received by the first reference voltage generation circuit. The semiconductor device described. The semiconductor device includes:
A plurality of the first reference voltage generation circuits;
One second reference voltage generation circuit;
A plurality of comparison target voltage generation circuits respectively corresponding to the plurality of first reference voltage generation circuits;
The comparison target voltage received from the corresponding comparison target voltage generation circuit and the first reference voltage received from the corresponding first reference voltage generation circuit respectively corresponding to the plurality of first reference voltage generation circuits. And a plurality of the output voltage generation circuits for generating the output voltage based on the comparison result,
A selection circuit that selects and outputs one of the first reference voltages received from the plurality of first reference voltage generation circuits to the second reference voltage generation circuit;
Switching to output the second reference voltage received from the second reference voltage generation circuit to the comparison target voltage generation circuit corresponding to the first reference voltage generation circuit that has generated the selected first reference voltage The semiconductor device according to claim 7, comprising a circuit.

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