201128910 、 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種應用於同步整流的死區調整電路及方 法，尤指一種具有粗調節功能及細調節功能的死區調整電路及 方法。 【先前技術】 ^著地辅化及石油能源的消耗，發射代能源及綠色能 源已是勢在必行，但以目前來看，麟替姐源及綠色能源完 全取代石油的階段還尚有努力空間，因此，如能提高電源轉換 效率便能有效的降低能量的耗損，而提高轉換效率的方法之一 便是使用同步整流電路。 而在同步整流電路中’其主要技術在於控制一次侧電路與 二次側電路的電路開關時間，而通常同步整理電路中之技術重 點便在於控制二次側電路中的電晶體關閉時間，稱之為死區時 間（Dead Time)之控制，如美國第6〇3815〇號專利案之” Φ transistorized rectifier for a multiple output CONVERTEK ’其_露了-種顧在電源轉換㈣無二極 體一-人側子電路（Secondary Subcircuit),請參閱圖1，其主要 技術在於利用利用複數電晶體2開關取代二極體電路，並且藉 由個一-人側後校準電路3 (Secondary Side post regulation， SSPR)從同步訊號起始點利則貞比比較的方式—步—步的逼 近一脈波寬度調變電路4中的開關訊號，藉此調整二次側子電 路1的死區時間以製造出同步整流訊號，但同步訊號的時間週 期將使二次侧後校準電路3用於記憶前次週期的電容面積過 201128910 大，進而提尚了電路的使用面積及元件成本，且由於是一步一 步的逼近，因此需要較多的時間以達到其預定的死區時間。 再者，如美國第6418039號專利案，該案揭露了一種控制 同步整理器的關閉時間的裝置及方法，請參閱圖2，其主要是 利用一數位關閉控制器5 (digital Turn-Off Controller)來控制 同步整流器中之二次側電晶體6的關閉時間，更進^步的說 明’該數位關閉控制器5藉由一固定頻率的時脈訊號來判斷關 閉該二次側電晶體6的時間，藉由全數位的方式來達成同步整 鲁 流器一次側電晶體6的開關控制，惟，時脈訊號的頻率控制著 '一a側電B曰體6的關閉延遲時間，若時脈訊號的頻率太低，容 易有關閉延遲時間過長的問題，造成與一次侧電路開關時間的 匹配誤差，但若提高時脈訊號的頻率，則必須使用較高頻的電 路元件及高頻比較器元件，間接提高了電路成本。 【發明内容】 本發明之主要目的，在於解決傳統類比電路中必須使用大 面積的電容來逼近一次侧電路中的開關訊號，藉此調整二次侧 電路的死區時間以製造出同步整流訊號。 本發明之另一目的，在於解決習知技術中之類比電路因使 用過多的時間完成死區的逼近而造成功率的損耗以及效率的 浪費。 本發明之再一目的，在於解決全數位關閉控制器必須使用 高頻的時脈訊號以避免關閉延遲時間過長，造成與一次侧電路 開關時間的匹配誤差。 為達上述目的’本發明提供一種具粗調節功能及細調節功 201128910 能的死區調整電路，以下簡稱為死區調整電路，其係應用於— 同步整流電路中’該同步整流電路主要包含有一個一次側子電 路（Primary Subcircuit)及一個二次側子電路（Sec〇nd 町 Subcircuit) ’而該死區調整電路應用於該二次側子電路，控制 該同步整流電路中的一死區時間，該死區調整電路包括有一粗 調節單元、一細調節單元及一分別與該粗調節單元及該細調節 單π連接的訊號合成單元。該粗調節單元設置於該同步整流電 路中，用以對一同步訊號進行粗調節後輸出一粗調節訊號丨該 細調節單元與該粗調節單元連接，用以將該粗調節訊號進行細 微調節後輸出一細調節訊號；而該訊號合成單元用以輸出一控 制訊號，該控制訊號用以控制該二次側子電路中的至少一電曰^ 體之開關’完成該死區時間的控制。 由上述說明可知’本發明利用該粗調節單元完成初步且較 大的死區時間控制，並得到該粗調節訊號，在將該粗調節訊號 傳遞至該細調節單元，再進行細微的死區時間調整，以達成最 佳化的死區時間，相較於習知技術的類比逼近電路，本發明利 用粗調節單元大幅縮小元件中的電容面積，並有效節省電路元 件的成本，且縮短了逼近死區所需要的時間，再利用細調節單 元進行死區時間微調，精準的得到最佳化的死區時間，提高同 步整流之效率及降低同步整流電路的成本。 【實施方式】 有關本發明之詳細說明及技術内容，現就配合圖式說明如 下： 明參閱圖3及圖4所示，圖3係本發明一較佳實施例之同 步整流電路架構示意圖’圖4係本發明-較佳實施例之方塊配 5 201128910201128910, VI. Description of the Invention: [Technical Field] The present invention relates to a dead zone adjustment circuit and method for synchronous rectification, and more particularly to a dead zone adjustment circuit and method having a coarse adjustment function and a fine adjustment function. [Prior Art] ^ Land-assisted and petroleum energy consumption, launching energy and green energy is imperative, but for the time being, there is still some effort in the stage of replacing the oil with the source of green energy and green energy. Space, therefore, if the power conversion efficiency can be improved, the energy consumption can be effectively reduced, and one of the methods for improving the conversion efficiency is to use a synchronous rectification circuit. In the synchronous rectification circuit, the main technique is to control the circuit switching time of the primary side circuit and the secondary side circuit. However, the technical focus in the synchronous finishing circuit is to control the transistor closing time in the secondary side circuit, which is called For the control of Dead Time, such as the US Patent No. 6, 3815 ” patent " Φ transistorized rectifier for a multiple output CONVERTEK ' _ _ _ _ Gu in the power conversion (four) no diode one - person The secondary subcircuit, please refer to FIG. 1 , the main technique is to replace the diode circuit by using the complex transistor 2 switch, and by the secondary side post regulation (SSPR). From the starting point of the synchronous signal, the method of comparing the step-step approaching the switching signal in the pulse width modulation circuit 4, thereby adjusting the dead time of the secondary side sub-circuit 1 to manufacture synchronous rectification Signal, but the time period of the synchronization signal will make the secondary side post-calibration circuit 3 used to remember that the capacitance area of the previous cycle is greater than 201128910, which in turn increases the use surface of the circuit. The cost of the component is accumulated, and because it is a step-by-step approach, it takes more time to reach its predetermined dead time. Furthermore, as disclosed in U.S. Patent No. 6,418,039, the disclosure of the present invention discloses the closure of a control synchronizer. For the device and method of time, please refer to FIG. 2, which mainly uses a digital turn-off controller 5 to control the closing time of the secondary side transistor 6 in the synchronous rectifier, and further description of the step. 'The digital off controller 5 determines the time to turn off the secondary side transistor 6 by a fixed frequency clock signal, and achieves the switching control of the primary side transistor 6 of the synchronous rectifier device by means of full digits. However, the frequency of the clock signal controls the turn-off delay time of the 'one-side side B-body 6. If the frequency of the clock signal is too low, it is easy to have a problem that the off-delay time is too long, causing the switching time with the primary side circuit. Matching error, but if the frequency of the clock signal is increased, higher frequency circuit components and high frequency comparator components must be used, which indirectly increases the circuit cost. The main purpose of the present invention is to solve the problem that a large-area capacitor must be used in a conventional analog circuit to approximate the switching signal in the primary side circuit, thereby adjusting the dead time of the secondary side circuit to manufacture a synchronous rectification signal. In order to solve the problem that the analog circuit in the prior art uses the excessive time to complete the dead zone, the power loss and the waste of efficiency are caused. A further object of the present invention is to solve the problem that the full digital shutdown controller must use high frequency. The pulse signal avoids the off delay time being too long, causing a matching error with the switching time of the primary side circuit. In order to achieve the above object, the present invention provides a dead zone adjustment circuit with a coarse adjustment function and a fine adjustment function 201128910, which is hereinafter referred to as a dead zone adjustment circuit, which is applied to a synchronous rectifier circuit. a primary sub-circuit (Primary Subcircuit) and a secondary side sub-circuit (Sec〇nd-cho Subcircuit)' and the dead zone adjustment circuit is applied to the secondary side sub-circuit to control a dead time in the synchronous rectification circuit, damn The zone adjustment circuit includes a coarse adjustment unit, a fine adjustment unit, and a signal synthesis unit respectively connected to the coarse adjustment unit and the fine adjustment unit π. The coarse adjustment unit is disposed in the synchronous rectification circuit for coarsely adjusting a synchronous signal and outputting a coarse adjustment signal, and the fine adjustment unit is connected to the coarse adjustment unit for finely adjusting the coarse adjustment signal. A fine adjustment signal is output; and the signal synthesizing unit is configured to output a control signal for controlling at least one of the switches of the secondary side sub-circuit to complete the control of the dead time. It can be seen from the above description that the present invention uses the coarse adjustment unit to perform preliminary and large dead time control, and obtains the coarse adjustment signal, and transmits the coarse adjustment signal to the fine adjustment unit, and then performs a fine dead time. Adjusting to achieve optimized dead time, compared with the analog approximation circuit of the prior art, the invention greatly reduces the capacitance area in the component by using the coarse adjustment unit, and effectively saves the cost of the circuit component, and shortens the approximation to death. The time required by the area is then fine-tuned by the fine adjustment unit to accurately optimize the dead time, improve the efficiency of synchronous rectification and reduce the cost of the synchronous rectification circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The detailed description and technical contents of the present invention will now be described with reference to the following drawings: FIG. 3 and FIG. 4, FIG. 3 is a schematic diagram of a synchronous rectification circuit architecture according to a preferred embodiment of the present invention. 4 is a block of the present invention - a preferred embodiment 5 201128910
圖所不：本發明係為—種具粗調節魏及細調節 死區調整電路’以下簡稱為死區調整電路1G，A係應 用於一同步整流電財，關步整流電路主要包含有—個^ 侧子電路2G及-個二次侧子電路％，而該死區調整電路⑺ 應用於該二次側子電路3G，用以控制該同步整流電路中的一 f時間’請再參閱圖4，該死區調整電路10包括有—粗調 早兀n、—細調節單元12及―分別與該粗調節單元Η及 該、’田°周節單元12連接的訊號合成單元I3。該粗調節單元η 設^於該同步整流電路巾，肋對—同步峨swc進行粗 調即後輸出一粗調節訊號rough;該細調節單元12與該粗調節 單元11連接’肋將雜瓣訊號咖助進行細微調節後輸 出「細調節訊號fine ;而該訊號合成單元〗3用以輸出一控制 訊號CS該控制訊號cs用以控制該二次側子電路中的至 少一電晶體31之開關時間，完成該死區時間的控制。 明再參閱圖5-1及圖5-2，圖5·1係本發明一較佳實施例 之數位調節電路示意圖，而圖5_2係本發明—較佳實施例之數 位調節電路時脈訊號示意圖。本發明之粗調節單元u係可藉 由一數位調節電路進行粗調節，如圖所示：該數位調節電路係 藉由兩時脈訊號clkl、clk2進行粗調節記數，該兩時脈訊號 did、Clk2會對該同步訊號sync進行記數比較，而得該粗調 節訊號rough’因為粗調節單元n即為一初步的死區時間控 制，因此不需要高頻率的時脈訊號，僅需要一較低頻率的時脈 訊號即可達成初步的死區時間控制。 而本發明之粗調節單元U亦可藉由一類比調節電路達成 粗调郎之功能，如圖6-1至圖6-5所示，其中，圖中各個接點 201128910 各具有其對應的接點名稱’相同之接點名稱代表各個路圖中 之接點相接，該類比調節電路包含有一第—調節單元丨丨丨、一 第一調節單元112及一連接該第一調節單元111及該第二調節 單元112的比較單元113,該類比調節電路藉由該比較單元113 對該第-調節單元m及該第二調節單元112進行峨比較而 得一粗調節訊號rough，而圖6-5為本發明一較佳實施例之類 比調節電路各接點訊號的時脈示意圖，由圖6_5搭配圖61至 圖64，可以很清楚的瞭解各個電路單元的操作狀態，並得到 一粗調節訊號rough。 再者，請參閱圖7-1及圖7-2，其係為本發明一較佳實施 例之細調節單元12及訊號合成單元13之電路及時脈示意圖， 其中’圖中各個接點各具有其對應的接點名稱，相同之接點名 稱代表各個電路圖中之接點相接’並且，各個接點的時脈狀態 如圖7-2所示，由圖中可知，透過一制動訊號Fenable的控制 對一電谷C1充放電產生一鑛嵩波電壓vsaw，該制動訊號 Fenable為該粗调郎訊號rough (示於圖6-5)與該同步訊號 SYNC比較後取得，而後透過該鋸齒波電壓Vsaw變化與一參 考電壓Vref做比較得到一細調節訊號fme，該細調節訊號fme 會在經過一斜率控制器121重新調整一輸入電壓v卜V2的大 小以調整該鑛齒波電麼Vsaw的波形斜率，該雜齒波電壓vsaw 的波形斜率不同便會影響到該細調節訊號fme的責任週期 (Duty Cycle)，該訊號合成單元13分析該細調節訊號fine與 該同步訊號SYNC後’得到一控制訊號CS，該控制訊號CS 用以控制該二次側子電路30的電晶體31 (示於圖3)之開關 時間，藉此縮小死區時間，以增加效率，需特別說明的是，藉 201128910 由該控制訊號cs控制該電晶體31關閉後，可得—死區時間 時脈Dt ’該死區時間時脈Dt越小，代表與該—次侧子電路2〇 的開’步率越高，也代表·的耗損率越低，賴7_2中可 知，該死區時剛寺脈Dt責任週期會隨著細調節訊號“的調 整而漸漸·，本發定—聽_最小值Dtm，當該死區 時間時脈Dt的責_期小於該聽時間最小值_的責任週 期時’該斜率控制器⑵就會調整該輸入電壓％、V2，以重 新調整該縣波電壓Vsaw，避免細卿峨fme調整過當， 反而超過了設定的時間週期。 更進一步的說明，請參閱圖8，圖8為本發明一較佳實施 例之流程步驟示意圖’藉由步驟S1_S5共五個步驟做更進一步 的解說，並請同時參閱圖3至圖7-2 : si:進行粗調節，將一同步訊號SYNC進行粗調節，藉 由一粗調節單元11對輸入之同步訊號SYNC進行粗調節，並 且得到一粗調節訊號rough，其中，係使用一數位粗調節的方 式對該同步訊號SYNC進行粗調節，該數位粗調節的方式係 才曰利用時脈訊號clkl、clk2之頻率來對該同步訊號sync進行 記數比較’而除了使用該數位粗調節的方式之外，亦可使用類 比粗調節的方式對該同步訊號SYNC進行粗調節； S2 .進行細調節’將該粗調節訊號^^沙輸入至一細調節 單元12 ’藉由該細調節單元12對該粗調節訊號rough進行細 微調整後輸出一細調節訊號fine，其中，請配合參閱圖7_丨及 圖7-2 ’該粗調節訊號會轉換成一反細調節制動訊號 Finable ’該細調節單元〗2便藉由該反細調節制動訊號Fenable 作為時脈訊號clkl、clk2進行細調節，並且，在本實施例中， 201128910 係使用一斜率調整的鋸齒波比較方法進行細調節，該鑛齒波比 較方法為藉由一鑛齒波電壓Vs aw變化與一參考電壓vref做比 較’進而取得一微調後的細調節訊號fme ; 53 :回授微調，將該細調節訊號fme經過一斜率分析，得 到一微調訊號後重新傳回給該細調節單元12進行微調，以得 到一較佳的細調節訊號fme ; 54 ·訊號合成’分別將該粗調節訊號r〇Ugh及該細調節訊 號fme經由一訊號合成單元13進行訊號合成為一控制訊號 cs ； 1 55 :控制死區時間，藉由該控制訊號〇§控制該同步整流 電路中的電晶體31開關，藉此調整死區時間時脈Dt。 綜上所述，由於本發明利用該粗調節單元u完成初步且 較大的死區時制’並制雜調節峨⑺喻，在將該粗 調節訊號rough傳遞至該細調節單元12，再進行細微的死^時 間调整，以達成最佳化的死區時間，相較知 近電路，本發日糊粗單元11A咖、元射的電1^ 積，並有效節省電路元件的成本，且縮短了逼近死區所需要的 時間’再彻細瓣單元12進行死區時間微調，精準的得到 最佳化的腿關，提如錄紅效率及降朗步整流電路 的成本。·本發雜具進步性及符合申請發明專利之要件， 麦依法提出申請，析狗局早曰賜准專利，實感德便。 =上已將本發養—詳細，惟以上所述者，僅爲本發 =-較佳實施綱已，#不能限定本發明實施之範圍。即凡 依本發明申請範圍所作之轉變化與修飾等，皆應仍 201128910The figure is not: the invention is a kind of coarse adjustment Wei and fine adjustment dead zone adjustment circuit 'hereinafter referred to as dead zone adjustment circuit 1G, A system is applied to a synchronous rectification power, the closed step rectifier circuit mainly includes one ^ side sub-circuit 2G and - secondary side sub-circuit %, and the dead zone adjustment circuit (7) is applied to the secondary side sub-circuit 3G for controlling an f-time in the synchronous rectification circuit. Please refer to FIG. 4 again. The dead zone adjustment circuit 10 includes a coarse adjustment unit n, a fine adjustment unit 12, and a signal synthesizing unit I3 connected to the coarse adjustment unit Η and the 'Tian Zhou section unit 12, respectively. The coarse adjustment unit η is disposed on the synchronous rectification circuit towel, and the rib pair-synchronous 峨swc is coarsely adjusted to output a coarse adjustment signal rough; the fine adjustment unit 12 is connected to the coarse adjustment unit 11 to rib the miscellaneous signal After the fine adjustment, the fine adjustment signal is output; and the signal synthesis unit 3 is used to output a control signal CS for controlling the switching time of the at least one transistor 31 in the secondary side sub-circuit. The control of the dead time is completed. Referring to FIG. 5-1 and FIG. 5-2, FIG. 5 is a schematic diagram of a digital adjustment circuit according to a preferred embodiment of the present invention, and FIG. 5_2 is a preferred embodiment of the present invention. The digital adjustment circuit of the present invention can be coarsely adjusted by a digital adjustment circuit, as shown in the figure: the digital adjustment circuit is coarsely adjusted by two clock signals clkl and clk2. Counting, the two clock signals did, Clk2 will count the synchronization signal sync, and the coarse adjustment signal rough' is because the coarse adjustment unit n is a preliminary dead time control, so no high frequency is needed. of The clock signal only needs a lower frequency clock signal to achieve the initial dead time control. The coarse adjustment unit U of the present invention can also achieve the function of coarse adjustment by an analog adjustment circuit, as shown in FIG. -1 to Figure 6-5, wherein each contact point 201128910 in the figure has its corresponding contact name 'the same contact name represents the contact point in each road map, the analog adjustment circuit includes a first An adjustment unit 丨丨丨, a first adjustment unit 112 and a comparison unit 113 connected to the first adjustment unit 111 and the second adjustment unit 112, the analog adjustment circuit is used by the comparison unit 113 for the first adjustment unit And the second adjusting unit 112 performs a coarse adjustment signal rough, and FIG. 6-5 is a clock diagram of the analog signal of the analog adjusting circuit according to a preferred embodiment of the present invention. 61 to 64, the operating state of each circuit unit can be clearly understood, and a coarse adjustment signal rough is obtained. Further, please refer to FIG. 7-1 and FIG. 7-2, which are a preferred embodiment of the present invention. Fine adjustment unit 12 and signal combination The circuit of the unit 13 is a schematic diagram of the circuit, wherein each contact in the figure has its corresponding contact name, and the same contact name represents the contact point in each circuit diagram and the clock state of each contact is as shown in the figure. As shown in Fig. 7-2, it can be seen from the figure that a mine ripple voltage vsaw is generated by charging and discharging a battery valley C1 through the control of a brake signal, and the brake signal is a rough signal (shown in Fig. 6). 5) Obtaining a comparison with the synchronization signal SYNC, and then comparing the sawtooth voltage Vsaw with a reference voltage Vref to obtain a fine adjustment signal fme, the fine adjustment signal fme is readjusted by an inclination controller 121. The magnitude of the voltage vV2 is used to adjust the slope of the waveform of the ore tooth wave, Vsaw, and the slope of the waveform of the noise wave voltage vsaw affects the duty cycle of the fine adjustment signal fme, the signal synthesis unit After analyzing the fine adjustment signal fine and the synchronization signal SYNC, a control signal CS is obtained, and the control signal CS is used to control the switching time of the transistor 31 (shown in FIG. 3) of the secondary side sub-circuit 30. In order to reduce the dead time, in order to increase the efficiency, it is necessary to specifically indicate that, by the control signal cs, the control signal cs is turned off, the dead time time clock Dt 'the dead time time clock Dt is smaller. , the higher the step rate of the second sub-circuit 2 ,, the lower the loss rate of the representative, the lower the loss rate of the lag 7_2, the Dt duty cycle of the dead zone will follow the fine adjustment signal Adjusting and gradually, the present setting - listening _ minimum value Dtm, when the dead time time clock Dt _ period is less than the listening time minimum _ the duty cycle 'the slope controller (2) will adjust the input voltage % V2, in order to re-adjust the county wave voltage Vsaw, to avoid the fine adjustment of the fme, but exceeded the set time period. For further explanation, please refer to FIG. 8. FIG. 8 is a schematic diagram of the process steps according to a preferred embodiment of the present invention, which is further illustrated by five steps in steps S1_S5, and please refer to FIG. 3 to FIG. 7-2 at the same time. : si: performing coarse adjustment, coarse adjustment of a synchronization signal SYNC, rough adjustment of the input synchronization signal SYNC by a coarse adjustment unit 11, and obtaining a coarse adjustment signal rough, wherein a digital adjustment is used. The method performs coarse adjustment on the synchronization signal SYNC, and the digital coarse adjustment method uses the frequency of the clock signals clk1 and clk2 to perform a log comparison of the synchronization signal sync', except for the manner of using the digital coarse adjustment. The synchronous signal SYNC can also be coarsely adjusted by analogy coarse adjustment; S2. Fine adjustment is performed 'the coarse adjustment signal ^^ sand is input to a fine adjustment unit 12' by the fine adjustment unit 12 Adjust the signal rough to fine-tune and output a fine adjustment signal fine. Please refer to Figure 7_丨 and Figure 7-2 for the coarse adjustment signal to be converted into a fine adjustment brake signal Fin. The 'fine adjustment unit〗 2 is finely adjusted by the inverse adjustment brake signal Fenable as the clock signals clkl, clk2, and, in this embodiment, 201128910 is thinned using a slope-adjusted sawtooth wave comparison method. Adjustment, the ore wave comparison method is to compare a reference voltage vref by a change of the ore wave voltage Vs aw' to obtain a fine adjustment signal fme; 53: feedback fine adjustment, the fine adjustment signal fme After a slope analysis, a fine adjustment signal is obtained and then returned to the fine adjustment unit 12 for fine adjustment to obtain a better fine adjustment signal fme; 54 · Signal synthesis 'the coarse adjustment signal r〇Ugh and the fine The adjustment signal fme is synthesized by a signal synthesizing unit 13 into a control signal cs; 1 55: controlling the dead time, and controlling the transistor 31 in the synchronous rectification circuit by the control signal, thereby adjusting the dead zone Time clock Dt. In summary, since the present invention utilizes the coarse adjustment unit u to complete a preliminary and large dead zone system, the coarse adjustment signal rough is transmitted to the fine adjustment unit 12, and then fine The dead time adjustment, in order to achieve the optimized dead time, compared to the near circuit, the power of the unit 11A coffee, the energy of the yuan shot, and effectively save the cost of circuit components, and shortened The time required to approach the dead zone is further refined by the fine-grained unit 12 to accurately optimize the dead leg, such as the efficiency of recording and the cost of the rectifier circuit. · The hairpin is progressive and meets the requirements of applying for a patent for invention. Mai applied for it according to law, and the dog bureau gave a patent in advance, and it was really sensible. = The above has been raised - detailed, but the above is only the present invention = - preferred implementation, # can not limit the scope of implementation of the present invention. That is, any changes and modifications made in accordance with the scope of the application of the present invention should still be 201128910
之專利涵蓋範圍内。 【圖式簡單說明】 圖1，係習知技術一之電路示意圖。 圖2，係習知技術二之電路示意圖。 圖3，係本發明一較佳實施例之同步整流電路架構示意圖。 圖4，係本發明一較佳實施例之方塊配置示意圖。 圖5-1 ’係本發明一較佳實施例之數位調節電路示意圖。 圖5-2，係本發明一較佳實施例之數位調節電路時脈訊號示音 圖。 〜 圖6-卜係本發明一較佳實施例之類比調節電路示意圖一。 圖6-2，係本發明一較佳實施例之類比調節電路示意圖二。 圖6-3，係本發明一較佳實施例之類比調節電路示意圖三。 圖6-4 ’係本發明一較佳實施例之類比調節電路示意圖四。 ’係本發明—較佳實關之鏡調節電路時脈示意圖。 崎綠蝴㈣魏號合成單元 圖8，係本發明—較佳實施例之流程步驟示意圖。 【主要元件符號說明】 習知技術 1:二次側子電路 2 :電晶體 3:二次側後校準電路 4:脈波寬度調變電路 5:數位關閉控制器 201128910 6:二次側電晶體 本發明 10 :死區調整電路 11 :粗調節單元 111 :第一調節單元 112 :第二調節單元 113 :比較單元 12 :細調節單元 Fenable :制動訊號 C1 :電容 121 :斜率控制器 VI、V2 :輸入電壓 13 :訊號合成單元 SYNC :同步訊號 CS :控制訊號 clkl、clk2 :時脈訊號 rough :粗調節訊號 fine :細調節訊號 Vref :參考電壓 Vsaw :鋸齒波電壓 20 一次侧子電路 30 二次側子電路 31 電晶體 Dt 死區時間時脈The patent covers the scope. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram of a circuit of the prior art. FIG. 2 is a schematic diagram of a circuit of the prior art 2. FIG. 3 is a schematic structural diagram of a synchronous rectification circuit according to a preferred embodiment of the present invention. 4 is a block diagram showing a configuration of a preferred embodiment of the present invention. 5-1 is a schematic diagram of a digital adjustment circuit in accordance with a preferred embodiment of the present invention. FIG. 5-2 is a timing diagram of a clock signal of a digital adjustment circuit according to a preferred embodiment of the present invention. ~ Figure 6 is a schematic diagram of an analog adjustment circuit of a preferred embodiment of the present invention. FIG. 6-2 is a second schematic diagram of an analog adjustment circuit according to a preferred embodiment of the present invention. FIG. 6-3 is a third schematic diagram of an analog adjustment circuit according to a preferred embodiment of the present invention. Figure 6-4 is a fourth schematic diagram of an analog adjustment circuit in accordance with a preferred embodiment of the present invention. </ RTI> is a schematic diagram of the clock of the mirror adjustment circuit of the present invention. Sakura Butterfly (4) Wei No. Synthesis Unit Figure 8 is a schematic diagram of the process steps of the present invention - a preferred embodiment. [Major component symbol description] Conventional technology 1: Secondary side sub-circuit 2: Transistor 3: Secondary side post-calibration circuit 4: Pulse width modulation circuit 5: Digital-off controller 201128910 6: Secondary side electricity Crystal 10: dead zone adjustment circuit 11: coarse adjustment unit 111: first adjustment unit 112: second adjustment unit 113: comparison unit 12: fine adjustment unit Fenable: brake signal C1: capacitance 121: slope controller VI, V2 : input voltage 13 : signal synthesis unit SYNC : synchronization signal CS : control signal clkl, clk2 : clock signal rough : coarse adjustment signal fine : fine adjustment signal Vref : reference voltage Vsaw : sawtooth voltage 20 primary side sub-circuit 30 twice Side sub-circuit 31 transistor Dt dead time clock
Dtm :死區時間最小值Dtm: dead time minimum