TWI676357B - Systems and methods for synchronizing execution of recipe sets - Google Patents

Abstract

A system and method for synchronizing the execution of a recipe group is described. One of the methods includes sending a recipe set to a main controller by an instruction controller, and sending the recipe set by a main controller for a subsystem controller of a plasma system to execute. The operation of sending the recipe group from the main controller to the subsystem controller is performed within a first clock cycle of a clock signal. The method includes generating a recipe event signal by the instruction controller and sending the recipe event signal to the subsystem controller by the instruction controller, and the recipe event signal instructs the subsystem controller to execute the recipe group. One execution time. The execution time occurs within a second clock cycle following the first clock cycle, wherein the second clock cycle belongs to the clock signal.

Description

Execution synchronization system and method of formula group

The present invention relates to a system and method for synchronizing the execution of a recipe group.

The plasma system is used to perform various operations. For example, a plasma system has multiple stations for cleaning wafers, depositing materials on the wafer, etching the wafer, and the like. Each station is controlled by one or more processing devices to perform operations.

Information is transmitted between these processing devices to perform operations. However, in order to transmit information, the scheduling of each processing device is quite urgent. For example, each processing device must process the data within a predetermined time window before providing the processed data to another processing device.

Such time window requirements lead to expensive processing equipment. In addition, when processing devices are being used, the data transmission rate between such processing devices is limited.

The present invention was developed in this context.

The embodiments of the present disclosure provide a device, a method, and a computer program for synchronizing the execution of the recipe group. I should understand that the present invention can be implemented in many ways, such as processing, equipment, systems, hardware, methods, or computer-readable media. Several embodiments are described below.

In one embodiment, before sending a signal to execute the recipe group, the recipe group to be executed is sent from one controller to another controller. For example, a master controller sends a recipe group to a slave controller before sending a pulse instructing a slave controller to execute the recipe group. The advance sending of such a recipe group provides the slave controller with the time to prepare the execution of the recipe group. Upon receiving a pulse instructing the slave controller to execute the recipe group, the slave controller executes the received recipe group, and the slave controller executes the recipe group by sending the recipe group for processing.

Sending multiple recipe groups to multiple slave controllers before sending a pulse indicating execution of the recipe groups saves each of the slave controllers from executing the recipe group within a time window. For example, in Ethernet for Control Automation Technology (EtherCAT), a slave controller receives multiple recipe groups, identifies one of the recipe groups, and sends the multiple recipe groups. The identified recipe group is executed before reaching another slave controller. The identification and execution should be completed within a time window, which is a limitation and increases costs. In addition, such EtherCAT slave controllers are expensive and difficult to obtain due to low production. In addition, EtherCAT slave controllers are speed limited, for example limited to megabits per second. By using a system and method for synchronizing the execution of a recipe group, the sending of multiple recipe groups is completed at a speed of one billion bits per second (Gbps) or higher, and there is no slave controller that must execute before it The identification and the execution time window. The slave controllers execute the recipe groups immediately after the slave controller receives a pulse indicating that the slave controllers execute the recipe groups.

In one embodiment, a method for synchronizing the execution of a recipe group is described. The method includes sending a recipe set to a main controller by an instruction controller, and sending the recipe set for a subsystem controller of a plasma system to be executed by the main controller. The operation of sending the recipe group from the main controller to the subsystem controller is performed within a first clock cycle of a clock signal. The method includes generating a recipe event signal by the instruction controller and sending the recipe event signal to the subsystem controller by the instruction controller, and the recipe event signal instructs the subsystem controller to execute the recipe group. One execution time. The execution time occurs in a second clock cycle following the first clock cycle. The second clock cycle belongs to the clock signal.

In one embodiment, a method for synchronizing the execution of a recipe group is described. The method includes sending a recipe set for a subsystem controller to execute in a first clock cycle of a clock signal by a main controller. The subsystem controller is used to control a component of a plasma system. The method further includes generating a recipe event signal by the main controller and sending the recipe event signal by the main controller, the recipe event signal instructing the subsystem controller of the plasma system to execute the recipe group One execution time. The execution time of the recipe group occurs within a second clock cycle after the first clock cycle that the recipe group sends during its period. The second clock cycle belongs to the clock signal.

In one embodiment, a method for synchronizing the execution of a recipe group is described. The method includes sending a recipe set to a processor of a subsystem of a plasma system by a main controller. The steps sent from the main controller occur within a first clock cycle of a clock signal. The method further includes generating a recipe event signal by the main controller and sending the recipe event signal to the processor of the subsystem by the main controller, the recipe event signal indicating an execution time of the recipe group . The operation of sending the recipe event signal occurs within a second clock cycle following the first clock cycle.

Some of the advantages of some of the above embodiments include synchronizing the execution of recipe groups among multiple controllers. For example, the (n + 1) th recipe group is sent from one sending controller to one or more receiving controllers in a synchronized manner. After sending the (n + 1) th recipe group to the receiving controller, the sending controller or another controller provides a recipe event signal to notify the receiving controllers to start the execution of the recipe group. The time between sending the (n + 1) th recipe group and sending the recipe event signal allows the receiving controller to prepare for execution of the (n + 1) th recipe group. For example, the (n + 1) th recipe set is sent to the receiving controller within a time when a wafer is being loaded into the plasma chamber. When the recipe event signal is sent to the receiving controller, the wafer has finished loading. In addition, once the receiving controller receives the recipe event signal, the receiving controller immediately executes the recipe group to start processing the wafer.

Other advantages include the use of communication protocols with data transfer rates of gigabits or more, such as the Ethernet protocol, Universal Datagram Protocol (UDP), UDP / Internet Protocol (UDP / IP), UDP / IP / Ethernet, custom agreements, etc. The (n + 1) th formula group is embedded in a packet generated by applying a communication protocol as a payload of the packet to transmit the (n + 1) th formula group. The use of such communication protocols allows us to achieve transmission rates of billions of bits per second or higher. The use of communication protocols saves time and is more cost effective than EtherCAT protocols.

Other aspects of the present invention will be more apparent from the following detailed description accompanying the drawings.

The following embodiments describe a system and method for synchronizing the execution of a recipe group. Obviously, this embodiment can be achieved without some or all of the specific details. In other cases, in order not to cause unnecessary confusion to this embodiment, well-known processing operations are not described in detail.

FIG. 1A-1 is a diagram of an embodiment of a system 100 for illustrating synchronization performed by recipe groups performed across different subsystem controllers. The system 100 includes an instruction controller 102 located in a computing device 108. As used herein, a controller includes one or more processors and one or more memory devices. Processor as used herein means the use of a central processing unit (CPU), an application specific integrated circuit (ASIC), or a programmable logic device (PLD), and these terms are used interchangeably herein. Examples of memory devices include read-only memory (ROM), random-access memory (RAM), hard disks, volatile memory, non-volatile memory, redundant arrays of storage disks, and flash memory. Examples of the computing device 108 include a laptop computer, a desktop computer, a tablet, or a mobile phone.

The system 100 further includes a main controller 106 connected to the command controller 102 through a transmission medium 112. As used herein, examples of transmission media include coaxial cables, conductor cables, wired media, twisted pair cables, fiber optic cables, cables, Ethernet cables, wireless media, wired The combination of media and wireless media. Examples of communication protocols include Universal Datagram Protocol (UDP), UDP over Internet Protocol (UDP over IP), UDP over IP over Ethernet (UDP over IP over Ethernet), custom protocols, serial transmission Protocols, parallel transmission protocols, universal serial bus (USB) protocols, custom communication protocols, etc. Examples of serial protocols include, for example, the RS 232 protocol, the RS 422 protocol, the RS 423 protocol, and the RS 485 protocol. In various embodiments, in the case of a serial protocol, data is transmitted in a serial manner. For example, one bit is transmitted sequentially after another. An example of a side-by-side agreement is where data is transmitted side-by-side. Further, in the case of a side-by-side agreement, multiple bits are transmitted simultaneously or in a similar manner. In some embodiments herein, the terms "transmission medium" and "connection" are used interchangeably. In several embodiments herein, a tandem agreement or a side-by-side agreement is referred to as a non-packetized protocol.

The system 100 includes a subsystem controller A, a subsystem controller B, and a subsystem controller C. Subsystem controller A is connected to main controller 106 via transmission medium 110A, subsystem controller B is connected to main controller 106 via transmission medium 110B, and subsystem controller C is connected to controller 106 via transmission medium 110C.

In addition, each subsystem controller is connected to a corresponding subsystem via one or more corresponding physical media, which are referred to as physical communication media in US Patent Application No. 14 / 974,915. For example, subsystem controller A is connected to subsystem A via a dedicated physical medium, subsystem controller B is connected to subsystem B via a dedicated physical medium, and subsystem controller C is connected to subsystem C via a dedicated physical medium.

I should note that in some embodiments herein, the terms "subsystem" and "component" are used interchangeably.

Examples of subsystems include radio frequency (RF) generators, pressure subsystems, temperature subsystems, gap subsystems, airflow subsystems, cooling liquid flow subsystems, or impedance matching networks. To further illustrate, subsystem A is a radio frequency (RF) generator of x million hertz (MHz), such as 2 MHz, subsystem B is an y million hertz RF generator, and subsystem C is z megahertz. RF generator. Examples of y include 2 or 27, and examples of z include 27 or 60. In one embodiment, a kilohertz (kHz) RF generator such as 400 KHz is used instead of an x MHz RF generator.

The pressure subsystem contains multiple components such as pressure controllers, drives, motors, one or more rods, limit rings, and so on. The pressure controller is connected to the motor via a driver, and the motor is further connected to a restriction ring in the plasma chamber via one or more rods. The plasma chamber is described further below. Examples of drivers include a transistor or a group of transistors. The processor of the pressure controller sends a signal to the driver to drive the motor to rotate the rotor of the motor. The rotation of the rotor controls the amount of movement of the restriction ring via the one or more rods to further change the pressure in the plasma chamber.

In one embodiment, instead of configuring the pressure controller in the pressure subsystem, the pressure controller is an example of the subsystem controller A and the above-mentioned remaining components of the pressure subsystem are located in the pressure subsystem.

The temperature subsystem contains multiple components such as temperature controllers, drives, heaters, and so on. The temperature controller is connected to the heater via a driver. The temperature processor of the temperature controller sends a signal to the driver to generate an amount of current. The driver generates this amount of current and supplies the current to the heater. The heater generates heat to heat the plasma chamber.

In one embodiment, instead of configuring the temperature controller in the temperature subsystem, the temperature controller is an example of the subsystem controller B and the remaining components of the temperature subsystem are located in the temperature subsystem.

The gap subsystem includes multiple components such as a gap controller, a gap drive, a motor, one or more rods, and so on. The gap controller is connected to the motor via a gap driver, and the motor is connected to the upper electrode of the plasma chamber via one or more rods. The gap controller of the gap controller sends a signal to the driver to generate an amount of current that is provided to the motor to rotate the rotor of the motor. Rotation of the rotor causes one or more rods to rotate to change the gap between the upper and lower electrodes of the plasma chamber.

In one embodiment, the gap controller is an example of the subsystem controller C and the remaining components of the gap subsystem are located in the gap subsystem, rather than the gap controller being located in the gap subsystem.

The airflow subsystem contains multiple components such as airflow controllers, drives, motors, valves, pipes, one or more rods, gas sources, and so on. The gas source stores a processing gas for processing substrates (such as semiconductor wafers) in the plasma chamber, such as depositing materials thereon, sputtering materials thereon, etching, cleaning, and the like. Examples of the processing gas include an oxygen-containing gas or a fluorine-containing gas. The gas flow processor of the airflow controller sends a signal to the driver, which generates current to drive the motor. The motor is rotated to change the position of the valve in the pipe via one or more rods to further achieve a gas flow from the gas source through the pipe to the plasma chamber.

In one embodiment, instead of disposing the airflow controller in the airflow subsystem, the airflow controller is an example of the subsystem controller A and the remaining components of the airflow subsystem are located in the airflow subsystem.

In one embodiment, an electromagnetic current generated by a driver of the airflow subsystem (rather than a motor in the airflow subsystem) controls the amount of valve opening or closing of the airflow subsystem.

The cooling flow subsystem has the same components and functions in the same manner as the gas flow subsystem except that it does not use a gas source, but a source that stores the cooling liquid, and the output of the cooling flow subsystem is connected to the plasma chamber An element (such as an upper electrode, a lower electrode, an upper electrode extension, a lower electrode extension, etc.) to supply a cooling liquid to the element to cool the element.

The impedance matching network includes multiple components, such as an impedance matching controller, one or more drivers, one or more motors, one or more capacitors, one or more inductors, one or more resistors, and the like. The processor of the impedance matching controller sends a signal to one of the drivers, and the driver generates a current. The current is provided to one of the motors to rotate the rotor of the motor to further change the area between the plates of one or more capacitors to change the capacitance of the capacitor. Similarly, the processor of the impedance matching controller sends a signal to the other of the drivers, and the driver generates a current. The current is supplied to the other of the motors to rotate the rotor of the motor, to further rotate the core of one of the inductors to change the inductance of the inductor, or to change one of the inductors. The distance between the coils of the user to change the inductance. For example, the inductance of an inductor of an impedance matching network is changed by sliding the core of the inductor into or out of the coil of the inductor. The core is a motor attached to the impedance matching network to slide the core.

The command controller 102 is connected to an input device (for example, a mouse, a keyboard, a stylus pen, a touch screen, etc.) via an input / output (I / O) interface. Examples of I / O interfaces include serial ports, parallel ports, or USB ports. Once a signal is received from the user via the input device and the I / O interface, the controller 102 instructs the controller (102) to use a (n + 1) recipe set for the subsystem A to execute through the transmission medium 112, and The (n + 1) th recipe group executed by the subsystem B and the (n + 1) th recipe group executed by the subsystem C are sent to the main controller 106. For example, the controller is instructed to apply a communication protocol to generate a packet containing a (n + 1) th recipe group to be executed by subsystem A, and apply a communication protocol to generate a (n + 1) th recipe to be executed by subsystem B A packet of the group, and a communication protocol is applied to generate a packet containing the (n + 1) th recipe group to be executed by the subsystem C, and these packets are transmitted to the main controller 106 via the transmission medium 112. As another example, the instruction controller 102 sends the (n + 1) th formula group by applying a non-packetizing protocol (eg, in a side-by-side manner or in a serial manner, etc.). In some embodiments, the instruction controller simultaneously (e.g., within the same clock cycle of a clock signal, on the rising edge of the clock cycle, on the falling edge of the clock cycle, etc.) via the transmission medium 112 will simultaneously The (n + 1) th recipe group is sent to the main controller.

I should note that in various embodiments, (n + 1) is used to explain that a formula group is the next formula group to be executed compared to the n formula group previously sent, where n is greater than Or an integer equal to zero. For example, the nth recipe group is sent before the (n + 1) th recipe group is sent. The (n + 1) th recipe group is sent after the nth recipe group is sent. In some embodiments, the nth recipe group is executed when the (n + 1) th recipe group is sent.

Once the (n + 1) th recipe group of subsystems A, B, and C is received from the instruction controller 102, the main controller 106 receives a packet containing one of the (n + 1) th recipe groups To identify a target address (for example, a media access control (MAC) address, etc.) to determine the (n + 1) formula group, one of which is for subsystem A, n + 1) identifies a target address in a packet of the other of the formula group to determine the (n + 1) formula group where the other is used for the subsystem B, from which the ( n + 1) A target address is identified in a packet of the other one of the formula group to determine the (n + 1) formula group where the further one is used for the subsystem C. The main controller 106 sends the packet containing the (n + 1) th recipe group for the subsystem A to the subsystem controller A via the transmission medium 110A, and the (n + 1) recipe group for the subsystem B is sent via the transmission medium 110B. n + 1) The packet of the recipe group is sent to the subsystem controller B, and the packet containing the (n + 1) th recipe group for the subsystem C is sent to the subsystem controller C via the transmission medium 110C.

In some embodiments using non-packetized protocols, once the (n + 1) th recipe group of subsystems A, B, and C is received from the instruction controller 102, the main controller 106 1) A target address in one of the recipe groups identifies the (n + 1) recipe group. One of the (n + 1) recipe groups is used for subsystem A. From the (n + 1) recipe group, the other A target address in the (n + 1) formula group where the other one is used for the subsystem B, and a target in the (n + 1) formula group among the other The address identifies the (n + 1) th recipe group where the other one is for the subsystem C. The main controller 106 sends the (n + 1) th recipe group for the subsystem A to the subsystem controller A in parallel or in series via the transmission medium 110A, and will use it in parallel or in series via the transmission medium 110B. The (n + 1) th recipe group of the subsystem B is sent to the subsystem controller B, and the (n + 1) th recipe group for the subsystem C is sent to the subsystem in parallel or in series via the transmission medium 110C Controller C.

The (n + 1) th recipe set for subsystems A, B, and C is simultaneously (e.g., within the first clock cycle of the clock signal, etc.) sent to the corresponding sub-nodes by the main controller 106. System controllers A, B, and C. Examples of the first clock cycle include clock cycle C1, time ts, and so on. To further explain, the (n + 1) th formula group for the A, B, and C subsystems is sent during the rising or falling edge of the first clock cycle to synchronize these (n + 1) The recipe group is sent to the corresponding subsystem controllers A, B, and C. The clock signal is generated by a clock source (such as an oscillator, an oscillator with a phase locked loop, etc.).

In one embodiment, the clock signal is generated by a clock source located in the computing device 108. In this embodiment, the clock signal is sent from the clock source to the instruction controller 102, the main controller 106, the subsystem controller A, the subsystem controller B, the subsystem controller C, and / or the subsystem A , B, and C. Any controller or processor.

In one embodiment, the clock signal is generated by a clock source located outside the computing device 108 and connected to the main controller 106. In this embodiment, the clock signal is sent from the clock source to the instruction controller 102, the main controller 106, the subsystem controller A, the subsystem controller B, the subsystem controller C, and / or the subsystem A , B, and C. Any controller or processor.

In some embodiments, the clock signal is generated by a clock source located in the main controller 106. In this embodiment, the clock signal is sent from the clock source to the instruction controller 102, the processor of the main controller 106, the subsystem controller A, the subsystem controller B, the subsystem controller C, and / or Any controller or processor in subsystems A, B, and C.

Upon receiving input from the user via the input device, the controller 102 is instructed to generate a recipe event signal 104. Examples of the recipe event signal 104 include a digital output signal or an analog output signal. The recipe event signal 104 is sent from the command controller 102 to the main controller 106 via the communication medium 126 and the communication medium 120, to the subsystem controller A via the communication medium 126 and the communication medium 124 and the communication medium 122A, and via the communication medium 126 and The communication medium 124 and the communication medium 122B to the subsystem controller B, and to the subsystem controller C via the communication medium 126 and the communication medium 124 and the communication medium 122C. Examples of communication media include wires, cables, or a combination of wired and wireless media.

The recipe event signal 104 indicates the time te at which the corresponding subsystem controllers A, B, and C execute the (n + 1) th recipe group. For example, upon receiving the recipe event signal 104, the subsystem controller A executes the (n + 1) th recipe group for the subsystem A by executing the (n + 1) recipe group for the subsystem A via the connection 114A. n + 1) recipe group. In addition, upon receiving the recipe event signal 104, the subsystem controller B executes the (n + 1) th recipe group for the subsystem B by sending the recipe group for the subsystem B to the subsystem B via the connection 114B. n + 1) recipe group. Similarly, upon receiving the recipe event signal 104, the subsystem controller C executes the first recipe for the subsystem C by sending the (n + 1) th recipe group for the subsystem C to the subsystem C via the connection 114C. (n + 1) Formulation group. Corresponding subsystem controllers A, B, and C execute the (n + 1) th recipe group at a second clock cycle following the first clock cycle (for example, C2, C3, C4, C5, C6, time te, etc.). For example, the first clock cycle precedes the second clock cycle. As another example, the second clock cycle occurs after one or more clock cycles after the first clock cycle. The one or more clock cycles precede the second clock cycle. The second clock period and any clock period between the first and second clock periods belong to the clock signal.

The recipe event signal 104 is used as a trigger signal for execution, for example, the (n + 1) th recipe group is sent from the subsystem controller to the corresponding subsystem. For example, after receiving the (n + 1) th recipe group for the subsystem A, the subsystem controller A waits to receive the recipe event signal 104 from the instruction controller 102. After waiting, once the recipe event signal 104 is received, the subsystem controller A immediately sends the (n + 1) th recipe group of the subsystem A to the subsystem A. To further explain, in the same clock cycle that the subsystem controller A receives the recipe event signal 104 from the instruction controller 102, the subsystem controller A will be used for the (n + 1) th recipe group of the subsystem A via the connection 114A. Sent to subsystem A. As another example, after receiving the (n + 1) th recipe group for the subsystem A, the subsystem controller A waits to receive the recipe event signal 104 from the instruction controller 102. During the waiting time, the subsystem controller A checks the frame check sequence field (FCS field) based on a frame in the packet containing the (n + 1) th recipe group for the subsystem A. Bit while performing error checking. To further explain, the subsystem controller A calculates a sequence from the bit of the (n + 1) th recipe group stored in the payload field of the Ethernet packet, and determines whether the calculated sequence is the same as that in the FCS field. Bits match. Once a mismatch is determined, the subsystem controller A generates and sends an error flag to the main controller 106 and / or to the command controller 102. On the other hand, once a match is detected, subsystem controller A transmits the Ethernet packet from the reception buffer of subsystem controller A to the transmission buffer of subsystem controller A, and waits to receive the recipe event Signal 104. Subsystem controller A sends (eg, transmits, etc.) an Ethernet packet to subsystem A within the clock cycle of receiving the recipe event signal.

The recipe event signal 104 directs execution of the (n + 1) th recipe group. For example, at a time (eg, within a clock cycle, etc.), a subsystem controller receives a recipe event signal 104 from the instruction controller 102 or the main controller 106, and the subsystem controller sends the (n + 1) th recipe The group is sent to the corresponding subsystem for processing.

When the subsystem controller of a subsystem receives the recipe event signal 104, the processing on behalf of the recipe group is immediately started. For example, when subsystem controller A receives recipe event signal 104 from instruction controller 102 or main controller 106 at a time (e.g., a clock cycle, etc.), subsystem controller A immediately (e.g., at the same clock) Within the cycle, on the rising edge of the clock cycle, on the falling edge of the clock cycle, etc.), send the (n + 1) th recipe group of the corresponding subsystem to the subsystem for processing.

An example of a communication method between a subsystem controller and a corresponding subsystem is provided in US Patent Application No. 14 / 974,915. For example, subsystem controller A applies a communication protocol to transfer the (n + 1) th recipe group for subsystem A to subsystem A via link 114A. As another example, the subsystem controller B applies a communication protocol to transfer the (n + 1) th recipe group for the subsystem B to the subsystem B via the link 114B.

Upon receiving the (n + 1) th recipe group for a subsystem, the subsystem processes the (n + 1) th recipe group for the subsystem to facilitate processing of the substrate. For example, when subsystem A is an RF generator, a processor (eg, processor PA, etc.) of the RF generator sends a frequency and a power amount of the RF signal to the driver and amplifier of the RF signal. The driver generates a current signal from the signal received from the processor, and the amplifier amplifies the current signal to generate an amplified current signal. The amplified current signal is provided to an RF power source to generate an RF signal having the frequency and the power amount. The frequency and the amount of power are within the (n + 1) th formula group for subsystem A. As another example, when the subsystem B is a pressure subsystem, the processor of the pressure controller (for example, the processor PB, etc.) sends a signal to the driver of the pressure subsystem to drive the motor of the pressure subsystem to make the motor's The rotor rotates. The rotation of the rotor controls a movement amount of the restriction ring to further achieve the pressure amount in the plasma chamber. This amount of pressure is provided in the (n + 1) th formula group for subsystem B. As yet another example, when the subsystem C is a temperature subsystem, a temperature processor (eg, a processor PC, etc.) of the temperature controller sends a signal to a driver of the temperature subsystem to generate an amount of current. The driver generates this amount of current and supplies the current to the heater. Upon receiving the current, the heater generates heat to heat the plasma chamber to generate a temperature amount within the plasma chamber. This amount of temperature is provided in the (n + 1) th formula group for subsystem C.

As another example, when the subsystem A is a gap subsystem, the gap processor (for example, the processor PA, etc.) of the gap controller sends a signal to the driver of the gap subsystem to generate a current amount, which is provided by To the motor of subsystem A to rotate the rotor of the motor. The rotation of the rotor causes one or more rods of the subsystem A to rotate to achieve a gap amount between the upper electrode and the lower electrode. This gap amount is provided in the (n + 1) th formula group for the subsystem A. As another example, when the subsystem B is an airflow subsystem, the airflow processor (for example, the processor PB, etc.) of the airflow controller sends a signal to the driver, and the driver generates a current to drive the motor of the subsystem B. The rotor of the motor rotates to change the position of the valve to further achieve a gas flow from the gas source of subsystem B to the plasma chamber through the pipeline of subsystem B. This gas flow is provided in the (n + 1) th formula group for subsystem B.

As another example, when the subsystem C is an impedance matching network, a processor (eg, a processor PC, etc.) of the impedance matching controller sends a signal to one of the drivers of the impedance matching network to generate a current. . The current is provided to one of the motors of the impedance matching network to rotate the rotor of the motor, and the area between the plates of one or more capacitors of the impedance matching network is further changed to achieve the capacitor. Capacitor. Similarly, the processor of the impedance matching controller sends a signal to the other of the drivers of the impedance matching network to generate a current. The current is provided to the other of the motors of the impedance matching network to rotate the rotor of the motor, and the position of a magnetic core of an inductor of the impedance matching network is further changed to achieve an inductance of the inductor. The capacitors and inductors are provided in the (n + 1) th formula group for subsystem C.

I should note that although three subsystems A, B, and C are shown in FIG. 1A-1, any number of subsystems may be used in one embodiment. For example, instead of using three subsystems, use two subsystems and their corresponding two subsystem controllers. As another example, a subsystem and a subsystem controller are used.

In an embodiment, each of the instruction controller 102, the main controller 106, the subsystem controller A, the subsystem controller B, and the subsystem controller C includes a gigabit physical layer that implements a gigabit physical layer. layer) of one or more transceivers. The one or more transceivers are used to send and receive packets.

In some embodiments, the transceiver of a controller is connected to the processor of the controller.

In several embodiments, the functions described herein as being performed by a controller are performed by a processor of the controller.

In various embodiments, the recipe event signal 104 is sent to the subsystem controller A via a first transmission medium similar to the transmission medium 110A. This first transmission medium connects the instruction controller 102 to the subsystem controller A. In addition, the recipe event signal 104 is transmitted to the subsystem controller B via a second transmission medium similar to the transmission medium 110B. This second transmission medium connects the instruction controller 102 to the subsystem controller B. Similarly, the recipe event signal 104 is sent to the subsystem controller C via a third transmission medium similar to the transmission medium 110C. This third transmission medium connects the instruction controller 102 to the subsystem controller C.

In some embodiments, the subsystem controller A sends an acknowledgement of receipt of each recipe group (e.g., (n + 1) th recipe group, etc.) to the main controller 106 via the transmission medium 110A, and upon receiving the acknowledgement Then, the main controller 106 sends the confirmation to the command controller 102 via the transmission medium 112. Similarly, the subsystem controller B sends an acknowledgement of receipt of a recipe group (e.g., (n + 1) recipe group, etc.) to the main controller 106 via the transmission medium 110B, and once receiving the acknowledgement, the main control The controller 106 sends the confirmation to the command controller 102 via the transmission medium 112. In addition, the subsystem controller C sends a confirmation of receipt of a recipe group (eg, (n + 1) recipe group, etc.) to the main controller 106 via the transmission medium 110C, and once the confirmation is received, the main controller 106 sends the confirmation to the command controller 102 via the transmission medium 112.

In various embodiments, the subsystem controller sends an acknowledgement to the main controller 106 after receiving the recipe group. For example, the subsystem controller sends an acknowledgement to the master controller 106 after receiving the (n + 1) th recipe group, and the subsystem controller sends another acknowledgement to the master after receiving the (n + 2) th recipe group The controller 106, and so on.

In some embodiments, the recipe group is sent as a payload in a packet, and each recipe group is sent in a different packet. For example, the (n + 1) th recipe group is sent in the (n + 1) th packet, and the (n + 2) th recipe group is sent in the (n + 2) th packet. The (n + 2) th packet follows the (n + 1) th packet.

1A-2 is a diagram of an embodiment of a system 150. The system 150 is similar to the system 100 of FIG. 1A-1 except that the subsystems A, B, and C are not shown in the system 150. The system 150 is used to explain that the connections 110A, 110B, and 110C are connections to which a communication protocol is applied. For example, an Ethernet packet containing the (n + 1) th recipe group for subsystems A, B, and C is communicated from the main controller 106 to the corresponding subsystem controllers A, B, and C. The The subsystem controller is a slave controller.

FIG. 1B-1 is a diagram of an embodiment of the system 160 for explaining the case where the subsystem controllers A, B, and C and the main controller 106 are not received when an input signal is received from a user via an input device. Synchronization. In the first clock cycle, the main controller 106 sends the (n + 1) th recipe group for the subsystem A to the subsystem controller A via the transmission medium 110A, and will use it for the subsystem via the transmission medium 110B. The (n + 1) th recipe group of B is sent to the subsystem controller B, and the (n + 1) th recipe group for the subsystem C is sent to the subsystem controller C via the transmission medium 110C. For example, the host controller 106 applies a communication protocol to generate a packet containing the (n + 1) th recipe group for subsystem A, and at the first clock cycle (for example, at the cycle C1 of the clock signal, etc.) The packet is transmitted to the subsystem controller A via the transmission medium 110A. As another example, the host controller 106 applies a communication protocol to generate a packet containing the (n + 1) th recipe group for the subsystem B, and via the transmission medium 110B during the first clock cycle of the clock signal The packet is sent to the subsystem controller B. In addition, as another example, the host controller 106 applies a communication protocol to generate a packet containing the (n + 1) th recipe group for the subsystem C, and passes through the first clock cycle of the clock signal. The transmission medium 110C sends the packet to the subsystem controller C. As another example, the main controller 106 applies the non-packetized communication protocol to send the (n + 1) th recipe group in series or in parallel to the subsystem controller A via the transmission medium 110A, and applies the non-packetized communication protocol The (n + 1) th formula group is sent to the subsystem controller B via the transmission medium 110B in a tandem or parallel manner, and the (n + 1) ) The recipe group is sent to the subsystem controller C via the transmission medium 110C.

Upon receiving the (n + 1) th recipe group from the main controller 106, the subsystem controllers A, B, and C send the (n + 1) th recipe group to the corresponding subsystems A, B, and C First wait to receive the recipe event signal 104. The main controller 106 generates a recipe event signal 104 and sends the recipe event signal 104 to the subsystem controller A via the communication medium 162 and the communication medium 164A. In addition, the main controller 106 sends the recipe event signal 104 to the subsystem controller B via the communication medium 162 and the communication medium 164B, and sends the recipe event signal 104 to the subsystem controller C via the communication medium 162 and the communication medium 164C. . The recipe event signal 104 indicates when the subsystem controllers A, B, and C execute the (n + 1) th recipe group. The main controller 106 sends the recipe event signal 104 to the subsystem controllers A, B, and C within the second clock cycle (eg, the clock cycle C2, etc.) of the clock signal.

The time when the subsystem controllers A, B, and C execute the (n + 1) th recipe group is the time when the subsystem controllers A, B, and C autonomous controller 106 receives the recipe event signal 104. For example, during the clock cycle (eg, clock cycle C2, etc.) of the subsystem controllers A, B, and C receiving the recipe event signal 104, the subsystem controllers A, B, and C execute the (n + 1 ) Recipe group.

The subsystem controllers A, B, and C execute the (n + 1) th recipe group by sending the (n + 1) th recipe group to the corresponding subsystems A, B, and C. For example, in response to receiving the recipe event signal 104, the subsystem controller A immediately sends the (n + 1) th recipe group for the subsystem A to the subsystem A via the connection 114A. To further explain, within the clock cycle C2 of receiving the recipe event signal 104, the subsystem controller A sends the (n + 1) th recipe group for the subsystem A to the subsystem A via the connection 114A for the subsystem A for processing. As another example, in response to receiving the recipe event signal 104, the subsystem controller B immediately sends the (n + 1) th recipe group for the subsystem B to the subsystem B via the connection 114B for the subsystem B to perform deal with. To further illustrate, within the clock period C2 of receiving the recipe event signal 104, the subsystem controller B sends the (n + 1) th recipe group for the subsystem B to the subsystem B via the connection 114B. As yet another example, in response to receiving the recipe event signal 104, the subsystem controller C immediately sends the (n + 1) th recipe group for the subsystem C to the subsystem C via the connection 114C for the subsystem C For processing. To further illustrate, within the clock period C2 of receiving the recipe event signal 104, the subsystem controller C sends the (n + 1) th recipe group for the subsystem C to the subsystem C via the connection 114C.

In various embodiments, the recipe event signal 104 is sent from the main controller 106 to the subsystem controller A via the transmission medium 110A. In addition, the recipe event signal 104 is transmitted from the main controller 106 to the subsystem controller B via the transmission medium 110B, and is transmitted from the main controller 106 to the subsystem controller C via the transmission medium 110C.

FIG. 1B-2 is a diagram of an embodiment of the system 180. The system 180 is similar to the system 160 of FIG. 1B-1 except that the subsystems A, B, and C are not shown in the system 180. The system 180 is used to explain that the communication protocols are applied to the connections 110A, 110B, and 110C. For example, a packet containing the (n + 1) th recipe group for subsystems A, B, and C is communicated from the main controller 106 to the corresponding subsystem controllers A, B, and C. These subsystems The controller is a slave controller. In addition, the recipe event signal 104 is generated by the main controller 106 and sent to the subsystem controllers A, B, and C.

FIG. 1C is a diagram of an embodiment of a system 190 for illustrating synchronization of subsystems A, B, and C based on a recipe event signal received from the main controller 106. The main controller 106 is connected to the subsystem A via a transmission medium 172A, is connected to the subsystem B via a transmission medium 172B, and is connected to the subsystem C via a transmission medium 172C. In addition, the main controller 106 is connected to the subsystem A via the communication medium 192 and the communication medium 194A, is connected to the subsystem B via the communication medium 192 and the communication medium 194B, and is connected to the subsystem C via the communication medium 192 and the communication medium 194C.

The main controller 106 sends the (n + 1) th recipe set for execution and processing of subsystem A to the processor PA of subsystem A, and the (n + 1) th order for execution and processing of subsystem B The recipe group is sent to the processor PB of the subsystem B, and the (n + 1) th recipe group for the subsystem C to execute and process is sent to the processor PC of the subsystem C. For example, the main controller 106 sends the (n + 1) th recipe group for the subsystem A via the transmission medium 172A, which should use the communication protocol to generate the (n + 1) th formula for the subsystem A ) A packet of the recipe group, and send the packet to subsystem A by transmitting medium 172A. As another example, the main controller 106 sends the (n + 1) th recipe group for the subsystem B via the transmission medium 172B, which should use the communication protocol to generate the (n + 1) a packet of the recipe group, and sends the packet to subsystem B by transmitting medium 172B. As another example, the main controller 106 sends the (n + 1) th recipe group for the subsystem C via the transmission medium 172C, which should use the communication protocol to generate the (n + 1) a packet of the recipe group, and sends the packet to the subsystem C via the transmission medium 172C. As yet another example, the main controller 106 sends the (n + 1) th formula group for the subsystem A to the subsystem A via the transmission medium 172A in a serial manner or a parallel manner, in a serial manner or a parallel manner The (n + 1) th recipe group for the subsystem B is sent to the subsystem B via the transmission medium 172B, and the (n + 1) th subsystem for the subsystem C is transmitted in series or in parallel via the transmission medium 172C. + 1) The recipe group is sent to subsystem C. Sending the (n + 1) th recipe group to the subsystems A, B, and C occurs within the first clock cycle (eg, time ts, clock cycle C1, etc.) of the clock signal. For example, the (n + 1) th recipe group is sent on the rising or falling edge of the first clock cycle.

Once the (n + 1) th recipe group is received, the processors PA, PB, and PC are executing the recipe group (eg, sending the recipe group and / or parameters identified using the recipe group to the subsystems A, B, And the corresponding component of C, etc.) before waiting to receive the recipe event signal 104. For example, during the waiting time, the processor PA analyzes the packet containing the (n + 1) th recipe group for the subsystem A, and extracts the (n + 1) th recipe group from the packet to Packet decapsulation. In order to decapsulate the packets, I applied a communication protocol. In addition, the processor PA identifies the one or more parameters from a mapping relationship between one or more variables and one or more parameters in the (n + 1) th recipe group of the subsystem A. The mapping relationship between one or more variables in the (n + 1) th recipe group for the subsystem A and the one or more parameters is stored in the memory device of the subsystem A. Examples of parameters include the amount of current. Examples of variables include the frequency of the RF signal and / or the power of the RF signal, or the pressure in the plasma chamber, or the gas flow into the plasma chamber, or the temperature in the plasma chamber, or up and down The gap between the electrodes, the capacitance of the capacitor of the impedance matching network, or the inductance of the inductor of the impedance matching network. To further illustrate, the processor PA recognizes a current to be provided to the driver of the subsystem A to generate an RF signal having a power amount or a frequency. As another example, the processor PA identifies a current to be provided to the driver of the subsystem A to generate a gap amount between the upper and lower electrodes, or achieves a pressure in the plasma chamber, or achieves a pressure in the plasma chamber. A temperature in the chamber, or a gas flow into the plasma chamber, or the capacitance of the capacitor of the impedance matching network, or the inductance of the inductor of the impedance matching network.

Similarly, during the waiting time, the processor PB parses the packet containing the (n + 1) th recipe group for the subsystem B and extracts the (n + 1) th recipe group from the packet. Unpack the packet. In addition, the processor PB identifies the one or more parameters from a mapping relationship between one or more variables and one or more parameters in the (n + 1) th recipe group for the subsystem B. The mapping relationship between one or more variables in the (n + 1) th recipe group for the subsystem B and the one or more parameters is stored in the memory device of the subsystem B. Similarly, during the waiting time, the processor PC analyzes the packet containing the (n + 1) th recipe group for the subsystem C, and extracts the (n + 1) th recipe group from the packet. Unpack the packet. In addition, the processor PC identifies the one or more parameters from a mapping relationship between one or more variables and one or more parameters in the (n + 1) th recipe group for the subsystem C. The mapping relationship between one or more variables in the (n + 1) th recipe group for the subsystem C and the one or more parameters is stored in the memory device of the subsystem C.

In one embodiment, a subsystem parses a packet, retrieves the (n + 1) th recipe group from the packet, and one or more of the (n + 1) th recipe group from the retrieved The mapping relationship between the variables to identify one or more parameters is executed by the processor after receiving the recipe event signal 104, rather than within the waiting time for waiting to receive the recipe event signal 104.

In some embodiments where the non-packetization protocol is applied, the processors PA, PB, and PC are not required to perform de-packetization to parse the packet and retrieve the (n + 1) th recipe group from the packet.

The main controller 106 generates a recipe event signal 104. The recipe event signal 104 is sent from the main controller 106 to the processor PA via communication media 192 and 194A, from the main controller 106 to the processor PB via communication media 192 and 194B, and from the main controller 106 via communication media 192 and 192. 194C is sent to the processor PC.

The recipe event signal 104 indicates when the processors PA, PB, and PC execute the (n + 1) th recipe group. The execution time is the time when the processors PA, PB, and PC receive the recipe event signal 104. For example, once the recipe event signal 104 is received, the processors PA, PB, and PC immediately drive the components of the subsystem by sending signals to the corresponding drivers of subsystems A, B, and C to execute the (n + 1) Recipe group. Sending a signal to the corresponding driver is an example of the microprocessor PA, PB, and PC executing the (n + 1) th recipe group. Further, once the recipe event signal 104 is received, the processor PA immediately sends a signal to the driver of the subsystem A, so that the subsystem A generates an RF signal having a frequency and / or a power amount. This signal contains the value of a parameter determined from the mapping relationship stored in the subsystem A. As another example, the recipe event signal 104 is used as a trigger signal (eg, a start signal, etc.) to enable the processor PA to send a signal to the driver of the subsystem A, and the signal includes the signal stored in the subsystem A. The value of the parameter identified by the mapping relationship. As an example, the processor PA sends a recipe event signal 104 and / or the main controller 106 sends the recipe event signal to the same clock cycle (for example, the clock cycle C2, etc.) of the processor PA. The processor PA sends a Signal to Subsystem A's driver. This signal contains the value of a parameter identified from the mapping relationship stored in the subsystem A.

As another example, upon receiving the recipe event signal 104, the processor PB sends a signal to the driver of the subsystem B to achieve the temperature or pressure amount in the plasma chamber. This signal contains the value of a parameter determined from the mapping relationship stored in the subsystem B. As another example, the recipe event signal 104 is used as a trigger signal (for example, a start signal, etc.) to enable the processor PB to send a signal to the driver of the subsystem B, and the signal includes a signal stored in the subsystem B. The value of the parameter identified by the mapping relationship. As another example, within the same clock cycle (eg, clock cycle C2, etc.) that the processor PB receives the recipe event signal 104, the processor PB sends a signal to the driver of the subsystem B. This signal contains the value of a parameter identified from the mapping relationship stored in the subsystem B.

As another example, once the recipe event signal 104 is received, the processor PC sends a signal to the driver of the subsystem C to achieve the gap between the upper electrode and the lower electrode. This signal contains the value of a parameter determined from the mapping relationship stored in the subsystem C. As another example, the recipe event signal 104 is used as a trigger signal (eg, a start signal, etc.) to enable the processor PC to send a signal to the driver of the subsystem C, and the signal includes the self-stored signal in the subsystem C. The value of the parameter identified by the mapping relationship. As another example, within the same clock cycle (eg, clock cycle C2, etc.) that the processor PC receives the recipe event signal 104, the processor PC sends a signal to the driver of the subsystem C. This signal contains the value of a parameter identified from the mapping relationship stored in the subsystem C.

The signals from the processors PA, PB, and PC are sent to the corresponding drivers of the subsystems A, B, and C within the second clock cycle (eg, the clock cycle C2, time te, etc.). The second clock cycle follows the first clock cycle. For example, the first clock cycle precedes the second clock cycle. As another example, the second clock cycle occurs after one or more clock cycles after the first clock cycle. The one or more clock cycles precede the second clock cycle. The second clock period and any clock period between the first and second clock periods belong to the clock signal.

The recipe event signal 104 directs execution of the (n + 1) th recipe group. For example, when the processor of the subsystem receives the recipe event signal 104 from the main controller 106 (for example, within a clock cycle, etc.), the processor sends a parameter identified based on the (n + 1) th recipe group to Subsystem driver for processing. To further explain, the driver of the subsystem drives the motor to achieve the pressure in the plasma chamber, or the gas flow into the plasma chamber, or the temperature in the plasma chamber, or the gap between the upper and lower electrodes, or The signal received from the processor of the subsystem is processed by the capacitance of the capacitor of the impedance matching network or the inductance of the inductor of the impedance matching network. As another example, the driver of the RF generator processes a signal received from a digital signal processor (DSP) of the RF generator by generating a driving signal, the driving signal is used to promote a signal having a frequency and a power amount. Generation of RF signals. The RF signal is generated by the RF power of the RF generator. RF power is connected to the driver. In some embodiments, the RF power is connected to the driver via an amplifier that amplifies the current signal generated by the driver and provides the amplified current signal to the RF power. The RF power source generates an RF signal after receiving the amplified current signal.

The recipe event signal 104 received by the processor of the subsystem instructs the processor to immediately start execution of the recipe group. For example, when the processor PA receives the recipe event signal 104 from the main controller 106 at a time (for example, within a clock cycle, etc.), the processor PA immediately sends a signal (for example, within the same clock cycle, etc.) to The driver of the subsystem to achieve a variable retrieved from the (n + 1) th recipe set for subsystem A.

I should note that in some embodiments, there is no relationship between the "first clock period" described above with reference to Figs. 1A-1 and 1B-1 and the "first clock period" described above with reference to Fig. 1C of. Similarly, there is no relationship between the "second clock cycle" described above with reference to Figs. 1A-1 and 1B-1 and the "second clock cycle" described above with reference to Fig. 1C. The “first clock period” described with reference to FIG. 1C is independent of the “first clock period” described with reference to FIGS. 1A-1 and 1B-1, and similarly, the “second clock period” described with reference to FIG. 1C The "pulse cycle" is independent of the "second clock cycle" described with reference to Figs. 1A-1 and 1B-1.

In an embodiment, a transceiver of each of the subsystems A, B, and C performs reception and transmission, instead of the reception and transmission performed by the processors PA, PB, and PC as described above, and processes The controllers PA, PB, and PC perform the remaining operations described above in relation to identifying a parameter from the memory device of the subsystem based on the variables received in the (n + 1) th recipe group. The transceiver of the subsystem is connected to the processor of the subsystem. The transceiver implements the physical layer used to implement the communication protocols.

In various embodiments, the recipe event signal 104 is sent from the main controller 106 to the subsystem A via the transmission medium 172A. In addition, the recipe event signal 104 is transmitted from the main controller 106 to the subsystem B via the transmission medium 172B, and is transmitted from the main controller 106 to the subsystem C via the transmission medium 172C.

In some embodiments, the processor's PA sends an acknowledgement of receipt of each recipe group (eg, (n + 1) th recipe group, etc.) to the main controller 106 via transmission medium 172A. Similarly, Subsystem B sends an acknowledgement of receipt of the recipe group to the main controller 106 via transmission medium 172B. In addition, the subsystem C sends a confirmation of receipt of the recipe group to the main controller 106 via the transmission medium 172C.

In various embodiments, the confirmation is sent by the subsystem to the main controller 106 after receiving the recipe group. For example, the subsystem sends an acknowledgement to the main controller 106 after receiving the (n + 1) th recipe group, and the subsystem sends another acknowledgement to the main controller 106 after receiving the (n + 2) th recipe group, And so on.

FIG. 1D is a diagram of an embodiment of a system 190 for illustrating synchronization between subsystem controllers A, B, and C and subsystems A, B, and C. The processors PA, PB, and PC receive the (n + 1) th recipe group from the corresponding subsystem controllers A, B, and C in the first clock cycle (for example, cycle C1, time ts, etc.). For example, the processor PA receives from the subsystem controller A the (n + 1) th recipe group for the subsystem A, and the processor PB receives from the subsystem controller B the (n + 1) th recipe for the subsystem B Group, and the processor PC subsystem controller C receives the (n + 1) th recipe group for the subsystem C.

In some embodiments, the clock signal is from another controller (e.g., main controller 106, command controller 102 (FIG. 1A-1), etc.), or a clock source (e.g., oscillator, with phase-locked loop Oscillator, etc.) to the subsystem controllers A, B, and C such that the subsystem controllers A, B, and C to the corresponding subsystems (A, B, and C) of the (n + 1) recipe group Send synchronization. In various embodiments, the clock source is located in one of the subsystem controllers A, B, and C, and is connected to one of the subsystem controllers A, B, and C via one or more communication media. The rest.

Until receiving the recipe event signal 104 from other controllers (for example, the main controller 106, or the instruction controller 102, etc.), the processors PA, PB, and PC wait for the identification from the (n + 1) th recipe group. One or more parameters are sent to the corresponding drivers of subsystems A, B, and C. I should note that other controllers send the recipe event signal 104 to the processor PA via one or more communication media, and send the recipe event signal 104 to the processor PB via one or more communication media, and via one or more communication The medium sends the recipe event signal 104 to the processor PC. Once the recipe event signal 104 is received, the processor PA sends a signal containing parameters identified using the mapping relationship stored in the memory device of the subsystem A to the driver of the subsystem A. For example, within the second clock cycle (eg, clock cycle C2, time te, etc.) of the recipe event signal 104 received by the processor PA, the processor PA will include the identification using the mapping relationship stored in the subsystem A A signal of the parameter is sent to the driver of the subsystem A. In addition, once the recipe event signal 104 is received, the processor PB sends a signal containing the parameters identified using the mapping relationship stored in the memory device of the subsystem B to the driver of the subsystem B. For example, during the second clock cycle when the processor PB receives the recipe event signal 104, the processor PB sends a signal containing the parameters identified using the mapping relationship stored in the subsystem B to the driver of the subsystem B . Similarly, once the recipe event signal 104 is received, the processor PC sends a signal containing the parameters identified using the mapping relationship stored in the memory device of the subsystem C to the driver of the subsystem C. For example, during the second clock cycle when the processor PC receives the recipe event signal 104, the processor PC sends a signal containing the parameters identified using the mapping relationship stored in the subsystem C to the driver of the subsystem C . The recipe event signal 104 is used as a trigger signal (for example, a start signal, etc.) to enable each of the processors PA, PB, and PC to send a signal including the value of the parameter to the corresponding subsystem A, B, And C's corresponding driver.

I should note that in some embodiments, between the "first clock period" described above with reference to Figs. 1A-1 and 1B-1 or Fig. 1C and the "first clock period" described above with reference to Fig. 1D It doesn't matter. Similarly, there is no relationship between the “second clock cycle” described above with reference to FIGS. 1A-1 and 1B-1 or FIG. 1C and the “second clock cycle” described above with reference to FIG. 1D. The "first clock cycle" described with reference to Fig. 1D is independent of the "first clock cycle" described with reference to Figs. 1A-1 and 1B-1 or Fig. 1C, and similarly, the "first clock cycle" described with reference to Fig. 1D The "second clock cycle" is independent of the "second clock cycle" described with reference to Figs. 1A-1 and 1B-1 or Fig. 1C.

In some embodiments, the processor's PA sends an acknowledgement of receipt of each recipe group (eg, (n + 1) th recipe group, etc.) to the subsystem controller A via transmission medium 114A. Similarly, the processor B sends an acknowledgement of receipt of the recipe group to the subsystem controller B via the transmission medium 114B. In addition, the processor C sends an acknowledgement of receipt of the recipe group to the subsystem controller C via the transmission medium 114C.

In various embodiments, the confirmation is sent by the subsystem to a corresponding subsystem controller connected to the subsystem. Acknowledgements are sent after receiving each recipe group. For example, the processor PA of subsystem A sends an acknowledgement to subsystem controller A after receiving the (n + 1) th recipe group, and the processor PA sends another after receiving the (n + 2) th recipe group Confirm to subsystem controller A, and so on.

FIG. 1E is a diagram of an embodiment of a system 151 for illustrating synchronization between a user interface (UI) computer 153 and RF generator controllers 155A, 155B, and 155C. The UI computer 153 is an example of the computing device 108 of FIG. 1A-1. In addition, the RF generator controller 155A is an example of the subsystem controller A (Figure 1A-1), the RF generator controller 155B is an example of the subsystem controller B (Figure 1A-1), and the RF generator controller 155C is an example of the subsystem controller C (Figure 1A-1). The system 151 further includes RF generators 1, 2, and 3. RF generator 1 is labeled RFG1, RF generator 2 is labeled RFG2, and RF generator 3 is labeled RFG3. RF generator 1 is an example of an x MHz RF generator, RF generator 2 is an example of a y MHz RF generator, and RF generator 3 is an example of a z MHz RF generator.

The operation of the system 151 is described with reference to FIG. 2B. As shown in FIG. 2B, the UI computer 153 passes the host by applying an Ethernet protocol and Transmission Control Protocol (TCP) / Internet Protocol (IP), or User Datagram Protocol (UDP) / IP through a transmission medium. The (n + 1) th recipe group is sent to the master controller 106 to the master-master controller. In one embodiment, the system 151 does not include a master-to-master controller. In one embodiment, the main controller 106 performs functions performed by the main controller.

The main controller 106 applies the TCP / IP protocol, or the UDP / IP protocol, and the Ethernet protocol to send the (n + 1) -th recipe group for the RF generator 1 to the RF generator controller 155A, which will be used for The (n + 1) th recipe group of the RF generator 2 is sent to the RF generator controller 155B, and the (n + 1) th recipe group for the RF generator 3 is sent to the RF generator controller 155C. For example, referring back to FIG. 1E, the (n + 1) th recipe set for the RF generator 1 is sent from the main controller 106 to the RF generator controller 155A via the switch 157. As another example, as shown in FIG. 1E, the (n + 1) th recipe group for the RF generator 2 is sent from the main controller 106 to the RF generator controller 155B via the switch 157. As another example, as shown in FIG. 1E, the (n + 1) th recipe group for the RF generator 3 is sent from the main controller 106 to the RF generator controller 155C via the switch 157. An example of an exchanger 157 is described in US Patent Application No. 14 / 974,915.

Referring to FIG. 2B, once the (n + 1) th recipe group is received from the main controller 106, the RF generator controllers 155A, 155B, and 155C are sending the (n + 1) th recipe group to the corresponding RF generator Wait for receiving recipe event signals from UI computer 153 before 1, 2, and 3. Referring back to FIG. 1E, a signal generator 159 (eg, a digital pulse signal generator, an analog pulse signal generator, a processor, etc.) is connected to the UI computer 153 via an input / output interface (I / O). The signal generator 159 generates a general-purpose I / O (GPIO) signal such as a digital signal, an analog signal, etc., and passes through the main-to-main controller 155C and the corresponding RF generator controllers 155A, 155B, And 155C corresponding GPIO pins to provide this signal to the RF generator controllers 155A, 155B, and 155C. The GPIO signal is an example of the recipe event signal 104. In some embodiments, the signal generator 159 is located in the UI computer 153. In some embodiments, the GPIO signal is generated when the UI computer 153 receives an input (eg, selection, click, etc.) from a user via an input device. The input device is a peripheral device connected to the UI computer 153.

Referring to FIG. 2B, immediately after receiving the GPIO signal (for example, within the same clock cycle as when the GPIO signal is received, etc.), the RF generator controller 155A applies the Ethernet protocol and the UDP / IP protocol and will be used for RF The (n + 1) th recipe group of generator 1 is sent to RF generator 1, and RF generator controller 155B applies the Ethernet protocol and UDP / IP protocol and will be used for (n + 1) th of RF generator 2 The recipe group is sent to the RF generator 2, and the RF generator controller 155C sends the (n + 1) th recipe group for the RF generator 3 to the RF generator 3 by applying the Ethernet protocol and the UDP / IP protocol.

FIG. 2A-1 is an embodiment of a timing diagram 200 for illustrating synchronization between the sending of the (n + 1) th recipe group and the time when the controller executes the recipe group. Timing diagram 200 shows a sequence 202A in which the (n + 1) th packet, the (n + 2) th packet, and the (n + 3) th packet are sent from the main controller 106 to the subsystem controller A (Figure 1A-1). In addition, the timing diagram 200 shows a sequence 202B in which the (n + 1) th packet, (n + 2) th packet, and (n + 3) th packet are sent from the main controller 106 to the subsystem control Device B (Figure 1A-1). Similarly, the timing diagram 200 shows a sequence 202C in which the (n + 1) th packet, the (n + 2) th packet, and the (n + 3) th packet are sent from the main controller 106 to the subsystem Controller C (Figure 1A-1).

In an embodiment described with reference to FIG. 1C, the sequence 202A of the packet is transmitted from the main controller 106 to the subsystem A, the sequence 202B of the packet is transmitted from the main controller 106 to the subsystem B, and the sequence 202C of the packet is from the The main controller 106 sends to the subsystem C.

In an embodiment described with reference to FIG. 1D, the sequence of packets 202A is sent from subsystem controller A to subsystem A, the sequence of packets 202B is sent from subsystem controller B to subsystem B, and the sequence of packets 202C Is sent from subsystem controller C to subsystem C.

The timing diagram 200 further includes a pulse signal 204A, which is an example of the recipe event signal 104. The timing diagram 200 includes a clock signal 202, which is generated by the main controller 106, or the command controller 102, or a clock source located outside the main controller 106, or the command controller 102 (Figure 1A-1). Generated by external clock sources.

In some embodiments, the pulse at time te1 of the pulse signal 204A is an example of the recipe event signal 104.

At time ts1, one or more controllers as described herein send the (n + 1) th packet for subsystems A, B, and C. At execution time te1, a digital pulse is received by one or more controllers as described herein to instruct execution of the (n + 1) th packet. In addition, at time ts2 (which coincides with time te1), one or more controllers as described herein send the (n + 2) th packet for subsystems A, B, and C. At execution time te2, a digital pulse is received by one or more controllers as described herein to instruct one or more controllers as described herein to execute the (n + 2) th packet. In addition, at time ts3 (which coincides with time te2), one or more controllers as described herein send the (n + 3) th packet for subsystems A, B, and C. At execution time te3, a digital pulse is received by one or more controllers as described herein to instruct the one or more controllers to execute the (n + 3) th packet.

In some embodiments, the processor (eg, the processor PA, or the processor PB, or the processor PC, etc.) is located in the controller.

I should note that time ts1 occurs during the first clock cycle C1 of the clock signal 202, time te1 and ts2 occur during the second clock cycle C2 of the clock signal 202, and time te2 and ts3 occur during The clock signal 202 is within the third clock period C3, and the time te3 occurs within the fourth clock period C4 of the clock signal 202.

I should also note that in some embodiments, the first clock cycle described with reference to each of FIGS. 1A-1, 1B-1, 1C, and 1D is the first clock described with reference to FIG. 2A-1 Paradigm of the cycle. In addition, in these embodiments, the second clock cycle described with reference to each of FIGS. 1A-1, 1B-1, 1C, and 1D is an example of the second clock cycle described with reference to FIG. 2A-1. .

I should note that in various embodiments, the sizes of the packets shown in Figure 2A-1 are different. For example, the payload of the (n + 1) th packet in the sequence 202A of subsystem A may have a smaller or larger size than the payload of the (n + 1) th packet in the sequence 202B of subsystem B . In addition, the payload of the (n + 1) th packet in the sequence 202B of subsystem B may have a smaller or larger size than the payload of the (n + 1) th packet in the sequence 202C of subsystem C .

FIG. 2A-2 is a diagram of an embodiment of a timing diagram 210, which is used to explain that the time when the controller executes a packet changes from the time when the controller receives the packet to a digital pulse indicating a later time when a packet to be executed has been received. The digital pulse belongs to a digital pulse signal 212, and the digital pulse signal is an example of the recipe event signal 104. In some embodiments, the pulse at time te1 of the pulse signal 212 is an example of the recipe event signal 104.

As shown in the timing diagram, the execution time te2 shown in FIG. 2A-2 occurs before the execution time te2 shown in the timing diagram 200 (FIG. 2A-1). For example, the execution time te2 shown in FIG. 2A-2 does not coincide with the time ts3 and occurs before the time ts3. As another example, the execution time te2 occurs between the time when the (n + 2) th packet is received and the end of the (n + 3) th packet.

In some embodiments, the execution time te1 shown in FIG. 2A-2 occurs before the execution time te1 shown in the timing diagram 200 (FIG. 2A-1). For example, the execution time te1 shown in FIG. 2A-2 does not coincide with the time ts2 and occurs before the time ts2. As another example, the execution time te1 occurs between the time when the (n + 1) th packet is received and the end of the (n + 2) th packet.

In some embodiments, the digital pulses of the pulse signal 212 are sent within a predetermined time interval after receiving the receipt confirmation of the recipe groups from all the controllers that have received the recipe groups. For example, a digital pulse of the pulse signal 212 is sent between receiving the confirmation of the (n + 1) th recipe group and receiving the confirmation of the (n + 2) th recipe group. To further explain, at the time te1 within the predetermined time interval after the receipt confirmation of the (n + 1) th recipe group is received from the subsystem controllers A, B, and C via the main controller 106, the controller 102 is instructed to modify the recipe The first digital pulse of the event signal 104 is sent to the main controller 106. The subsystem controllers A, B, and C receive the (n + 1) th recipe group from the main controller 106. Receipt confirmation of the (n + 1) recipe group is sent from the subsystem controllers A, B, and C to the main controller 106, and the master controller 106 sends the receipt confirmation of the (n + 1) recipe group to the command control器 102。 102. To further explain, the receipt confirmation of the recipe group is sent from the subsystem controller A to the main controller 106 via the transmission medium, and the main controller 106 sends the confirmation to the instruction controller 102 via the transmission medium 112. In addition, at the time te2 within the predetermined time interval after the receipt confirmation of the (n + 2) th recipe group is received from the subsystem controllers A, B, and C via the main controller 106, the controller 102 is instructed to set the recipe event The second digital pulse of the signal 104 is sent to the main controller 106. The subsystem controllers A, B, and C receive the (n + 2) th recipe group from the main controller 106. Receipt confirmation of the (n + 2) recipe group is sent from the subsystem controllers A, B, and C to the main controller 106, and the master controller 106 sends the receipt confirmation of the (n + 2) recipe group to the command control器 102。 102. In some embodiments, the receipt confirmation of the recipe group is sent from the subsystem controller A to the command controller 102 via the communication media 122A, 124, and 126, and the receipt confirmation of the recipe group is from the subsystem controller B via the communication medium 122B. , 124, and 126 are sent to the instruction controller 102, and the receipt confirmation of the recipe group is sent from the subsystem controller C to the instruction controller 102 via the communication media 122C, 124, and 126.

For another example, at the time te1 within the predetermined time interval after the receipt confirmation of the (n + 1) th recipe group is received from the subsystem controllers A, B, and C, the main controller 106 sends the recipe event signal 104 The first digital pulse is sent to the subsystem controllers A, B, and C. In addition, at the time te2 within the predetermined time interval after receiving the confirmation of the (n + 2) th recipe group from the subsystem controllers A, B, and C, the main controller 106 sets the second digit of the recipe event signal 104 Pulses are sent to subsystem controllers A, B, and C. In some embodiments, the acknowledgement is sent to the master controller 106 via a transmission medium connecting the subsystem controller to the master controller 106. In various embodiments, the confirmation slave subsystem controller is sent to the master controller 106 via one or more communication media connecting the subsystem controller to the master controller 106. As another example, at the time te1 within the predetermined time interval after the receipt confirmation of the (n + 1) th recipe group is received from the processors PA, PB, and PC, the main controller 106 sends the first A digital pulse is sent to the processors PA, PB, and PC. In addition, at the time te2 within the predetermined time interval after receiving the confirmation of the (n + 2) th recipe group from the processors PA, PB, and PC, the main controller 106 pulses the second digital pulse of the recipe event signal 104 Send to processors PA, PB, and PC. In some embodiments, the acknowledgement is sent to the master controller 106 via a transmission medium connecting the subsystem to the master controller 106. In various embodiments, the confirmation slave subsystem is sent to the master controller 106 via one or more communication media connecting the subsystem to the master controller 106. As yet another example, at the time te1 within the predetermined time interval after the receipt confirmation of the (n + 1) th recipe group is received from the processor, the subsystem controller sends the first digital pulse of the recipe event signal 104 to The processor of the subsystem. In addition, at the time te2 within the predetermined time interval after the receipt confirmation of the (n + 2) th recipe group is received from the processor, the subsystem controller sends the second digital pulse of the recipe event signal 104 to the subsystem for processing Device.

In some embodiments, the predetermined time interval is received from a user via an input device. For example, the predetermined time interval is a time interval between receipt confirmation of receipt of two consecutive packets (for example, (n + 1) th packet and (n + 2) th packet, etc.).

In various embodiments, the digital pulses of the pulse signal 212 are sent from a sending controller based on a predetermined amount of time required to send a recipe set from the sending controller to the corresponding one or more receiving controllers, and The sending controller does not need to receive one or more acknowledgements from the one or more receiving controllers. The one or more receiving controllers are connected to the transmitting controller. For example, a user specifies a sending controller via an input device, specifying that a predetermined amount of time required to communicate a recipe from the sending controller to the one or more receiving controllers is x units (e.g., x microseconds, or x milliseconds, or x nanoseconds, etc.). After each x unit, the transmitting controller sends a pulse of the pulse signal 212 to the one or more receiving controllers. An example of the sending controller is the command controller 102 when the one or more receiving controllers are the subsystem controllers A, B, and C. Another example of the sending controller is the main controller 106 when the one or more receiving controllers are the subsystem controllers A, B, and C. Yet another example of the sending controller is the main controller 106 when the one or more receiving controllers are processors PA, PB, and PC.

In various embodiments, the predetermined amount of time required to send a recipe group from the sending controller to one or more receiving controllers is determined by the sending controller during a learning procedure. For example, the sending controller sends packets of various sizes (for example, recipe groups with different bits as payload, etc.) to one or more receiving controllers. The transmission controller determines a maximum amount of time required to transmit the largest packet among packets of various sizes, and determines the maximum amount of time as a predetermined amount of time.

In several embodiments, the time te2 is between the time ts3 and the time when the (n + 2) th packet is received by one or more receiving controllers.

FIG. 2B is a timing diagram 230 described above with reference to FIG. 1E.

FIG. 3A is a diagram of an embodiment of an Ethernet packet 300. The Ethernet packet 300 includes a preamble field, a start of frame delimiter field, a destination media access control (MAC) address field, Source MAC address field, Ethernet type field, payload field, frame check sequence (FCS) field, and packet gap. The preceding text and frame start delimiter are filled in to indicate the start of the Ethernet frame. The Ethernet frame includes a destination MAC address field, a source MAC address field, an Ethernet type field, a payload field, and an FCS field.

The MAC target address field contains an address that uniquely identifies a network interface (for example, the network interface of the main controller 106 or the network of the subsystem controller A) to which the Ethernet packet 300 is to be received. Road interface, or the network interface of subsystem controller B, or the network interface of subsystem controller C, or the network interface of subsystem A, or the network interface of subsystem B, or the network of subsystem C Interface, etc.). Examples of the network interface include a network interface controller, a network interface card, and the like.

The network interface of the host controller 106 is connected to one or more transmission media and to a processor of the host controller 106. For example, the network interface of the main controller 106 is connected to the transmission media 110A, 110B, and 110C (FIG. 1A-1). As another example, the network interface of the main controller 106 is connected to the transmission media 164A, 164B, and 164C (FIG. 1B-1). As yet another example, the network interface of the main controller 106 is connected to the transmission media 172A, 172B, and 172C (FIG. 1C).

Similarly, the network interface of the subsystem controller is connected to one or more transmission media and to the processor of the subsystem controller. For example, the network interface of subsystem controller A is connected to transmission media 110A and 114A (Figure 1A-1), the network interface of subsystem controller B is connected to transmission media 110B and 114B (Figure 1A-1), and The network interface of the system controller C is connected to the transmission media 110C and 114C (Figure 1A-1).

In addition, the network interface of the subsystem is connected to one or more transmission media and to the processor of the subsystem. For example, the network interface of subsystem A is connected to transmission medium 114A (Figure 1A-1), the network interface of subsystem B is connected to transmission medium 114B (Figure 1A-1), and the network interface of subsystem C is connected to Transmission medium 114C (Figure 1A-1). As another example, the network interface of subsystem A is connected to transmission medium 172A (Figure 1C), the network interface of subsystem B is connected to transmission medium 172B (Figure 1C), and the network interface of subsystem C is connected to transmission Medium 172C (Figure 1C).

In one embodiment, the network interface is implemented by a controller (e.g., main controller 106, or subsystem controller A, or subsystem controller B, or subsystem controller C, or processing) described herein. Processor PA, or processor PB, or processor PC, etc.).

The MAC source address field contains a location that uniquely identifies a network interface that sends the Ethernet packet 300. The Ethernet type field contains data to indicate either the protocol encapsulated in the payload (for example, Internet Protocol Version 4, Apple Talk ™, etc.) or the length of the payload. The payload field can hold one or more recipe groups (e.g. (n + 1) recipe group, (n + 2) recipe group, (n + 3) recipe group, etc.) with different numbers of bits ( Such as between 42 and 1500 bytes). The FCS field is used to check the integrity of the frame. The packet gap is the idle time between two consecutive packets.

FIG. 3B is a diagram illustrating an embodiment of a packet 320 (eg, a datagram, etc.). The packet 320 includes a header field and a payload field (for example, a field including a formula group, etc.). The header field contains fields for identification of the source address (for example, the location of the network interface from which the packet 320 was sent, etc.), and for the destination address (of the network interface designated to receive the packet 320). Position), a field for the combined length of the header and the payload attached to the header, and a field for the checksum vaule.

In various embodiments, the packet 320 is customized (eg, generated by using a customized communication protocol, etc.) to exclude the source address field used to identify the source address, and to identify the target The destination address field of the address. In point-to-point communication, there is no need to identify the source and destination addresses. This exclusion increases the data rate between the main controller 106 and the subsystem controller connected to the main controller 106, or the data rate between the subsystem controller and the subsystem connected to the subsystem controller, or the main controller Data rate between the controller and the subsystem connected to the main controller.

In some embodiments, the header is customized (e.g., generated by using a customized communication protocol, etc.) to exclude fields for checking the sum value, and / or for header and payload Combine length fields. This exclusion increases the data rate between the main controller 106 and the subsystem controller connected to the main controller 106, or the data rate between the subsystem controller and the subsystem connected to the subsystem controller, or the main controller Data rate between the controller and the subordinates connected to the main controller.

In various embodiments, the checksum value is generated by the network interface that sends the packet 320. The check sum value is generated by the payload of the packet 320, the header of the packet 320, or a combination thereof. Compare the checksum value with another checksum value calculated by the receiver of the packet 320 (eg, the target network interface, etc.) to determine whether the payload and / or header of the packet 320 is on the sending network interface Changes during transmission to the receiving network interface.

In some embodiments, the datagram (eg, UDP datagram, etc.) is embedded in the IP packet, and the IP packet is further embedded in the Ethernet packet.

In various embodiments, the packet 320 is customized (e.g., generated by using a customized communication protocol, etc.) such that the columns are located at different positions than shown in FIG. 3B. For example, the field for payload precedes the field for length. As another example, the field of the destination address is before the field of the source address or after the length of the field. Customized protocols are applied by the physical layer that generates one or more customized packets.

FIG. 4 is a diagram of an embodiment of a plasma processing system 400. The plasma processing system 400 includes a main controller 106, an x MHz RF generator, a y MHz RF generator, a z MHz RF generator, a subsystem controller A, a subsystem controller B, and a subsystem controller C. In addition, the plasma processing system 400 includes an impedance matching network 402 and a plasma chamber 404.

In one embodiment, a RF generator of kHz is used instead of an x MHz RF generator.

Once the (n + 1) th recipe group is received, the x MHz RF generator generates an RF signal. For example, the RF signal generated by the x MHz RF generator has an amount of power and / or frequency specified in the (n + 1) th recipe group received by the x MHz RF generator. Similarly, once the (n + 1) th recipe group is received, the y MHz RF generator generates an RF signal, and once the (n + 1) th recipe group is received, the z MHz RF generator generates an RF signal. For example, the RF signal generated by the y MHz RF generator has a power amount and / or a frequency amount specified in the (n + 1) th recipe group received by the y MHz RF generator. As another example, the RF signal generated by the z MHz RF generator has a power amount and / or a frequency amount specified in the (n + 1) th recipe group received by the z MHz RF generator. The RF signals are provided to the impedance matching network 402 via corresponding RF cables 406A, 406B, and 406C. The impedance matching network 402 matches the impedance of a load connected to the output of the impedance matching network 402 with the impedance of a source connected to one or more input terminals of the impedance matching network 402 to generate a modified RF signal. For example, the impedance matching network 402 matches the impedance of the plasma chamber 404 and the RF transmission line 408 with the impedance of the RF cables 406A, 406B, and 406C, the x MHz RF generator, the y MHz RF generator, and the z MHz RF generator match.

The modified RF signal is sent to the lower electrode 410 of the plasma chamber 404 via the RF transmission line 408. The lower electrode 410 is part of a chuck (for example, an electrostatic chuck (ESC) or the like). The upper electrode 412 of the plasma chamber 404 faces the lower electrode 410 and is located opposite to the lower electrode. Each of the upper electrode 412 and the lower electrode 410 is made of metal, such as aluminum, aluminum alloy, or the like.

When the process gas is supplied to the plasma chamber 404 and the modified RF signal is supplied to the lower electrode, the plasma is excited or maintained in the plasma chamber 404 to process the wafer 416 placed on the upper surface of the lower electrode 410 .

FIG. 5 is a diagram of an embodiment of a system for describing subsystem 500 (eg, subsystem A, or subsystem B, or subsystem C, etc.). The subsystem 500 includes a processor 502 (for example, a processor PA, or a processor PB, or a processor PC, etc.). The processor 502 is connected to a driver 504 (eg, one or more transistors, one or more current generating devices, etc.). The driver is connected to a mechanical or electrical component 506. Examples of the component 506 include a motor or an amplifier.

When the subsystem 500 is an RF generator, the component 506 includes an amplifier connected to an RF power source. In addition, when the subsystem 500 is a pressure subsystem, or a gap subsystem, or an airflow subsystem, or a cooling liquid flow subsystem, the component 506 is a motor.

The processor 502 generates a signal provided to the driver 504. Upon receiving the signal from the processor 502, the driver 504 generates a driving signal, which is provided to the component 506 to operate the component 506. When the component 506 is a motor, the motor controls the amount of opening or closing of the valve of the cooling flow subsystem, or the amount of opening or closing of the valve of the air flow subsystem, or the opening or closing of the limit ring, or the upper electrode 412 (Fig. 4) The amount of gap with the lower electrode 410 (FIG. 4). When the component 506 is a heater, the heater is heated when the driver 504 supplies a current signal to the heater. When the component 506 is an amplifier, once the current signal is received from the driver 504, the amplifier generates an amplified signal, and the amplified signal is provided to an RF power source to generate an RF signal.

FIG. 6 is a diagram of an embodiment of a system for explaining a plasma chamber 626, which is an example of a plasma chamber 404 (FIG. 4). The system includes a plasma reactor 620 and an RF transmission line 624, which is an example of an RF transmission line 408 (FIG. 4). The RF transmission line 624 is connected to the plasma reactor 620. The RF transmission line 624 includes an RF rod 661 and an RF channel 662. The RF rod 661 is used to facilitate transmission of the modified RF signal received from the impedance matching network 402 (FIG. 4).

The plasma reactor 620 includes a plasma chamber 626 and an RF tube 610, which is connected to an RF rod 661 via an RF band 668. The plasma reactor 620 further includes RF bands 674 and 677, a ground shield 680, and a bottom electrode housing 676.

The plasma chamber 626 includes an upper electrode 660, an upper electrode extension 628, a C-shaped shield 670, a ground ring 672, and a chuck assembly. The chuck assembly includes a chuck 658 and a facility board 630. The upper electrode 660 is an example of the upper electrode 412 (FIG. 4). The substrate 416 is placed on top of the chuck 658 to process the substrate 416. Examples of processing the substrate 416 include cleaning the substrate 416, or etching the substrate 416, or etching the oxide on the top of the substrate 416, or depositing a material (e.g., oxide, dioxide, photoresist material, etc.) on the substrate 416, or Its combination.

The C-shaped shield 670 includes a slit for controlling the pressure in the plasma chamber 626. For example, opening the slit to increase the gas flow through the slit to reduce the gas pressure in the gap 671 of the plasma chamber 626. The slit is closed to reduce the gas flow to increase the gas pressure in the gap 671.

In various embodiments, the bottom electrode housing 676 may be of any shape, such as cylindrical, square, polygonal, and the like.

In various embodiments, the RF tube 610 is not a cylinder and has a polygonal shape, such as a rectangular shape, a square shape, and the like.

The upper electrode extension 628 surrounds the upper electrode 660. The C-shaped shield 670 includes C-shaped shield portions 670A and 670B. The ground ring 672 includes a ground ring portion 672A and another ground ring portion 672B. The bottom electrode case 676 includes a bottom electrode case portion 676A, another bottom electrode case portion 676B, and still another bottom electrode case portion 676C. Each of the bottom electrode case portions 676A and 676B forms a side wall of the bottom electrode case 676. The bottom electrode case 676C forms a bottom wall of the bottom electrode case 676. The ground shield 680 includes a shield portion 680A and another shield portion 680B.

The top surface of the chuck 658 faces the bottom surface 636 of the upper electrode 660. The plasma chamber 626 is surrounded by the upper electrode 660 and the upper electrode extension 628. The plasma chamber 626 is further surrounded by a C-shaped shield 670 and a chuck 658.

The ground ring 672 is located below the C-shaped shield 670. In some embodiments, the ground ring 672 is located below and adjacent to the C-shaped shield 670. The return RF band 674 is connected to the ground loop portion 672A, and the return RF band 677 is connected to the ground loop portion 672B. The return RF band 674 is connected to the bottom electrode case portion 676A, and the return RF band 677 is connected to the bottom electrode case portion 676B. The bottom electrode case portion 676A is connected to the shield portion 680A, and the bottom electrode case portion 676B is connected to the shield portion 680B. The shielding portion 680A is connected to the RF channel 662 via the bottom electrode case portion 676A, and the shielding portion 680B is connected to the grounded RF channel 662 via the bottom electrode case portion 676C.

In some embodiments, the bottom electrode housing portion 676 is a cylinder surrounding the RF barrel 610. The RF tube 610 is a medium for passing the modified RF signal. The modified RF signal is supplied to the lower electrode of the chuck 658 via the RF rod 661, the RF band 668, and the RF barrel 610 to generate or maintain a plasma within the gap 671 of the plasma chamber 626. The gap 671 is formed between the upper electrode 660 and the lower electrode of the chuck 658.

In some embodiments, the upper electrode 660 is grounded.

In various embodiments, instead of the RF band 668, some RF bands are used to connect the RF barrel 610 to the RF rod 661.

In one embodiment, instead of providing a C-shield 670, a restriction ring is provided to control the gas exit from the plasma chamber 626 to further control the pressure within the plasma chamber 626.

I should note that in some of the above embodiments, the modified RF signal is provided to the lower electrode 410 (FIG. 4), and the upper electrode 412 (FIG. 4) is grounded. In various embodiments, the modified RF signal is provided to the upper electrode 412, and the lower electrode 410 is grounded.

In one embodiment, the functions described herein as being performed by one processor are performed by multiple processors, such as being distributed among multiple processors.

In one embodiment, the functions described herein as being performed by a controller are performed by multiple controllers, such as being distributed among multiple controllers.

In some embodiments, functions described herein as being performed by multiple controllers are performed by a controller.

The embodiments described herein can be implemented in a variety of computer system architectures, including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, microcomputers, mainframe computers, and similar Device. The embodiments described herein can also be implemented in a decentralized computing environment, where tasks are performed by remote processing hardware units connected via a computer network.

In some implementations, the controller is part of the system, which may be part of the above example. The system includes semiconductor processing equipment, which includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing elements (substrate base, airflow system, etc.) . The system is integrated with electronic equipment to control the operation of the system before, during, and after semiconductor wafer or substrate processing. Electronic equipment can be called a "controller", which can control various elements or sub-parts of the system. Depending on the processing needs and / or type of the system, the controller can be programmed to control any process disclosed herein, including: process gas delivery, temperature setting (e.g., heating and / or cooling), pressure setting, vacuum setting , Power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, access tools, and other transfer tools, and / or load locks connected or interfaced with the system The substrate of the chamber is transferred.

Broadly speaking, in various embodiments, the controller is defined as an electronic device that has various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, and enables Cleaning operations, enabling endpoint measurements, etc. An integrated circuit can include a chip in the form of firmware that stores program instructions, a digital signal processor (DSP), a chip defined as a special application integrated circuit (ASIC), a programmable logic device (PLD), one or more microchips A processor, or a microcontroller that executes program instructions, such as software. Program instructions are instructions communicated to the controller in the form of various individual settings (or program files). These settings define the operating parameters used to perform processes on or to the semiconductor wafer. In some embodiments, the operating parameters are part of a recipe defined by a process engineer to one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafers One or more processing steps are completed during the fabrication of the die.

In some implementations, the controller is part of or connected to a computer that is integrated with the system, connected to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be in whole or in part in a "cloud" or factory host computer system, which may allow remote access to substrate processing. The computer allows remote access to the system to monitor the current progress of manufacturing operations, check the history of past manufacturing operations, check trends or performance metrics from multiple manufacturing operations, change the parameters of the current process, and set the process after the current operation Steps, or start a new process.

In some embodiments, a remote computer (such as a server) can provide process recipes to the system via a network, which can include a local area network or the Internet. The remote computer may include a user interface that allows entry or programming of parameters and / or settings that are then passed from the remote computer to the system. In some examples, the controller receives instructions in a set form to process the wafer. I should understand that the settings are specific to the type of process that will be performed on the wafer, and the type of tool with which the controller interfaces or controls it. Therefore, as described above, the controllers can be decentralized, for example, by including one or more decentralized controllers that are connected together by a network and work toward a common purpose (e.g., to complete the processes described herein). ). An example of a decentralized controller for these purposes includes one or more integrated circuits on a chamber that communicate with one or more integrated circuits that are located remotely (such as at the platform level or as part of a remote computer) Circuitry that combines to control the processes in the chamber.

In various embodiments, without limitation, the system includes a plasma etching chamber, a deposition chamber, a spin-rinsing chamber, a metal plating chamber, a cleaning chamber, a beveled etching chamber, and a physical vapor phase. Deposition (PVD) chamber, chemical vapor deposition (CVD) chamber, atomic layer deposition (ALD) chamber, atomic layer etching (ALE) chamber, ion implantation chamber, orbital chamber, and any associated or Other semiconductor processing systems used in semiconductor wafer manufacturing and / or production.

I should also note that although the above operation is described with reference to a parallel plate plasma chamber, such as a capacitive coupling plasma chamber, etc., in some embodiments, the above operation is applicable to other types of plasma chambers, such as A plasma chamber including an inductively coupled plasma (ICP) reactor, a transformer coupled plasma (TCP) reactor, a conductor tool, a dielectric tool, and a plasma chamber including an electron cyclotron resonance (ECR) reactor ,Wait. For example, x MHz RF generator, y MHz RF generator, and z MHz RF generator are connected to an inductor in an ICP plasma chamber via an impedance matching network.

As described above, depending on the processing steps to be performed by the tool, the controller can communicate with one or more other tool circuits or modules, other tool components, group tools, other tool interfaces, adjacent tools, adjacent tools , Tools located throughout the factory, a host computer, another controller, or tools for material transfer that carry containers of wafers into and out of the tool location and / or loading in a semiconductor production plant port.

After understanding the above embodiments, I should understand that some of these embodiments use operations performed by various computers, where the operations involve data stored in a computer system. These computers perform operations that manipulate physical quantities.

Some of these embodiments also pertain to hardware units or devices used to perform these operations. These devices are specially constructed for special purpose computers. When it is defined as a special-purpose computer, while the computer can still perform special purposes, it can also perform other processing, program execution, or routine procedures for non-special-purpose parts.

In some embodiments, the operations described herein are performed by a computer, wherein the computer is selectively activated or configured by one or more computer programs stored in computer memory or obtained through a network. When data is obtained through a computer network, the data is processed by other computers on the computer network, such as cloud computing resources.

One or more embodiments described herein may also be made as computer-readable code on a non-transitory computer-readable medium. The non-transitory computer-readable medium is any data storage hardware unit (eg, a memory device, etc.) that can store data, and the data storage hardware unit can be read by a computer system afterwards. Examples of non-transitory computer-readable media include hard drives, network-attached storage (NAS), ROM, RAM, CD-ROMs, CD-Rs, CD-RWs, magnetic tapes, and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer-readable medium includes computer-readable tangible media, wherein the computer-readable tangible media is distributed through a computer system connected to a network, so that the computer-readable code is distributed. Way to store and execute.

Although some of the method operations described above are described in a specific order, I should understand that in various embodiments, other task operations can be performed between method operations, or method operations can be adjusted so that they occur at slightly different times, or It is decentralized in a system that allows method operations to occur in different intervals, or to be performed in a different order than described above.

I should also note that in some embodiments, one or more features of any of the above embodiments may be combined with one or more features of any other embodiment without exceeding the description of the various embodiments described in this disclosure. Range.

Although the foregoing embodiments have been described in detail for the purpose of clear understanding, it is obvious that certain changes and modifications can be implemented within the scope of the accompanying patent application. Therefore, the embodiments of the present invention should be considered as illustrative and not restrictive, and the embodiments of the present invention are not limited to the details provided herein, but can be within the scope and equality of the scope of the accompanying patent application. Modify it in-kind.

100‧‧‧ system

102‧‧‧Command Controller

104‧‧‧ Recipe event signal

106‧‧‧Main controller

108‧‧‧ Computing Device

110A‧‧‧Transmission Media

110B‧‧‧Transmission Media

110C‧‧‧Transmission Media

112‧‧‧ Transmission media

114A‧‧‧Connection

114B‧‧‧ Connection

114C‧‧‧ Connection

120‧‧‧ communication media

122A‧‧‧communication media

122B‧‧‧communication media

122C‧‧‧communication media

124‧‧‧ communication media

126‧‧‧communication media

150‧‧‧System

151‧‧‧System

153‧‧‧User interface (UI) computer

155A‧‧‧RF generator controller

155B‧‧‧RF generator controller

155C‧‧‧RF generator controller

157‧‧‧exchanger

159‧‧‧Signal generator

160‧‧‧System

162‧‧‧communication media

164A‧‧‧communication media

164B‧‧‧communication media

164C‧‧‧communication media

172A‧‧‧Transmission Media

172B‧‧‧Transmission Media

172C‧‧‧Transmission Media

180‧‧‧System

190‧‧‧System

192‧‧‧communication media

194A‧‧‧communication media

194B‧‧‧communication media

194C‧‧‧communication media

200‧‧‧ timing diagram

202‧‧‧clock signal

202A‧‧‧Sequence

202B‧‧‧ sequence

202C‧‧‧Sequence

204A‧‧‧pulse signal

210‧‧‧ timing diagram

212‧‧‧pulse signal

230‧‧‧Function Diagram

300‧‧‧ Ethernet Packet

320‧‧‧ packets

400‧‧‧ system

402‧‧‧Impedance matching network

404‧‧‧plasma chamber

406A‧‧‧RF cable

406B‧‧‧RF cable

406C‧‧‧RF cable

408‧‧‧RF transmission line

410‧‧‧lower electrode

412‧‧‧up electrode

416‧‧‧ substrate

500‧‧‧ subsystem

502‧‧‧ processor

504‧‧‧Drive

506‧‧‧ Parts

620‧‧‧plasma reactor

624‧‧‧RF transmission line

626‧‧‧ Plasma Chamber

628‧‧‧upper electrode extension

630‧‧‧facility board

636‧‧‧ bottom surface

658‧‧‧chuck

660‧‧‧RF tube

661‧‧‧RF rod

662‧‧‧RF channel

668‧‧‧RF band

670‧‧‧C-shaped shield

670A ‧‧‧C-shaped shield part

670B ‧‧‧C-shaped shield part

671‧‧‧Gap

672‧‧‧ ground ring

672A‧‧‧Ground ring part

672B‧‧‧Ground ring part

674‧‧‧Return to RF band

676‧‧‧ bottom electrode housing

676A‧‧‧Bottom electrode housing part

676B‧‧‧Bottom electrode housing part

676C‧‧‧Bottom electrode housing part

677‧‧‧Return to RF band

680‧‧‧ ground shield

680A‧‧‧Ground shield

680B‧‧‧Ground shield

The invention can best be understood with reference to the following detailed description taken in conjunction with the accompanying drawings.

FIG. 1A-1 is a diagram of an embodiment of a system for illustrating synchronization performed by recipe groups performed across different subsystem controllers.

FIG. 1A-2 is a diagram of an embodiment of a system similar to the system of FIG. 1A-1.

FIG. 1B-1 is a diagram of an embodiment of a system for explaining synchronization between a subsystem controller and a main controller without receiving an input signal from a user via an input device.

FIG. 1B-2 is a diagram of an embodiment of a system similar to the system of FIG. 1B-1.

FIG. 1C is a diagram of an embodiment of a system for explaining synchronization of a subsystem according to a recipe event signal received from a main controller.

FIG. 1D is a diagram of an embodiment of a system for explaining synchronization between a subsystem controller and a subsystem.

FIG. 1E is a diagram of an embodiment of a system for explaining a user interface (UI) computer to achieve synchronization between a main controller and an RF generator controller.

FIG. 2A-1 is an example of a timing chart for illustrating synchronization between the time when the (n + 1) th recipe group is sent to the controller and the controller executes the recipe group.

FIG. 2A-2 is a diagram of an embodiment of a timing diagram, which is used to explain that the time when the controller executes a packet varies between the time when the controller receives the packet and the later time when a digital pulse is received, the digital pulse indicates the reception To the pending packet.

FIG. 2B is a timing diagram for explaining the operation of the system of FIG. 1E.

FIG. 3A is a diagram of an embodiment of an Ethernet packet.

According to an embodiment described in this disclosure, FIG. 3B is a diagram for explaining a packet.

FIG. 4 is a diagram of an embodiment of a plasma processing system.

FIG. 5 is a diagram of an embodiment of a system for describing a subsystem.

FIG. 6 is a diagram of an embodiment of a plasma chamber.

Claims (30)

A method for synchronizing the execution of a recipe group includes: sending a recipe group to a main controller by an instruction controller; sending the recipe group by the main controller for control of a subsystem of a plasma system Controller execution, wherein the step of sending the recipe group from the main controller to the subsystem controller is executed within a first clock cycle of a clock signal; the controller generates a recipe event signal by the instruction; The instruction controller sends the recipe event signal to the subsystem controller, and the recipe event signal instructs the subsystem controller to execute an execution time of the recipe group, wherein the execution time occurs at the first clock Within a second clock cycle after the cycle, wherein the second clock cycle belongs to the clock signal; sending an additional recipe set to the main controller by the command controller; and sending by the main controller The additional recipe group to the subsystem controller for execution by the subsystem controller of the plasma system, wherein the step of sending the additional recipe group from the main controller to the subsystem controller is The second portion of the clock period of the clock signal is performed therein. For example, the method for synchronizing the execution of a recipe set in the first patent application, wherein the step of sending the recipe set to the main controller by the instruction controller includes sending a packet to the main controller via a transmission medium. The step of sending the recipe group from the main controller to the subsystem controller includes sending the packet to the subsystem controller via a transmission medium. For example, the method for synchronizing the execution of a recipe group in the first scope of the patent application further includes: sending another recipe group by the main controller for another subsystem controller of the plasma system at the first time Within the pulse cycle, wherein the execution time is used for the other subsystem controller of the plasma system to execute the another recipe group. For example, the method for synchronizing the execution of a recipe group in the first patent application scope, wherein the instruction controller is located in a computing device, and the computing device includes a laptop computer, or a desktop computer, or a tablet computer. , Or mobile phone. For example, the method for synchronizing the execution of a formula group in the first patent application range, wherein the formula group includes the power of a radio frequency (RF) signal to be generated by an RF generator, or the frequency of the RF signal, or the The pressure in a plasma chamber of a plasma system, or the temperature in the plasma chamber, or the gap between the electrodes of the plasma chamber, the air flow into the plasma chamber, and an impedance of the plasma system The capacitance of a capacitor of the matching network, or the inductance of an inductor of the impedance matching network, or a combination thereof. For example, the method for synchronizing the execution of a recipe group in the first patent application scope, wherein the recipe group is executed by the subsystem controller when the recipe group is sent from the subsystem controller to a subsystem, where the sub The system controller is connected to the main controller. For example, the method for synchronizing the execution of a formula group in the patent application item 6, wherein the subsystem is a radio frequency (RF) generator, or a pressure subsystem, or a temperature subsystem, or a gap subsystem, or An airflow subsystem, or an impedance matching network. For example, the method for synchronizing the execution of a formula group in the first patent application scope, wherein the plasma system includes one or more radio frequency (RF) generators, an impedance matching network, and a plasma chamber, wherein One or more RF generators are connected to the impedance matching network via corresponding one or more RF cables, wherein the impedance matching network is connected to the plasma chamber via an RF transmission line. For example, the method for synchronizing the execution of a recipe group in the first patent application scope, wherein the execution time is the time when the subsystem controller receives the recipe event signal from the instruction controller, wherein the subsystem controller is connected to The main controller also controls a subsystem, wherein the recipe event signal received by the subsystem controller causes immediate execution of the recipe group. For example, the method for synchronizing the execution of a recipe group according to item 1 of the application, wherein the execution time is the time when the recipe group is sent from the subsystem controller to a subsystem, and the subsystem controller is connected to the subsystem. The main controller is used to receive the recipe group from the main controller. For example, the method for synchronizing the execution of a recipe group according to item 1 of the patent application, wherein the recipe event signal triggers the execution of the recipe group. For example, the method for synchronizing the execution of a recipe group according to item 1 of the scope of the patent application, wherein the recipe event signal is received by the subsystem controller of a subsystem to indicate the immediate start of the execution of the recipe group. For example, the method for synchronizing the execution of a recipe group in the first patent application scope further includes: generating an additional recipe event signal by the instruction controller; and sending the additional recipe event signal to the child by the instruction controller. The system controller, the recipe event signal instructs the subsystem controller to execute an execution time of the additional recipe group, wherein the execution time occurs in a third clock cycle subsequent to the second clock cycle, wherein The third clock cycle belongs to the clock signal. A method for synchronizing the execution of a recipe group includes: sending a recipe group for execution by a subsystem controller through a main controller within a first clock cycle of a clock signal, wherein the subsystem The controller is used to control a component of a plasma system; a recipe event signal is generated by the main controller; the recipe event signal is sent by the main controller, and the recipe event signal indicates the plasma system The subsystem controller executes an execution time of the recipe group, wherein the execution time of the recipe group occurs in a second clock cycle after the first clock cycle, and the recipe group is at the first clock Sent during a cycle, wherein the second clock cycle belongs to the clock signal; and sending an additional recipe set to the subsystem controller by the main controller for execution by the subsystem controller of the plasma system, The step of sending the additional recipe group from the main controller to the subsystem controller is performed within a part of the second clock cycle of the clock signal. For example, the method for synchronizing the execution of a recipe group according to item 14 of the patent application, wherein sending the recipe group includes sending a packet to the subsystem controller via a cable. For example, the method for synchronizing the execution of a recipe group in the scope of application for patent No. 14 wherein the plasma system includes one or more radio frequency (RF) generators, an impedance matching network, and a plasma chamber, wherein One or more RF generators are connected to the impedance matching network, wherein the impedance matching network is connected to the plasma chamber. For example, the method for synchronizing the execution of a recipe group in the scope of application for patent No. 14 further includes: sending, by the main controller, another subsystem controller to the first clock cycle of the clock signal Another set of recipes executed, wherein the other subsystem controller is used to control another element of the plasma system, and the execution time is used to allow the other subsystem controller of the plasma system The other recipe group is executed. For example, the method for synchronizing the execution of a recipe group in the scope of application for patent No. 14 wherein the recipe group is executed by the subsystem controller by sending the recipe group to the element. For example, the method for synchronizing the execution of a recipe group in the scope of patent application No. 14 wherein the execution time is the time when the subsystem controller receives the recipe event signal from the main controller, wherein the subsystem controller is connected to The main controller also controls the element. For example, the method for synchronizing the execution of a recipe group according to item 14 of the application, wherein the execution time is the time when the recipe group is sent from the subsystem controller to the component. For example, the method for synchronizing the execution of a recipe group according to item 14 of the application, wherein the recipe event signal triggers the execution of the recipe group. For example, the method for synchronizing the execution of a recipe group according to item 14 of the application, wherein when the recipe event signal is received by the subsystem controller of the subsystem, it indicates that the execution of the recipe group is immediately started. A method for synchronizing the execution of a recipe group includes: sending a recipe group to a processor of a subsystem of a plasma processing system by a main controller, wherein the sending step from the main controller occurs at Within a first clock cycle of a clock signal; a recipe event signal is generated by the main controller; the recipe event signal is sent by the main controller to the processor of the subsystem, and the recipe event signal indicates An execution time of the recipe group, wherein sending the recipe event signal occurs within a second clock cycle subsequent to the first clock cycle; and sending an additional recipe group to the child by the main controller The processor of the system for execution by the processor of the subsystem, wherein the step of sending the additional recipe group from the main controller to the processor of the subsystem is based on the second clock of the clock signal Executed during part of the cycle. For example, the method for synchronizing the execution of a recipe group according to item 23 of the patent application, wherein sending the recipe group includes sending a packet to the processor of the subsystem via a cable. For example, the method for synchronizing the execution of a recipe group in the scope of the patent application No. 23 further includes: sending, by the main controller, another recipe group for execution by another processor of another subsystem, The other processor is used to control the other subsystem of the plasma processing system, and the sending of the other recipe group occurs in the first clock cycle, and the execution time is used for the other processor The other processor of a subsystem executes the other recipe group. For example, the method for synchronizing the execution of a recipe group in the scope of patent application No. 23, wherein the recipe group is executed by the processor when the processor of the subsystem sends a signal to a driver to generate a signal. For example, the method for synchronizing the execution of a recipe group according to item 23 of the patent application, wherein the execution time is the time when the processor receives the recipe event signal from the main controller, and the processor is connected to the main controller And controls the subsystem. For example, the method for synchronizing the execution of a recipe group in the patent application No. 23, wherein the execution time is the time from the processor to send the recipe group to a driver to drive a part of the plasma system. For example, the method for synchronizing the execution of a recipe group according to item 23 of the patent application, wherein the recipe event signal triggers the execution of the recipe group. For example, the method for synchronizing the execution of a recipe group according to item 23 of the patent application, wherein when the recipe event signal is received by the processor, the execution of the recipe group is instructed to start immediately.