KR20230171417A - Systems and methods for synchronizing execution of recipe sets - Google Patents

Abstract

Systems and methods for synchronizing the execution of recipe sets are described. One of the methods includes transmitting a recipe set by a command controller to a master controller and transmitting the recipe set by the master controller for execution by a subsystem controller of the plasma system. Transferring the recipe set from the master controller to the subsystem controller is performed during the first clock cycle of the clock signal. The method includes generating by the command controller a recipe event signal and transmitting by the command controller to the subsystem controller a recipe event signal indicative of an execution time of the recipe set by the subsystem controller. Execution time occurs during the second clock cycle following the first clock cycle. The second clock cycle is a cycle of the clock signal.

Description

Systems and methods for synchronizing execution of recipe sets {SYSTEMS AND METHODS FOR SYNCHRONIZING EXECUTION OF RECIPE SETS}

Present embodiments relate to systems and methods for synchronizing execution of recipe sets.

Plasma systems are used to perform a variety of operations. For example, plasma systems have multiple stations for cleaning wafers, depositing materials on wafers, etching wafers, etc. Each station is controlled by one or more processing devices to perform operations.

Information is transferred between processing devices to perform operations. However, in order to transmit information, each processing device is under a tight schedule. For example, each processing device must process data within a predefined time window before providing the processed data to another processing device.

These time window requirements result in expensive processing devices. Additionally, when using processing devices, data transfer rates are limited between the processing devices.

It is in this context that the embodiments described in this disclosure occur.

Embodiments of the present disclosure provide apparatus, methods, and computer programs for synchronizing execution of recipe sets. It should be understood that the present embodiments may be implemented in a number of ways, for example, as a process, or device, or system, or part of hardware, or method, or computer-readable medium. Some embodiments are described below.

In one embodiment, a set of recipes to be executed is transmitted from a controller to another controller prior to transmitting signals for execution of the recipe set. For example, a master controller transmits a recipe set to a slave controller before the slave controller transmits a pulse indicating that it is executing the recipe set. This prior transmission of the recipe set provides the slave controller with preparation time for execution of the recipe set. As soon as a pulse is received indicating that the slave controller is executing the recipe set, the slave controller executes the recipe set by transmitting the recipe set for processing.

Transmitting multiple recipe sets to multiple slave controllers before transmitting a pulse indicating execution of the recipe sets ensures that each slave controller does not execute the recipe sets within a time window. For example, in EtherCAT (Ethernet for Control Automation Technology), one slave controller receives a plurality of recipe sets, identifies one of the recipe sets, and transmits the plurality of recipe sets to another slave controller. Executes the identified recipe set. Identification and execution are performed within time windows that are constraining and impose costs. Additionally, these EtherCAT slave controllers are expensive and difficult to obtain due to their low volumes. Additionally, EtherCAT slave controllers are limited in speed, for example, Mbps (mega bits per second). By using systems and methods for synchronizing the execution of recipe sets, the step of transferring multiple recipe sets can be performed at a rate of Gbps (gigabits per second) or more, before the time that slave controllers must perform identification and execution. There is no window. The slave controllers execute the recipe sets immediately after a pulse is received by the slave controllers indicating that the slave controllers are executing the recipe sets.

In one embodiment, a method for synchronizing execution of recipe sets is described. The method includes transmitting a recipe set by a command controller to a master controller and transmitting the recipe set by the master controller for execution by a subsystem controller of the plasma system. Transferring the recipe set from the master controller to the subsystem controller is performed during the first clock cycle of the clock signal. The method includes generating by the command controller a recipe event signal and transmitting by the command controller to the subsystem controller a recipe event signal indicative of an execution time of the recipe set by the subsystem controller. Execution time occurs during the second clock cycle following the first clock cycle. The second clock cycle is a cycle of the clock signal.

In one embodiment, a method for synchronizing execution of recipe sets is described. The method includes transmitting a set of recipes by a master controller for execution by a subsystem controller during a first clock cycle of the clock signal. The subsystem controller is configured to control components of the plasma system. The method further includes generating a recipe event signal by the master controller and transmitting by the master controller a recipe event signal indicative of an execution time of the recipe set by a subsystem controller of the plasma system. The execution time of the recipe set occurs during the second clock cycle following the first clock cycle in which the recipe set is transmitted. The second clock cycle is a cycle of the clock signal.

In one embodiment, a method for synchronizing execution of recipe sets is described. The method includes transmitting a recipe set by a master controller to a processor of a subsystem of the plasma system. The transfer operation from the master controller occurs during the first clock cycle of the clock signal. The method further includes generating a recipe event signal by the master controller and transmitting, by the master controller, the recipe event signal indicating the execution time of the recipe set to a processor of the subsystem. The operation of transmitting the recipe event signal occurs during a second clock cycle following the first clock cycle.

Some advantages of some of the embodiments described above include synchronizing execution of recipe sets between a plurality of controllers. For example, the (n+1)th recipe sets are transmitted in a synchronized manner from a transmitting controller to one or more receiving controllers. After transmitting the (n+1)th recipe sets to the receiving controllers, the transmitting controller or another controller provides a recipe event signal to signal the receiving controllers to initiate the recipe sets. The time between transmission of the (n+1)th recipe sets and transmission of the recipe event signal causes receiving controllers to prepare for execution of the (n+1)th recipe sets. For example, the (n+1)th recipe sets are sent to the receiving controllers some time after the wafer is loaded into the plasma chamber. When the recipe event signal is sent to the receiving controllers, the wafer has already been loaded. Additionally, as soon as a recipe event signal is received by the receive controllers, the receive controllers execute recipe sets to initiate wafer processing.

Other advantages include the use of communication protocols, such as the Ethernet protocol, universal datagram protocol (UDP), UDP over Internet Protocol (UDP over IP), UDP over IP over Ethernet, customized protocols with data transfer rates of gigabit and higher, etc. Includes. The (n+1)th recipe sets are embedded within packets when their payloads are generated by applying a communication protocol to transmit the (n+1)th recipe sets. This use of a communication protocol makes it possible to achieve transfer rates in excess of Gbps. The use of communication protocols saves time and is more cost-effective compared to the EtherCAT protocol.

Other aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings.

Embodiments are understood with reference to the following description taken in conjunction with the accompanying drawings.
1AA is a diagram of an embodiment of a system to illustrate synchronization of execution of recipe sets across different subsystem controllers.
Figure 1ab is a diagram of an embodiment of a system similar to the system of Figure 1aa.
1Ba is a diagram of an embodiment of a system to illustrate synchronization between subsystem controllers and a master controller without receiving an input signal from a user via an input device.
Figure 1bb is a diagram of an embodiment of a system similar to the system of Figure 1ba.
1C is a diagram of an embodiment of a system to illustrate synchronization of subsystems according to a recipe event signal received from a master controller.
1D is a diagram of an embodiment of a system to illustrate subsystem controllers and synchronization between subsystems.
1E is a diagram of an embodiment of a system to illustrate the use of a user interface (UI) computer to achieve synchronization between a master controller and RF generator controllers.
Figure 2aa is an embodiment of a timing diagram to illustrate synchronization between transmitting (n+1)th recipe sets to controllers and execution time of the recipe sets by the controllers.
Figure 2ab is an embodiment of a timing diagram to illustrate that the execution time of a packet by a controller varies between the time the packet is received by the controller and a later time a digital pulse is received indicating that the packet has been executed.
Figure 2B is an embodiment of a timing diagram used to illustrate the functionality of the system of Figure 1E.
3A is a diagram of an embodiment of an Ethernet packet.
3B is a diagram illustrating a packet, according to an embodiment described in this disclosure.
4 is a diagram of an embodiment of a plasma processing system.
5 is a diagram of an embodiment of a system for illustrating subsystems.
Figure 6 is a diagram of an embodiment of a plasma chamber.

The following embodiments describe systems and methods for synchronizing the execution of recipe sets. It will be apparent that the present embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations are not described in detail so as not to unnecessarily obscure the present embodiments.

1AA is a diagram of an embodiment of system 100 to illustrate synchronization of execution of recipe sets across different subsystem controllers. System 100 includes a command controller 102 located within computing device 108. As used herein, a controller includes one or more processors and one or more memory devices. As used herein, processor refers to a CPU, application specific integrated circuit (ASIC), or programmable logic device (PLD), and these terms are used interchangeably herein. Examples of memory devices include read-only memory (ROM), random access memory (ROM), hard disks, volatile memory, non-volatile memory, redundant array of storage disks, flash memory, etc. Examples of computing devices 108 include laptop computers or desktop computers or tablets or mobile phones.

System 100 further includes a master controller 106 coupled to command controller 102 via transmission medium 112. As used herein, examples of transmission media include coaxial cables, conductor cables, wired media, twisted pair, fiber optic cables, cables, Ethernet cables, wireless media, combinations of wired and wireless media, etc. Examples of communication protocols include universal datagram protocol (UDP), UDP over IP (UDP over Internet Protocol), UDP over IP over Ethernet, customized protocol, serial transmission protocol, parallel transmission protocol, universal serial bus (USB) protocol, customized Includes communication protocols, etc. Examples of serial protocols include, for example, RS 232 protocol, RS 422 protocol, RS 423 protocol, RS 485 protocol, etc. In various embodiments, in a serial protocol, data is transmitted serially. For example, 1 bit is transmitted, followed by another bit. An example of a parallel protocol is a protocol that transfers data in a parallel manner. For illustration purposes, in a parallel protocol, multiple bits are transmitted simultaneously, etc. In some embodiments, the terms transmission medium and link are used interchangeably herein. In some embodiments, a serial protocol or parallel protocol is referred to herein as a non-packetized protocol.

System 100 includes subsystem controller A, subsystem controller B, and subsystem controller C. Subsystem controller A is coupled to master controller 106 via transmission medium 110A, subsystem controller B is coupled to master controller 106 via transmission medium 110B, and subsystem controller C is coupled to master controller 106 via transmission medium 110A. It is connected to the master controller 106 via (110C).

Additionally, each subsystem controller is coupled to a corresponding subsystem via one or more corresponding physical media, described as physical communication media in U.S. Patent Application Serial No. 14/974,915. For example, subsystem controller A is connected to subsystem A through a dedicated physical medium, subsystem controller B is connected to subsystem B through a dedicated physical medium, and subsystem controller C is connected to subsystem A through a dedicated physical medium. Connected to system C.

It should be noted that in some embodiments, the terms subsystem and component are used interchangeably herein.

Examples of subsystems include a radio frequency (RF) generator, or pressure subsystem, or temperature subsystem, or gap subsystem, or gas flow subsystem, or coolant flow subsystem, or impedance matching network. For illustration purposes, subsystem A is a radio frequency (RF) generator of x MHz (megahertz), e.g. 2 MHz, etc., subsystem B is a y MHz RF generator, and subsystem C is a z MHz RF generator. It is a generator. Examples of y include 2 or 27, and examples of z include 27 or 60. In one embodiment, instead of an x MHz RF generator, a kilohertz (kHz) RF generator, such as 400 kHz, is used.

The pressure subsystem includes a plurality of parts, such as a pressure controller, driver, motor, one or more rods, confinement rings, etc. The pressure controller is connected to the motor via a driver, and the motor is further connected to the confinement rings via one or more rods within the plasma chamber. The plasma chamber is described further below. Examples of drivers include a transistor or group of transistors. The pressure controller's processor sends a signal to the driver to drive the motor to rotate the motor's rotor. Rotation of the rotor controls the amount of movement of the confinement rings through one or more rods to further change the pressure within the plasma chamber.

In one embodiment, instead of the pressure controller being located within the pressure subsystem, the pressure controller is an example of subsystem controller A and the remaining portions of the pressure subsystem described above are located within the pressure subsystem.

The temperature subsystem includes a plurality of parts, such as temperature controllers, drivers, heaters, etc. The temperature controller is connected to the heater via a driver. The temperature processor in the temperature controller sends a signal to the driver to generate a significant amount of current. The driver generates this significant amount of current and provides it to the heater. The heater generates heat to heat the plasma chamber.

In one embodiment, instead of the temperature controller being located within the temperature subsystem, the temperature controller is an example of subsystem controller B and the remaining portions of the temperature subsystem described above are located within the temperature subsystem.

The gap subsystem includes parts such as a gap controller, gap driver, motor, one or more loads, etc. The gap controller is connected to the motor through a gap driver, and the motor is connected to the upper electrode of the plasma chamber through one or more rods. The gap processor of the gap controller sends a signal to the driver to generate a significant amount of current provided to the motor to rotate the motor's rotor. Rotation of the rotor rotates one or more rods to change the gap between the upper and lower electrodes of the plasma chamber.

In one embodiment, instead of the gap controller being located within the gap subsystem, the gap controller is subsystem controller C and the remaining portions of the gap subsystem described above are located within the gap subsystem.

The gas flow subsystem includes a plurality of parts, such as a gas flow controller, driver, motor, valve, tube, one or more rods, gas source, etc. The gas source stores process gases for processing, e.g., depositing materials, sputtering, etching, cleaning materials, on a substrate, e.g., a semiconductor wafer, etc., within the plasma chamber. Examples of process gases include oxygen-containing gas or fluorine-containing gas, etc. The gas flow processor of the gas flow controller transmits a signal to the driver, which generates current to drive the motor. The motor rotates to change the position of the valve within the tube via one or more rods to further achieve a significant flow of gas through the tube from the gas source to the plasma chamber.

In one embodiment, instead of the gas flow controller being located within the gas flow subsystem, the gas flow controller is an example of subsystem controller A and the remaining portions of the gas flow subsystem described above are located within the gas flow subsystem.

In one embodiment, instead of a motor within the gas flow subsystem, an electromagnetic current generated by a driver of the gas flow subsystem controls the amount opened and closed by a valve of the gas flow subsystem.

The coolant flow subsystem has the same parts, a source storing coolant is used instead of a gas source, and the output of the coolant flow subsystem is directed to a component of the plasma chamber, e.g. the upper electrode, to supply coolant to the component for cooling the component. , operates in the same manner as the gas flow subsystem except that it is connected to the lower electrode, upper electrode extension, lower electrode extension, etc.

The impedance matching network includes a plurality of parts, such as an impedance matching controller, one or more drivers, one or more motors, one or more capacitors, one or more inductors, one or more resistors, etc. The impedance matching controller's processor sends a signal to one of the drivers that generates the current. Current is provided to one of the motors to rotate the rotor of the motor to further change the area between the plates of one of the one or more capacitors to change the capacitance of the capacitor. Similarly, the impedance matching controller's processor sends a signal to another of the drivers that generates the current. Current flows through one of the motors to change the spacing between the coils of one of the inductors to change the inductance, or to rotate the rotor of the motor to further wind (turn) the core of one of the inductors to change the inductance of the inductor. Also available as another motor. For example, the inductance of an inductor in an impedance matching network is modified by shielding the inductor's core inside or outside the inductor's coils. The core is attached to a motor in an impedance matching network to slide the magnetic core.

Command controller 102 is coupled to an input device, such as a mouse, keyboard, stylus, touch screen, etc., through an input/output (I/O) interface. Examples of I/O interfaces include a serial port, or parallel port, or USB port, etc. Upon receiving a signal from the user via the input device and I/O interface, the command controller 102 generates the (n+1)th recipe set for execution by subsystem A, and (n+)th recipe set for execution by subsystem B. 1) The (n+1)th recipe set is transmitted to the master controller 106 via the transmission medium 112 for execution by subsystem C. For example, the command controller applies the communication protocol to generate a packet containing the (n+1)th recipe set to be executed by subsystem A, and the (n+1)th recipe set to be executed by subsystem B. and apply the communication protocol to generate packets containing the (n+1)th recipe set to be executed by subsystem C, via transmission medium 112 to master controller 106. ) transmit packets. As another example, command controller 102 transmits the (n+1)th recipe set, for example, by applying a non-packetized protocol, in a parallel manner or serial manner, etc. In some embodiments, the command controller may be configured to transmit (n +1) The recipe sets are transmitted simultaneously.

Note that in various embodiments, the (n+1)th is used to instantiate the next set of recipes to be executed compared to the previously transmitted nth recipe set, where n is an integer greater than or equal to 0. For example, the nth recipe set is transmitted before transmitting the (n+1)th recipe set. The (n+1)th recipe set is transmitted consecutively to transmitting the nth recipe set. In some embodiments, the nth recipe set is executed when the (n+1)th recipe set is transmitted.

Upon receiving the (n+1)th recipe sets for subsystem A, subsystem B, and subsystem C from command controller 102, master controller 106 selects one of the (n+1)th recipe sets. Identify the destination address, e.g., a media access control (MAC) address, etc., in a packet containing one of the (n+1)th recipe sets, and determine that (n+1) is for subsystem A. Identify from the destination address in a packet containing another of the (n+1)th recipe sets to determine that another of the (n+1)th recipe sets is for subsystem B, and from the destination address in the packet containing yet another one of the (n+1)th recipe sets to determine that yet another one of them is for subsystem C. Master controller 106 transmits a packet containing the (n+1)th recipe set for subsystem A to subsystem controller A via transmission medium 110A and the (n+1)th recipe set for subsystem B. Transmit the packet containing the recipe set to subsystem controller B via transmission medium 110B, and transmit the packet containing the (n+1)th recipe set for subsystem C to subsystem controller B via transmission medium 110C. Transmit to controller C.

In some embodiments where a non-packetized protocol is applied, upon receiving the (n+1)th recipe sets for subsystem A, subsystem B, and subsystem C from command controller 102, master controller 106 identifies one of the (n+1)th recipe sets as being for subsystem A from a destination address in one of the (n+1)th recipe sets, and another one of the (n+1)th recipe sets. Identify that another one of the (n+1)th recipe sets is for subsystem B, and from a destination address in still another one of the (n+1)th recipe sets (n+1) Still another one of the first set of recipes is identified as being for subsystem C. Master controller 106 transmits the (n+1)th recipe set for subsystem A to subsystem controller A via transmission medium 110A, in parallel or serial manner, and for subsystem B in parallel or serial manner. Transmit the (n+1)th recipe set to subsystem controller B via transmission medium 110B, and transmit the (n+1)th recipe set for subsystem C in parallel or serial manner to transmission medium 110C. It is transmitted to subsystem controller C through.

The (n+1)th recipe sets for subsystem A, subsystem B, and subsystem C are simultaneously transmitted by master controller 106 to the corresponding subsystem A, subsystem B, and subsystem C, e.g. , during the first clock cycle of the clock signal, etc., are transmitted. Examples of the first clock cycle include clock cycle C1, time ts, etc. For illustration purposes, the (n+1)th recipe sets for subsystem A, subsystem B, and subsystem C correspond to the (n+1)th recipe sets in a synchronized manner. and transmitted during the rising edge or falling edge of the first clock cycle for transmission to subsystem C. The clock signal is generated by a clock source, such as an oscillator, an oscillator with a phase-locked loop (PLL), etc.

In one embodiment, the clock signal is generated by a clock source located within computing device 108. In this embodiment, the clock signal is transmitted from a clock source to command controller 102, master controller 106, subsystem controller A, subsystem controller B, subsystem controller C, and/or subsystem A, subsystem B, and It is transmitted to any controllers or processors in subsystem C.

In one embodiment, the clock signal is generated by a clock source located external to computing device 108 and coupled to master controller 106. In this embodiment, the clock signal is transmitted from a clock source to command controller 102, master controller 106, subsystem controller A, subsystem controller B, subsystem controller C, and/or subsystem A, subsystem B, and It is transmitted to any controllers or processors in subsystem C.

In some embodiments, the clock signal is generated by a clock source located within master controller 106. In this embodiment, the clock signal is transmitted from a clock source to command controller 102, a processor in master controller 106, subsystem controller A, subsystem controller B, subsystem controller C, and/or subsystem A, subsystem B. , and transmitted to any controllers or processors in subsystem C.

Upon receiving input from a user via an input device, command controller 102 generates a recipe event signal 104. Examples of recipe event signals 104 include digital output signals or analog output signals. Recipe event signal 104 is transmitted from command controller 102 via communication medium 126 and communication medium 120 to master controller 106, communication medium 126 and communication medium 124 and communication medium 122A. to subsystem controller A, via communication medium 126 and communication medium 124 and communication medium 122B to subsystem controller B, and through communication medium 126 and communication medium 124 and communication medium 122C. ) is transmitted to the subsystem controller C through . Examples of communication media include wired or cable, or a combination of wired and wireless media.

Recipe event signal 104 indicates the execution time te of the (n+1)th recipe sets by the corresponding subsystem A, subsystem B, and subsystem C. For example, upon receipt of recipe event signal 104, subsystem controller A transmits the (n+1)th recipe set for subsystem A to subsystem A via link 114A. Execute the (n+1)th recipe set. Additionally, upon receipt of recipe event signal 104, subsystem controller B transmits the (n+1)th recipe set for subsystem B to subsystem B via link 114B, thereby creating (n+1)th recipe set for subsystem B. +1) Execute the second recipe set. Additionally, upon receiving the recipe event signal 104, subsystem controller C transmits the (n+1)th recipe set for subsystem C to subsystem C via link 114C, thereby creating (n+1)th recipe set for subsystem C. +1) Execute the second recipe set. The execution time of the (n+1)th recipe sets by the corresponding subsystem A, subsystem B, and subsystem C is during the second clock cycle following the first clock cycle, e.g., C2, C3, C4, It happens at C5, C6, time te, etc. For example, the first clock cycle precedes the second clock cycle. As another example, the second clock cycle occurs one or more clock cycles preceding the first clock cycle. One or more clock cycles precede the second clock cycle. The second clock cycle and all clock cycles between the first and second clock cycles are cycles of the clock signal.

Recipe event signal 104 serves as a trigger for execution, e.g., transfer of the (n+1)th recipe set from the subsystem controller to the corresponding subsystem. For example, after receiving the (n+1)th recipe set for subsystem A, subsystem controller A waits to receive recipe event signal 104 from command controller 102. After waiting, upon receipt of the recipe event signal 104, subsystem controller A immediately transmits the (n+1)th recipe set for subsystem A to subsystem A. For illustration, during the same clock cycle that recipe event signal 104 is received by subsystem controller A from command controller 102, subsystem controller A receives (n+1) signal for subsystem A via link 114A. ) transmit the second recipe set to subsystem A. As another example, after receiving the (n+1)th recipe set for subsystem A, subsystem controller A waits to receive recipe event signal 104 from command controller 102. During the waiting time, subsystem controller A performs an error check according to the bits of the frame check sequence (FCS) field in the packet containing the (n+1)th recipe set for subsystem A. For example, subsystem controller A computes a sequence from the bits of the (n+1)th recipe set stored in the payload field of an Ethernet packet and determines whether the computed sequence matches bits in the FCS field. do. Upon determining that there is no match, subsystem controller A generates an error flag and transmits the error flag to master controller 106 and/or command controller 102. Meanwhile, upon determining that there is a match, subsystem controller A transmits an Ethernet packet from subsystem controller A's receive buffer to subsystem controller A's transmit buffer, and waits to receive the recipe event signal 104. During the clock cycle in which the recipe event signal is received, subsystem controller A transmits, e.g., transmits, etc., an Ethernet packet to subsystem A.

Recipe event signal 104 instructs execution of the (n+1)th recipe set. For example, during a time e.g. clock cycle, etc., recipe event signal 104 is received by the subsystem controller from command controller 102 or master controller 106, and the subsystem controller processes (n +1) Transmit the second recipe set to the corresponding subsystem.

A recipe event signal 104 for a subsystem when received by the subsystem controller indicates immediate activation of processing of a recipe set. For example, when a recipe event signal 104 is received by subsystem controller A, from command controller 102 or master controller 106, e.g., at a time during a clock cycle, etc. A is the (n+1)th recipe set for the corresponding subsystem for processing by the subsystem immediately, e.g., during the same clock cycle, during the rising edge of a clock cycle, during the falling edge of a clock cycle, etc. transmit.

An example of a communication scheme between a subsystem controller and a corresponding subsystem is provided in US patent application Ser. No. 14/974,915. For example, a communication protocol is applied by subsystem controller A to transmit the (n+1)th recipe set for subsystem A to subsystem A over link 114A. As another example, a communication protocol is applied by subsystem controller B to transmit the (n+1)th recipe set for subsystem B to subsystem B over link 114B.

Upon receiving the (n+1)th recipe set for the subsystem, the subsystem processes the (n+1)th recipe set for the subsystem to facilitate processing of the substrate. For example, when subsystem A is an RF generator, the RF generator's processor, e.g., processor PA, etc., transfers a significant amount of power and frequency of the RF signal to the driver and amplifier of the RF signal. The driver generates a current signal from a signal received from the processor and the amplifier amplifies the current signal to produce an amplified current signal. The amplified current signal is provided to the RF power supply to generate an RF signal with this significant amount of power and frequency. This significant amount of power and frequency is within the (n+1)th recipe set for subsystem A. As another example, when subsystem B is a pressure subsystem, the processor of the pressure controller, e.g., processor PB, etc., acts as a driver of the pressure subsystem to drive the motor of the pressure subsystem to rotate the rotor of the motor. transmit a signal The rotation of the rotor controls the movement of a significant amount of confinement rings to further achieve a significant amount of pressure within the plasma chamber. This significant amount of pressure is provided within the (n+1)th recipe set for subsystem B. As yet another example, when subsystem C is a temperature subsystem, the temperature processor of the temperature controller, e.g., processor PC, etc., sends a signal to the driver of the temperature subsystem to generate a significant amount of current. The driver generates this significant amount of current and provides it to the heater. Upon receiving electrical current, the heater generates heat to heat the plasma chamber to create a significant amount of temperature within the plasma chamber. This significant amount of temperature is provided within the (n+1)th recipe set for subsystem C.

As another example, when subsystem A is a gap subsystem, the gap processor of the gap controller, e.g., processor PA, etc., generates a significant amount of current that is provided to the motor of the subsystem to rotate the rotor of the motor. A signal is sent to the driver of the gap subsystem to do this. Rotation of the rotor rotates one or more rods of subsystem A to achieve a significant amount of gap between the upper and lower electrodes. This significant gap is provided within the (n+1)th recipe set for subsystem A. As still another example, when subsystem B is a gas flow subsystem, the gas flow processor of the gas flow controller, e.g., processor PB, etc., sends a signal to a driver that generates a current to drive the motor of subsystem B. transmit. The rotor of the motor rotates to change the position of the valve to further achieve a significant amount of gas flow from the gas source of subsystem B through the tube of subsystem B to the plasma chamber. This significant amount of gas flow is provided within the (n+1)th recipe set for subsystem B.

As another example, when subsystem C is an impedance matching network, the processor of the impedance matching controller, e.g., processor PC, etc., sends a signal to one of the drivers of the impedance matching network to generate a current. Current is provided to one of the motors in the impedance matching network to rotate the rotor of the motor to further change the area between the plates of one of the one or more capacitors in the impedance matching network to achieve the capacitance of the capacitor. Similarly, the processor of the impedance matching controller sends a signal to another one of the drivers of the impedance matching network to generate a current. Current is provided to another one of the motors in the impedance matching network to rotate the rotor of the motor to further change the position of the core of the inductor in the impedance matching network to achieve the inductance of the inductor. Capacitance and inductance are provided in the (n+1)th recipe set for subsystem C.

Although three subsystems A, subsystem B, and subsystem C are shown in FIG. 1aa, it should be noted that in one embodiment, any number of subsystems are used. For example, instead of three subsystems, two subsystems and corresponding two subsystem controllers are used. As another example, one subsystem and one subsystem controller are used.

In one embodiment, command controller 102, master controller 106, subsystem controller A, subsystem controller B, and subsystem controller C each include one or more transceivers, the transceivers implementing a gigabit physical layer. One or more transceivers are used to transmit and receive packets.

In some embodiments, the controller's transceiver is coupled to the controller's processor.

In some embodiments, functions described herein as being performed by a controller are performed by a processor of the controller.

In various embodiments, recipe event signal 104 is transmitted to subsystem controller A via a first transmission medium similar to transmission medium 110A. A first transmission medium couples command controller 102 to subsystem controller A. Recipe event signal 104 is also transmitted to subsystem controller B via a second transmission medium similar to transmission medium 110B. A second transmission medium couples command controller 102 to subsystem controller B. Recipe event signal 104 is also transmitted to subsystem controller C via a third transmission medium similar to transmission medium 110C. A third transmission medium couples command controller 102 to subsystem controller C.

In some embodiments, subsystem controller A sends an acknowledgment of receipt of each recipe set, e.g., the (n+1)th recipe set, etc., to master controller 106 via transmission medium 110A. and upon receipt of the acknowledgment, master controller 106 transmits the acknowledgment to command controller 102 via transmission medium 112. Similarly, subsystem controller B transmits an acknowledgment of receipt of a recipe set, e.g., the (n+1)th recipe set, etc., to the master controller 106 via transmission medium 110B, and receives the acknowledgment. Upon receipt, master controller 106 transmits an acknowledgment to command controller 102 via transmission medium 112. Additionally, subsystem controller C transmits an acknowledgment of receipt of a recipe set, e.g., the (n+1)th recipe set, etc., to the master controller 106 via transmission medium 110C, and receives the acknowledgment. Upon completion, master controller 106 transmits an acknowledgment to command controller 102 via transmission medium 112.

In various embodiments, an acknowledgment is sent by the subsystem controller to the master controller 106 after receiving the recipe set. For example, an acknowledgment is sent by the subsystem controller to the master controller 106 after receiving the (n+1)th recipe set, and another acknowledgment is sent after receiving the (n+2)th recipe set. is transmitted by the subsystem controller to the master controller 106, and so on.

In some embodiments, recipe sets are transmitted as payload within a packet, and each recipe set is transmitted in a different packet. For example, the (n+1)th recipe set is transmitted in the (n+1)th packet and the (n+2)th recipe set is transmitted in the (n+2)th packet. The (n+2)th packet is consecutive to the (n+1)th packet.

FIG. 1AB is a diagram of an embodiment of system 150 similar to system 100 of FIG. 1AA except that in system 150, subsystem A, subsystem B, and subsystem C are not shown. System 150 is used to illustrate that links 110A, 110B, and 110C are links that apply a communication protocol. For example, Ethernet packets containing the (n+1)th recipe sets for subsystem A, subsystem B, and subsystem C are transmitted from the master controller 106 to the corresponding subsystem A, subsystem B, slave controllers. , and are communicated to subsystem C.

1BA is a diagram of an embodiment of system 160 to illustrate synchronization between subsystem controller A, subsystem controller B, and subsystem controller C and master controller 106 without receiving input signals from a user via an input device. am. During the first clock cycle, master controller 106 transmits the (n+1)th recipe set for subsystem A to subsystem controller A via transmission medium 110A and the (n+1)th recipe set for subsystem B. )th recipe set is transmitted to the subsystem controller B through the transmission medium 110B, and the (n+1)th recipe set for subsystem C is transmitted to the subsystem controller C through the transmission medium 110C. For example, master controller 106 applies a communication protocol to generate a packet containing the (n+1)th recipe set for subsystem A and the first clock cycle of the clock signal, e.g., cycle C1. , etc., while transmitting packets to subsystem controller A via transmission medium 110A. As another example, master controller 106 applies a communication protocol to generate a packet containing the (n+1)th recipe set for subsystem B and transmits a packet to transmission medium 110B during the first clock cycle of the clock signal. The packet is transmitted to subsystem controller B through . Additionally, as yet another example, master controller 106 applies a communication protocol to generate a packet containing the (n+1)th recipe set for subsystem C and transmits the transmission medium during the first clock cycle of the clock signal. A packet is transmitted to subsystem controller C through (110C). As another example, master controller 106 applies a non-packetized communication protocol to transmit the (n+1)th recipe set to subsystem controller A via transmission medium 110A in a serial or parallel manner, Apply a non-packetized communication protocol to transmit the (n+1)th recipe set to subsystem controller B via transmission medium 110B in a serial or parallel manner, and serially transmit the (n+1)th recipe set. A non-packetized communication protocol is applied to transmit to the subsystem controller C over the transmission medium 110C in a straight or parallel manner.

Upon receiving the (n+1)th recipe sets from the master controller 106, subsystem controller A, subsystem controller B, and subsystem controller C configure the (n+1)th recipe sets corresponding to subsystem A, subsystem Waits to receive recipe event signal 104 before transmitting to system B, and subsystem C. Master controller 106 generates recipe event signal 104 and transmits recipe event signal 104 to subsystem controller A via communication medium 162 and communication medium 164A. Master controller 106 also transmits recipe event signal 104 to subsystem controller B via communication medium 162 and communication medium 164B, and sends recipe event signal 104 to communication medium 162 and communication medium 164B. Transmits to subsystem controller C via medium 164C. Recipe event signal 104 indicates the execution time of the (n+1)th recipe sets by subsystem controller A, subsystem controller B, and subsystem controller C. Master controller 106 transmits recipe event signal 104 to subsystem controller A, subsystem controller B, and subsystem controller C during the second clock cycle of the clock signal, e.g., clock cycle C2, etc. .

The execution time of the (n+1)th recipe sets by subsystem controller A, subsystem controller B, and subsystem controller C is determined when the recipe event signal 104 from the master controller 106 is transmitted to subsystem controller A, subsystem controller C. B, and the time received by subsystem controller C. For example, during a clock cycle when the recipe event signal 104 is received by subsystem controller A, subsystem controller B, and subsystem controller C, e.g., clock cycle C2, etc. System controller B, and subsystem controller C execute the (n+1)th recipe sets.

Subsystem controller A, subsystem controller B, and subsystem controller C set the (n+1)th recipe sets by transferring the (n+1)th recipe sets to the corresponding subsystem A, subsystem B, and subsystem C. run them. For example, in response to receiving recipe event signal 104, subsystem controller A immediately transmits the (n+1)th recipe set for subsystem A to subsystem A over link 114A. For illustration, during clock cycle C2 when the recipe event signal 104 is received, subsystem controller A links the (n+1)th recipe set for subsystem A to link 114A for processing by subsystem A. It is transmitted to subsystem A through. As another example, in response to receiving recipe event signal 104, subsystem controller B links 114B to the (n+1)th recipe set for subsystem B for processing by subsystem B. It is immediately transmitted to subsystem B through. For illustration purposes, during clock cycle C2 when recipe event signal 104 is received, subsystem controller B transmits the (n+1)th recipe set for subsystem B to subsystem B over link 114B. As still another example, in response to receiving the recipe event signal 104, subsystem controller C links 114C the (n+1)th recipe set for subsystem C for processing by subsystem C. It is immediately transmitted to subsystem C through . For illustration, during clock cycle C2 when recipe event signal 104 is received, subsystem controller C transmits the (n+1)th recipe set for subsystem C to subsystem C over link 114C.

In various embodiments, recipe event signal 104 is transmitted from master controller 106 to subsystem controller A via transmission medium 110A. Recipe event signal 104 is also transmitted from master controller 106 to the subsystem via transmission medium 110B and by master controller 106 to subsystem controller C via transmission medium 110C.

FIG. 1BB is a diagram of an embodiment of a system 180 similar to system 160 of FIG. 1BA except that subsystem A, subsystem B, and subsystem C in system 180 are not shown. System 180 is used to illustrate that links 110A, 110B, and 110C apply a communication protocol. For example, packets containing the (n+1)th recipe sets for subsystem A, subsystem B, and subsystem C are transmitted from the master controller 106 to the corresponding subsystem A, subsystem B, and slave controllers. and subsystem C. Recipe event signal 104 is also generated by master controller 106 and transmitted to subsystem controller A, subsystem controller B, and subsystem controller C.

1C is a diagram of an embodiment of system 190 to illustrate synchronization of subsystem A, subsystem B, and subsystem C according to a recipe event signal received from master controller 106. Master controller 106 is coupled to subsystem A via transmission medium 172A, to subsystem B via transmission medium 172B, and to subsystem C via transmission medium 172C. Additionally, master controller 106 is coupled to subsystem A via communication medium 192 and communication medium 194A, is coupled to subsystem B via communication medium 192 and communication medium 194B, and communicates It is connected to subsystem C via medium 192 and communication medium 194C.

Master controller 106 transmits the (n+1)th recipe set to processor PA of subsystem A for execution and processing by subsystem A, and the (n+1)th recipe set for execution by subsystem B. and transmit to processor PB of subsystem B for processing, and transmit the (n+1)th recipe set to processor PC of subsystem C for execution and processing by subsystem C. For example, master controller 106 applies a communication protocol to generate a packet containing the (n+1)th recipe set for subsystem A over transmission medium 172A and By transmitting a packet to subsystem A, the (n+1)th recipe set for subsystem A is transmitted. As another example, master controller 106 applies a communication protocol to generate a packet containing the (n+1)th recipe set for subsystem B over transmission medium 172B and By transmitting a packet to subsystem B, the (n+1)th recipe set for subsystem B is transmitted. As another example, master controller 106 applies a communication protocol to generate a packet containing the (n+1)th recipe set for subsystem C over transmission medium 172C and By transmitting a packet to subsystem C, the (n+1)th recipe set for subsystem C is transmitted. As still another example, master controller 106 transmits the (n+1)th recipe set for subsystem A to subsystem A via transmission medium 172A, either serially or in parallel, and or transmit the (n+1)th recipe set for subsystem B to subsystem B via transmission medium 172B in a parallel manner, and to subsystem C via transmission medium 172C in a serial or parallel manner. The (n+1)th recipe set for is transmitted to subsystem C. The transfer of the (n+1)th recipe sets to subsystem A, subsystem B, and subsystem C occurs during the first clock cycle of the clock signal, e.g., time ts, clock cycle C1, etc. For example, the (n+1)th recipe sets are transmitted during the rising edge or falling edge of the first clock cycle.

Upon receiving the (n+1)th recipe sets, processor PA, processor PB, and processor PC execute the recipe sets, e.g., subsystem A, Waits to receive the recipe event signal 104 before transmitting to corresponding parts of subsystem B, and subsystem C, etc. For example, during the wait time, processor PA parses a packet containing the (n+1)th recipe set for subsystem A and reverses the packet by extracting the (n+1)th recipe set from the packet. Packetize (depacketize). To depacketize a packet, a communication protocol is applied. Additionally, processor PA identifies one or more parameters from a mapping between one or more parameters and one or more variables in the (n+1)th recipe set for subsystem A. A mapping between one or more parameters and one or more variables in the (n+1)th recipe set for subsystem A is stored in a memory device of subsystem A. Examples of parameters include the amount of current. Examples of variables include the frequency of the RF signal, and/or the power of the RF signal, or the pressure within the plasma chamber, or the gas flow into the plasma chamber, or the temperature within the plasma chamber, or the gap between the upper and lower electrodes, or impedance matching. Includes the capacitance of the capacitor of the network, or the inductance of the inductor of the impedance matching network, etc. For illustration purposes, processor PA identifies the current to be provided to the drivers of subsystem A to generate an RF signal with a significant amount of power or frequency. As another example, the processor PA may be configured to create a significant amount of gap in the gap between the upper and lower electrodes, or to achieve a pressure within the plasma chamber, or to achieve a temperature within the plasma chamber, or to create a significant amount of gap into the plasma chamber. Identify the current to be provided to the driver of subsystem A to achieve a gas flow of, or to achieve the capacitance of the capacitor of the impedance matching network, or to achieve the inductance of the inductor of the impedance matching network.

Similarly, during the wait time, processor PB parses the packet containing the (n+1)th recipe set for subsystem B and depacketizes the packet by extracting the (n+1)th recipe set from the packet. Additionally, processor PB identifies one or more parameters from a mapping between one or more parameters and one or more variables in the (n+1)th recipe set for subsystem B. A mapping between one or more parameters and one or more variables in the (n+1)th recipe set for subsystem B is stored in a memory device of subsystem B. Additionally, during the waiting time, the processor PC depacketizes the packet by parsing the packet containing the (n+1)th recipe set for subsystem C and extracting the (n+1)th recipe set from the packet. Additionally, the processor PC identifies one or more parameters from a mapping between one or more parameters and one or more variables in the (n+1)th recipe set for subsystem C. A mapping between one or more parameters and one or more variables in the (n+1)th recipe set for subsystem C is stored in a memory device of subsystem C.

In one embodiment, parsing a packet by a processor of a subsystem, extracting an (n+1)th recipe set from the packet, and mapping between one or more variables in the extracted (n+1)th recipe set. Identification of one or more parameters from is performed by the processor after receiving the recipe event signal 104, instead of during the waiting time to receive the recipe event signal 104.

In some embodiments where a non-packetized protocol is applied, depacketization needs to be performed by processor PA, processor PB, and processor PC to parse the packet and extract the (n+1)th recipe set from the packet. There is no

Master controller 106 generates recipe event signal 104. Recipe event signal 104 is transmitted from master controller 106 via communication media 192 and 194A to processor PA, and from master controller 106 via communication media 192 and 194B to processor PB. , and transmitted from master controller 106 to processor PC via communication media 192 and 194C.

Recipe event signal 104 represents the execution time te of the (n+1)th recipe sets by processor PA, processor PB, and processor PC. Execution time is the time when the recipe event signal 104 is received by processor PA, processor PB, and processor PC. For example, upon receipt of the recipe event signal 104, processor PA, processor PB, and processor PC switch to the corresponding drivers of subsystem A, subsystem B, and subsystem C to drive portions of the subsystems. Immediately execute the (n+1)th recipe sets by transmitting signals. Transmitting signals to the corresponding drivers is an example of execution of the (n+1)th recipe sets by processor PA, processor PB, and processor PC. For illustration, upon receipt of the recipe event signal 104, the processor PA immediately transmits a signal to the driver of subsystem A such that subsystem A generates an RF signal with a significant amount of power and/or frequency. The signal contains the value of the identified parameter from a mapping stored within subsystem A. As another example, the recipe event signal 104 acts as a trigger, e.g., an activation signal, etc., for the processor PA to send a signal to the driver of subsystem A, where the signal is identified from a mapping stored within subsystem A. Contains the values of the specified parameters. By way of example, during the same clock cycle, e.g., clock cycle C2, etc., that the recipe event signal 104 is received by the processor PA and/or transmitted by the master controller 106 to the processor PA, the processor PA Send a signal to the driver of system A. The signal contains the value of the identified parameter from a mapping stored within subsystem A.

As another example, upon receipt of the recipe event signal 104, processor PB transmits a signal to the driver of subsystem B to achieve a significant positive pressure or temperature within the plasma chamber. The signal contains the value of the identified parameter from a mapping stored within subsystem B. As another example, the recipe event signal 104 acts as a trigger, e.g., an activation signal, etc., for processor PB to send a signal to the driver of subsystem B, which signal is identified from a mapping stored within subsystem B. Contains the values of the specified parameters. As another example, during the same clock cycle that recipe event signal 104 is received by processor PB, e.g., clock cycle C2, etc., processor PB transmits a signal to the driver of subsystem B. The signal contains the value of the identified parameter from a mapping stored within subsystem B.

As yet another example, upon receipt of the recipe event signal 104, the processor PC sends a signal to the driver of subsystem C to achieve a significant gap between the upper and lower electrodes. The signal contains the value of the identified parameter from a mapping stored within subsystem C. As another example, the recipe event signal 104 acts as a trigger, e.g., an activation signal, etc., for the processor PC to send a signal to the driver of subsystem C, which signal is identified from a mapping stored within subsystem C. Contains the values of the specified parameters. As another example, during the same clock cycle that recipe event signal 104 is received by processor PC, e.g., clock cycle C2, etc., processor PC transmits a signal to the driver of subsystem C. The signal contains the value of the identified parameter from a mapping stored within subsystem C.

During the second clock cycle, e.g., clock cycle C2, time te, etc., signals from processor PA, processor PB, and processor PC are sent to the corresponding drivers of subsystem A, subsystem B, and subsystem C. is transmitted. The second clock cycle follows the first clock cycle. For example, the first clock cycle precedes the second clock cycle. As another example, the second clock cycle occurs one or more clock cycles preceding the first clock cycle. One or more clock cycles precede the second clock cycle. The second clock cycle and all clock cycles between the first and second clock cycles are cycles of the clock signal.

Recipe event signal 104 instructs execution of the (n+1)th recipe set. For example, during a time, e.g., a clock cycle, etc., a recipe event signal 104 is received by a processor of the subsystem from master controller 106, and the processor identifies based on the (n+1)th recipe set. The parameters are transmitted to the driver of the subsystem for processing. By way of example, the driver of the subsystem may be controlled by the pressure within the plasma chamber, or a significant amount of gas flow into the plasma chamber, or the temperature within the plasma chamber, or the gap between the upper and lower electrodes, or the capacitance of the capacitors of the impedance matching network, or Processes the signal received from the processor of the subsystem by driving the motor to achieve the inductance of the inductor of the impedance matching network. As another example, the driver of an RF generator can control the signal received from the digital signal processor (DSP) of the RF generator by generating drive signals to facilitate the generation of RF signals with significant amounts of power and frequency. Process. The RF signal is generated by the RF power supply of the RF generator. The RF power supply is connected to the driver. In some embodiments, the RF power supply is coupled to the driver through an amplifier that amplifies the current signal generated by the driver and provides the amplified current signal to the RF power supply. The RF power supply unit generates an RF signal upon receipt of the amplified current signal.

Recipe event signal 104 when received by a processor of a subsystem indicates immediate activation of execution of a recipe set by the processor. For example, when a recipe event signal 104 is received by the processor PA from the master controller 106 during a time, e.g., a clock cycle, etc., the processor PA immediately, e.g., during the same clock cycle, etc. While sending a signal to the driver of the subsystem to achieve the variables extracted from the (n+1)th recipe set for subsystem A.

It should be noted that in some embodiments, there is no relationship between the “first clock cycle” described above with reference to FIGS. 1AA and 1BA and the “first clock cycle” described above with reference to FIG. 1C. Similarly, there is no relationship between the “second clock cycle” described above with reference to FIGS. 1AA and 1BA and the “second clock cycle” described above with reference to FIG. 1C. The “first clock cycle” described above with reference to Figure 1C is independent of the “first clock cycle” described above with reference to Figures 1AA and 1BA, and similarly, the “second clock cycle” described above with reference to Figure 1C The “clock cycle” is independent of the “second clock cycle” described above with reference to FIGS. 1AA and 1BA.

In one embodiment, instead of the receiving and transmitting described above being performed by processor PA, processor PB, and processor PC, each of subsystem A, subsystem B, and subsystem C transceivers perform transmitting and receiving; Processor PA, processor PB, and processor PC perform the remaining operations described above for identifying parameters from the subsystem's memory devices based on the received variables in the (n+1)th recipe set. The subsystem's transceiver is connected to the subsystem's processor. The transceiver implements the physical layer to implement the communication protocol.

In various embodiments, recipe event signal 104 is transmitted from master controller 106 to subsystem A via transmission medium 172A. Recipe event signal 104 is also transmitted from master controller 106 to subsystem B via transmission medium 172B, and from master controller 106 to subsystem C via transmission medium 172C.

In some embodiments, the processor PA transmits an acknowledgment of receipt of each recipe set, e.g., the (n+1)th recipe set, etc., to master controller 106 via transmission medium 172A. Similarly, subsystem B transmits an acknowledgment of receipt of the recipe set to master controller 106 via transmission medium 172B. Subsystem controller C also transmits an acknowledgment of receipt of the recipe set to master controller 106 via transmission medium 172C.

In various embodiments, an acknowledgment is sent by the subsystem to the master controller 106 after receiving the recipe set. For example, an acknowledgment is sent by the subsystem to the master controller 106 after receiving the (n+1)th recipe set, and another acknowledgment is sent to the subsystem after receiving the (n+2)th recipe set. This is transmitted by the system to the master controller 106 and so on.

1D is a diagram of an embodiment of system 190 to illustrate synchronization between subsystem controller A, subsystem controller B, and subsystem controller C and subsystem A, subsystem B, and subsystem C. Processor PA, processor PB, and processor PC execute the (n+1)th recipe set from corresponding subsystem A, subsystem B, and subsystem C during a first clock cycle, e.g., cycle C1, time ts, etc. receive them. For example, processor PA receives the (n+1)th recipe set for subsystem A from subsystem controller A, and processor PB receives the (n+1)th recipe set for subsystem B from subsystem controller B. and the processor PC receives the (n+1)th recipe set for subsystem C from the subsystem controller C.

In some embodiments, subsystem controller A, subsystem controller B, and subsystem controller C include corresponding subsystem A, subsystem B, and and another controller, e.g., master controller 106, command controller 102 (FIG. 1aa), etc., or a clock source, e.g., to synchronize transmission of the (n+1)th recipe sets to subsystem C. For example, a clock signal from an oscillator, an oscillator with a PLL, etc. is provided. In various embodiments, the clock source is located within one of subsystem controller A, subsystem controller B, and subsystem controller C, and via one or more communication media to subsystem controller A, subsystem controller B, and subsystem controller C. It is connected to the remaining one of C.

Processor PA, processor PB, and processor PC signal a recipe event to transmit one or more parameters identified from the (n+1)th recipe sets to the corresponding drivers of subsystem A, subsystem B, and subsystem C. 104 waits until received from another controller, such as master controller 106 or command controller 102, etc. Note that the other controller transmits the recipe event signal 104 to processor PA over one or more communication media, to processor PB over one or more communication media, and to processor PC over one or more communication media. Upon receipt of the recipe event signal 104, processor PA transmits a signal containing the identified parameters using the mapping stored within memory device A of subsystem A to the driver of subsystem A. For example, during a second clock cycle, e.g., clock cycle C2, time te, etc., the recipe event signal 104 is received by the processor PA, and the processor PA determines the identified parameter using the mapping stored therein. The signal included is transmitted to the driver of subsystem A. Additionally, upon receipt of the recipe event signal 104, processor PB transmits a signal containing the identified parameters using the mapping stored within memory device B of subsystem B to the driver of subsystem B. For example, during the second clock cycle in which the recipe event signal 104 is received by processor PB, processor PB sends a signal containing the identified parameters using the mapping stored within subsystem B to the driver of subsystem B. do. Additionally, upon receipt of the recipe event signal 104, the processor PC transmits a signal containing the identified parameters to the driver of subsystem C using the mapping stored within memory device C of the subsystem. For example, during the second clock cycle in which the recipe event signal 104 is received by processor PC, processor PC transmits a signal containing the identified parameters using the mapping stored within subsystem C to the driver of subsystem C. do. The recipe event signal 104 is a trigger for transmitting a signal containing the value of the parameter from processor PA, processor PB, and processor PC, respectively, to corresponding drivers of subsystem A, subsystem B, and subsystem C. , for example, acts as an activation signal, etc.

Note that in some embodiments, there is no relationship between the “first clock cycle” described above with reference to Figures 1AA, 1B, or 1C and the “first clock cycle” described above with reference to Figure 1D. do. Similarly, there is no relationship between the “second clock cycle” described above with reference to FIGS. 1AA, 1BA, or 1C and the “second clock cycle” described above with reference to FIG. 1D. The “first clock cycle” described above with reference to Figure 1D is independent of the “first clock cycle” described above with reference to Figures 1AA, 1B, or 1C, and similarly, the “first clock cycle” described above with reference to Figure 1D The “second clock cycle” described above is independent of the “second clock cycle” described above with reference to FIGS. 1AA, 1BA, or 1C.

In some embodiments, processor PA transmits an acknowledgment of receipt of each recipe set, e.g., the (n+1)th recipe set, etc., to subsystem controller A via transmission medium 114A. Similarly, processor PB transmits an acknowledgment of receipt of to subsystem controller B via transmission medium 114B. Additionally, processor PC transmits an acknowledgment of receipt of the recipe set to subsystem controller C via transmission medium 114C.

In various embodiments, an acknowledgment is sent by the subsystem to a corresponding subsystem controller coupled to the subsystem. A receipt is sent after receipt of each recipe set. For example, an acknowledgment is sent by processor PA to subsystem controller A after receiving the (n+1)th recipe set, and another acknowledgment is sent to processor PA after receiving the (n+2)th recipe set. is transmitted to subsystem controller A, and so on.

1E is a diagram of an embodiment of system 151 to illustrate synchronization between user interface (UI) computer 153 and RF generator controllers 155A, 155B, and 155C. UI computer 153 is an example of computing device 108 of Figure 1AA. Additionally, RF generator controller 155A is an example of subsystem controller A (Figure 1aa), RF generator controller 155B is an example of subsystem controller B (Figure 1aa), and RF generator controller 155C is an example of subsystem controller 155C. This is an example of controller C (Figure 1aa). System 151 further includes RF Generator 1, RF Generator 2, and RF Generator 3. RF generator 1 is labeled RFG1, RF generator 2 is labeled RFG2, and RF generator 3 is labeled RFG3. RF generator 1 is an example of an x MHz RF generator, RF generator 2 is an example of a y MHz RF generator, and RF generator 3 is an example of a z MHz RF generator.

The functionality of system 151 is illustrated with reference to FIG. 2B. As shown in FIG. 2B, the UI computer 153 connects the master-master controller through a transmission medium by applying the Ethernet protocol and Transmission Control Protocol (TCP)/Internet Protocol (IP) or User Datagram Protocol (UDP)/IP. The (n+1)th recipe sets are transmitted to the master controller 106 via. In one embodiment, system 151 excludes a master-master controller. In one embodiment, master controller 106 performs the functions performed by a master-master controller.

Master controller 106 transmits the (n+1)th recipe set for RF generator 2 to RF generator controller 155B such that the (n+1)th recipe set for RF generator 1 is transmitted to RF generator controller 155A. and apply the TCP/IP protocol or UDP/IP protocol and the Ethernet protocol to transmit the (n+1)th recipe set for RF generator 3 to the RF generator controller 155C. For example, referring again to FIG. 1E, the (n+1)th recipe set for RF generator 1 is transferred from master controller 106 to RF generator controller 155A via switch 157. As another example, as shown in FIG. 1E, the (n+1)th recipe set for RF generator 2 is transferred from master controller 106 to RF generator controller 155B via switch 157. As yet another example, as shown in FIG. 1E, the (n+1)th recipe set for RF generator 3 is transferred from master controller 106 to RF generator controller 155C via switch 157. An example of switch 157 is described in US patent application Ser. No. 14/974,915.

Referring to FIG. 2B, upon receiving the (n+1)th recipe sets from master controller 106, RF generator controllers 155A, 155B, and 155C generate the (n+1)th recipe sets corresponding to the RF generator. 1, RF Generator 2, and RF Generator 3 wait to receive a recipe event signal from UI computer 153 before transmitting. Referring back to FIG. 1E , a signal generator 159, e.g., a digital pulse signal generator, an analog pulse signal generator, a processor, etc., is coupled to the UI computer 153 via an I/O (input/output) interface. do. Signal generator 159 generates general-purpose I/O (GPIO) signals, e.g., digital signals, analog signals, etc., and operates as a master-master controller and corresponding RF generator controllers 155A, 155B, and 155C. ) provides signals to the RF generator controllers 155A, 155B, and 155C through the corresponding GPIO pins. A GPIO signal is an example of a recipe event signal 104. In some embodiments, signal generator 159 is located within UI computer 153. In some embodiments, a GPIO signal is generated when input, e.g., selection, click, etc., is received by UI computer 153 from a user via an input device. An input device is a peripheral device connected to the UI computer 153.

2B, upon receiving the GPIO signal, e.g., during the same clock cycle as receiving the GPIO signal, RF generator controller 155A generates the (n+1)th recipe set for RF generator 1. Apply the Ethernet protocol and UDP/IP protocol to transmit to RF generator 1, and RF generator controller 155B apply the Ethernet protocol and UDP/IP to transmit the (n+1)th recipe set for RF generator 2 to RF generator 2. Apply the protocol, and RF generator controller 155C applies the Ethernet protocol and UDP/IP protocol to transmit the (n+1)th recipe set for RF generator 3 to RF generator 3.

2AA is an embodiment of a timing diagram 200 to illustrate synchronization between transmitting (n+1)th recipe sets to controllers and execution time of the recipe sets by the controllers. Timing diagram 200 shows the (n+1)th packet, (n+2)th packet, and (n+3)th packet being transmitted from master controller 106 to subsystem controller A (FIG. 1aa) in series 202A. shows. Additionally, timing diagram 200 shows the (n+1)th packet, (n+2)th packet, and (n+3)th packet being transmitted from master controller 106 to subsystem controller B (FIG. 1aa). Shows series 202B. Additionally, timing diagram 200 shows the (n+1)th packet, (n+2)th packet, and (n+3)th packet being transmitted from master controller 106 to subsystem controller C (FIG. 1aa). Shows series 202C.

In one embodiment illustrated with reference to FIG. 1C, series of packets 202A are transmitted from master controller 106 to subsystem A, series of packets 202B are transmitted from master controller 106 to subsystem B, and packets Series 202C of these is transmitted from master controller 106 to subsystem C.

In one embodiment illustrated with reference to FIG. 1D , series of packets 202A are transmitted from subsystem controller A to subsystem A, series of packets 202B are transmitted from subsystem controller B to subsystem B, and series of packets 202C is transmitted from subsystem controller C to subsystem C.

Timing diagram 200 further includes pulsed signal 204A, which is an example of recipe event signal 104. Timing diagram 200 may be generated by a clock source located external to master controller 106 or command controller 102 or master controller 106 or by a clock source located external to command controller 102 (FIG. 1aa). Includes clock signal 202.

In some embodiments, the pulse at time te1 of pulsed signal 204A is an example of recipe event signal 104.

At time ts1, the (n+1)th packets for subsystem A, subsystem B, and subsystem C are transmitted by one or more controllers as described herein. At execution time te1, a digital pulse is received by one or more controllers as described herein to indicate that the (n+1)th packets are to be executed. Additionally, at time ts2, which coincides with time te1, the (n+2)th packets for subsystem A, subsystem B, and subsystem C are transmitted by one or more controllers as described herein. During execution time te2, a digital pulse is received by one or more controllers as described herein to indicate that the (n+2)th packets are executed by one or more controllers as described herein. Additionally, at time ts3, which coincides with time te2, the (n+3)th packets for subsystem A, subsystem B, and subsystem C are transmitted by one or more controllers as described herein. During execution time te3, a digital pulse is received by one or more controllers as described herein to indicate that the (n+3)th packets are to be executed by one or more controllers.

In some embodiments, a processor, such as processor PA, or processor PB, or processor PC, etc., is located within a controller.

Occurs during the first clock cycle C1 of clock signal 202, time te1 and time ts2 occur during the second clock cycle C2 of clock signal 202, and time te2 and time ts3 occur during the third clock cycle of clock signal 202. Note that this occurs during C3, and that time te3 occurs during the fourth clock cycle C4 of clock signal 202.

It should also be noted that in some embodiments, the first clock cycle described with reference to FIGS. 1AA, 1BA, 1C, and 1D, respectively, is an example of the first clock cycle described with reference to FIG. 2AA. Additionally, in these embodiments, the second clock cycle described with reference to FIGS. 1AA, 1BA, 1C, and 1D, respectively, is an example of the second clock cycle described with reference to FIG. 2AA.

Note that in various embodiments, the size of the packets shown in Figure 2aa are different. For example, the (n+1)th packet of series 202A for subsystem A is a payload of a larger size or a smaller payload than the size of the (n+1)th packet of series 202B for subsystem B. has Additionally, the (n+1)th packet of the series 202B for subsystem B has a larger or smaller payload size than the (n+1)th packet of the series 202C for subsystem C.

2AB is an embodiment of a timing diagram 210 to illustrate that the execution time of a packet by a controller varies from the time the packet is received by the controller to a later time when a digital pulse indicating that the packet is to be executed is received. . The digital pulse is a pulse of the digital pulse signal 212, which is an example of the recipe event signal 104. In some embodiments, the pulse at time te1 of pulsed signal 212 is an example of recipe event signal 104.

As shown in the timing diagram, execution time te2 shown in Figure 2ab occurs before execution time te2 shown in timing diagram 200 (Figure 2aa). For example, execution time te2 shown in Figure 2ab does not occur simultaneously with time ts3, but occurs before time ts3. As another example, execution time te2 occurs between the time the (n+2)th packet is received and the completion of reception of the (n+3)th packet.

In some embodiments, execution time te1 shown in Figure 2ab occurs before execution time te1 shown in timing diagram 200 (Figure 2aa). For example, execution time te1 shown in Figure 2ab does not occur simultaneously with time ts2, but occurs before time ts2. As another example, execution time te1 occurs between the time the (n+1)th packet is received and the completion of reception of the (n+2)th packet.

In some embodiments, the digital pulse of pulsed signal 212 is transmitted within a predetermined time interval after receiving acknowledgments of receipt of the recipe sets from all controllers that have received the recipe sets. For example, the digital pulse of pulsed signal 212 may be configured to receive acknowledgments for receipt of (n+1)th recipe sets and to receive acknowledgments for receipt of (n+2)th recipe sets. transmitted between. For illustration purposes, command controller 102 receives acknowledgments of receipt of the (n+1)th recipe sets from subsystem controller A, subsystem controller B, and subsystem controller C via master controller 106. Then, the first digital pulse of the recipe event signal 104 is transmitted to the master controller 106 at time te1 within the predetermined time interval. The (n+1)th recipe sets are received from master controller 106 by subsystem controller A, subsystem controller B, and subsystem controller C. Acknowledgments of receipt of the (n+1)th recipe sets are sent from subsystem controller A, subsystem controller B, and subsystem controller C to master controller 106, which receives (n+1) Acknowledgments of receipt of the first recipe sets are sent to the command controller 102. For the sake of illustration, an acknowledgment of receipt of the recipe set is transmitted from subsystem controller A via transmission medium to master controller 106, which then transmits the acknowledgment to command controller 102 via transmission medium 112. ) and send it to . Additionally, the command controller 102, after receiving acknowledgments of receipt of the (n+2)th recipe sets, from subsystem controller A, subsystem controller B, and subsystem controller C via master controller 106. , transmitting the second digital pulse of the recipe event signal 104 to the master controller 106 at time te2 within the predetermined time interval. The (n+2)th recipe sets are received from master controller 106 by subsystem controller A, subsystem controller B, and subsystem controller C. Acknowledgments of receipt of the (n+2)th recipe sets are sent from subsystem controller A, subsystem controller B, and subsystem controller C to master controller 106, which receives (n+2) Acknowledgments of receipt of the first recipe sets are sent to the command controller 102. In some embodiments, acknowledgments of receipt of recipe sets are transmitted from subsystem controller A to command controller 102 via communication media 122A, 124, and 126, and acknowledgments of receipt of recipe sets are transmitted from subsystem controller A to command controller 102. are transmitted from system controller B to command controller 102 over communication media 122B, 124, and 126, and acknowledgments of receipt of the recipe sets are transmitted from subsystem controller C to command controller 102 over communication media (122B, 124, and 126). 122C, 124, and 126).

As another example, master controller 106, after receiving acknowledgments of receipt of the (n+1)th recipe sets from subsystem controller A, subsystem controller B, and subsystem controller C, performs a predetermined time interval. Transmits the first digital pulse of the recipe event signal 104 to subsystem controller A, subsystem controller B, and subsystem controller C at time te1 within. Additionally, the master controller 106, after receiving acknowledgments of receipt of the (n+2)th recipe sets from subsystem controller A, subsystem controller B, and subsystem controller C, at time te2 within the predetermined time interval. The second digital pulse of the recipe event signal 104 is transmitted to subsystem controller A, subsystem controller B, and subsystem controller C. In some embodiments, the acknowledgment is transmitted from the subsystem controller to the master controller 106 via a transmission medium that couples the subsystem controller to the master controller 106. In various embodiments, the acknowledgment is transmitted from the subsystem controller to the master controller 106 via one or more communication media connecting the subsystem controller to the master controller 106. As another example, master controller 106, after receiving acknowledgments of receipt of the (n+1)th recipe sets from processor PA, processor PB, and processor PC, generates a recipe event at time te1 within a predetermined time interval. The first digital pulse of signal 104 is transmitted to processor PA, processor PB, and processor PC. Additionally, the master controller 106, after receiving acknowledgments of receipt of the (n+2)th recipe sets from processor PA, processor PB, and processor PC, sends the recipe event signal 104 at time te2 within the predetermined time interval. ) transmits the second digital pulse to processor PA, processor PB, and processor PC. In some embodiments, the acknowledgment is transmitted from the subsystem to master controller 106 via a transmission medium that couples the subsystem to master controller 106. In various embodiments, the acknowledgment is transmitted from the subsystem to the master controller 106 via one or more communication media connecting the subsystem to the master controller 106. As still another example, the subsystem controller, after receiving acknowledgment of receipt of the (n+1)th recipe set from the processor, sends the first digital pulse of the recipe event signal 104 at time te1 within a predetermined time interval. is transmitted to the processor of the subsystem. Additionally, the subsystem controller, after receiving acknowledgment of receipt of the (n+2)th recipe set from the processor, sends a second digital pulse of the recipe event signal 104 at time te2 within the predetermined time interval to the subsystem. sent to the processor.

In some embodiments, a predetermined time interval is received from the user via an input device. For example, the predetermined time interval is the time interval between two consecutive packets, for example, the (n+1)th packet and the (n+2)th packet, etc.

In various embodiments, the digital pulse of pulsed signal 212 transmits a recipe set from a transmit controller to one or more receive controllers without the transmit controller receiving one or more acknowledgments from the corresponding one or more receive controllers. Transmission is made from the transmission controller based on a predetermined amount of time taken. One or more receive controllers are coupled to the transmit controller. For example, a predetermined amount of time taken to communicate a recipe set from a transmitting controller to one or more receiving controllers may be x units, e.g. It is provided to the transmission controller by . After every x units, the transmit controller transmits a pulse of pulsed signal 212 to one or more receive controllers. An example of a transmitting controller is command controller 102 when the one or more receiving controllers are subsystem controller A, subsystem controller B, and subsystem controller C. Another example of a transmitting controller is the master controller 106 when one or more receiving controllers are subsystem controller A, subsystem controller B, and subsystem controller C. Still another example of a transmitting controller is the master controller 106 when one or more receiving controllers are processor PA, processor PB, and processor PC.

In various embodiments, a predetermined amount of time taken to transmit a recipe set from a transmitting controller to one or more receiving controllers is determined by the transmitting controller during a learning routine. For example, a transmit controller transmits packets with various sizes, e.g., different recipe sets of bits, as payload, etc., to one or more receive controllers. The transmission controller determines the longest amount of time taken to transmit the largest size packet among packets of various sizes, and determines the longest amount of time with a predetermined amount of time.

In some embodiments, time te2 is between time ts3 and the reception time of the (n+2)th packets by one or more reception controllers.

FIG. 2B is the timing diagram 230 described above with reference to FIG. 1E.

3A is a diagram of an embodiment of an Ethernet packet 300. The Ethernet packet 300 includes a preamble field, a frame start partition field, a destination media access control (MAC) address field, a source MAC address field, an Ethernet type field, a payload field, a frame check sequence (FCS) field, and an inter-packet gap. Includes. The Preamble field and Frame Start section field are populated to indicate the start of an Ethernet frame. The Ethernet frame includes a destination MAC address field, a source MAC address field, an Ethernet type field, a payload field, and an FCS field.

The MAC destination address field represents a network interface for receiving the Ethernet packet 300, e.g., the network interface of master controller 106, or the network interface of subsystem controller A, or the network interface of subsystem controller B, or the network interface of subsystem controller 106. and an address that uniquely identifies the network interface of system controller C, or the network interface of subsystem A, or the network interface of subsystem B, or the network interface of subsystem C, etc. Examples of network interfaces include network interface controllers, network interface cards, etc.

A network interface of master controller 106 is coupled to one or more transmission media and a processor of master controller 106. For example, the network interface of master controller 106 is coupled to transmission media 110A, 110B, and 110C (Figure 1aa). As another example, the network interface of master controller 106 is coupled to transmission media 164A, 164B, and 164C (Figure 1Ba). As yet another example, the network interface of master controller 106 is coupled to transmission media 172A, 172B, and 172C (Figure 1C).

Similarly, the network interface of the subsystem controller is coupled to one or more transmission media and the processor controller of the subsystem. For example, the network interface of subsystem controller A is coupled to transmission media 110A and 114A (Figure 1aa), and the network interface of subsystem controller B is coupled to transmission media 110B and 114B (Figure 1aa). ), and the network interface of subsystem controller C is connected to transmission media 110C and 114C (FIG. 1aa).

Additionally, the subsystem's network interface is coupled to one or more transmission media and to the subsystem's processor. For example, subsystem A's network interface is coupled to transmission medium 114A (Figure 1aa), subsystem B's network interface is coupled to transmission medium 114B (Figure 1aa), and subsystem C's network The interface is connected to transmission medium 114C (FIG. 1aa). As another example, the network interface of subsystem A is coupled to transmission medium 172A (FIG. 1C), the network interface of subsystem B is coupled to transmission medium 172B (FIG. 1C), and the network interface of subsystem C is coupled to transmission medium 172B (FIG. 1C), and The network interface is connected to transmission medium 172C (FIG. 1C).

In one embodiment, the network interface is a controller described herein, such as master controller 106, or subsystem controller A, or subsystem controller B, or subsystem controller C, or processor PA, or processor PB. , or is implemented in a processor PC, etc.

The MAC source address field contains an address that uniquely identifies the network interface transmitting the Ethernet packet 300. The Ethernet Type field contains data to indicate the length of the payload or the protocol encapsulated within the payload, such as Internet Protocol version 4, Apple Talk™, etc. The payload field may contain a different number of bits for one or more recipe sets, e.g., (n+1)th recipe set, (n+2)th recipe set, (n+3)th recipe set, etc. For example, it can accommodate a range from 42 octets to 1500 octets, etc. The FCS field is used to check the integrity of the frame. Interpacket gap is the idle time between two consecutive packets.

3B is a diagram of an embodiment to illustrate a packet 320, e.g., a datagram, etc. Packet 320 includes fields including a header field and a payload field, such as a recipe set, etc. The header field is a field for the identity of the source address to which the packet 320 is sent, e.g., the address of the network interface, etc., and the identity of the destination address designated to receive the packet 320, e.g., the address of the network interface. , etc., a field for the combined length of the header and the combined length of the payload attached to the header, and a field for the checksum value.

In various embodiments, packet 320 is generated using a communication protocol, e.g., customized to exclude a source address field to identify a source address and a destination address field to identify a destination address, etc. do. In point-to-point communication, there is no need to identify the source address and destination address. The exclusion increases the data rate between the master controller 106 and the subsystem controllers connected to the master controller 106, or between the subsystem controller and the subsystems connected to the subsystem controller, or between the master controller and the subsystems connected to the master controller. .

In some embodiments, the header is customized to exclude fields for the checksum value and/or fields for the combined length of the header and the combined length of the payload, e.g., created using a customized communication protocol, etc. do. The exclusion increases the data rate between the master controller 106 and the subsystem controllers connected to the master controller 106, or between the subsystem controller and the subsystems connected to the subsystem controller, or between the master controller and the subsystems connected to the master controller. .

In various embodiments, the checksum value is generated by the network interface transmitting packet 320. The checksum value is generated from the payload of packet 320, or the header of packet 320, or a combination thereof. The checksum value is calculated by the receiver of the packet 320, e.g., the destination network interface, etc., to determine whether the payload and/or header of the packet 320 changes during transfer from the sending network interface to the receiving network interface. It is compared with another checksum value.

In some embodiments, a datagram, eg, a UDP datagram, etc., is embedded within an IP packet, and the IP packet is also embedded within an Ethernet packet.

In various embodiments, packet 320 is created using customization, e.g., a customized protocol, etc., such that fields are in different positions than shown in FIG. 3B. For example, the field for payload comes before the field for length. As another example, the field for the destination address is before the field for the source address or after the field for the length. The customized protocol is applied by the physical layer creating one or more customized packets.

4 is a diagram of an embodiment of a plasma processing system 400. Plasma processing system 400 includes master controller 106, x MHz RF generator, y MHz RF generator, z MHz RF generator, subsystem controller A, subsystem controller B, and subsystem controller C. The plasma processing system 400 also includes an impedance matching network 402 and a plasma chamber 404.

In one embodiment, instead of an x MHz RF generator, a kHz RF generator is used.

Upon receipt of the (n+1)th recipe set, the x MHz RF generator generates an RF signal. For example, an RF signal generated by an x MHz RF generator has a significant amount of power and/or a significant amount of frequency specified in the (n+1)th recipe set received by the x MHz RF generator. Similarly, upon receipt of the (n+1)th recipe set, the y MHz RF generator generates an RF signal and upon receipt of the (n+1)th recipe set, the z MHz RF generator generates an RF signal. For example, an RF signal generated by a y MHz RF generator has a significant amount of power and/or a significant amount of frequency specified in the (n+1)th recipe set received by the y MHz RF generator. As another example, the RF signal generated by the z MHz RF generator has a significant amount of power and/or a significant amount of frequency specified in the (n+1)th recipe set received by the z MHz RF generator. RF signals are provided to impedance matching network 402 via corresponding RF cables 406A, 406B, and 406C. Impedance matching network 402 matches the impedance of a load connected to the output of impedance matching network 402 with the impedance of a source connected to one or more inputs of impedance matching network 402 to generate a modified RF signal. For example, impedance matching network 402 matches the impedances of plasma chamber 404 and RF transmission line 408 and RF cables 406A, 406B, and 406C, x MHz RF generator, y MHz RF generator, and z Match the impedance of the MHz RF generator.

The modified RF signal is transmitted to the lower electrode 410 of the plasma chamber 404 via RF transmission line 408. The lower electrode 410 is part of a chuck, such as an electrostatic chuck (ESC), etc. The upper electrode 412 of the plasma chamber 404 faces the lower electrode 410 and is located opposite the lower electrode 410. Each of the upper electrode 412 and the lower electrode 410 is made of a metal, such as aluminum, an alloy of aluminum, etc.

When the process gas is supplied to the plasma chamber 404 and the modified RF signal is supplied to the lower electrode, the plasma is struck or transferred to the plasma chamber 404 to process the wafer 416 placed on the upper surface of the lower electrode 410. ) is maintained within.

FIG. 5 is a diagram of an embodiment of a system to illustrate subsystem 500, e.g., subsystem A, or subsystem B, or subsystem C, etc. Subsystem 500 includes a processor 502, such as processor PA, processor PB, processor PC, etc. Processor 502 is coupled to driver 504, such as one or more transistors, one or more current generating devices, etc. The driver is connected to a mechanical or electrical part 506. Examples of component 506 include a motor or amplifier.

When subsystem 500 is an RF generator, component 506 includes an amplifier coupled to an RF power supply. Additionally, when subsystem 500 is a pressure subsystem, or gap subsystem, or gas flow subsystem, or coolant flow subsystem, component 506 is a motor.

Processor 502 generates signals that are provided to driver 504. Upon receiving a signal from processor 502, driver 504 generates a drive signal that is provided to component 506 to operate component 506. When component 506 is a motor, the motor controls the amount by which the valves of the coolant flow subsystem open and close, or the amount by which the valves of the gas flow subsystem open and close, or the amount by which the confinement rings open and close, or the amount by which the upper electrode 412 (see 4) Control the amount of gap between and lower electrode 410 (FIG. 4). When component 506 is a heater, the heater heats when driver 504 supplies a current signal to the heater. When component 506 is an amplifier, the amplifier generates an amplified signal upon receipt of a current signal from driver 504 and the amplified signal is provided to an RF power supply to generate an RF signal.

FIG. 6 is a diagram of an embodiment of a system for illustrating a plasma chamber 626, which is an example of plasma chamber 404 (FIG. 4). The system includes a plasma reactor 620 and an RF transmission line 624, which is an example of an RF transmission line 408 (FIG. 4). RF transmission line 624 is connected to plasma reactor 620. RF transmission line 624 includes an RF load 661 and an RF tunnel 662. RF load 661 is used to facilitate transmission of modified RF signals received from impedance matching network 402 (FIG. 4).

The plasma reactor 620 includes a plasma chamber 626 and an RF cylinder 610, where the RF cylinder 610 is connected to an RF rod 661 via an RF strap 668. Plasma reactor 620 further includes RF straps 674 and 677, ground shield 680, and bottom electrode housing 676.

The plasma chamber 626 includes an upper electrode 660, an upper electrode extension 628, a C-shroud 670, a ground ring 672, and a chuck assembly. The chuck assembly includes a chuck 658 and a fixture plate 630. Top electrode 660 is an example of top electrode 412 (FIG. 4). Substrate 416 is placed on top of chuck 658 for processing substrate 416 . Examples of substrate 416 processing include cleaning of the substrate 416, or etching of the substrate 416, or etching of oxides on top of the substrate 416, or processing of materials, e.g., oxides, dioxides, Resist materials, etc. may be deposited on the substrate 416, or combinations thereof.

C-shroud 670 includes slots used to control the pressure within plasma chamber 626. For example, the slots are opened to increase gas flow through the slots to reduce the gas pressure in gap 671 of plasma chamber 626. The slots are closed to reduce gas flow to raise the gas pressure in gap 671.

In various embodiments, bottom electrode housing 676 is any shape, such as cylindrical, square, polygonal, etc.

In various embodiments, the RF cylinder 610 is not cylindrical, but has a polygonal shape, eg, a rectangular shape, a square shape, etc.

Upper electrode extension 628 surrounds upper electrode 660. C-shroud 670 includes portions 670A and 670B. Ground ring 672 includes a ground ring portion 672A and another ground ring portion 672B. Bottom electrode housing 676 includes a bottom electrode housing portion 676A, another bottom electrode housing portion 676B, and still another bottom electrode housing portion 676C. Bottom electrode housing portions 676A and 676B each form a side wall of bottom electrode housing 676. Bottom electrode housing 676C forms the bottom wall of bottom electrode housing 676. Ground shield 680 includes shield 680A and another shield 680B.

The top surface of chuck 658 faces the bottom surface 636 of top electrode 660. The plasma chamber 626 is surrounded by an upper electrode 660 and an upper electrode extension 628. Plasma chamber 626 is also surrounded by C-shroud 670, and chuck 658.

Ground ring 672 is located below C-shroud 670. In some embodiments, ground ring 672 is located below C-shroud 670 and adjacent to C-shroud 670. Return RF strap 674 is connected to ground ring portion 672A and return RF strap 677 is connected to ground ring portion 672B. The return RF strap 674 is connected to the lower electrode housing portion 676A and the return RF strap 677 is connected to the lower electrode housing portion 676B. The lower electrode housing portion 676A is connected to the shield portion 680A and the lower electrode housing portion 676B is connected to the shield portion 680B. The shield 680A is connected to the RF tunnel 662 through the lower electrode housing portion 676A, and the shield 680B is connected to the grounded RF tunnel 662 through the lower electrode housing portion 676C.

In some embodiments, bottom electrode housing portion 676 is a cylinder surrounding RF cylinder 610. RF cylinder 610 is a medium for the passage of modified RF signals. The modified RF signal is transmitted to the bottom of chuck 658 through RF rod 661, RF strap 668, and RF cylinder 610 to generate or maintain a plasma within gap 671 of plasma chamber 626. supplied to the electrode. A gap 671 is formed between the upper electrode 660 and the lower electrode of the chuck 658.

In some embodiments, top electrode 660 is grounded.

In various embodiments, instead of RF strap 668, multiple RF straps are used to connect RF cylinder 610 to RF rod 661.

In one embodiment, instead of the C-shroud 670, confinement rings are provided to control the exit of gases from the plasma chamber 626 to further control the pressure within the plasma chamber 626.

It should be noted that in some of the above-described embodiments, the modified RF signal is provided to the lower electrode 410 (Figure 4) and the upper electrode 412 (Figure 4) is grounded. In various embodiments, the modified RF signal is provided to the upper electrode 412 and the lower electrode 410 is grounded.

In one embodiment, functions described herein as being performed by one processor are performed by a plurality of processors, e.g., distributed among the plurality of processors.

In one embodiment, functions described herein as being performed by one controller are performed by, e.g., distributed among, multiple controllers.

In some embodiments, functions described herein as being performed by a plurality of controllers are performed by one controller.

Embodiments described herein may be practiced in a variety of computer system configurations, including portable hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics products, minicomputers, mainframe computers, and the like. Embodiments described herein can also be practiced in distributed computing environments, where tasks are performed by remote processing hardware units that are linked through a computer network.

In some embodiments, a controller may be part of a system that may be part of the examples described above. The system may include semiconductor processing equipment, including a processing tool or tools, a chamber or chambers, a platform or platforms for processing, and/or specific processing components (wafer pedestal, gas flow system, etc.). The system is integrated with electronics to control its operation before, during and after processing of a semiconductor wafer or substrate. Electronic devices are referred to as “controllers” that may control various components or sub-parts of the system. The controller controls delivery of process gases, temperature settings (e.g., heating and/or cooling), pressure settings, vacuum settings, and power settings, depending on the processing requirements and/or type of system. , RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and motion settings, tools and other transfer tools and/or connection to this system. Programmed to control any of the processes disclosed herein, including wafer transfers into and out of loaded or interfaced loadlocks.

Generally speaking, in various embodiments, a controller may include various integrated circuits, logic, etc., that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. It is defined as an electronic device having , memory, and/or software. Integrated circuits include chips in the form of firmware that store program instructions, digital DSPs, chips defined as ASICs, PLDs, one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Includes. Program instructions are instructions delivered to the controller in the form of various individual settings (or program files) that specify operating parameters for executing a process on or for a semiconductor wafer. In some embodiments, operating parameters may be used to achieve one or more processing steps during fabrication of dies of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or wafers. It is part of a recipe prescribed by the engineer.

The controller, in some embodiments, is coupled to or part of a computer that may be integrated into the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be all or part of a fab host computer system or within the “cloud” enabling remote access to wafer processing. The controller monitors the current progress of manufacturing operations, examines the history of past manufacturing operations, examines trends or performance metrics from a plurality of manufacturing operations, changes parameters of the current processing, and performs processing steps following the current processing. Enables remote access to the system to configure, or start new processes.

In some embodiments, a remote computer (e.g., a server) provides process recipes to the system over a computer network, including a local network or the Internet. The remote computer includes a user interface that enables entry or programming of parameters and/or settings to be subsequently transferred to the system from the remote computer. In some examples, the controller receives instructions in the form of settings for processing a wafer. It should be understood that these settings are specific to the type of tool the controller is controlling or interfacing with and the type of process to be performed on the wafer. Accordingly, as described above, a controller may be distributed, comprising one or more separate controllers that are networked together to cooperate for a common purpose, such as carrying out the processes described herein. An example of a distributed controller for this purpose is one or more integrated circuits in the chamber that communicate with one or more remotely located integrated circuits (e.g., at the platform level or as part of a remote computer) that combine to control processes within the chamber. Contains circuits.

Without limitation, in various embodiments, the system may include a plasma etch chamber or module, a deposition chamber, a spin-rinse chamber, a metal plating chamber, a clean chamber, a bevel edge etch chamber, a physical vapor deposition (PVD) chamber, a chemical vapor deposition (CVD) chamber, deposition) chamber, atomic layer deposition (ALD) chamber, atomic layer etch (ALE) chamber, ion implantation chamber, track chamber, and any other semiconductor processing used or associated in the fabrication and/or fabrication of semiconductor wafers. Includes chamber.

Although the operations described above have been described with reference to a parallel plate plasma chamber, e.g., a capacitively coupled plasma chamber, etc., in some embodiments, the operations described above can be applied to other types of plasma chambers, e.g., an ICP. It should also be noted that it is applied to an inductively coupled plasma (TCP) reactor, a plasma chamber including a TCP (transformer coupled plasma) reactor, conductor tools, dielectric tools, a plasma chamber including an ECR (electron cyclotron resonance) reactor, etc. For example, the x MHz RF generator, y MHz RF generator, and z MHz RF generator are coupled to an inductor in the ICP plasma chamber through an impedance matching network.

As described above, depending on the process operation to be performed by the tool, the controller may control other tool circuits used in material transfer to move containers of wafers to and from tool locations and/or load ports within the semiconductor fabrication plant. Communicates with one or more of the following: fields or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, the main computer, or another controller or tools.

With the above embodiments in mind, it will be appreciated that some embodiments employ various computer-implemented operations involving data stored within computer systems. These computer-implemented operations are operations that manipulate physical quantities.

Some embodiments also relate to hardware units or devices for performing these operations. The device consists inter alia of a special purpose computer. When defined as a special purpose computer, the computer performs other processing, program execution, or routines that are not part of the special purpose, while still being able to operate for the special purpose.

In some embodiments, the operations described herein are selectively performed by an activated computer, configured by one or more computer programs stored in computer memory, or obtained over a computer network. When data is obtained over a computer network, the data may be processed by other computers on the computer network, eg, a cloud of computing resources.

One or more embodiments described herein may be produced as computer readable code on a non-transitory computer-readable medium. A non-transitory computer-readable medium is any data storage hardware unit, such as a memory device, etc., that stores data that is later read by a computer system. Examples of non-transitory computer-readable media include hard drives, network attached storage (NAS), read-only memory (RAM), random-access memory (ROM), compact disc-ROMs (CD-ROMs), and CD-Rs ( CD-recordables), CD-RWs (CD-rewritables), magnetic tapes, and other optical and non-optical data storage hardware units. In some embodiments, non-transitory computer-readable media includes tangible computer-readable media distributed over a network coupled computer system such that computer readable code is stored and executed in a distributed manner.

Although some of the method operations described above are presented in a particular order, in various embodiments, other housekeeping operations are performed between the method operations, the method operations are coordinated so that the operations occur at slightly different times, or at various intervals. It should be understood that the method operations may be distributed within the system causing them to occur, or may be performed in a different order than that described above.

It is also noted that, in one embodiment, one or more features from any of the embodiments described above are combined with one or more features of any other embodiment without departing from the scope described in the various embodiments described in this disclosure. do.

Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be made within the scope of the appended claims. Accordingly, the present embodiments are to be considered illustrative and non-limiting, and the embodiments are not limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.

Claims (20)

a first subsystem controller;
a second subsystem controller;
a first subsystem coupled to the first subsystem controller; and
a second subsystem coupled to the second subsystem controller,
the first subsystem controller is configured to transmit a first recipe set to the first subsystem, and the second subsystem controller is configured to transmit a second recipe set to the second subsystem,
wherein the first subsystem is configured to execute the first recipe set upon receiving an event signal, and the second subsystem is configured to execute the second recipe set upon receiving the event signal. According to claim 1,
The first subsystem controller is configured to transmit the first recipe set to the first subsystem during a first clock cycle, and the second subsystem controller is configured to transmit the second recipe set to the first subsystem during the first clock cycle. A system configured to transmit to a second subsystem. According to claim 2,
The system of claim 1, wherein the event signal is received during a second clock cycle following the first clock cycle. According to claim 3,
The event signal indicates an execution time of the first recipe set and the second recipe set, the execution time occurring during the second clock cycle. According to claim 1,
The system wherein the first subsystem controller and the second subsystem controller are configured to be coupled to another controller. According to claim 5,
The system wherein the event signal is received from the another controller. According to claim 1,
The first subsystem includes a first radio frequency (RF) generator and the second subsystem includes a second RF generator, the second RF generator generating a different frequency than the first RF generator. Having, system. According to claim 7,
The first recipe set includes the amount of power and frequency of the RF signal to be generated by the first RF generator, and the second recipe set includes the amount of power of the RF signal to be generated by the second RF generator. and a quantity of frequency. a first subsystem configured to receive a first recipe set from a first subsystem controller via a first link; and
a second subsystem configured to receive a second recipe set from a second subsystem controller via a second link;
wherein the first subsystem is configured to execute the first recipe set upon receiving an event signal, and the second subsystem is configured to execute the second recipe set upon receiving the event signal. According to clause 9,
The system wherein the first recipe set is received during a first clock cycle, and the second recipe set is received during the first clock cycle. According to claim 10,
The system of claim 1, wherein the event signal is received during a second clock cycle following the first clock cycle. According to claim 11,
The event signal indicates an execution time of the first recipe set and the second recipe set, the execution time occurring during the second clock cycle. transmitting a first recipe set from a first subsystem controller to a first subsystem;
transmitting a second recipe set from a second subsystem controller to a second subsystem;
Upon receiving an event signal, executing, by the first subsystem, the first recipe set; and
Executing, by the second subsystem, the second recipe set upon receipt of the event signal. According to claim 13,
The first recipe set is sent to the first subsystem during a first clock cycle, and the second recipe set is sent to the second subsystem during the first clock cycle. According to claim 14,
The method of claim 1, wherein the event signal is received during a second clock cycle following the first clock cycle. According to claim 15,
The method of claim 1, wherein the event signal indicates an execution time of the first recipe set and the second recipe set, the execution time occurring during the second clock cycle. According to claim 13,
The method of claim 1, wherein the first subsystem controller and the second subsystem controller are configured to be coupled to another controller. According to claim 17,
The method of claim 1, wherein the event signal is received from the another controller. According to claim 13,
The method of claim 1, wherein the first subsystem includes a first RF generator and the second subsystem includes a second RF generator, the second RF generator having a different frequency than the first RF generator. According to claim 19,
The first recipe set includes the amount of power and frequency of the RF signal to be generated by the first RF generator, and the second recipe set includes the amount of power of the RF signal to be generated by the second RF generator. and a quantity of frequency.