TWI675457B - Memory structure and manufacturing method thereof - Google Patents

Abstract

A memory structure is provided, which includes two word lines, a plurality of floating gates, and a control gate. Two word lines are arranged on the substrate. The top width of each character line is greater than its bottom width. The plurality of floating gates are arranged between the word lines and separated from the word lines. The control gate is arranged between the floating gates and separated from the floating gates.

Description

Memory structure and manufacturing method thereof

The present invention relates to a semiconductor structure and a manufacturing method thereof, and more particularly, to a memory structure and a manufacturing method thereof.

Because non-volatile memory (non-volatile memory) can perform multiple operations of storing, reading, and erasing data, and has the ability to save stored data when the power supply is interrupted, the data access time is short And low power consumption, it has become a kind of memory widely used in personal computers and electronic devices.

Under the current trend of increasing the degree of component accumulation, how to increase the reading speed and erasing speed of the memory without increasing the size of the memory cell has become a consensus goal in the industry.

In view of this, the present invention provides a memory structure and a manufacturing method thereof, which can increase the reading speed and erasing speed of the memory without increasing the size of the memory cell.

The invention provides a memory structure, which includes two word lines, a plurality of floating gates, and a control gate. Two word lines are arranged on the substrate. The top width of each character line is greater than its bottom width. The plurality of floating gates are arranged between the word lines and separated from the word lines. The control gate is arranged between the floating gates and separated from the floating gates.

In an embodiment of the present invention, each character line has a reentrant profile, and the floating gate has a corresponding salient profile.

In an embodiment of the present invention, the floating gate has an inclined outer surface.

According to an embodiment of the present invention, the memory structure further includes a plurality of first insulating layers and a second insulating layer. A plurality of first insulating layers are respectively disposed between each word line and the substrate. The second insulating layer covers the top and side walls of each word line and is connected to the first insulating layer.

In an embodiment of the present invention, the memory structure further includes a third insulation layer, which is disposed between the floating gate and the control gate and between the control gate and the substrate.

In an embodiment of the present invention, the third insulation layer further covers the top and sidewalls of each word line.

In an embodiment of the present invention, the memory structure further includes a plurality of isolation structures disposed in the substrate, wherein each word line is interleaved with a part of the isolation structures, and the isolation structures and the floating gates are alternately disposed.

In an embodiment of the present invention, an edge of the floating gate is protruded from an edge of the isolation structure.

In an embodiment of the present invention, the memory structure further includes a first doped region and a plurality of second doped regions. The first doped region is disposed in a substrate below the control gate. The plurality of second doped regions are disposed in the substrate outside the word line.

In an embodiment of the present invention, the above memory structure further includes a plurality of isolation structures arranged in the substrate, wherein each word line is interleaved with a part of the isolation structures, and the isolation structures are alternately disposed with the second doped regions.

In an embodiment of the present invention, the first doped region further extends into the substrate below the floating gate.

In an embodiment of the present invention, the second doped region further extends into the substrate below the adjacent word line.

The invention further provides a method for manufacturing a memory structure, which includes the following steps. A plurality of isolation structures are formed in the substrate. A first insulating material layer is formed on a substrate between the isolation structures. Two character lines are formed on the substrate, and each character line is interleaved with a part of the isolation structure. The first insulating material layer and the character line are processed to make the character line have a concave corner profile. A plurality of floating gates are formed between the word lines. A control gate is formed between the floating gates.

In an embodiment of the present invention, the processing steps include the following steps. A portion of the first insulating material layer is removed so as to form a plurality of first insulating layers between each word line and the substrate, wherein the width of the first insulating layer is smaller than the width of the word lines. An oxidation step is performed to form a second insulating layer on the top and side walls of each word line, and form a concave corner profile at the bottom corner of each word line, and the second insulating layer is connected to the first insulating layer.

In an embodiment of the present invention, the step of forming the floating gate includes the following steps. Two conductor gaps are formed on both sides of each word line. The conductor gap wall is patterned to remove the conductor gap wall on the outside of the character lines and form a floating gate between the character lines.

In an embodiment of the present invention, the method for manufacturing a memory structure further includes forming a third insulating layer on the substrate, and the third insulating layer is disposed between the floating gate and the control gate and between the control gate and the control gate. Between the substrates.

In an embodiment of the present invention, the floating gate and the isolation structure are alternately arranged.

In an embodiment of the present invention, the method for manufacturing a memory structure further includes forming a first doped region in a substrate between the word lines, and forming a plurality of second dopings in the substrate outside the word lines. Area.

In an embodiment of the invention, the second doped regions and the isolation structure are alternately arranged.

In an embodiment of the present invention, the second doped region further extends into the substrate below the adjacent word line.

Based on the above, by the manufacturing method of the present invention, a memory structure can be manufactured, which can increase the reading speed and erasing speed of the memory without increasing the size of the memory cell.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

1A to 1H are schematic top views of a method for manufacturing a memory structure according to an embodiment of the present invention. 2A to 2H are schematic cross-sectional views taken along a line I-I 'in FIGS. 1A to 1H. For clarity, some components are sometimes omitted in the top view. For example, FIGS. 1G and 1H omit the third insulating layer.

Referring to FIG. 1A and FIG. 2A, a plurality of isolation structures 102 are formed in the substrate 100. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. The substrate 100 may have a well region therein. In one embodiment, the isolation structure 102 is configured as a first group G1 and a second group G2, and each group has a plurality of isolation structures 102 arranged in parallel. The isolation structures 102 extend along the first direction D1, and the isolation structures 102 of adjacent groups are configured in an end-to-end manner. In one embodiment, the isolation structure 102 may be a shallow trench isolation (STI) structure.

The isolation structure 102 is used to define an active block. In one embodiment, at least one first active block AA1, at least one second active block AA2, and a third active block AA3 are formed in the substrate 100. The first active block AA1 and the second active block AA2 extend in the first direction D1, and the third active block AA3 is located between the first active block AA1 and the first active block AA2 and extends in the second direction D2 . The first direction D1 and the second direction D2 are staggered, for example, perpendicular to each other.

Referring to FIG. 1B and FIG. 2B, a first insulating material layer 104 is formed on the substrate 100 between the isolation structures 102. More specifically, the first insulating material layer 104 is formed on the substrate 100 of the first active region AA1, the second active region AA2, and the third active region AA3. In an embodiment, a material of the first insulating material layer 104 includes silicon oxide, and a method for forming the first insulating material layer 104 includes performing a thermal oxidation method.

Next, two word lines 106 are formed on the substrate 100, and each word line 106 is intersected with a part of the isolation structure 102. More specifically, one word line 106 is staggered with the isolation structure 102 of the first group G1, and the other word line 106 is staggered with the isolation structure 102 of the second group G2. In one embodiment, the method for forming the word line 106 includes a patterning step of forming a doped polycrystalline silicon layer on the substrate 100 and then performing a lithographic etching on the doped polycrystalline silicon layer.

Referring to FIGS. 1C to 1D and FIGS. 2C to 2D, processing steps are performed on the first insulating material layer 104 and the word line 106 so that the word line 106 has a concave corner profile R.

In one embodiment, the processing step includes removing a portion of the first insulating material layer 104 to form a plurality of first insulating layers 104a between each word line 106 and the substrate 100, as shown in FIGS. 1C and 2C. In one embodiment, the width of the first insulating layer 104 a is smaller than the width of the word lines 106. In one embodiment, a method of removing a portion of the first insulating material layer 104 includes performing an isotropic etching process.

In one embodiment, the processing step further includes performing an oxidation step to form a second insulating layer 108 on the top and sidewalls of each word line 106, and form a concave corner profile R at the bottom corner of each word line 106 , As shown in Figure 1D and Figure 2D. More specifically, a thermal oxidation method is performed to consume a part of the word lines 106 to form the second insulating layer 108. In one embodiment, the parameters of the oxidation step are controlled so that the bottom corner portion of the character line 106 is consumed faster, so that a concave corner profile R is formed at the bottom corner of each character line 106. After the processing step, the upper width of the word line 106 is greater than the lower width, and there are turning points on the sidewalls. More specifically, the upper side walls of the word line 106 are substantially vertical, and the opposite lower side walls are inclined toward each other. In one embodiment, the substrate 100 is also consumed by the thermal oxidation method; that is, the second insulating layer 108 is also formed on the substrate 100. In one embodiment, the second insulating layer 108 and the first insulating layer 104a are connected to each other.

Referring to FIGS. 1E to 1F and FIGS. 2E to 2F, a plurality of floating gates 110 a are formed between the word lines 106.

In one embodiment, as shown in FIG. 1E and FIG. 2E, two conductor gaps 110 are formed on both sides of each word line 106. In one embodiment, the method for forming the conductive spacer 110 includes forming a doped polycrystalline silicon layer on the substrate 100, and then performing an anisotropic etching process on the doped polycrystalline silicon layer.

Next, as shown in FIG. 1F and FIG. 2F, the conductor gap wall 110 is patterned to remove the conductor gap wall 110 outside the word line 106, and a floating gate electrode 110 a is formed between the word lines. In one embodiment, a method of patterning the conductive spacer 110 includes the following steps. First, a photoresist layer is formed on the substrate 100. Then, an etching process is performed using the photoresist layer as a mask to remove the conductive spacers 110 outside the word lines 106 and remove the conductive spacers 110 on the isolation structure 102 between the word lines 106. In one embodiment, the floating gate 110 a is inlaid with the undercut portion of the word line 106. More specifically, the floating gate electrode 110 a is formed with a salient contour corresponding to the concave-corner contour R of the word line 106.

In one embodiment, as shown in FIG. 2F, the floating gates 110 a and the isolation structures 102 are alternately arranged. More specifically, the isolation structure 102 of the first group G1 and the floating gate 110a of the first active block AA1 are alternately arranged, and the isolation structure 102 of the second group G2 and the floating gate of the second active block AA2 are alternately arranged. The poles 110a are alternately arranged.

1G and 2G, a first doped region 112 is formed in the substrate 100 between the word lines 106, and a plurality of second doped regions 114 is formed in the substrate 100 outside the word lines 106.

In one embodiment, a method of forming the first doped region 112 and the second doped region 114 includes performing an ion implantation process. In one embodiment, the first doped region 112 further extends into the substrate 100 below the adjacent floating gate 110 a, and the second doped region 114 further extends into the substrate 100 below the adjacent word line 106.

In one embodiment, the second doped regions 114 and the isolation structures 102 are alternately arranged. More specifically, the isolation structure 102 of the first group G1 and the second doped region 114 of the first active block AA1 are alternately arranged, and the isolation structure 102 of the second group G2 and the second active region AA2 of the second The doped regions 114 are alternately arranged.

Next, a third insulating layer 116 is formed on the substrate 100. More specifically, the third insulating layer 116 is formed on the sidewall of the floating gate 110 a and extends laterally to the top and sidewall of the word line 106, and the On the top. In one embodiment, the method for forming the third insulating layer 116 includes performing a chemical vapor deposition process.

Referring to FIG. 1H and FIG. 2H, a control gate 118 is formed between the floating gates 110a. In one embodiment, a method for forming the control gate 118 includes forming a doped polycrystalline silicon layer on the substrate 100, and a top surface of the doped polycrystalline silicon layer is lower than a top surface of the word line 106. Next, a patterning step of lithographic etching is performed on the doped polycrystalline silicon layer to remove the doped polycrystalline silicon layer outside the word line 106. So far, the fabrication of the memory structure 10 of the present invention is completed.

Hereinafter, the memory structure of the present invention will be described with reference to FIGS. 1H and 2H. In one embodiment, the memory structure 10 of the present invention includes two word lines 106, a plurality of floating gates 110a, and a control gate 118. Two word lines 106 are disposed on the substrate 100, and the top width of each word line 106 is greater than the bottom width. The plurality of floating gates 110 a are disposed between the word lines 106 and are separated from the word lines 106. The control gate 118 is disposed between the floating gates 110a and is separated from the floating gates 110a.

In one embodiment, the memory structure 10 further includes a plurality of first insulating layers 104 a, a second insulating layer 108, and a third insulating layer 116. The plurality of first insulating layers 104 a are respectively disposed between each of the word lines 106 and the substrate 100. The second insulating layer 108 covers the top and side walls of each word line and is connected to the first insulating layer 104a. The third insulating layer 116 is disposed between the floating gate 110 a and the control gate 118 and between the control gate 118 and the substrate 100. In one embodiment, the third insulating layer 116 further covers the top and sidewalls of each word line 106.

In one embodiment, each word line 106 has a reentrant outline, and the floating gate 110a has a corresponding salient outline. From another perspective, each word line 106 has an undercut concave portion, the floating gate electrode 110a has a corresponding convex portion, and the word line 106 and the floating gate electrode 110a are fitted to each other.

In one embodiment, the floating gate electrode 110a has an inclined outer surface. More specifically, the floating gate electrode 110 a is arranged inside the adjacent word line 106 in the form of a gap wall.

In one embodiment, the memory structure 10 further includes a plurality of isolation structures 102 configured in the substrate 100. Each word line 106 is interleaved with a part of the isolation structure 102. In one embodiment, each word line 106 and a part of the isolation structure 102 are perpendicular to each other.

In one embodiment, the isolation structures 102 and the floating gates 110 a are alternately arranged. In one embodiment, the edge of the floating gate electrode 110 a protrudes from the edge of the isolation structure 102, but the invention is not limited thereto. In another embodiment, the edge of the isolation structure 102 may be aligned with the edge of the floating gate 110a.

In one embodiment, the memory structure 10 further includes a first doped region 112 and a plurality of second doped regions 114. The first doped region 112 is disposed in the substrate 100 under the control gate 118. In one embodiment, the first doped region 112 further extends into the substrate 100 below the floating gate 110a. The plurality of second doped regions 114 are disposed in the substrate 100 outside the word line 106. In one embodiment, the second doped region 114 further extends into the substrate 100 below the adjacent word line 106. In one embodiment, the first doped region 112 serves as a source of the memory structure 10, and the second doped region 114 serves as a drain of the memory structure 10. In one embodiment, the isolation structures 102 and the second doped regions 114 are alternately arranged.

The memory structure 10 of the present invention may have a plurality of memory cell units C. In an embodiment, as shown in FIG. 1H, the memory structure 10 may have four memory cell units C, but the present invention is not limited thereto.

FIG. 3 is a schematic diagram of a programming operation of a memory structure according to an embodiment of the present invention. FIG. 4 is a schematic diagram of an erasing operation of a memory structure according to an embodiment of the present invention.

Hereinafter, an operation method of the memory structure of the present invention will be described with reference to FIGS. 3 and 4. In an embodiment, when performing a stylized operation on the memory structure of the present invention, refer to Table 1. Apply 0.6V to the word line WL, 8V to the control gate CG, 4V to the source S, and 0V to Drain D and apply 0V to the well region W in the substrate. At this time, the electron e is injected from the drain D on the drain side to the floating gate FG on the source side, so it is called source-side injection, as shown in FIG. 3. Since the memory structure of the present invention has a large CG-FG coupling voltage, the programming speed can be increased.

In an embodiment, when performing an erasing operation on the memory structure of the present invention, please refer to Table 1. Apply 4V to the word line WL, apply -8V to the control gate CG, and float the source S and the drain D. And apply 0V to the well region W in the substrate. At this time, the electron e is injected from the floating gate FG through the concave angle of the erased gate EG, so it is called enhanced F-N tunneling, as shown in FIG. 4. Since the memory structure of the present invention has a large WL-FG coupling voltage, the erasing speed can be increased.

Table I WL (EG) CG S D W Stylized operation 0.6V (Vt) 8V 4V 0V 0V Erase operation 4V -8V Float Float 0V

Based on the above, by the manufacturing method of the present invention, a memory structure can be manufactured, which can increase the reading speed and erasing speed of the memory without increasing the size of the memory cell.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

10‧‧‧Memory structure

100‧‧‧ substrate

102‧‧‧Isolation structure

104‧‧‧first insulating material layer

104a‧‧‧First insulation layer

106‧‧‧Character line

108‧‧‧Second insulation layer

110‧‧‧Conductor bulkhead

110a‧‧‧floating gate

112‧‧‧first doped region

114‧‧‧second doped region

116‧‧‧Third insulation layer

118‧‧‧Control gate

AA1‧‧‧The first active block

AA2‧‧‧Second Active Block

AA3‧‧‧The third active block

C‧‧‧Memory Cell Unit

CG‧‧‧Control gate

D‧‧‧ Drain

D1‧‧‧ first direction

D2‧‧‧ Second direction

e‧‧‧Electronics

FG‧‧‧Floating Gate

G1‧‧‧The first group

G2‧‧‧Second Group

R‧‧‧ Concave Contour

S‧‧‧Source

W‧‧‧well area

WL‧‧‧Character Line

1A to 1H are schematic top views of a method for manufacturing a memory structure according to an embodiment of the present invention. 2A to 2H are schematic cross-sectional views taken along a line I-I 'in FIGS. 1A to 1H. FIG. 3 is a schematic diagram of a programming operation of a memory structure according to an embodiment of the present invention. FIG. 4 is a schematic diagram of an erasing operation of a memory structure according to an embodiment of the present invention.

Claims (20)

A memory structure includes: two word lines arranged on a substrate, wherein a top width of each of the word lines is greater than a bottom width thereof; a plurality of floating gates arranged between the word lines And is separated from the word line; and a control gate is disposed between the floating gates and separated from the floating gates. The memory structure according to item 1 of the scope of the patent application, wherein each of the word lines has a reentrant outline, and the floating gate has a corresponding salient outline. The memory structure according to item 1 of the patent application scope, wherein the floating gate has an inclined outer surface. The memory structure according to item 1 of the patent application scope further comprises: a plurality of first insulating layers respectively disposed between each of the word lines and the substrate; and a second insulating layer covering each A top and a side wall of one of the word lines are connected to the first insulating layer. The memory structure according to item 1 of the patent application scope further includes: a third insulating layer disposed between the floating gate and the control gate and between the control gate and the substrate . According to the memory structure of claim 5, the third insulating layer further covers the top and sidewalls of each of the word lines. The memory structure according to item 1 of the patent application scope further includes: a plurality of isolation structures disposed in the substrate, wherein each of the word lines is interleaved with a part of the isolation structures, and the isolation structure Alternately with the floating gate. The memory structure according to item 7 of the application, wherein an edge of the floating gate protrudes from an edge of the isolation structure. The memory structure according to item 1 of the patent application scope further includes: a first doped region disposed in the substrate below the control gate; and a plurality of second doped regions disposed in the substrate. In the base outside the word line. The memory structure according to item 9 of the scope of patent application, further comprising: a plurality of isolation structures disposed in the substrate, wherein each of the word lines is interleaved with a part of the isolation structures, and the isolation structure And alternately arranged with the second doped region. The memory structure according to item 9 of the application, wherein the first doped region further extends into the substrate below the floating gate. The memory structure according to item 9 of the application, wherein the second doped region further extends into the substrate below the adjacent word line. A method of manufacturing a memory structure includes: forming a plurality of isolation structures in a substrate; forming a first insulating material layer on the substrate between the isolation structures; forming two word lines on the substrate, Each of the word lines is interleaved with a part of the isolation structure; processing steps are performed on the first insulating material layer and the word lines so that the word lines have a concave corner profile; Forming a plurality of floating gates therebetween; and forming a control gate between the floating gates. The method of manufacturing a memory structure according to item 13 of the application, wherein the processing step includes: removing a portion of the first insulating material layer between each of the word lines and the substrate Forming a plurality of first insulating layers, wherein the width of the first insulating layer is smaller than the width of the word lines; and performing an oxidation step to form a second insulating layer on the top and sidewalls of each of the word lines And forming the concave corner contour at the bottom corner of each of the word lines, and the second insulating layer is connected to the first insulating layer. The method for manufacturing a memory structure according to item 13 of the application, wherein the step of forming the floating gate comprises: forming two conductor gaps on both sides of each of the word lines; and The conductor gap wall is patterned to remove the conductor gap wall outside the character line, and form the floating gate between the character lines. The method for manufacturing a memory structure according to item 13 of the scope of patent application, further comprising: forming a third insulating layer on the substrate, the third insulating layer being disposed on the floating gate and the control gate. Between the poles and between the control gate and the substrate. The method for manufacturing a memory structure according to item 13 of the scope of patent application, wherein the floating gate and the isolation structure are alternately arranged. The method for manufacturing a memory structure according to item 13 of the scope of patent application, further comprising: forming a first doped region in the substrate between the word lines; and a region outside the word lines. A plurality of second doped regions are formed in the substrate. The method for manufacturing a memory structure according to item 18 of the scope of the patent application, wherein the second doped regions and the isolation structure are alternately arranged. The method for manufacturing a memory structure according to item 18 of the application, wherein the second doped region further extends into the substrate below the adjacent word line.