TWI672746B - Method for annealing in semiconductor device - Google Patents
Method for annealing in semiconductor device Download PDFInfo
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- TWI672746B TWI672746B TW107103831A TW107103831A TWI672746B TW I672746 B TWI672746 B TW I672746B TW 107103831 A TW107103831 A TW 107103831A TW 107103831 A TW107103831 A TW 107103831A TW I672746 B TWI672746 B TW I672746B
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01001—Hydrogen [H]
Abstract
本發明揭露配置擴散控制膜，從而，僅在設定區域中，界面的陷阱電荷被鈍化的半導體裝置退火的方法。在本發明中，藉由以往的退火製程，在半導體裝置的所有區域中，為了解決在相同條件下，執行氫或氘退火的問題而配置氫或氘無法透過的擴散控制膜，在半導體裝置的各個區域中，執行不同的氫或氘退火，從而執行在半導體裝置最優化的退火。 The invention discloses a method for disposing a diffusion control film so that a semiconductor device whose interface trap charges are passivated is annealed only in a set region. In the present invention, by a conventional annealing process, in order to solve the problem of performing hydrogen or deuterium annealing under the same conditions in all regions of the semiconductor device, a diffusion control film impermeable to hydrogen or deuterium is disposed in the semiconductor device. In each region, a different hydrogen or deuterium anneal is performed, thereby performing an anneal optimized for a semiconductor device.
Description
本發明關於在氫或氘氣氛下，對半導體裝置進行設定的溫度、設定的壓力、設定時間的退火的退火方法。尤其，關於當對半導體裝置進行退火時，控制向半導體裝置滲透的氫或氘的量，由此，改善半導體裝置的移動並謀求可靠性的半導體裝置退火方法。 The invention relates to an annealing method for annealing a semiconductor device at a set temperature, a set pressure, and a set time in a hydrogen or deuterium atmosphere. In particular, when annealing a semiconductor device, the semiconductor device annealing method is to control the amount of hydrogen or deuterium permeating into the semiconductor device, thereby improving the movement of the semiconductor device and achieving reliability.
例示性地，半導體裝置從準備基板的步驟進行擴散、光阻塗敷，曝光，顯影，蝕刻，離子注入，化學氣相蒸鍍等製程之後，進行金屬配線製程，最終，為了改善裝置的特性，執行1號的氫或氘退火製程。 Exemplarily, after the semiconductor device performs processes such as diffusion, photoresist coating, exposure, development, etching, ion implantation, chemical vapor deposition, and the like from the step of preparing a substrate, a metal wiring process is performed. Finally, in order to improve the characteristics of the device, Perform hydrogen or deuterium annealing process No. 1.
氫或氘退火製程中，藉由氫使存在於界面的陷阱電荷被鈍化，由此，降低界面電荷的密度，從而確保優秀電荷移動度特性。 In the hydrogen or deuterium annealing process, the trap charge existing at the interface is passivated by hydrogen, thereby reducing the density of the interface charge and ensuring excellent charge mobility characteristics.
在上述退火製程中，半導體裝置領域的技術越發展，其重要性越明顯，半導體裝置越縮小，柵絕緣膜的厚度變為限界以上，從而發生漏電問題，為了克服這種問題，使用改善的高介電常數(High-K)(HfO2、HfSix、HfAlx)。 In the above annealing process, the more developed the technology in the field of semiconductor devices, the more important it becomes, the smaller the semiconductor device becomes, the thickness of the gate insulating film becomes more than the limit, and the problem of leakage occurs. In order to overcome this problem, an improved Dielectric constant (High-K) (HfO 2 , HfSix, HfAlx).
這是因為藉由高-K物質製造的絕緣膜中，組織的缺陷為以 往絕緣膜(SiO2)的缺陷的100倍以上。 This is because, in an insulating film made of a high-K substance, the defects in the structure are 100 times or more the defects of the conventional insulating film (SiO 2 ).
但是，相對於上述退火製程的重要性及優點，上述退火製程也存在缺點，若大量氫情或氘向界面滲透，則裝置的可靠性被劣化。因此，氫或氘退火製程根據半導體裝置最優化。 However, compared with the importance and advantages of the above annealing process, the above annealing process also has disadvantages. If a large amount of hydrogen or deuterium penetrates into the interface, the reliability of the device is deteriorated. Therefore, the hydrogen or deuterium annealing process is optimized according to the semiconductor device.
另一方面，半導體裝置產業中，與上述高-K物質的發展及使用單獨地，構成半導體裝置的各層的物質及半導體裝置的形狀等發展為三維結構。隨著這種發展，在執行氫或氘退火製程的過程中，半導體裝置的各個區域的界面的鈍化不相同。 On the other hand, in the semiconductor device industry, separately from the development and use of the high-K materials described above, the materials constituting each layer of the semiconductor device, the shape of the semiconductor device, and the like have developed into a three-dimensional structure. With this development, during the hydrogen or deuterium annealing process, the passivation of the interfaces of various regions of the semiconductor device is different.
但是，如上所述，退火製程為在完成金屬配線製程之後最後執行的製程，因此，所有裝置在相同條件下被退火，從而退火製程會面臨窘境。 However, as described above, the annealing process is the last process performed after the metal wiring process is completed. Therefore, all devices are annealed under the same conditions, and the annealing process may face a dilemma.
透過圖1說明這種窘境，圖1的A區域在A條件下執行退火的情況下最優化，若在B條件下執行退火製程，則可靠性會降低，B區域在A條件下，退火製程在界面的陷阱電荷無法被鈍化，若在B條件下執行退火製程，則被最優化，從而面臨通過A條件執行退火製程或通過B條件下執行退火製程。 This dilemma is illustrated by referring to FIG. 1. The area A in FIG. 1 is optimized under the condition that annealing is performed under A conditions. If the annealing process is performed under B conditions, the reliability will be reduced. The B area is under A conditions, and the annealing process is The trap charge at the interface cannot be passivated. If the annealing process is performed under the B condition, it is optimized, so that the annealing process is performed under the A condition or the annealing process is performed under the B condition.
亦即，為了使A區域最優化，若在A條件下執行退火製程，則B區域的缺陷不會被改善，因此，為了提高B區域的電特性，若在B條件下執行退火製程，則A區域的可靠性會降低。 That is, in order to optimize the A region, if the annealing process is performed under the A condition, the defects in the B region will not be improved. Therefore, in order to improve the electrical characteristics of the B region, if the annealing process is performed under the B condition, then A Area reliability is reduced.
[先前技術文獻] [Prior technical literature]
[專利文獻] [Patent Literature]
專利文獻1：韓國授權專利授權號“10-1400699”“半導體基板及半導體裝置及其製造方法(Semiconductor substrate,semiconductor device and manufacturing method thereof)”。 Patent Document 1: Korean authorized patent grant number "10-1400699" "Semiconductor substrate, semiconductor device and manufacturing method thereof".
專利文獻2：韓國公開專利公開號“10-2015-0088324”“半導體裝置的製造方法(METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE)”。 Patent Document 2: Korean Published Patent Publication No. "10-2015-0088324" "Method for Manufacturing Semiconductor Device (METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE)".
本發明的目的在於，提供在對半導體裝置執行氫或氘退火製程的過程中，配置防止氫或氘的透過的擴散控制膜，從而，僅在擴散控制膜之外的部分被鈍化的半導體裝置退火的方法。 An object of the present invention is to provide a diffusion control film that prevents hydrogen or deuterium from permeating during a hydrogen or deuterium annealing process performed on a semiconductor device, so that only a portion of the semiconductor device that is passivated except for the diffusion control film is passivated. Methods.
並且，本發明的目的在於，提供在配置擴散控制膜的區域中，在設定部分中，配置允許氫或氘的擴散的擴散控制膜，從而，在設定部分，氫或氘可被鈍化的半導體裝置退火的方法。 Furthermore, an object of the present invention is to provide a semiconductor device in which a diffusion control film is disposed in a region where a diffusion control film that allows diffusion of hydrogen or deuterium is disposed in a setting portion so that hydrogen or deuterium can be passivated in the setting portion. Method of annealing.
並且，本發明的目的在於，提供使用防止氫或氘的透過的擴散控制膜來執行多次退火製程的半導體裝置退火的方法。 Another object of the present invention is to provide a method for annealing a semiconductor device using a diffusion control film that prevents the transmission of hydrogen or deuterium to perform multiple annealing processes.
本發明所要解決的技術問題並不局限於上述提及的技術問題，本發明所屬技術領域中具有通常知識者可明確理解未提及的其他技術問題。 The technical problems to be solved by the present invention are not limited to the above-mentioned technical problems, and those with ordinary knowledge in the technical field to which the present invention belongs can clearly understand other technical problems not mentioned.
本發明的半導體裝置退火的方法在氫或氘氣氛下對半導體裝置進行退火。本發明的半導體裝置退火的方法中，配置擴散控制膜，半導體裝置的所有區域並非在相同條件下被退火，而是在不同的條件下被退火。 The method for annealing a semiconductor device of the present invention anneals a semiconductor device in a hydrogen or deuterium atmosphere. In the method for annealing a semiconductor device of the present invention, a diffusion control film is disposed, and all regions of the semiconductor device are not annealed under the same conditions, but annealed under different conditions.
特定地，在上述半導體裝置的設定區域中，配置防止氫或氘透過的擴散控制膜。 Specifically, in the setting region of the semiconductor device, a diffusion control film is provided to prevent hydrogen or deuterium from transmitting.
其中，上述擴散控制膜中，在設定部分形成孔，在形成上述孔的部分中，氫或氘能夠透過。 In the diffusion control film, a hole is formed in a set portion, and hydrogen or deuterium is permeable in a portion where the hole is formed.
並且，擴散控制膜形成有複數個，上述複數個擴散控制膜中，至少一個的厚度與其他的厚度不同，上述厚度不同的複數 個擴散控制膜分別配置於設定的區域。 In addition, a plurality of diffusion control films are formed. At least one of the plurality of diffusion control films has a thickness different from the other thicknesses, and the plurality of diffusion control films having different thicknesses are respectively disposed in predetermined regions.
並且，上述擴散控制膜的厚度為3nm以上。 The thickness of the diffusion control film is 3 nm or more.
並且，上述擴散控制膜由SixNy形成。 And the diffusion control film formed of Si x N y.
並且，上述擴散控制膜形成有複數個，上述複數個擴散控制膜中，至少一個擴散控制膜的厚度和其他擴散控制膜的厚度不相同，上述厚度不同的複數個擴散控制膜分別配置於設定的區域。 In addition, a plurality of the diffusion control films are formed. Among the plurality of diffusion control films, the thickness of at least one diffusion control film is different from the thickness of other diffusion control films, and the plurality of diffusion control films having different thicknesses are respectively disposed in the set region.
在本發明中，半導體裝置退火的方法利用擴散控制膜執行多次退火，上述半導體裝置退火的方法包括：步驟(1)，在氫或氘氣氛下，進行第一退火；步驟(2)，在半導體裝置的設定區域配置上述擴散控制膜；以及步驟(3)，在氫或氘氣氛下，進行第二退火。 In the present invention, the method for annealing a semiconductor device uses a diffusion control film to perform multiple annealing. The method for annealing a semiconductor device includes: step (1), performing a first annealing under a hydrogen or deuterium atmosphere; step (2), The diffusion control film is arranged in a set region of the semiconductor device; and in step (3), a second annealing is performed in a hydrogen or deuterium atmosphere.
藉由上述方法執行的本發明的半導體裝置退火的方法在相同條件下執行退火製程，從而，設定區域的界面的陷阱電荷被鈍化。 The method for annealing a semiconductor device of the present invention performed by the above method performs an annealing process under the same conditions, so that the trap charges at the interface of the set region are passivated.
並且，在擴散控制膜形成孔，在對應部分，氫或氘透過擴散控制膜並擴散，從而，在配置擴散控制膜的區域，設定部分中，界面的陷阱電荷可被鈍化。 Further, a hole is formed in the diffusion control film, and hydrogen or deuterium penetrates the diffusion control film and diffuses in the corresponding portion, so that in the region where the diffusion control film is disposed, the trap charge at the interface can be passivated.
並且，在設定區域配置擴散控制膜，由此，對應區域的界面不會被鈍化，從而可執行多次退火製程。 In addition, a diffusion control film is disposed in the set region, so that the interface of the corresponding region is not passivated, and multiple annealing processes can be performed.
100‧‧‧擴散控制膜 100‧‧‧ diffusion control membrane
110‧‧‧(擴散控制膜的)孔 110‧‧‧ (diffusion control membrane) hole
圖1示出當執行先前技術的半導體裝置的退火時發生的問題。 FIG. 1 illustrates a problem that occurs when annealing of a semiconductor device of the prior art is performed.
圖2示出本發明第一實施例的半導體裝置退火的方法。 FIG. 2 illustrates a method for annealing a semiconductor device according to a first embodiment of the present invention.
圖3示出本發明第二實施例的半導體裝置退火的方法。 FIG. 3 illustrates a method for annealing a semiconductor device according to a second embodiment of the present invention.
圖4示出本發明第三實施例的半導體裝置退火的方法。 FIG. 4 illustrates a method for annealing a semiconductor device according to a third embodiment of the present invention.
圖5示出本發明第四實施例的半導體裝置退火的方法。 FIG. 5 illustrates a method for annealing a semiconductor device according to a fourth embodiment of the present invention.
圖6示出本發明第五實施例的半導體裝置退火的方法。 FIG. 6 illustrates a method for annealing a semiconductor device according to a fifth embodiment of the present invention.
以下，本發明的一實施例藉由例示性圖式進行詳細說明。但是，這並不意味著限定本發明的範圍。 Hereinafter, an embodiment of the present invention will be described in detail by way of illustrative drawings. However, this is not meant to limit the scope of the invention.
在向各個圖中的結構要素賦予元件符號的過程中，雖然呈現在不同圖式中，對相同結構要素盡可能賦予相同元件符號。並且，在說明本發明的過程中，在判斷為相關的公知結構或功能的具體說明使本發明的主旨不清楚的情況下，將省略對其的詳細說明。 In the process of assigning an element symbol to a structural element in each figure, although it is shown in different drawings, the same element is given the same element symbol as much as possible. Furthermore, in the course of explaining the present invention, if it is determined that the specific description of a related known structure or function makes the subject matter of the present invention unclear, a detailed description thereof will be omitted.
並且，圖中示出的結構要素的大小或形狀等為了說明的明確性和便利性而被擴大。並且，考慮到本發明的結構及作用，特殊定義的術語用於說明本發明的實施例，而並非用於限定本發明的範圍。 In addition, the sizes, shapes, and the like of the structural elements shown in the drawings are enlarged for clarity and convenience of explanation. In addition, in consideration of the structure and function of the present invention, specially defined terms are used to describe embodiments of the present invention, but not to limit the scope of the present invention.
本發明的半導體裝置退火的方法當在氫或氘氣氛下執行退火時，在設定的區域內，配置氫或氘無法透過的擴散控制膜100，在設定區域中，無法滲透氫或氘。 In the method for annealing a semiconductor device according to the present invention, when annealing is performed in a hydrogen or deuterium atmosphere, a diffusion control film 100 that is impervious to hydrogen or deuterium is arranged in a set area, and hydrogen or deuterium cannot be penetrated in the set area.
以下，為了方便說明，將擴散控制膜100所在的區域命名為A區域，將擴散控制膜100不在的區域命名為B區域。 Hereinafter, for convenience of explanation, a region where the diffusion control film 100 is located is named as an A region, and a region where the diffusion control film 100 is not located is named as a B region.
並且，在本說明書中，退火製程的條件在高濃度的氫或氘的氣氛下具有設定的溫度及設定時間來執行，這根據使用人員改變。 In addition, in this specification, the conditions of the annealing process are performed under a high-concentration hydrogen or deuterium atmosphere with a set temperature and a set time, which varies depending on the user.
擴散控制膜100防止氫或氘的透過。 The diffusion control film 100 prevents transmission of hydrogen or deuterium.
例示性地，擴散控制膜100由氮化矽(SixNy)製造。更準確地，較佳地，由Si3N4製造。Si3N4的組織緻密，硬度高，從而氫或氘無法透過，若在設定的區域配置由Si3N4製造的擴散控制膜100，則在對應區域中，氫或氘無法透過。 Illustratively, the diffusion control film 100 is made of silicon nitride (Si x N y ). More precisely, preferably, made of Si 3 N 4 . Si 3 N 4 has a dense structure and high hardness, so that hydrogen or deuterium cannot pass through. If a diffusion control film 100 made of Si 3 N 4 is arranged in a set region, hydrogen or deuterium cannot pass through in the corresponding region.
圖2示出本發明第一實施例的半導體裝置退火的方法。 FIG. 2 illustrates a method for annealing a semiconductor device according to a first embodiment of the present invention.
若A區域的界面被鈍化，則可靠性降低，B區域的界面的陷阱電荷密度高，從而需要被鈍化。 If the interface in the A region is passivated, the reliability is reduced, and the trap charge density at the interface in the B region is high, and thus it needs to be passivated.
在上述情況下，在A區域配置擴散控制膜100並執行退火製程。 In the above case, the diffusion control film 100 is disposed in the A region and an annealing process is performed.
因此，配置擴散控制膜100的區域中，氫或氘無法透過擴散控制膜100，從而在A區域中，氫或氘無法滲透，從而導致可靠性降低。但是，未配置擴散控制膜100的B區域的界面的缺陷被改善。 Therefore, in the region where the diffusion control film 100 is disposed, hydrogen or deuterium cannot pass through the diffusion control film 100, and in the region A, hydrogen or deuterium cannot penetrate, and reliability is lowered. However, defects at the interface of the B region where the diffusion control film 100 is not disposed are improved.
因此，A區域、B區域的半導體裝置所有電特性可提高。 Therefore, all the electrical characteristics of the semiconductor device in the A region and the B region can be improved.
圖3示出本發明第二實施例的半導體裝置退火的方法。 FIG. 3 illustrates a method for annealing a semiconductor device according to a second embodiment of the present invention.
最近，藉由半導體裝置的發電，即使是相同的裝置，界面有可能不同，從而用於改善界面缺陷的程度不同。 Recently, with the power generation of semiconductor devices, even for the same device, the interface may be different, and thus the degree of improving interface defects is different.
亦即，圖3中，A區域中，在k部分中，陷阱電荷需要被鈍化。在第一實施例的情況下，上述k部分的界面的缺陷可以改善。 That is, in FIG. 3, in the region A, the trap charge needs to be passivated. In the case of the first embodiment, the defects of the interface of the above k portion can be improved.
本發明第二實施例的半導體裝置退火的方法中使用的擴散控制膜100形成有孔110。 The diffusion control film 100 used in the method for annealing a semiconductor device according to the second embodiment of the present invention is formed with a hole 110.
若擴散控制膜100配置於A區域，則孔110與k部分對應形成。因此，在氫或氘氣氛下執行退火製程的情況下，配置擴散控制膜100的部分防止氫或氘的透過，因在k部分形成孔110，因此，氫或氘可以透過。 When the diffusion control film 100 is disposed in the A region, the hole 110 is formed corresponding to the k portion. Therefore, in the case where the annealing process is performed in a hydrogen or deuterium atmosphere, the portion where the diffusion control film 100 is arranged prevents the transmission of hydrogen or deuterium, and since the hole 110 is formed in the k portion, the hydrogen or deuterium is permeable.
因此，k部分中，通過氫或氘，界面的陷阱電荷可以被鈍化。 Therefore, in the k part, the trap charge at the interface can be passivated by hydrogen or deuterium.
孔110可以與k部分對應形成。因此，可形成複數個。 The hole 110 may be formed corresponding to the k portion. Therefore, a plurality of them can be formed.
圖4示出本發明第三實施例的半導體裝置退火的方法。 FIG. 4 illustrates a method for annealing a semiconductor device according to a third embodiment of the present invention.
在第三實施例的半導體裝置退火的方法中，可形成複數個擴散控制膜100。 In the method of annealing a semiconductor device according to the third embodiment, a plurality of diffusion control films 100 may be formed.
通過圖4進行說明，在半導體裝置的A區域配置厚度為3nm的擴散控制膜100，在B區域配置厚度為1nm的擴散控制膜100。 4, a diffusion control film 100 having a thickness of 3 nm is arranged in the A region of the semiconductor device, and a diffusion control film 100 having a thickness of 1 nm is arranged in the B region.
因此，位於A區域的半導體裝置中，氫或氘無法透過，位於B區域的半導體裝置中，透過一些薄的擴散控制膜100的氫或氘滲透，從而，陷阱電荷可以被鈍化。 Therefore, in the semiconductor device located in the A region, hydrogen or deuterium cannot pass through, and in the semiconductor device located in the B region, hydrogen or deuterium penetrates through some thin diffusion control films 100, and thus the trapped charges can be passivated.
藉由上述方法，位於A區域和B區域的半導體裝置可執行不同的退火。 By the above method, the semiconductor devices located in the A region and the B region can perform different annealing.
並且，藉由上述說明及圖式說明第三實施例的半導體裝置退火的方法，為了說明的便利，配置於A區域的擴散控制膜100和配置於B區域的擴散控制膜100的厚度被限定，但是，並不局限於這種厚度，可根據情況或使用人員隨意變更。 In addition, the method for annealing the semiconductor device according to the third embodiment is described by the above description and drawings. For convenience of explanation, the thicknesses of the diffusion control film 100 disposed in the A region and the diffusion control film 100 disposed in the B region are limited. However, it is not limited to this thickness, and can be changed at will according to the situation or the user.
圖5示出本發明第四實施例的半導體裝置退火的方法。 FIG. 5 illustrates a method for annealing a semiconductor device according to a fourth embodiment of the present invention.
第四實施例的本發明的半導體裝置退火的方法可執行多次退火步驟。 The method for annealing a semiconductor device according to the fourth embodiment of the present invention can perform multiple annealing steps.
亦即，可執行第一退火步驟、第二退火步驟。 That is, the first annealing step and the second annealing step may be performed.
半導體裝置中，A區域藉由第一退火改善電特性，若B區域執行第一退火步驟、第二退火步驟，則改善電特性。 In the semiconductor device, the A region is improved in electrical characteristics by the first annealing. If the B region is performed in the first annealing step and the second annealing step, the electrical characteristics are improved.
其中，若A區域在第一退火步驟之後後續進行作為退火製程的第二退火步驟，則可靠性會降低。 Wherein, if the A region is followed by a second annealing step as an annealing process after the first annealing step, the reliability will be reduced.
為了解決這種問題，本發明第五實施例的半導體裝置退火的方法可包括第一退火步驟、擴散控制膜100配置步驟及第二 退火步驟。 In order to solve such a problem, the method for annealing a semiconductor device according to the fifth embodiment of the present invention may include a first annealing step, a diffusion control film 100 configuration step, and a second annealing step.
亦即，在第一退火步驟中，未在A區域和B區域配置擴散控制膜100，A區域及B區域的界面的陷阱電荷被鈍化。之後，在A區域配置擴散控制膜100。之後，繼續執行第二退火步驟。在此情況下，A區域中，氫或氘藉由擴散控制膜100無法通過，B區域藉由氫或氘，陷阱電荷被鈍化。 That is, in the first annealing step, the diffusion control film 100 is not disposed in the A region and the B region, and the trap charges at the interface between the A region and the B region are passivated. Thereafter, the diffusion control film 100 is arranged in the A region. After that, the second annealing step is continued. In this case, hydrogen or deuterium cannot pass through the diffusion control film 100 in the region A, and trap charges are passivated by the hydrogen or deuterium in the region B.
圖6示出本發明第五實施例的半導體裝置退火的方法。 FIG. 6 illustrates a method for annealing a semiconductor device according to a fifth embodiment of the present invention.
第五實施例的本發明的半導體裝置退火的方法與第四實施例相同，可執行多次退火步驟。 The method of annealing a semiconductor device according to the fifth embodiment of the present invention is the same as that of the fourth embodiment, and multiple annealing steps can be performed.
亦即，可執行第一退火步驟、第二退火步驟。 That is, the first annealing step and the second annealing step may be performed.
與第五實施例不同，第一退火步驟、第二退火步驟中可分別適用擴散控制膜100。 Different from the fifth embodiment, the diffusion control film 100 can be applied in each of the first annealing step and the second annealing step.
第五實施例的半導體裝置退火的方法中，可依次進行在A區域配置擴散控制膜100的步驟、第一退火步驟、在B區域配置擴散控制膜100的步驟及第二退火步驟。 In the method for annealing a semiconductor device according to the fifth embodiment, a step of disposing the diffusion control film 100 in the A region, a first annealing step, a step of disposing the diffusion control film 100 in the B region, and a second annealing step may be sequentially performed.
在第一退火步驟中，配置於B區域的半導體裝置的界面的陷阱電荷被鈍化，在第二退火步驟中，A區域的界面的陷阱電荷被鈍化。 In the first annealing step, the trap charges at the interface of the semiconductor device disposed in the B region are passivated, and in the second annealing step, the trap charges at the interface of the A region are passivated.
由此，即使執行多次退火步驟，A區域、B區域均改善點處理製程並不會降低可靠性。 Therefore, even if the annealing step is performed multiple times, improving the spot processing process in both the A region and the B region does not reduce reliability.
其中，第四實施例、第五實施例中，配置基於第一實施例的擴散控制膜100，但是本發明並不局限於此，可由基於第二實施例至第三實施例的擴散控制膜100代替。 Among them, in the fourth and fifth embodiments, the diffusion control film 100 based on the first embodiment is configured, but the present invention is not limited to this, and the diffusion control film 100 based on the second to third embodiments may be used. instead.
本發明與特定實施例相關地示出並說明，但是，在不超出藉由以下的發明要求保護範圍提供的本發明的技術思想的範圍內，本發明所屬技術領域中具有通常知識者可進行多種改良及 變化。 The present invention is shown and explained in relation to specific embodiments, but within the scope of the technical idea of the present invention provided by the following claims, a person with ordinary knowledge in the technical field to which the present invention pertains can perform various operations. Improvements and changes.
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