TWI670706B - Driving voltage generator - Google Patents

Abstract

The driving voltage generator includes a first amplifier circuit and a second amplifier circuit. The first amplifier circuit has a plurality of first differential pairs, and all of the first differential pairs have the first conductivity type. The first input terminal of each first differential pair receives the first input voltage or the second input voltage. The second amplifier circuit has a plurality of second differential pairs, and all the second differential pairs have the same second conductivity type. The first input terminal of each second differential pair receives the third input voltage or the fourth input voltage. Wherein the first conductivity type is opposite to the second conductivity type, the voltage values of the first input voltage and the second input voltage are between the first voltage range, and the voltage values of the third input voltage and the fourth input voltage are between Between the second voltage ranges, the first voltage range and the second voltage range do not overlap.

Description

Driving voltage generator

The present invention relates to a driving voltage generator, and in particular to a driving voltage generator with differential computing capability.

In order to provide a high-resolution driving voltage, the conventional technology proposes an amplifying circuit with interpolation operation capability to process part of the input signal. In the conventional amplifier circuit, there are multiple differential pairs constructed by multiple P-type transistors and multiple N-type transistors, and one input terminal of each differential pair receives the output voltage, while the other input terminal Receive input voltage that may be high or low.

When the input voltage is close to the power supply voltage or the reference ground voltage, half of the differential pairs in the conventional amplifier circuit will be disconnected, and the interpolation operation cannot be effectively performed, resulting in an inaccurate output voltage.

On the other hand, the conventional technology also proposes to simultaneously provide P-type and N-type differential pairs to simultaneously receive an input voltage to overcome the above-mentioned problems. However, this type of amplifier circuit requires a large number of transistors, and when some N-type differential pairs are turned on, and some N-type differential pairs are turned off, and all P-type differential pairs are turned on When it is down, the interpolation operation performed by the amplifier circuit will also generate an error.

The invention provides a driving voltage generator which can generate an accurate output voltage.

The driving voltage generator of the present invention includes a first amplifier circuit and a second amplifier circuit. The first amplifier circuit has a plurality of first transistors. The first transistors form a plurality of first differential pairs, and all the first transistors have the same first conductivity type. The first input terminal of each first differential pair receives the first input voltage or the second input voltage, and the second input terminal of the first differential pair is commonly coupled to the output terminal of the first amplifier circuit to receive the first output voltage. The second amplifier circuit has a plurality of second transistors. The second transistors form a plurality of second differential pairs, and all the second transistors have the same second conductivity type. The first input terminal of each second differential pair receives the third input voltage or the fourth input voltage, and the second input terminal of the second differential pair is coupled to the output terminal of the second amplifier circuit to receive the second output voltage. Wherein the first conductivity type is opposite to the second conductivity type, the voltage values of the first input voltage and the second input voltage are between the first voltage range, and the voltage values of the third input voltage and the fourth input voltage are between Between the second voltage ranges, the first voltage range and the second voltage range do not overlap.

Based on the above, the driving voltage generator provided by the present invention provides differential pairs of different conductivity types according to different input voltage voltage ranges to perform interpolation operations. In this way, the error of the output voltage generated by the driving voltage generator according to the interpolation operation can be reduced, improving the accuracy of the output voltage.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below and described in detail in conjunction with the accompanying drawings.

Please refer to FIG. 1, which is a schematic diagram of a driving voltage generator according to an embodiment of the invention. The driving voltage generator 100 includes amplifier circuits 110 and 120. The amplifying circuit 110 includes a plurality of transistors N11-NN1 and N12-NN2, and the transistors N11-NN1 form a plurality of differential pairs with the transistors N12-NN2, respectively. The amplifier circuit 110 receives a plurality of input voltages VIN1 and generates an output voltage AVF1. It is worth noting that in this embodiment, all the transistors N11 ~ NN1 and N12 ~ NN2 used to form multiple differential pairs have the same conductivity type. In this embodiment, all the transistors N11 ~ NN1 and N12 ~ NN2 are N-type transistors. Taking a single differential pair as an example (for example, a differential pair formed by transistors N11 and N12), the control terminal of the transistor N12 receives the output voltage AVF1 generated by the amplifier circuit 110. The control terminal of the transistor N11 receives one of the input voltage VIN1. In this embodiment, each input voltage VIN1 may be the input voltage VH1 or the input voltage VL1, where the voltage value of the input voltage VH1 is greater than the voltage value of the input voltage VL1. The amplifier circuit 110 generates the output voltage AVF1 by receiving a plurality of input voltages VIN1 as the input voltage VH1 or the input voltage VL1, and performing interpolation operations on the plurality of input voltages VIN1.

In this embodiment, the voltage values of the input voltage VH1 and the input voltage VL1 can be set to be between a first voltage range. The first voltage range is greater than the voltage value of a reference power supply and less than the voltage value of the power supply voltage received by the amplifier circuit 110. Taking the driving voltage generator applied to the display device as an example, the reference power source may be a common voltage in the display device.

On the other hand, the amplifier circuit 120 includes a plurality of transistors P11 to PN1 and P12 to PN2. The transistors P11 to PN1 form a plurality of differential pairs with the transistors P12 to PN2, respectively. The amplifier circuit 120 receives a plurality of input voltages VIN2 and generates an output voltage AVF2. It is worth noting that in this embodiment, all the transistors P11 ~ PN1 and P12 ~ PN2 used to form multiple differential pairs have the same conductivity type. In this embodiment, all the transistors P11 ~ PN1 and P12 ~ PN2 are P-type transistors. Taking a single differential pair as an example (for example, a differential pair formed by transistors P11 and P12), the control terminal of the transistor P12 receives the output voltage AVF2 generated by the amplifier circuit 120. The control terminal of the transistor P11 receives one of the input voltage VIN2. In this embodiment, each input voltage VIN2 may be the input voltage VH2 or the input voltage VL2, wherein the voltage value of the input voltage VH2 is greater than the voltage value of the input voltage VL2, and the voltage value of the input voltage VH2 is less than the voltage value of the input voltage VL1 . The amplifier circuit 120 generates the output voltage AVF2 by receiving a plurality of input voltages VIN2 as the input voltage VH2 or the input voltage VL2, and performing interpolation operations on the plurality of input voltages VIN2.

In this embodiment, the voltage values of the input voltage VH2 and the input voltage VL2 can be set between a second voltage range. The second voltage range is smaller than the aforementioned voltage value of the reference power source and greater than the voltage value of the reference ground voltage received by the amplifier circuit 120. Also taking the driving voltage generator applied to the display device as an example, the reference power source is a common voltage in the display device.

It can be known from the above description that in the driving voltage generator 100, the amplifier circuit 110 provides N-type differential pairs formed by N-type transistors N11 ~ NN2 to receive input voltages VH1 and VL1 having relatively high voltages, the amplifier circuit 120 provides P-type differential pairs formed by P-type transistors P11 ~ PN2 to receive input voltages VH2 and VL2 having relatively low voltages, and performs interpolation operations respectively. Under this premise, the N-type transistors N11-NN2 in the amplifier circuit 110 and the P-type transistors P11-PN2 in the amplifier circuit 120 will not be turned off due to the change in the input voltage. It can effectively ensure the accuracy of the generated output voltages AVF1 and AVF2. Moreover, the driving voltage generator 100 of the embodiment of the present invention can effectively reduce the number of differential pairs required in a single amplifier circuit 110, 120, reduce the area required by the circuit, and reduce the cost.

It is worth mentioning that, when applied to a liquid crystal display device, the driving voltage generator 100 can simultaneously provide a positive driving voltage and a negative driving voltage. The output voltage AVF1 generated by the amplifier circuit 110 can be used as a positive driving voltage, and the output voltage AVF2 generated by the amplifier circuit 120 can be used as a negative driving voltage.

Please refer to FIG. 2, which is a schematic diagram of an implementation of an amplifier circuit according to an embodiment of the present invention. The amplifier circuit 200 shown in FIG. 2 can be used to generate an output voltage AVF1 as a positive driving voltage. The amplifying circuit 200 includes transistors N11 ~ NN1 and N12 ~ NN2. Transistors N11 ~ NN1 and transistors N12 ~ NN2 respectively form multiple differential pairs. Among them, transistors N11 ~ NN1 and transistors N12 ~ NN2 are all N-type. Transistor. The amplifier circuit 200 also includes current sources IS1 ~ ISN, a gain stage circuit 210, and an output stage circuit 220. The current sources IS1 ~ ISN are respectively coupled to the differential pairs formed by the transistors N11 ~ NN1 and the transistors N12 ~ NN2, respectively, and are coupled to the reference ground voltage AGND.

In this embodiment, the end points of each transistor N11 ~ NN1 that are not coupled to the current sources IS1 ~ ISN are commonly coupled to the differential output DE1, and the transistor N12 ~ NN2 are not coupled to the current sources IS1 ~ ISN The end of is commonly coupled to the differential output DE2. In addition, the input voltage VIN1 may have N voltages, including A input voltages VH1 and B input voltages VL1, where A + B = N, and A, B, and N are all natural numbers. The differential pairs of transistors N11 ~ NN1 and transistors N12 ~ NN2 are interpolated by receiving the input voltage VIN1 as the input voltage VH1 or the input voltage VL1, and according to the size of the respective current sources IS1 ~ ISN Finally, the result is transmitted to the differential output terminals DE1 and DE2, where IS1 ~ ISN can be current sources of equal or different sizes.

On the other hand, the gain stage circuit 210 is coupled to the differential output terminals DE1 and DE2. The gain stage circuit 210 provides an active load and amplifies the results of the interpolation operation generated according to the differentials formed by the transistors N11-NN1 and N12-NN2, respectively, and generates the gain voltage VG1 and the gain voltage VG2.

The output stage circuit 220 is coupled to the gain stage circuit 210 and receives the gain voltage VG1 and the gain voltage VG2. The output stage circuit 220 generates the output voltage AVF1 according to the gain voltage VG1 and the gain voltage VG2.

Please refer to FIG. 3 below, which illustrates a schematic diagram of an implementation of an amplifier circuit according to an embodiment of the present invention. The amplifying circuit 300 shown in FIG. 3 can be used to generate an output voltage AVF1 as a positive driving voltage. The amplifier circuit 300 includes a plurality of differential pairs composed of transistors N11 to NN2, current sources IS1 to ISN, a gain stage circuit 310, and an output stage circuit 320. All the differential pairs in the amplifier circuit 300 are composed of the same conductivity type (N-type) transistors N11 ~ NN2, where the control terminals of the transistors N11 ~ NN1 receive the input voltage VH1 or VL1, and the transistor N12 ~ The control terminal of NN2 receives the output voltage AVF1 together. The first ends of the transistors N11 ~ NN1 are commonly coupled to the differential output terminal DE1, and the second ends of the transistors N11 ~ NN1 are respectively coupled to the current sources IS1 ~ ISN. The first ends of the transistors N12 ~ NN2 are commonly coupled to the differential output terminal DE2, and the second ends of the transistors N12 ~ NN2 are respectively coupled to the current sources IS1 ~ ISN.

Each current source IS1 ~ ISN can be composed of one or more transistors. Taking the current source IS1 as an example, the current source IS1 includes transistors N4_1 and N3_1. The transistors N4_1 and N3_1 are connected in series between the second end of the transistor N11 and the reference ground AGND, and are respectively controlled by the bias voltage AVBN2 And AVBN1. Taking the current source ISN as an example, the current source ISN includes transistors N4_N and N3_N. The transistors N4_N and N3_N are connected in series between the second end of the transistor NN1 and the reference ground AGND, and are controlled by the bias voltage AVBN2 and AVBN1. Among them, the transistors N4_1 ~ N4_N and N3_1 ~ N3_N are N-type transistors, and have the same conductivity type as the transistors N11 ~ NN2.

The gain stage circuit 310 includes transistors P5 ~ P8, N5 ~ N8, P10, P11, N10, and N11. The first terminal of the transistor P5 receives the power supply voltage AVDD, the control terminal of the transistor P5 is coupled to the control terminal of the transistor P6, and the control terminal of the transistor P5 is coupled to the second terminal of the transistor P5 through the transistor P7 . The first end of the transistor P6 receives the power supply voltage AVDD, and the second end of the transistor P6 is coupled to the first end of the transistor P8. The transistor P7 is connected in series between the control terminal of the transistor P5 and the second terminal. The control terminal of the transistor P7 is coupled to the control terminal of the transistor P8 and receives the bias voltage AVBP4P.

It is worth mentioning that the coupling terminals CP1 of the transistors P5 and P7 are further coupled to the differential output terminal DE2, and the coupling terminals CP of the transistors P6 and P8 are further coupled to the differential output terminal DE1.

Transistors P10 and N10 are coupled in parallel with each other and connected in series between the second end of transistor P7 and the first end of transistor N7. Transistors N10 and P10 are controlled by bias voltages AVBN3P and AVBP3P, respectively. Transistors N11 and P11 are coupled in parallel with each other and connected in series between the second end of transistor P8 and the first end of transistor N8. Transistors N11 and P11 are controlled by bias voltages AVBN5P and AVBP5P, respectively.

The first end of the transistor N5 is coupled to the second end of the transistor N7, the control terminal of the transistor N5 is coupled to the first end of the transistor N7, and is coupled to the control terminal of the transistor N6. The second terminal receives the reference power supply VMID or the reference ground voltage AGND. The first terminal of the transistor N6 is coupled to the second terminal of the transistor N8. The second terminal of the transistor N6 receives the reference power supply VMID or the reference ground voltage AGND. Transistor N7 is connected in series between transistors N5 and N10, transistor N8 is connected in series between transistors N6 and N11, and the control terminals of transistors N7 and N8 are coupled to each other and receive the bias voltage AVBN4P.

The gain stage circuit 310 generates a gain voltage VG1 at the terminal SP where the transistors P8 and P11 are coupled, and generates a gain voltage VG2 at the terminal SN where the transistors N8 and N11 are coupled. The gain voltages VG1 and VG2 are provided to the output stage circuit 320.

The output stage circuit 320 includes transistors P9 and N9 and capacitors MCP and MCN. The first terminal of the transistor P9 receives the power supply voltage AVDD, the control terminal of the transistor P9 is coupled to the terminal SP, and receives the gain voltage VG1. The second terminal of the transistor P9 forms an output terminal and generates an output voltage AVF1. The first terminal of the transistor N9 is coupled to the second terminal of the transistor P9. The second terminal of the transistor N9 receives the reference power supply VMID or the reference ground voltage AGND. Gain voltage VG2. The capacitor MCP is connected in series between the terminal CP and the second end of the transistor P9, and the capacitor MCN is connected in series between the terminal CN and the first end of the transistor N9, where the terminal CN is the transistors N8 and N6 coupled to each other Endpoint. Among them, the transistors P9 and N9 generate the output voltage AVF1 according to the gain voltages VG1 and VG2 respectively received.

In this embodiment, the voltage value of the power supply voltage AVDD is greater than the voltage value of the reference power supply VMID, and the voltage value of the reference power supply VMID is greater than the voltage value of the reference ground voltage AGND.

Since the input voltages VH1 and VL1 have relatively high voltage values, the transistors N11 ~ NN2 used to form the differential pair will not be turned off. Therefore, the interpolation operation of the amplifying circuit 300 can be correctly performed, and an accurate output voltage AVF1 can be generated. When the amplifier circuit 300 is applied to a display device, the input voltages VH1 and VL1 are both greater than the common voltage.

Please refer to FIG. 4, which is a schematic diagram of an implementation manner of an amplifier circuit according to an embodiment of the present invention. The amplifier circuit 400 shown in FIG. 4 can be used to generate an output voltage AVF2 as a negative polarity driving voltage. Amplifier circuit 400 includes transistors P11 ~ PN1 and P12 ~ PN2. Transistors P11 ~ PN1 and transistors P12 ~ PN2 respectively form multiple differential pairs. Among them, transistors P11 ~ PN1 and transistors P12 ~ PN2 are all P-type. Transistor. The amplifier circuit 400 also includes current sources IS1 ~ ISN, a gain stage circuit 410, and an output stage circuit 420. The current sources IS1 ~ ISN are respectively coupled to the differential pairs formed by the transistors P11 ~ PN1 and the transistors P12 ~ PN2, respectively, and are coupled to the power supply voltage AVDD.

In this embodiment, the terminals of each transistor P11 ~ PN1 that are not coupled to the current sources IS1 ~ ISN are commonly coupled to the differential output DE1, and the transistors P12 ~ PN2 are not coupled to the current sources IS1 ~ ISN The end of is commonly coupled to the differential output DE2. In addition, the input voltage VIN2 may have N voltages, including A input voltages VH2 and B input voltages VL2, where A + B = N, and A, B, and N are all natural numbers. The differential pairs of transistors P11 ~ PN1 and P12 ~ PN2 are interpolated by receiving the input voltage VIN2 as the input voltage VH2 or the input voltage VL2 and according to the size of the respective current sources IS1 ~ ISN After the operation, the result is finally transmitted to the differential output terminals DE1 and DE2, where IS1 ~ ISN can be current sources of equal or different sizes.

On the other hand, the gain stage circuit 410 is coupled to the differential output terminals DE1 and DE2. The gain stage circuit 410 provides an active load and amplifies the result of the interpolation operation generated according to the differentials formed by the transistors P11 ~ PN1 and P12 ~ PN2, respectively, and generates the gain voltage VG1 and the gain voltage VG2.

The output stage circuit 420 is coupled to the rail-type gain stage circuit 410 and receives the gain voltage VG1 and the gain voltage VG2. The output stage circuit 420 generates the output voltage AVF2 according to the gain voltage VG1 and the gain voltage VG2.

Please refer to FIG. 5 below, which illustrates a schematic diagram of an implementation of an amplifier circuit according to an embodiment of the present invention. The amplifier circuit 500 shown in FIG. 5 can be used to generate an output voltage AVF2 as a negative polarity driving voltage. The amplifier circuit 500 includes a plurality of differential pairs composed of transistors P11 to PN2, current sources IS1 to ISN, a gain stage circuit 510, and an output stage circuit 520. All the differential pairs in the amplifier circuit 500 are composed of (P-type) transistors P11 ~ PN2 of the same conductivity type, where the control terminals of the transistors P11 ~ PN1 receive the input voltage VH2 or VL2, and the transistor P12 ~ The control terminal of PN2 receives the output voltage AVF2 together. The second ends of the transistors P11 ~ PN1 are commonly coupled to the differential output DE1, and the first ends of the transistors P11 ~ PN1 are respectively coupled to the current sources IS1 ~ ISN. The second ends of the transistors P12 ~ PN2 are commonly coupled to the differential output DE2, and the first ends of the transistors P12 ~ PN2 are respectively coupled to the current sources IS1 ~ ISN.

Each current source IS1 ~ ISN can be composed of one or more transistors. Taking the current source IS1 as an example, the current source IS1 includes transistors P3_1 and P4_1. The transistors P3_1 and P4_1 are connected in series between the power supply voltage AVDD and the first end of the transistor P11, and are respectively controlled by the bias voltages AVBP1 and AVBP2. Taking the current source ISN as an example, the current source ISN includes transistors P3_N and P4_N. The transistors P3_N and P4_N are connected in series between the power supply voltage AVDD and the first end of the transistor PN1, and are controlled by the bias voltage AVBP1 And AVBP2. Among them, the transistors P4_1 ~ P4_N and P3_1 ~ P3_N are P-type transistors, and have the same conductivity type as the transistors P11 ~ PN2.

The gain stage circuit 510 includes transistors P5 ~ P8, N5 ~ N8, P10, P11, N10, and N11. The first terminal of the transistor P5 receives the power supply voltage AVDD or the reference power supply VMID, the control terminal of the transistor P5 is coupled to the control terminal of the transistor P6, and the control terminal of the transistor P5 is coupled to the transistor P5 through the transistor P7 The second end. The first end of the transistor P6 receives the power supply voltage AVDD or the reference power supply VMID, and the second end of the transistor P6 is coupled to the first end of the transistor P8. The transistor P7 is connected in series between the control terminal of the transistor P5 and the second terminal. The control terminal of the transistor P7 is coupled to the control terminal of the transistor P8 and receives the bias voltage AVBP4N.

Transistors P10 and N10 are coupled in parallel with each other and connected in series between the second end of transistor P7 and the first end of transistor N7. Transistors N10 and P10 are controlled by bias voltages AVBN3N and AVBP3N, respectively. Transistors N11 and P11 are coupled in parallel with each other and connected in series between the second end of transistor P8 and the first end of transistor N8. Transistors N11 and P11 are controlled by bias voltages AVBN5N and AVBP5N, respectively.

The first end of the transistor N5 is coupled to the second end of the transistor N7, the control terminal of the transistor N5 is coupled to the first end of the transistor N7, and is coupled to the control terminal of the transistor N6. The second terminal receives the reference ground voltage AGND. The first terminal of the transistor N6 is coupled to the second terminal of the transistor N8, and the second terminal of the transistor N6 receives the reference ground voltage AGND. Transistor N7 is connected in series between transistors N5 and N10, transistor N8 is connected in series between transistors N6 and N11, and the control terminals of transistors N7 and N8 are coupled to each other and receive the bias voltage AVBN4N.

It is worth mentioning that the coupling terminals CN1 of the transistor N5 and the transistor N7 are further coupled to the differential output terminal DE2, and the coupling terminals CN of the transistor N6 and the transistor N8 are additionally coupled to the differential output terminal DE1.

The gain stage circuit 510 generates a gain voltage VG1 at the terminal SP where the transistors P8 and P11 are coupled, and generates a gain voltage VG2 at the terminal SN where the transistors N8 and N11 are coupled. The gain voltages VG1 and VG2 are provided to the output stage circuit 520.

The output stage circuit 520 includes transistors P9 and N9 and capacitors MCP and MCN. The first terminal of the transistor P9 receives the power supply voltage AVDD or the reference power supply VMID. The control terminal of the transistor P9 is coupled to the terminal SP and receives the gain voltage VG1. The second terminal of the transistor P9 forms an output terminal and generates an output voltage AVF2. The first terminal of the transistor N9 is coupled to the second terminal of the transistor P9. The second terminal of the transistor N9 receives the reference ground voltage AGND. The control terminal of the transistor N9 is coupled to the terminal SN and receives the gain voltage VG2. The capacitor MCP is connected in series between the terminal CP and the second end of the transistor P9, and the capacitor MCN is connected in series between the terminal CN and the first end of the transistor N9, where the terminal CN is the transistors N8 and N6 coupled to each other Endpoint. Among them, the transistors P9 and N9 generate the output voltage AVF2 according to the gain voltages VG1 and VG2 respectively received.

In this embodiment, the voltage value of the power supply voltage AVDD is greater than the voltage value of the reference power supply VMID, and the voltage value of the reference power supply VMID is greater than the voltage value of the reference ground voltage AGND.

Since the input voltages VH2 and VL2 have relatively low voltage values, the transistors P11 ~ PN2 used to form a differential pair will not be turned off. Therefore, the interpolation operation of the amplifying circuit 500 can be correctly executed, and an accurate output voltage AVF2 can be generated. When the amplifier circuit 500 is applied to a display device, the input voltages VH2 and VL2 are less than the common voltage.

Please refer to FIG. 6, which is a schematic diagram of a driving voltage generator according to another embodiment of the invention. The driving voltage generator 600 includes amplifier circuits 612 and 622, decoders 611 and 621, and a signal switcher 630. The decoder 611 is coupled to the amplifier circuit 612. The decoder 611 receives the input voltages VH1 and VL1, and receives the data signal DIN1, and selects the input voltages VH1 and VL1 according to the data signal DIN1 to generate a plurality of input voltages VIN1. For example, taking the data signal DIN1 having three bits as an example, the decoder 611 can generate eight input voltages VIN1. According to the value of the data signal DIN1, the decoder 611 can select A of the eight input voltages VIN1 to be equal to the input voltage VH1, and make the remaining 8-A input voltages VIN1 equal to the input voltage VL1. In addition, according to different designs, the decoder 611 can also generate five input voltages VIN1, and the differential pairs corresponding to the five input voltages can be designed to form 8: 4: 2: 1: 1 according to the current size of IS1 ~ IS5. Five weight ratios. According to the value of the data signal DIN1, the decoder 611 can select A of the five input voltages VIN1 equal to the input voltage VH1, and make the remaining 5-A input voltages VIN1 equal to the input voltage VL1. Of course, the above-mentioned weight ratio can also be designed in other forms. The above description is only an example of implementation and does not limit the scope of implementation of the present invention.

The input voltage VIN1 is transmitted to a plurality of differential pairs in the amplifier circuit 612. The amplifier circuit 612 interpolates according to the input voltage VIN1 and generates an output voltage AVF1.

In addition, the decoder 621 is coupled to the amplifier circuit 622. The decoder 621 receives the input voltages VH2 and VL2, and receives the data signal DIN2, and selects the input voltages VH2 and VL2 according to the data signal DIN2 to generate a plurality of input voltages VIN2. For example, taking the data signal DIN2 having three bits as an example, the decoder 621 can generate eight input voltages VIN2. According to the value of the data signal DIN2, the decoder 621 can select B of the eight input voltages VIN2 to be equal to the input voltage VH2, and make the remaining 8-B input voltages VIN2 equal to the input voltage VL2. In addition, according to different designs, the decoder 621 can also generate five input voltages VIN2, and the differential pairs corresponding to the five input voltages can be designed to form 8: 4: 2: 1: 1 according to the current size of IS1 ~ IS5. Five weight ratios. According to the value of the data signal DIN2, the decoder 621 can select A of the five input voltages VIN2 equal to the input voltage VH2, and make the remaining 5-A input voltages VIN2 equal to the input voltage VL2. By transmitting the input voltage VIN2 to multiple differential pairs in the amplifier circuit 622, the amplifier circuit 622 performs an interpolation operation according to the input voltage VIN2, and generates an output voltage AVF2. Similarly, the above-mentioned weight ratio can also be designed in other forms. The above description is only an example of implementation and does not limit the scope of implementation of the present invention.

In this embodiment, the voltage value of the input voltage VH1 is greater than the voltage value of the input voltage VL1, the voltage value of the input voltage VL1 is greater than the voltage value of the input voltage VH2, and the voltage value of the input voltage VH2 is greater than the voltage value of the input voltage VL2. Moreover, the voltage values of the input voltages VH1 and VL1 can be set to be greater than that of a reference power supply. In the field of display devices, the reference power supply can be a common voltage. Correspondingly, the voltage values of the input voltages VH2 and VL2 can be set to be less than the common voltage.

The signal switch 630 includes a plurality of switches SW1 to SW4, and is coupled between the output terminal of the amplifier circuit 612, the output terminal of the amplifier circuit 622, and the driving terminals DRVE1 and DRVE2. The signal switch 630 receives the control signal CTRL, and according to the control signal CTRL, the output voltage AVF1 is transmitted to one of the driving terminal DRVE1 and the driving terminal DRVE2, and the output voltage AVF2 is transmitted to the driving terminal DRVE1 and the driving terminal DRVE2 One of them.

In detail, when the switches SW1 and SW4 are turned on according to the control signal CTRL, the switches SW2 and SW3 can be turned off according to the control signal CTRL. At the same time, the output voltages AVF1 and AVF2 are transmitted to the driving terminal DRVE1 and the driving terminal DRVE2 through the switches SW1 and SW4, respectively. In this way, a positive output voltage AVF1 and a negative output voltage AVF2 can be generated on the driving terminal DRVE1 and the driving terminal DRVE2, respectively.

On the other hand, when the switches SW2 and SW3 are turned on according to the control signal CTRL, the switches SW1 and SW4 can be turned off according to the control signal CTRL. At the same time, the output voltages AVF1 and AVF2 are transmitted to the driving terminal DRVE2 and the driving terminal DRVE1 through the switches SW3 and SW2, respectively. In this way, a negative output voltage AVF2 and a positive output voltage AVF1 can be generated on the driving terminal DRVE1 and the driving terminal DRVE2 respectively, and the purpose of polarity inversion is achieved.

In this embodiment, the switches SW1 to SW4 can be constructed by any form of transistors, or can also be constructed by circuit elements of a transmission gate, without specific restrictions.

It is worth noting that when setting a high-bit drive voltage generator, a 7-bit decoder, for example, can be provided at the front end of the drive voltage generator 600, and then the drive voltage generator 600 can be used to provide a 3-bit inner-difference operation The ability to amplify circuits 612, 622 can complete the design of a 10-bit drive voltage generator. Moreover, on the premise that the amplifying circuits 612 and 622 can generate accurate interpolation calculation results, the performance of the driving voltage generator 600 can be effectively improved.

In summary, the present invention provides a plurality of differential pairs including only a single conductivity type to configure an amplifier circuit, and enable different amplifier circuits to receive input voltages in different voltage ranges to perform internal difference operations. In this way, each amplifying circuit can generate an accurate internal difference calculation result, and improve the accuracy of the output voltage generated by the driving voltage generator.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100, 600‧‧‧ drive voltage generator

110, 120, 200, 300, 400, 500, 612, 622

210, 310, 410, 510‧‧‧ gain stage circuit

220, 320, 420, 520‧‧‧ output stage circuit

611、621‧‧‧decoder

630‧‧‧Signal switch

N11 ~ NN1, N12 ~ NN2, P11 ~ PN1, P12 ~ PN2, N3_1 ~ N3_N, N4_1 ~ N4_N, P3_1 ~ P3_N, P4_1 ~ P4_N, P5 ~ P11, N5 ~ N11

VIN1, VIN2, VH1, VH2, VL1, VL2 ‧‧‧ input voltage

AVF1, AVF2 ‧‧‧ output voltage

IS1 ~ ISN‧‧‧Current source

AGND‧‧‧Reference ground voltage

DE1, DE2‧‧‧ differential output

VG1, VG2 ‧‧‧ gain voltage

AVBN2, AVBN1, AVBP1, AVBP2, AVBN3N, AVBN3P, AVBP3P, AVBP3N, AVBP4P, AVBP4N, AVBN4P, AVBN4N, AVBN5N, AVBP5N, AVBN5P, AVBP5P‧‧‧ bias voltage

VMID‧‧‧Reference power supply

MCP, MCN‧‧‧Capacitor

SP, SN, CN, CN1, CP, CP1‧‧‧ endpoint

AVDD‧‧‧Power supply voltage

SW1 ~ SW4‧‧‧ switch

DRVE1, DRVE2 ‧‧‧ drive end

DIN1, DIN2‧‧‧ data signal

CTRL‧‧‧Control signal

FIG. 1 is a schematic diagram of a driving voltage generator according to an embodiment of the invention. FIG. 2 is a schematic diagram of an implementation of an amplifier circuit according to an embodiment of the invention. FIG. 3 is a schematic diagram of an implementation of an amplifier circuit according to an embodiment of the invention. FIG. 4 is a schematic diagram of an implementation of an amplifier circuit according to an embodiment of the invention. FIG. 5 is a schematic diagram of an implementation of an amplifier circuit according to an embodiment of the invention. 6 is a schematic diagram of a driving voltage generator according to another embodiment of the invention.

Claims (14)

A driving voltage generator includes: a first amplifier circuit having a plurality of first transistors, the first transistors forming a plurality of first differential pairs, all of the first transistors have the same first A conductive type, wherein the first input terminals of each first differential pair receive a first input voltage or a second input voltage, and the second input terminals of the first differential pairs are commonly coupled to the first An output terminal of an amplifier circuit to receive a first output voltage; and a second amplifier circuit having a plurality of second transistors, the second transistors forming a plurality of second differential pairs, all of the second The transistors have the same second conductivity type, wherein the first input of each second differential pair receives a third input voltage or a fourth input voltage, and the second inputs of the second differential pairs The terminal is coupled to the output terminal of the second amplifying circuit to receive a second output voltage, wherein the first conductivity type is opposite to the second conductivity type, the first input voltage and the second input voltage The voltage value is between a first voltage range, the third input And the fourth voltage value is interposed between the input voltage and a second voltage range, the voltage of the first voltage range and the second range do not overlap. The driving voltage generator according to item 1 of the patent application range, wherein the first voltage range is between a power supply voltage and a reference power supply, and the second voltage range is between the reference power supply and a reference ground voltage, the The first conductivity type is N-type, the second conductivity type is P-type, the power supply voltage is greater than the reference power supply, and the reference power supply is greater than the reference ground voltage. The driving voltage generator as described in item 1 of the patent application scope, wherein the first amplifying circuit further includes: a plurality of current sources respectively connected in series between the first differential pair and a reference ground voltage, according to a first A bias voltage to generate a plurality of currents; a gain stage circuit, coupled to a first differential output terminal and a second differential output terminal of each first differential pair, the gain stage circuit provides an active load And generate a first gain voltage and a second gain voltage; and an output stage circuit, coupled to the gain stage circuit, to generate the first output voltage according to the first gain voltage and the second gain voltage. The driving voltage generator of claim 3, wherein each of the current sources includes: at least one third transistor having a first end coupled to the corresponding first differential pair, the at least one third power The second terminal of the crystal receives a reference ground voltage, the control terminal of the at least one third transistor receives the first bias voltage, and the conductivity type of the at least one third transistor and the conductivity of the first transistors Same type. The driving voltage generator as described in item 3 of the patent application range, wherein the gain stage circuit includes: a third transistor having a first terminal to receive a power supply voltage, the second terminal of the third transistor and the control terminal Coupled to the second differential output terminal; a fourth transistor having a first terminal to receive the power supply voltage, a second terminal of the fourth transistor coupled to the first differential output terminal, the fourth The control terminal of the crystal is coupled to the control terminal of the third transistor; a fifth transistor, the first terminal and the control terminal are coupled to each other, and the second terminal of the fifth transistor is coupled to a reference ground voltage or a A reference power source; a sixth transistor having a control terminal coupled to the control terminal of the fifth transistor, a second terminal of the sixth transistor coupled to the reference ground voltage or the reference power source; a seventh transistor , Connected in series between the second end of the third transistor and the first end of the fifth transistor, controlled by a second bias voltage; an eighth transistor, connected in series with the third transistor The second end and the first end of the fifth transistor are controlled by a third bias voltage A ninth transistor, connected in series between the second end of the fourth transistor and the first end of the sixth transistor, controlled by a fourth bias voltage; and a tenth transistor, in series Connected between the second end of the fourth transistor and the first end of the sixth transistor, controlled by a fifth bias voltage. The driving voltage generator as described in item 5 of the patent application scope, wherein the gain stage circuit further comprises: an eleventh transistor connected in series to the second end of the third transistor and the control of the third transistor Between the ends; a twelfth transistor having a first end coupled to the second end of the fourth transistor, the second end of the twelfth transistor coupled to the ninth transistor, and used to generate The first gain voltage, the control terminal of the twelfth transistor is coupled to the control terminal of the eleventh transistor; a thirteenth transistor is connected in series between the first end of the fifth transistor and the first Between seven transistors; and a fourteenth transistor connected in series between the first end of the sixth transistor and the ninth transistor, the control end of the fourteenth transistor is coupled to the thirteenth transistor The control end of the crystal. The driving voltage generator according to item 3 of the patent application scope, wherein the output stage circuit includes: a third transistor having a first terminal to receive a power supply voltage, and a control terminal of the third transistor to receive the first gain Voltage, the second terminal of the third transistor outputs the first output voltage; a first capacitor is connected in series between the gain stage circuit and the second terminal of the third transistor; a fourth transistor has a One end is coupled to the second end of the third transistor, the control end of the fourth transistor receives the second gain voltage, and the second end of the fourth transistor receives a reference ground voltage or a reference power source; and A second capacitor is connected in series between the first end of the fourth transistor and the gain stage circuit. The driving voltage generator as described in item 1 of the patent application scope, wherein the second amplifying circuit further includes: a plurality of current sources respectively connected in series between the second differential pairs and a power supply voltage, according to a first Bias voltage to generate multiple currents respectively; a gain stage circuit coupled to a first differential output terminal and a second differential output terminal of each second differential pair, the gain stage circuit provides an active load, And generate a first gain voltage and a second gain voltage; and an output stage circuit, coupled to the gain stage circuit, to generate the second output voltage according to the first gain voltage and the second gain voltage. The driving voltage generator according to item 8 of the patent application scope, wherein each of the current sources includes: at least one third transistor having a first terminal to receive the power supply voltage, and a second terminal of the at least one third transistor Connected to the corresponding second differential pair, the control terminal of the at least one third transistor receives the first bias voltage, and the conductivity type of the at least one third transistor and the conductivity type of the second transistors The state is the same. The driving voltage generator as described in item 8 of the patent application range, wherein the gain stage circuit includes: a third transistor having a first terminal to receive the power supply voltage or a reference power, and a second terminal of the third transistor A control transistor is coupled to the control terminal; a fourth transistor has a first terminal to receive the power supply voltage or the reference power supply; the control terminal of the fourth transistor is coupled to the control terminal of the third transistor; a fifth circuit The crystal has a first end and a control end coupled to the second differential output end together, the second end of the fifth transistor is coupled to a reference ground voltage; a sixth transistor has a first end coupling To the first differential output terminal, the second terminal of the sixth transistor is coupled to the reference ground voltage, the control terminal of the sixth transistor is coupled to the control terminal of the fifth transistor; a seventh A crystal connected in series between the second end of the third transistor and the first end of the fifth transistor, controlled by a second bias voltage; an eighth transistor connected in series to the third transistor Between the second end of the second transistor and the first end of the fifth transistor, controlled by a third bias Voltage; a ninth transistor connected in series between the second end of the fourth transistor and the first end of the sixth transistor, controlled by a fourth bias voltage; and a tenth transistor, Connected in series between the second end of the fourth transistor and the first end of the sixth transistor, it is controlled by a fifth bias voltage. The driving voltage generator as described in item 10 of the patent application range, wherein the gain stage circuit further includes: an eleventh transistor connected in series to the second end of the third transistor and the control of the third transistor Between the ends; a twelfth transistor having a first end coupled to the second end of the fourth transistor, the second end of the twelfth transistor coupled to the ninth transistor, and used to generate The first gain voltage, the control terminal of the twelfth transistor is coupled to the control terminal of the eleventh transistor; a thirteenth transistor is connected in series between the first end of the fifth transistor and the first Between seven transistors; and a fourteenth transistor connected in series between the first end of the sixth transistor and the ninth transistor, the control end of the fourteenth transistor is coupled to the thirteenth transistor The control end of the crystal. The driving voltage generator according to item 8 of the patent application scope, wherein the output stage circuit includes: a third transistor having a first terminal to receive the power supply voltage or a reference voltage, and a control terminal of the third transistor to receive The first gain voltage, the second terminal of the third transistor outputs the second output voltage; a first capacitor connected in series between the gain stage circuit and the second terminal of the third transistor; a fourth power The crystal has a first end coupled to the second end of the third transistor, the control end of the fourth transistor receives the second gain voltage, and the second end of the fourth transistor receives a reference ground voltage; and A second capacitor is connected in series between the first end of the fourth transistor and the gain stage circuit. The driving voltage generator as described in item 1 of the patent application scope further includes: a first decoder coupled to the first input terminals of the first differential pairs, and receiving a first bit having a plurality of bits A digital signal, and selectively provide the first input voltage or the second input voltage to the first input terminal of each first differential pair according to the first digital signal; and a second decoder coupled to the several The first input terminal of the second differential pair receives a second digital signal having multiple bits, and selects to provide the third input voltage or the fourth input voltage to each second according to the second digital signal The first input of the differential pair. The driving voltage generator as described in item 1 of the patent application scope further includes: a signal switch coupled to the output terminal of the first amplifying circuit, the output terminal of the second amplifying circuit, a first driving terminal and A control signal is received between a second driving terminal, and the first output voltage is transmitted to one of the first driving terminal and the second driving terminal according to the control signal, so that the second output voltage is transmitted To the other of the first driving end and the second driving end.