TW201442418A - Folding operational amplifier - Google Patents
Folding operational amplifier Download PDFInfo
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- TW201442418A TW201442418A TW102114350A TW102114350A TW201442418A TW 201442418 A TW201442418 A TW 201442418A TW 102114350 A TW102114350 A TW 102114350A TW 102114350 A TW102114350 A TW 102114350A TW 201442418 A TW201442418 A TW 201442418A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
- H03F1/22—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
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Abstract
Description
本發明係有關於一種摺疊式運算放大電路，其係尤指一種可減少產生一靜態電流的摺疊式運算放大電路。
The present invention relates to a foldable operational amplifier circuit, and more particularly to a foldable operational amplifier circuit that reduces the generation of a quiescent current.
按，隨著半導體技術的進步，積體電路的操作電壓也越來越低。因此，在設計類比電路時，常會發生運算放大器的輸入和輸出共模電壓不足的問題。為了解決此問題，運算放大器需要具備有軌對軌(Rail-to-Rail)輸入及輸出之共模電壓範圍。
一般來說，傳統運算放大器通常為一兩級結構的放大器，其包含有一第一級放大電路(放大級)以及一第二級輸出電路(輸出級)。傳統運算放大器中之第一級放大電路係用來提高運算放大器的增益，而第二級輸出電路則用來推動運算放大器所連接的電容性或是電阻性負載。According to the advancement of semiconductor technology, the operating voltage of the integrated circuit is also getting lower and lower. Therefore, when designing an analog circuit, the problem of insufficient input-output common-mode voltage of the operational amplifier often occurs. To solve this problem, the op amp needs to have a common-mode voltage range of the rail-to-rail input and output.
In general, a conventional operational amplifier is usually a two-stage amplifier including a first-stage amplifying circuit (amplifying stage) and a second-stage output circuit (output stage). The first stage of the amplifier in a conventional operational amplifier is used to increase the gain of the operational amplifier, while the second stage of the output is used to drive the capacitive or resistive load to which the operational amplifier is connected.
現今在高解析度(例如24位元灰階)之驅動晶片設計方面，經常使用差動對(Differential Pair)線性內插技術。然而，現今使用差動對的架構均為”單一”輸入差動對，但在實際應用於顯示裝置的驅動晶片上，由於輸入影像資料範圍很廣，故大部分多使用”雙”輸入差動對，其中，雖然使用雙輸入差動對可以含蓋所有影像資料，但必須增加一路徑的靜態電流消耗，進而增加耗電。Differential pair linear interpolation techniques are often used today in high resolution (e.g., 24-bit gray scale) drive wafer design. However, today's architectures using differential pairs are "single" input differential pairs, but on the driver chips actually used in display devices, most of the "double" input differentials are used because of the wide range of input image data. Yes, although the use of a dual input differential pair can cover all image data, it is necessary to increase the quiescent current consumption of a path, thereby increasing power consumption.
因此，如何針對上述問題而提出一種新穎摺疊式運算放大電路，其可避免增加一路徑的靜態電流消耗，進而達到省電的目的，使可解決上述之問題。
Therefore, how to solve the above problems and propose a novel folding operation amplifying circuit, which can avoid the quiescent current consumption of a path, thereby achieving the purpose of power saving, so that the above problems can be solved.
本發明之目的之一，在於提供一種摺疊式運算放大電路，其藉由一控制開關電路依據一珈瑪電路之一珈瑪訊號而控制該差動輸入級電路產生該第一尾端電流或該第二尾端電流，以減少一路徑的靜態電流消耗，進而達到省電的目的。One of the objectives of the present invention is to provide a foldable operational amplifier circuit that controls a differential input stage circuit to generate the first tail current or a control circuit according to a gamma signal of a gamma circuit. The second tail current is used to reduce the quiescent current consumption of a path, thereby achieving the purpose of power saving.
本發明之摺疊式運算放大電路包含一差動輸入級電路、一電流鏡電路、一輸出級電路與一控制開關電路。差動輸入級電路依據至少一輸入訊號，產生一第一尾端電流與一第二尾端電流；電流鏡電路耦接差動輸入級電路，並依據第一尾端電流與第二尾端電流，產生一第一鏡電流與一第二鏡電流；輸出級電路耦接電流鏡電路，並依據第一鏡電流與第二鏡電流，產生一輸出電流；以及控制開關電路耦接差動輸入級電路與電流鏡電路之間，並依據一珈瑪電路之一珈瑪訊號而控制差動輸入級電路產生第一尾端電流或第二尾端電流。如此，本發明藉由控制開關電路依據珈瑪電路之珈瑪訊號而控制差動輸入級電路產生第一尾端電流或第二尾端電流，以減少一路徑的靜態電流消耗，進而達到省電的目的。
The folding operational amplifier circuit of the present invention comprises a differential input stage circuit, a current mirror circuit, an output stage circuit and a control switch circuit. The differential input stage circuit generates a first tail current and a second tail current according to the at least one input signal; the current mirror circuit is coupled to the differential input stage circuit, and according to the first tail current and the second tail current Generating a first mirror current and a second mirror current; the output stage circuit is coupled to the current mirror circuit, and generates an output current according to the first mirror current and the second mirror current; and the control switch circuit is coupled to the differential input stage Between the circuit and the current mirror circuit, the differential input stage circuit is controlled to generate a first tail current or a second tail current according to a gamma signal of a gamma circuit. In this way, the present invention controls the differential input stage circuit to generate the first tail current or the second tail current according to the gamma signal of the gamma circuit to reduce the quiescent current consumption of a path, thereby achieving power saving. the goal of.
1．．．摺疊式運算放大電路1. . . Folding operational amplifier circuit
10．．．差動輸入級電路10. . . Differential input stage circuit
12．．．第一差動輸入單元12. . . First differential input unit
120．．．差動單元120. . . Differential unit
122．．．尾端電流源122. . . Tail current source
14．．．第二差動輸入單元14. . . Second differential input unit
140．．．差動單元140. . . Differential unit
142．．．尾端電流源142. . . Tail current source
22．．．第一差動輸入模組twenty two. . . First differential input module
220．．．第一尾端差動單元220. . . First end differential unit
222．．．第二尾端差動單元222. . . Second tail differential unit
224．．．第三尾端差動單元224. . . Third tail differential unit
226．．．第四尾端差動單元226. . . Fourth tail differential unit
24．．．第二差動輸入模組twenty four. . . Second differential input module
240．．．第五尾端差動單元240. . . Fifth tail differential unit
242．．．第六尾端差動單元242. . . Sixth end differential unit
244．．．第七尾端差動單元244. . . Seventh end differential unit
246．．．第八尾端差動單元246. . . Eighth end differential unit
30．．．電流鏡電路30. . . Current mirror circuit
32．．．第一電流鏡32. . . First current mirror
34．．．第二電流鏡34. . . Second current mirror
35．．．第一電流控制器35. . . First current controller
36．．．第二電流控制器36. . . Second current controller
37．．．第三電流控制器37. . . Third current controller
38．．．第四電流控制器38. . . Fourth current controller
50．．．輸出級電路50. . . Output stage circuit
52．．．第一電晶體52. . . First transistor
54．．．第二電晶體54. . . Second transistor
70．．．控制開關電路70. . . Control switch circuit
72．．．第一開關模組72. . . First switch module
720．．．第一控制開關720. . . First control switch
722．．．第二控制開關722. . . Second control switch
724．．．第三控制開關724. . . Third control switch
726．．．第四控制開關726. . . Fourth control switch
74．．．第二開關模組74. . . Second switch module
740．．．第五控制開關740. . . Fifth control switch
742．．．第六控制開關742. . . Sixth control switch
744．．．第七控制開關744. . . Seventh control switch
746．．．第八控制開關746. . . Eighth control switch
82．．．第一電容82. . . First capacitor
84．．．第二電容84. . . Second capacitor
90．．．解碼電路90. . . Decoding circuit
900．．．第一解碼單元900. . . First decoding unit
902．．．第二解碼單元902. . . Second decoding unit
9020．．．2對4解碼器9020. . . 2-to-4 decoder
9022．．．第一邏輯電路9022. . . First logic circuit
9024．．．第一輸出開關電路9024. . . First output switching circuit
904．．．第三解碼單元904. . . Third decoding unit
9040．．．4對16解碼器9040. . . 4 to 16 decoder
9042．．．第二邏輯電路9042. . . Second logic circuit
9044．．．第二輸出開關電路9044. . . Second output switching circuit
906．．．第四解碼單元906. . . Fourth decoding unit
908．．．數位類比轉換單元908. . . Digital analog conversion unit
9080．．．第三輸出開關電路9080. . . Third output switching circuit
92．．．比較器92. . . Comparators
94．．．數位比較電路94. . . Digital comparison circuit
第一圖為本發明之一實施例之摺疊式放大電路的電路圖；
第二圖為本發明之一實施例之控制開關電路依據珈碼電路之珈碼訊號而導通或截止的動作示意圖；
第三圖為本發明之一實施例之第二解碼單元的電路圖；
第四圖為本發明之一實施例之第三解碼單元與第四解碼單元的電路圖；
第五圖為本發明之一實施例之數位類比轉換單元的電路圖；
第六圖為本發明之另一實施例之控制開關電路依據珈碼電路之珈碼訊號而導通或截止的動作示意圖；以及
第七圖為本發明之另一實施例之摺疊式放大電路的電路圖。
The first figure is a circuit diagram of a folding amplifier circuit according to an embodiment of the present invention;
2 is a schematic diagram of an operation of controlling a switching circuit to be turned on or off according to a weight signal of a weight circuit according to an embodiment of the present invention;
The third figure is a circuit diagram of a second decoding unit according to an embodiment of the present invention;
The fourth figure is a circuit diagram of a third decoding unit and a fourth decoding unit according to an embodiment of the present invention;
Figure 5 is a circuit diagram of a digital analog conversion unit according to an embodiment of the present invention;
6 is a schematic diagram of an operation of controlling a switching circuit to be turned on or off according to a weight signal of a weight circuit according to another embodiment of the present invention; and a seventh diagram of a circuit diagram of a folding type amplifying circuit according to another embodiment of the present invention; .
在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域中具有通常知識者應可理解，硬體製造商可能會用不同的名詞來稱呼同一個元件。本說明書及後續的申請專利範圍並不以名稱的差異來作為區分元件的方式，而是以元件在功能上的差異來作為區分的準則。在通篇說明書及後續的請求項當中所提及的「包含」係為一開放式的用語，故應解釋成「包含但不限定於」。以外，「耦接」一詞在此係包含任何直接及間接的電氣連接手段。因此，若文中描述一第一裝置耦接於一第二裝置，則代表該第一裝置可直接電氣連接於該第二裝置，或透過其他裝置或連接手段間接地電氣連接至該第二裝置。Certain terms are used throughout the description and following claims to refer to particular elements. Those of ordinary skill in the art should understand that a hardware manufacturer may refer to the same component by a different noun. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device through other devices or connection means.
茲為使 貴審查委員對本發明之結構特徵及所達成之功效有更進一步之瞭解與認識，謹佐以較佳之實施例及配合詳細之說明，說明如後：In order to provide a better understanding and understanding of the structural features and efficacies of the present invention, the preferred embodiments and detailed descriptions are provided as follows:
請參閱第一圖，係為本發明之一實施例之摺疊式放大電路的電路圖。如圖所示，本發明之摺疊式運算放大電路1包含一差動輸入級電路10、一電流鏡電路30、一輸出級電路50與一控制開關電路70。差動輸入級電路10依據至少一輸入訊號，控制一第一尾端電流I1與一第二尾端電流I2流入差動輸入級之電流大小。於本實施例中，差動輸入級電路10接收4個輸入訊號，分別為一第一輸入訊號IN1、一第二輸入訊號IN2、一第三輸入訊號IN3與一第四輸入訊號IN4。差動輸入級電路10依據第一輸入訊號IN1至第四輸入訊號IN4而控制第一尾端電流I1與第二尾端電流I2流入差動輸入級之各元件之電流大小，其中第一輸入訊號IN1至第四輸入訊號IN4代表類比訊號。參考第二圖之D[7]~D[0]數位訊號，該些數位訊號的數值決定第一尾端電流I1與第二尾端電流I2的產生與否。Please refer to the first figure, which is a circuit diagram of a folding amplifier circuit according to an embodiment of the present invention. As shown, the folding operational amplifier circuit 1 of the present invention comprises a differential input stage circuit 10, a current mirror circuit 30, an output stage circuit 50 and a control switch circuit 70. The differential input stage circuit 10 controls the current flowing into the differential input stage by a first tail current I 1 and a second tail current I 2 according to at least one input signal. In this embodiment, the differential input stage circuit 10 receives four input signals, which are a first input signal IN1, a second input signal IN2, a third input signal IN3, and a fourth input signal IN4. The differential input stage circuit 10 controls the currents of the first tail current I 1 and the second tail current I 2 flowing into the components of the differential input stage according to the first input signal IN1 to the fourth input signal IN4, wherein the first The input signal IN1 to the fourth input signal IN4 represent analog signals. Referring to the D[7]~D[0] digital signals of the second figure, the values of the digital signals determine whether the first tail current I 1 and the second tail current I 2 are generated.
電流鏡電路30耦接差動輸入級電路10，並依據差動輸入級電路10產生之第一尾端電流I1與第二尾端電流I2，而產生一第一鏡電流Im1與一第二鏡電流Im2。輸出級電路50耦接電流鏡電路30，並依據第一鏡電流Im1與第二鏡電流Im2，而產生一輸出電流Io。控制開關電路70耦接差動輸入級電路10與電流鏡電路30之間，並依據D[7]~D[0]之數位訊號而控制差動輸入級電路10產生第一尾端電流I1或第二尾端電流I2，即珈瑪電路產生的珈瑪電壓為差動輸入級電路10的輸入訊號，並且差動輸入級電路10由接收的該些輸入訊號而決定線性內插之電壓值，並由D[7]~D[0]之數位訊號控制第一尾端電流I1與第二尾端電流I2之開或關，所以，控制開關電路70係依據D[7]~D[0]之數位訊號控制產生第一尾端電流I1或第二尾端電流I2。The current mirror circuit 30 is coupled to the differential input stage circuit 10, and generates a first mirror current I m1 and a first tail current I 1 and a second tail current I 2 generated by the differential input stage circuit 10 . The second mirror current I m2 . The output stage circuit 50 is coupled to the current mirror circuit 30 and generates an output current Io according to the first mirror current I m1 and the second mirror current I m2 . The control switch circuit 70 is coupled between the differential input stage circuit 10 and the current mirror circuit 30, and controls the differential input stage circuit 10 to generate the first tail current I 1 according to the digital signals of D[7]~D[0]. Or the second tail current I 2 , that is, the gamma voltage generated by the gamma circuit is the input signal of the differential input stage circuit 10 , and the differential input stage circuit 10 determines the linear interpolation voltage from the received input signals. The value, and the digital signal of D[7]~D[0] controls the opening and closing of the first tail current I 1 and the second tail current I 2 , so the control switch circuit 70 is based on D[7]~ The digital signal control of D[0] produces a first tail current I 1 or a second tail current I 2 .
承上所述，由於本發明之摺疊式運算放大器1係依據D[7]~D[0]之數位訊號而決定使用第一尾端電流I1或第二尾端電流I2，產生輸出電流Io，所以，本發明之摺疊式運算放大器1每次僅會使用第一尾端電流I1或第二尾端電流I2，所以，當本發明之摺疊式運算放大器1使用第一尾端電流I1產生輸出電流Io時，第二尾端電流I2就不需要，如此，本發明之控制開關電路70係會截止差動輸入級電路10停止產生第二尾端電流I2，以減少一路徑的靜態電流消耗，進而達到省電的目的。反之，當本發明之摺疊式運算放大器1使用第二尾端電流I2產生輸出電流Io時，第一尾端電流I1就不需要，如此，本發明之控制開關電路70係會截止差動輸入級電路10停止產生第一尾端電流I1，以達到省電的目的。其中，上述D[7]~D[0]之數位訊號對應一珈瑪電路之一珈瑪訊號，也就是D[7]~D[0]之數位訊號決定珈瑪訊號的電壓準位。As described above, the folding operational amplifier 1 of the present invention determines the use of the first tail current I 1 or the second tail current I 2 to generate an output current according to the digital signal of D[7]~D[0]. Io, therefore, the folding operational amplifier 1 of the present invention only uses the first tail current I 1 or the second tail current I 2 at a time , so when the folding operational amplifier 1 of the present invention uses the first tail current I 1 when the output current Io is generated, a second tail current I 2 does not need, thus, controls the switch circuit 70 of the present invention will be based off of the differential input stage circuit 10 stops generating a second tail current I 2, to reduce a The quiescent current consumption of the path, in order to achieve the purpose of power saving. On the contrary, when the folding operational amplifier 1 of the present invention generates the output current Io using the second tail current I 2 , the first tail current I 1 is not required, and thus, the control switch circuit 70 of the present invention will cut off the differential. The input stage circuit 10 stops generating the first tail current I 1 for power saving purposes. Wherein, the digital signal of the above D[7]~D[0] corresponds to one of the gamma circuits, that is, the digital signal of D[7]~D[0] determines the voltage level of the gamma signal.
本發明之差動輸入級電路10包含一第一差動輸入單元12與一第二差動輸入單元14。第一差動輸入單元12接收輸入訊號，於本實施例中，第一差動輸入單元12接收第一輸入訊號IN1至第四輸入訊號IN4，並依據第一輸入訊號IN1至第四輸入訊號IN4，控制第一尾端電流I1流入差動輸入級之各元件之電流大小，第二差動輸入單元14接收第一輸入訊號IN1至第四輸入訊號IN4，並依據第一輸入訊號IN1至第四輸入訊號IN4，控制第二尾端電流I2流入差動輸入級之各元件之電流大小。The differential input stage circuit 10 of the present invention includes a first differential input unit 12 and a second differential input unit 14. The first differential input unit 12 receives the input signal. In the embodiment, the first differential input unit 12 receives the first input signal IN1 to the fourth input signal IN4, and according to the first input signal IN1 to the fourth input signal IN4. , a first control tail current I 1 flows into each of the magnitude of the current element of the differential input stage, the second differential input unit 14 receives a first input signal IN1 to IN4 of the fourth input signal, and a first input signal IN1 according to the second The four-input signal IN4 controls the current of the second tail current I 2 flowing into each component of the differential input stage.
接上所述，第一差動輸入單元12包含一差動單元120與一尾端電流源122。差動單元120接收第一輸入訊號IN1至第四輸入訊號IN4，並依據第一輸入訊號IN1至第四輸入訊號IN4控制第一尾端電流I1流入差動輸入級之各元件之電流大小，尾端電流源122耦接差動單元120，並依據差動單元120的輸入訊號大小而控制第一尾端電流I1流入差動輸入級之各元件之電流大小，其中，差動單元120包含四組差動對，每一組差動對皆由二個N型場效電晶體組成，四組差動對分別接收第一輸入訊號IN1至第四輸入訊號IN4，於本實施例中，四組差動對中的一個N型場效電晶體的閘極分別接收第一輸入訊號IN1至第四輸入訊號IN4，而四組差動對中的另一個N型場效電晶體的閘極耦接至本發明之摺疊式運算放大器之輸出端。In addition, the first differential input unit 12 includes a differential unit 120 and a tail current source 122. A first differential unit 120 receives the input signal IN1 to IN4 of the fourth input signal, and controls the first tail current I based on the first input signal IN1 to IN4 1 flows into the fourth input signal of the differential input stage of each element of the current magnitude, tail current source 122 coupled to the differential unit 120, and based on the size of the differential input signal to control unit 120 and a first tail current magnitude of the current I 1 flows into each of the elements of the differential input stage, wherein the differential unit 120 comprises Four sets of differential pairs, each set of differential pairs is composed of two N-type field effect transistors, and the four sets of differential pairs respectively receive the first input signal IN1 to the fourth input signal IN4, in this embodiment, four The gates of one of the N-type field effect transistors of the differential pair receive the first input signal IN1 to the fourth input signal IN4, respectively, and the gate coupling of the other N-type field effect transistor of the four sets of differential pairs Connected to the output of the folded operational amplifier of the present invention.
同理，第二差動輸入單元14包含一差動單元140與一尾端電流源142。差動單元140接收第一輸入訊號IN1至第四輸入訊號IN4，並依據第一輸入訊號IN1至第四輸入訊號IN4控制第二尾端電流I2流入差動輸入級之各元件之電流大小，尾端電流源142耦接差動單元140，並依據差動單元140的輸入訊號大小而控制第二尾端電流I2流入差動輸入級之各元件之電流大小，其中，差動單元140包含四組差動對，每一組差動對皆由二個P型場效電晶體組成，四組差動對分別接收第一輸入訊號IN1至第四輸入訊號IN4，於本實施例中，四組差動對中的一個P型場效電晶體的閘極分別接收第一輸入訊號IN1至第四輸入訊號IN4，而四組差動對中的另一個P型場效電晶體的閘極耦接至本發明之摺疊式運算放大器之輸出端。Similarly, the second differential input unit 14 includes a differential unit 140 and a tail current source 142. The differential unit 140 receives the first input signal IN1 to the fourth input signal IN4, and controls the current of the second tail current I 2 flowing into each component of the differential input stage according to the first input signal IN1 to the fourth input signal IN4. The tail current source 142 is coupled to the differential unit 140, and controls the current of the second tail current I 2 flowing into each component of the differential input stage according to the input signal size of the differential unit 140, wherein the differential unit 140 includes Four sets of differential pairs, each set of differential pairs is composed of two P-type field effect transistors, and four sets of differential pairs respectively receive the first input signal IN1 to the fourth input signal IN4, in this embodiment, four The gates of one P-type field effect transistor of the differential pair receive the first input signal IN1 to the fourth input signal IN4, respectively, and the gate coupling of the other P-type field effect transistor of the four sets of differential pairs Connected to the output of the folded operational amplifier of the present invention.
本發明之電流鏡電路30包含一第一電流鏡32與一第二電流鏡34。第一電流鏡32耦接第一差動輸入單元12，並依據第一尾端電流I1而產生第一鏡電流與第二鏡電流之電流Im1與Im2，第二電流鏡34耦接第二差動輸入單元14，並依據第二尾端電流I2，而產生第一鏡電流與第二鏡電流之電流Im1與Im2。此外，本發明之摺疊式運算放大電路1更包含一第一電流控制器35、一第二電流控制器36、一第三電流控制器37與一第四電流控制器38。第一電流控制器35與第二電流控制器36位於第一電流鏡32與第二電流鏡34之間，並第一電流控制器35與第二電流控制器36相互並聯，第三電流控制器37與第四電流控制器38位於第一電流鏡32與第二電流鏡34之間，並第三電流控制器37與第四電流控制器38相互並聯，其中，第一電流控制器35與第四電流控制器38皆受控於一第一偏壓bias1，而第二電流控制器36與第三電流控制器37皆受控於一第二偏壓bias2。再者，第一電流控制器35、第二電流控制器36、第三電流控制器37與第四電流控制器38為一場效電晶體。The current mirror circuit 30 of the present invention includes a first current mirror 32 and a second current mirror 34. The first current mirror 32 is coupled to the first differential input unit 12, and generates currents I m1 and I m2 of the first mirror current and the second mirror current according to the first tail current I 1 , and the second current mirror 34 is coupled The second differential input unit 14 generates currents I m1 and I m2 of the first mirror current and the second mirror current according to the second tail current I2. In addition, the folding operational amplifier circuit 1 of the present invention further includes a first current controller 35, a second current controller 36, a third current controller 37 and a fourth current controller 38. The first current controller 35 and the second current controller 36 are located between the first current mirror 32 and the second current mirror 34, and the first current controller 35 and the second current controller 36 are connected in parallel with each other, and the third current controller 37 and the fourth current controller 38 are located between the first current mirror 32 and the second current mirror 34, and the third current controller 37 and the fourth current controller 38 are connected in parallel with each other, wherein the first current controller 35 and the first The four current controllers 38 are both controlled by a first bias bias1, and the second current controller 36 and the third current controller 37 are both controlled by a second bias bias2. Moreover, the first current controller 35, the second current controller 36, the third current controller 37, and the fourth current controller 38 are one-shot transistors.
本發明之輸出級電路50包含一第一電晶體52與一第二電晶體54。第一電晶體52耦接電流鏡電路30，第二電晶體54耦接電流鏡電路30與第一電晶體52，第一電晶體52與第二電晶體54依據第二鏡電流Im2，而產生輸出電流Io，第一電晶體52與第二電晶體54相互互補，即第一電晶體52為P型場效電晶體，而第二電晶體54為N型場效電晶體。The output stage circuit 50 of the present invention includes a first transistor 52 and a second transistor 54. The first transistor 52 is coupled to the current mirror circuit 30, and the second transistor 54 is coupled to the current mirror circuit 30 and the first transistor 52. The first transistor 52 and the second transistor 54 are based on the second mirror current I m2 . The output current Io is generated, and the first transistor 52 and the second transistor 54 are complementary to each other, that is, the first transistor 52 is a P-type field effect transistor, and the second transistor 54 is an N-type field effect transistor.
另外，本發明之摺疊式運算放大器1更包含一第一電容82與一第二電容84。第一電容82具有一第一端與一第二端，第一電容82之第一端耦接電流鏡電路30之第一電流鏡32，第二電容84具有一第一端與一第二端，第二電容84之第一端耦接第一電容之第二端，第二電容84之第二端耦接於電流鏡電路30之第二電流鏡34，如此，本發明之摺疊式運算放大器1可藉由第一電容82與第二電容84而達到穩定迴路的效果。In addition, the folding operational amplifier 1 of the present invention further includes a first capacitor 82 and a second capacitor 84. The first capacitor 82 has a first end and a second end. The first end of the first capacitor 82 is coupled to the first current mirror 32 of the current mirror circuit 30. The second capacitor 84 has a first end and a second end. The first end of the second capacitor 84 is coupled to the second end of the first capacitor, and the second end of the second capacitor 84 is coupled to the second current mirror 34 of the current mirror circuit 30. Thus, the folded operational amplifier of the present invention 1 The effect of stabilizing the loop can be achieved by the first capacitor 82 and the second capacitor 84.
本發明之控制開關電路70包含一第一開關模組72與一第二開關模組74。第一開關模組72耦接於差動輸入級電路10與電流鏡電路30之間；第二開關模組74耦接於差動輸入級電路10與電流鏡電路30之間，其中，第一開關模組72與第二開關模組74依據D[7]~D[0]之數位訊號而導通或截止。The control switch circuit 70 of the present invention includes a first switch module 72 and a second switch module 74. The first switch module 72 is coupled between the differential input stage circuit 10 and the current mirror circuit 30; the second switch module 74 is coupled between the differential input stage circuit 10 and the current mirror circuit 30, wherein The switch module 72 and the second switch module 74 are turned on or off according to the digital signals of D[7]~D[0].
承上所述，第一開關模組72包含一第一控制開關720、一第二控制開關722、一第三控制開關724與一第四控制開關726。第一控制開關720具有一第一端與一第二端，第一控制開關720之第一端耦接於第一差動輸入單元12之差動單元120，而第一控制開關720之第二端耦接於電源端VP，並第一控制開關720係依據D[7]~D[0]之數位訊號而導通或截止，第二控制開關722具有一第一端與一第二端，第二控制開關722之第一端耦接於差動單元120，而第二控制開關722之第二端耦接於電源端VP，並第二控制開關722依據D[7]~D[0]之數位訊號而導通或截止，第三控制開關724具有一第一端與一第二端，第三控制開關724之第一端耦接差動單元120，而第三控制開關之第二端耦接於第一電流鏡32，並第三控制開關724依據D[7]~D[0]之數位訊號而導通或截止，第四控制開關726具有一第一端與一第二端，第四控制開關726之第一端耦接差動單元120，而第四控制開關726之第二端耦接於第一電流鏡32，並第四控制開關726依據D[7]~D[0]之數位訊號而導通或截止。As described above, the first switch module 72 includes a first control switch 720, a second control switch 722, a third control switch 724, and a fourth control switch 726. The first control switch 720 has a first end and a second end. The first end of the first control switch 720 is coupled to the differential unit 120 of the first differential input unit 12, and the second control switch 720 is second. The end is coupled to the power terminal VP, and the first control switch 720 is turned on or off according to the digital signal of D[7]~D[0], and the second control switch 722 has a first end and a second end, The first end of the second control switch 722 is coupled to the differential unit 120, and the second end of the second control switch 722 is coupled to the power terminal VP, and the second control switch 722 is based on D[7]~D[0] The third control switch 724 has a first end and a second end. The first end of the third control switch 724 is coupled to the differential unit 120, and the second end of the third control switch is coupled. In the first current mirror 32, and the third control switch 724 is turned on or off according to the digital signal of D[7]~D[0], the fourth control switch 726 has a first end and a second end, and the fourth control The first end of the switch 726 is coupled to the differential unit 120, and the second end of the fourth control switch 726 is coupled to the first current mirror 32, and the fourth control switch 726 is based on D[7]~D. The digital signal of [0] is turned on or off.
同理，第二開關模組74包含一第五控制開關740、一第六控制開關742、一第七控制開關744與一第八控制開關746。第五控制開關740具有一第一端與一第二端，第五控制開關740之第一端耦接於第二差動輸入單元14之差動單元140，而第五控制開關740之第二端耦接於參考端VN，並第五控制開關740係依據D[7]~D[0]之數位訊號而導通或截止，第六控制開關742具有一第一端與一第二端，第六控制開關742之第一端耦接於差動單元140，而第六控制開關742之第二端耦接於參考端VN，並第六控制開關742依據D[7]~D[0]之數位訊號而導通或截止，第七控制開關744具有一第一端與一第二端，第七控制開關744之第一端耦接差動單元140，而第七控制開關之第二端耦接於第二電流鏡34，並第七控制開關744依據D[7]~D[0]之數位訊號而導通或截止，第八控制開關746具有一第一端與一第二端，第八控制開關746之第一端耦接差動單元140，而第八控制開關746之第二端耦接於第二電流鏡34，並第八控制開關746依據D[7]~D[0]之數位訊號而導通或截止。如此，本發明藉由控制開關電路70之第一控制開關模組72與第二控制關模組74依據D[7]~D[0]之數位訊號而控制差動輸入級電路10產生第一尾端電流I1或第二尾端電流I2，以減少一路徑的靜態電流消耗，進而達到省電的目的。Similarly, the second switch module 74 includes a fifth control switch 740, a sixth control switch 742, a seventh control switch 744 and an eighth control switch 746. The fifth control switch 740 has a first end and a second end. The first end of the fifth control switch 740 is coupled to the differential unit 140 of the second differential input unit 14, and the second control switch 740 is second. The terminal is coupled to the reference terminal VN, and the fifth control switch 740 is turned on or off according to the digital signal of D[7]~D[0], and the sixth control switch 742 has a first end and a second end, The first end of the sixth control switch 742 is coupled to the differential unit 140, and the second end of the sixth control switch 742 is coupled to the reference terminal VN, and the sixth control switch 742 is based on D[7]~D[0] The seventh control switch 744 has a first end and a second end. The first end of the seventh control switch 744 is coupled to the differential unit 140, and the second end of the seventh control switch is coupled. In the second current mirror 34, and the seventh control switch 744 is turned on or off according to the digital signal of D[7]~D[0], the eighth control switch 746 has a first end and a second end, and the eighth control The first end of the switch 746 is coupled to the differential unit 140, and the second end of the eighth control switch 746 is coupled to the second current mirror 34, and the eighth control switch 746 is based on D[7]~D. The digital signal of [0] is turned on or off. As such, the first control switch module 72 and the second control switch module 74 of the control switch circuit 70 control the differential input stage circuit 10 to generate the first according to the digital signals of D[7]~D[0]. The tail current I 1 or the second tail current I 2 is used to reduce the quiescent current consumption of a path, thereby achieving the purpose of power saving.
承上所述，由於本發明之摺疊式運算放大器1係依據D[7]~D[0]之數位訊號而決定使用第一尾端電流I1或第二尾端電流I2，產生輸出電流Io，所以，本發明之摺疊式運算放大器1每次僅會使用第一尾端電流I1或第二尾端電流I2，當本發明之摺疊式運算放大器1使用第一尾端電流I1產生輸出電流Io時，第二尾端電流I2就不需要，如此，本發明之控制開關電路70係會截止差動輸入級電路10停止產生第二尾端電流I2，以減少一路徑的靜態電流消耗，進而達到省電的目的。反之，當本發明之摺疊式運算放大器1使用第二尾端電流I2產生輸出電流Io時，第一尾端電流I1就不需要，如此，本發明之控制開關電路70係會截止差動輸入級電路10停止產生第一尾端電流I1，以達到省電的目的。As described above, the folding operational amplifier 1 of the present invention determines the use of the first tail current I 1 or the second tail current I 2 to generate an output current according to the digital signal of D[7]~D[0]. Io, therefore, the folding operational amplifier 1 of the present invention will only use the first tail current I 1 or the second tail current I 2 at a time , when the folding operational amplifier 1 of the present invention uses the first tail current I 1 When the output current Io is generated, the second tail current I 2 is not required. Thus, the control switch circuit 70 of the present invention cuts off the differential input stage circuit 10 to stop generating the second tail current I 2 to reduce a path. Static current consumption, in order to achieve power saving purposes. On the contrary, when the folding operational amplifier 1 of the present invention generates the output current Io using the second tail current I 2 , the first tail current I 1 is not required, and thus, the control switch circuit 70 of the present invention will cut off the differential. The input stage circuit 10 stops generating the first tail current I 1 for power saving purposes.
此外，本發明之控制開關電路70依據D[7]~D[0]之數位訊號，而控制差動輸入級電路10產生第一尾端電流I1或第二尾端電流I2的方式有數種，本發明於此提供三種不同控制方式進行說明。首先，本發明之控制開關電路70可以利用珈瑪訊號中的最高位元MSB來決定差動輸入級電路10產生第一尾端電流I1或第二尾端電流I2，例如當D[7]~D[0]之數位訊號對應的選擇訊號為8位元資料(即00000000~11111111)，則控制開關電路70在選擇訊號為0000000~01111111時，則控制差動輸入級電路10產生第一尾端電流I1，而停止產生第二尾端電流I2；當控制開關電路70在選擇訊號為1000000~11111111時，則控制差動輸入級電路10產生第二尾端電流I2，而停止產生第一尾端電流I1。In addition, the control switch circuit 70 of the present invention controls the differential input stage circuit 10 to generate the first tail current I 1 or the second tail current I 2 according to the digital signals of D[7]~D[0]. The invention provides three different control modes for illustration. First, the control switch circuit 70 of the present invention can use the highest bit MSB of the gamma signal to determine whether the differential input stage circuit 10 generates the first tail current I 1 or the second tail current I 2 , for example, when D[7 When the selection signal corresponding to the digital signal of the ~D[0] is 8-bit data (ie, 00000000~11111111), the control switch circuit 70 controls the differential input stage circuit 10 to generate the first when the selection signal is 0000000~01111111. The tail current I 1 stops generating the second tail current I 2 ; when the control switch circuit 70 selects the signal 1000000~11111111, the differential input stage circuit 10 is controlled to generate the second tail current I 2 , and stops. A first tail current I 1 is generated.
請一併參閱第二圖，係為本發明之一實施例之控制開關電路依據D[7]~D[0]之數位訊號而導通或截止的動作示意圖。如圖所示，控制差動輸入級電路10產生第一尾端電流I1或第二尾端電流I2的第二種方式，即是利用類比方式控制該控制開關電路70，即本發明之摺疊式運算放大器1更包含一解碼電路90與一比較器92。解碼電路90耦接珈碼電路之複數珈碼輸出線(gamma lines)，解碼電路90依據顯示資料(即D[7]~D[0]之數位訊號)而產生解碼電壓，不同的珈碼電壓對應不同解碼電壓。比較器92具有一第一輸入端、一第二輸入端與一輸出端。比較器92之第一輸入端耦接該些珈碼輸出線之其中之一條，比較器92之第二輸入端耦接解碼電路90之輸出端，比較器92之第一輸入端耦接該些珈碼輸出線之其中之一條所對應之珈碼電壓作為一門檻值，並比較器92比較門檻值與第二輸入端所接收的解碼電壓而決定差動輸入級電路10產生第一尾端電流I1或第二尾端電流I2。Please refer to the second figure, which is a schematic diagram of the action of controlling the switch circuit to be turned on or off according to the digital signal of D[7]~D[0] according to an embodiment of the present invention. As shown, the second method of controlling the differential input stage circuit 10 to generate the first tail current I 1 or the second tail current I 2 is to control the control switch circuit 70 by analogy, that is, the present invention The folded operational amplifier 1 further includes a decoding circuit 90 and a comparator 92. The decoding circuit 90 is coupled to the plurality of gamma lines of the weight circuit, and the decoding circuit 90 generates the decoding voltage according to the display data (ie, the digital signal of D[7]~D[0]), and the different weights are generated. Corresponding to different decoding voltages. The comparator 92 has a first input terminal, a second input terminal and an output terminal. The first input end of the comparator 92 is coupled to one of the output lines, and the second input end of the comparator 92 is coupled to the output end of the decoding circuit 90. The first input end of the comparator 92 is coupled to the first input end of the comparator 92. The weight corresponding to one of the weight output lines is used as a threshold, and the comparator 92 compares the threshold value with the decoded voltage received by the second input to determine the differential input stage circuit 10 to generate the first tail current. I 1 or second tail current I 2 .
例如珈碼電路之該些珈碼輸出線總共有88條，並該些珈碼輸出線分別對應88個不同電壓準位，即第88條的珈碼電壓大於第87條的珈碼電壓大於86條的珈碼電壓，以此類推，當比較器92之第一輸入端耦接第44條珈碼輸出線，則在比較器92之第二輸入端接收到解碼電壓為第10條珈碼輸出線的珈碼電壓時，比較器92之輸出端產生低準位訊號low，並傳送低準位訊號low至差動輸入級電路10的第一開關模組72與第二開關模組74，以控制差動輸入級電路10產生第一尾端電流I1。同理，當比較器92之第二輸入端接收到解碼電壓為第50條珈碼輸出線的珈碼電壓時，比較器92之輸出端產生高準位訊號high，並傳送高準位訊號high至差動輸入級電路10的第一開關模組72與第二開關模組74，以控制差動輸入級電路10產生第二尾端電流I2。For example, the weight output lines of the weight circuit have a total of 88, and the weight output lines respectively correspond to 88 different voltage levels, that is, the weight voltage of the 88th is greater than the weight of the 87th is greater than 86. The weight of the bar voltage, and so on, when the first input of the comparator 92 is coupled to the 44th weight output line, the second input of the comparator 92 receives the decoded voltage as the 10th weight output. When the voltage of the line is voltage, the output of the comparator 92 generates a low level signal low, and transmits the low level signal low to the first switch module 72 and the second switch module 74 of the differential input stage circuit 10 to The differential input stage circuit 10 is controlled to generate a first tail current I 1 . Similarly, when the second input of the comparator 92 receives the output voltage of the 50th weight output line, the output of the comparator 92 generates a high level signal high and transmits a high level signal high. The first switch module 72 and the second switch module 74 of the differential input stage circuit 10 are controlled to generate a second tail current I 2 by the differential input stage circuit 10.
接上所述，本實施例之解碼電路90包含一第一解碼單元900、一第二解碼單元902、一第三解碼單元904、一第四解碼單元906與一數位類比轉換單元908。第一解碼單元900耦接該些珈碼線，並依據該些顯示資料(即D[7]~D[4])而輸出複數第一解碼資料(即B15~B00)至第二解碼單元902、第三解碼單元904與第四解碼單元906，於本實施中，第一解碼單元900為一4對16的解碼器，第一解碼單元900為四位元的輸入資料(即D[7]~D[4])，而對應輸出16位元的輸出資料(即B15~B00)，第一位元的輸出資料(即B00)傳送至第四解碼單元906，第二位元至第十五位元的輸出資料(即B14~B01)傳送至第二解碼單元902，而第十六位元的輸出資料(即B15)傳送至第三解碼單元904。The decoding circuit 90 of the present embodiment includes a first decoding unit 900, a second decoding unit 902, a third decoding unit 904, a fourth decoding unit 906, and a digital analog conversion unit 908. The first decoding unit 900 is coupled to the weight lines, and outputs a plurality of first decoded data (ie, B15~B00) to the second decoding unit 902 according to the display materials (ie, D[7]~D[4]). The third decoding unit 904 and the fourth decoding unit 906. In this implementation, the first decoding unit 900 is a 4-pair 16 decoder, and the first decoding unit 900 is a four-bit input data (ie, D[7] ~D[4]), and corresponding to output 16-bit output data (ie, B15~B00), the output data of the first bit (ie, B00) is transmitted to the fourth decoding unit 906, and the second bit to the fifteenth The output data of the bit (i.e., B14~B01) is transferred to the second decoding unit 902, and the output data of the sixteenth bit (i.e., B15) is transferred to the third decoding unit 904.
第二解碼單元902接收第一解碼單元900之輸出資料(即B14~B01)與輸入資料(即D[3]~D[2])，而依據第一解碼單元900之輸出資料(即B14~B01)與輸入資料(即D[3]~D[2])而產生一第一電壓(VH)與一第二電壓(VL)，如第三圖所示，第二解碼單元902包含一2對4解碼器9020、一第一邏輯電路9022與一第一輸出開關電路9024。2對4解碼器9020依據顯示資料(即D[3]~D[2])而輸出一解碼資料至第一邏輯電路9022，第一邏輯電路9022依據二對四解碼器9020輸出的解碼資料與第一解碼單元900之輸出資料(即B14~B01)而決定第一輸出開關電路9024中的哪一個開關模組導通，以產生第一解碼電壓與第二解碼電壓。其中，第一輸出開關電路9024之每一個方塊內為兩組4對1多工器。The second decoding unit 902 receives the output data (ie, B14~B01) and the input data (ie, D[3]~D[2]) of the first decoding unit 900, and according to the output data of the first decoding unit 900 (ie, B14~) B01) generates a first voltage (VH) and a second voltage (VL) with the input data (ie, D[3]~D[2]). As shown in the third figure, the second decoding unit 902 includes a 2 The 4 decoder 9020, a first logic circuit 9022 and a first output switch circuit 9024. The 2 to 4 decoder 9020 outputs a decoded data to the first according to the display data (ie, D[3]~D[2]). The logic circuit 9022, the first logic circuit 9022 determines which one of the first output switch circuits 9024 is based on the decoded data output by the two-to-four decoder 9020 and the output data of the first decoding unit 900 (ie, B14~B01). Turning on to generate a first decoded voltage and a second decoded voltage. Wherein, each of the first output switch circuits 9024 is a set of two pairs of one-to-one multiplexers.
第三解碼單元904與第四解碼單元906分別接收第一解碼單元900輸出的第十六位元的輸出資料與第一位元的輸出資料，並依據顯示資料(即D[3]~D[0])而分別產生第三解碼電壓與第四解碼電壓，並傳送第三解碼電壓與第四解碼電壓至數位類比轉換單元908，即如第四圖所示，第三解碼單元904與第四解碼單元906皆為同一電路，所以本實施例以第三解碼單元904為例，第三解碼單元904包含一4對16解碼器9040、一第二邏輯電路9042與一第二輸出開關電路9044。4對16解碼器9040依據顯示資料(即D[3]~D[0])而輸出一解碼資料至第二邏輯電路9042，第二邏輯電路9042依據4對16解碼器9040輸出的解碼資料與第一解碼單元900之輸出資料(即B15)而決定第二輸出開關電路9044中的哪一個開關模組導通，以產生第三解碼電壓(從電壓V255~V240選出其中之一電壓)。同理，第四解碼單元906產生第四解碼電壓(從電壓V15~V0選出其中之一電壓)。其中，第二輸出開關電路9044為一組4對1多工器。The third decoding unit 904 and the fourth decoding unit 906 respectively receive the output data of the sixteenth bit output by the first decoding unit 900 and the output data of the first bit, and according to the display data (ie, D[3]~D[ 0]) respectively generating a third decoding voltage and a fourth decoding voltage, and transmitting a third decoding voltage and a fourth decoding voltage to the digital analog converting unit 908, as shown in the fourth figure, the third decoding unit 904 and the fourth The decoding unit 906 is the same circuit. Therefore, the third decoding unit 904 is used as an example. The third decoding unit 904 includes a 4-to-16 decoder 9040, a second logic circuit 9042 and a second output switch circuit 9044. The 4-to-16 decoder 9040 outputs a decoded data to the second logic circuit 9042 according to the display data (ie, D[3]~D[0]), and the second logic circuit 9042 outputs the decoded data according to the 4-pair 16 decoder 9040. The output data of the first decoding unit 900 (ie, B15) determines which one of the second output switch circuits 9044 is turned on to generate a third decoded voltage (one of the voltages is selected from the voltages V255 to V240). Similarly, the fourth decoding unit 906 generates a fourth decoding voltage (one of the voltages is selected from the voltages V15 to V0). The second output switch circuit 9044 is a set of 4-to-1 multiplexers.
數位類比轉換單元908接收第一解碼電壓、第二解碼電壓、第三解碼電壓與第四解碼電壓，並從中選擇二個解碼電壓為一高電壓VH與一低電壓VL，並依據顯示資料(即D[1]~D[0])而進行數位類比轉換。即如第五圖所示，數位類比轉換單元908包含一第三輸出開關電路9080與摺疊式放大電路1。第三輸出開關電路9080依據依據顯示資料(即D[1]~D[0])而選擇高電壓VH或低電壓VL作為摺疊式放大電路1的輸入訊號，以進行數位類比轉換，並將轉後的訊號傳送至比較器92，以進行比較。其中，第三輸出開關電路9080之每一個方塊內為三組接到VH或VL的開關。The digital analog conversion unit 908 receives the first decoding voltage, the second decoding voltage, the third decoding voltage, and the fourth decoding voltage, and selects two decoding voltages from a high voltage VH and a low voltage VL, and according to the display data (ie, D[1]~D[0]) performs digital analog conversion. That is, as shown in the fifth figure, the digital analog conversion unit 908 includes a third output switching circuit 9080 and a folding amplifier circuit 1. The third output switch circuit 9080 selects the high voltage VH or the low voltage VL as the input signal of the fold-type amplifier circuit 1 according to the display data (ie, D[1]~D[0]), for digital analog conversion, and will turn The subsequent signal is passed to comparator 92 for comparison. Therein, three blocks of the third output switch circuit 9080 are connected to the switches of VH or VL.
請一參閱第六圖，係為本發明之另一實施例之控制開關電路依據珈碼電路之珈碼訊號而導通或截止的動作示意圖。如圖所示，控制差動輸入級電路10產生第一尾端電流I1或第二尾端電流I2的第三種方式，即是利用數位方式控制該控制開關電路70，也就是本發明之摺疊式運算放大器1更包含一數位比較電路94。數位比較電路94具有一第一輸入端與一第二輸入端，數位比較電路94之第一輸入端接收D[7]~D[0]之數位訊號對應的選擇訊號A，並將選擇訊號A作為門檻值，而數位比較電路94之第二輸入端接收顯示資料B，顯示資料B對應D[7]~D[0]之數位訊號，所以，本實施例利用數位比較電路94之第一輸入端的門檻值比較顯示資料B大於或小於此選擇訊號A，以控制差動輸入級電路10產生第一尾端電流I1或第二尾端電流I2。Please refer to the sixth figure, which is a schematic diagram of the action of controlling the switch circuit to be turned on or off according to the weight signal of the weight circuit according to another embodiment of the present invention. As shown, the third method of controlling the differential input stage circuit 10 to generate the first tail current I 1 or the second tail current I 2 is to control the control switch circuit 70 in a digital manner, that is, the present invention. The folded operational amplifier 1 further includes a digital comparison circuit 94. The digital comparison circuit 94 has a first input end and a second input end, and the first input end of the digital comparison circuit 94 receives the selection signal A corresponding to the digital signal of D[7]~D[0], and selects the signal A. As the threshold value, the second input end of the digital comparison circuit 94 receives the display data B, and the display data B corresponds to the digital signal of D[7]~D[0]. Therefore, the first input of the digital comparison circuit 94 is used in this embodiment. The threshold value comparison of the terminal indicates that the data B is greater or smaller than the selection signal A to control the differential input stage circuit 10 to generate the first tail current I 1 or the second tail current I 2 .
例如當D[7]~D[0]之數位訊號對應的選擇訊號為8位元資料(即00000000~11111111)，數位比較電路94之第一輸入端接收的選擇訊號A為00101000，當數位比較電路94之第二輸入端接收的顯示資料B為00100111時，數位比較電路94之一輸出端輸出一高準位訊號high，並傳送高準位訊號high至差動輸入級電路10的第一開關模組72與第二開關模組74，以控制差動輸入級電路10產生第二尾端電流I2，同理，當數位比較電路94之第二輸入端接收的顯示資料B為00101001時，數位比較電路94之一輸出端輸出一低準位訊號Low，並傳送低準位訊號low至差動輸入級電路10的第一開關模組72與第二開關模組74，以控制差動輸入級電路10產生第一尾端電流I1，如此，本發明藉由控制開關電路70依據珈瑪電路之珈瑪訊號而控制差動輸入級電路10產生第一尾端電流I1或第二尾端電流I2，以減少一路徑的靜態電流消耗，進而達到省電的目的。For example, when the selection signal corresponding to the digital signal of D[7]~D[0] is 8-bit data (ie, 00000000~11111111), the selection signal A received by the first input terminal of the digital comparison circuit 94 is 00101000, when the digital comparison is performed. When the display data B received by the second input terminal of the circuit 94 is 00100111, one of the digital comparison circuits 94 outputs a high level signal high, and transmits the high level signal high to the first switch of the differential input stage circuit 10. The module 72 and the second switch module 74 are configured to control the differential input stage circuit 10 to generate the second tail current I 2 . Similarly, when the display data B received by the second input end of the digital comparison circuit 94 is 00101001, The output of one of the digital comparison circuits 94 outputs a low level signal Low, and transmits the low level signal low to the first switch module 72 and the second switch module 74 of the differential input stage circuit 10 to control the differential input. The stage circuit 10 generates a first tail current I 1 . Thus, the present invention controls the differential input stage circuit 10 to generate a first tail current I 1 or a second tail by controlling the switching circuit 70 according to the sinus signal of the gamma circuit. Terminal current I 2 to reduce the quiescent current of a path Consumption, and thus achieve the purpose of power saving.
請參閱第七圖，其為本發明之另一實施例之摺疊式放大電路的電路圖。如圖所示，本實施例與第一圖之實施例不同之處，在於本實施例之差動輸入級電路10包含第一差動輸入模組22與一第二差動輸入模組24。第一差動輸入模組22包含一第一尾端差動單元220、一第二尾端差動單元222、一第三尾端差動單元224與一第四尾端差動單元226。第一尾端差動單元220、第二尾端差動單元222、第三尾端差動單元224與第四尾端差動單元226耦接第一開關模組72，並依據第一開關模組72導通而分別產生電流，再加總第一尾端差動單元220、第二尾端差動單元222、第三尾端差動單元224與第四尾端差動單元226產生的電流，以產生第一尾端電流I1。Please refer to the seventh figure, which is a circuit diagram of a folding amplifier circuit according to another embodiment of the present invention. As shown in the figure, the difference between the embodiment and the embodiment of the first embodiment is that the differential input stage circuit 10 of the embodiment includes a first differential input module 22 and a second differential input module 24. The first differential input module 22 includes a first tail differential unit 220, a second tail differential unit 222, a third tail differential unit 224 and a fourth tail differential unit 226. The first tail differential unit 220, the second tail differential unit 222, the third tail differential unit 224 and the fourth tail differential unit 226 are coupled to the first switch module 72, and according to the first switch mode The group 72 is turned on to generate currents respectively, and the currents generated by the first tail differential unit 220, the second tail differential unit 222, the third tail differential unit 224, and the fourth tail differential unit 226 are added. To generate a first tail current I 1 .
同理，第二差動輸入模組24包含一第五尾端差動單元240、一第六尾端差動單元242、一第七尾端差動單元244與一第八尾端差動單元246。第五尾端差動單元240、第六尾端差動單元242、第七尾端差動單元244與第八尾端差動單元246耦接第二開關模組74，並依據第二開關模組74導通而分別產生電流，再加總第五尾端差動單元240、第六尾端差動單元242、第七尾端差動單元244與第八尾端差動單元246產生的電流，以產生第二尾端電流I2。其餘電路部分與第一圖之實施例相同，於此就不再加以贅述。Similarly, the second differential input module 24 includes a fifth tail differential unit 240, a sixth tail differential unit 242, a seventh tail differential unit 244, and an eighth tail differential unit. 246. The fifth end differential unit 240, the sixth end differential unit 242, the seventh end differential unit 244 and the eighth end differential unit 246 are coupled to the second switch module 74, and according to the second switch mode The group 74 is turned on to generate current respectively, and the current generated by the fifth tail differential unit 240, the sixth tail differential unit 242, the seventh tail differential unit 244, and the eighth tail differential unit 246 is added. To generate a second tail current I 2 . The rest of the circuit parts are the same as the embodiment of the first figure, and will not be further described herein.
綜上所述，本發明之摺疊式運算放大電路由一差動輸入級電路依據至少一輸入訊號，產生一第一尾端電流與一第二尾端電流；一電流鏡電路耦接差動輸入級電路，並依據第一尾端電流與第二尾端電流，產生一第一鏡電流與一第二鏡電流；一輸出級電路耦接電流鏡電路，並依據第一鏡電流與第二鏡電流產生一輸出電流；一控制開關電路耦接差動輸入級電路與電流鏡電路之間，並依據一珈瑪電路之一珈瑪訊號而控制差動輸入級電路產生第一尾端電流或第二尾端電流。如此，本發明藉由控制開關電路依據珈瑪電路之珈瑪訊號而控制差動輸入級電路產生第一尾端電流或第二尾端電流，以減少一路徑的靜態電流消耗，進而達到省電的目的。In summary, the folding operational amplifier circuit of the present invention generates a first tail current and a second tail current according to at least one input signal by a differential input stage circuit; a current mirror circuit coupled with the differential input a first circuit current and a second mirror current according to the first tail current and the second tail current; an output stage circuit coupled to the current mirror circuit and based on the first mirror current and the second mirror The current generates an output current; a control switch circuit is coupled between the differential input stage circuit and the current mirror circuit, and controls the differential input stage circuit to generate the first tail current or the first according to a gamma signal of a gamma circuit Two tail currents. In this way, the present invention controls the differential input stage circuit to generate the first tail current or the second tail current according to the gamma signal of the gamma circuit to reduce the quiescent current consumption of a path, thereby achieving power saving. the goal of.
本發明係實為一具有新穎性、進步性及可供產業利用者，應符合我國專利法所規定之專利申請要件無疑，爰依法提出發明專利申請，祈 鈞局早日賜准專利，至感為禱。The invention is a novelty, progressive and available for industrial use, and should meet the requirements of the patent application stipulated in the Patent Law of China, and the invention patent application is filed according to law, and the prayer bureau will grant the patent as soon as possible. prayer.
惟以上所述者，僅為本發明之一較佳實施例而已，並非用來限定本發明實施之範圍，舉凡依本發明申請專利範圍所述之形狀、構造、特徵及精神所為之均等變化與修飾，均應包括於本發明之申請專利範圍內。
However, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and the shapes, structures, features, and spirits described in the claims are equivalently changed. Modifications are intended to be included in the scope of the patent application of the present invention.
1．．．摺疊式運算放大電路1. . . Folding operational amplifier circuit
10．．．差動輸入級電路10. . . Differential input stage circuit
12．．．第一差動輸入單元12. . . First differential input unit
120．．．差動單元120. . . Differential unit
122．．．尾端電流源122. . . Tail current source
14．．．第二差動輸入單元14. . . Second differential input unit
140．．．差動單元140. . . Differential unit
142．．．尾端電流源142. . . Tail current source
30．．．電流鏡電路30. . . Current mirror circuit
32．．．第一電流鏡32. . . First current mirror
34．．．第二電流鏡34. . . Second current mirror
35．．．第一電流控制器35. . . First current controller
36．．．第二電流控制器36. . . Second current controller
37．．．第三電流控制器37. . . Third current controller
38．．．第四電流控制器38. . . Fourth current controller
50．．．輸出級電路50. . . Output stage circuit
52．．．第一電晶體52. . . First transistor
54．．．第二電晶體54. . . Second transistor
70．．．控制開關電路70. . . Control switch circuit
72．．．第一開關模組72. . . First switch module
720．．．第一控制開關720. . . First control switch
722．．．第二控制開關722. . . Second control switch
724．．．第三控制開關724. . . Third control switch
726．．．第四控制開關726. . . Fourth control switch
74．．．第二開關模組74. . . Second switch module
740．．．第五控制開關740. . . Fifth control switch
742．．．第六控制開關742. . . Sixth control switch
744．．．第七控制開關744. . . Seventh control switch
746．．．第八控制開關746. . . Eighth control switch
82．．．第一電容82. . . First capacitor
84．．．第二電容84. . . Second capacitor
Claims (11)
一差動輸入級電路，依據至少一輸入訊號，控制一第一尾端電流與一第二尾端電流流入；
一電流鏡電路，耦接該差動輸入級電路，並依據該第一尾端電流與該第二尾端電流，產生一第一鏡電流與一第二鏡電流；
一輸出級電路，耦接該電流鏡電路，並依據該第一鏡電流與該第二鏡電流，產生一輸出電流；以及
一控制開關電路，耦接該差動輸入級電路與該電流鏡電路之間，並依據一數位訊號而控制該差動輸入級電路產生該第一尾端電流或該第二尾端電流；其中，該數位訊號對應一珈瑪電路之一珈瑪訊號。A folding operational amplifier comprising:
a differential input stage circuit controls a first tail current and a second tail current to flow according to at least one input signal;
a current mirror circuit coupled to the differential input stage circuit, and generating a first mirror current and a second mirror current according to the first tail current and the second tail current;
An output stage circuit coupled to the current mirror circuit and generating an output current according to the first mirror current and the second mirror current; and a control switch circuit coupled to the differential input stage circuit and the current mirror circuit And controlling the differential input stage circuit to generate the first tail current or the second tail current according to a digital signal; wherein the digital signal corresponds to one of the gamma circuits.
一第一差動輸入單元，接收該輸入訊號，並依據該輸入訊號控制該第一尾端電流流入該第一差動輸入單元之一電流大小；以及
一第二差動輸入單元，接收該輸入訊號，並依據該輸入訊號控制該第二尾端電流流入該第二差動輸入單元之一電流大小。The folding operational amplifier circuit of claim 1, wherein the differential input stage circuit comprises:
a first differential input unit receives the input signal, and controls a current of the first tail current flowing into the first differential input unit according to the input signal; and a second differential input unit receives the input a signal, and controlling, according to the input signal, a current flowing into the second differential input unit of the second tail current.
一差動單元，接收該輸入訊號，並依據該輸入訊號而控制該電流大小；以及
一尾端電流源，耦接該差動單元，並依據該差動單元導通或截止而提供該第一尾端電流。The folding operational amplifier circuit of claim 4, wherein the first differential input unit comprises:
a differential unit receives the input signal and controls the current according to the input signal; and a tail current source coupled to the differential unit and provides the first tail according to the differential unit being turned on or off Terminal current.
一差動單元，接收該輸入訊號，並依據該輸入訊號而控制該電流大小；以及
一尾端電流源，耦接該差動單元，並依據該差動單元導通或截止而提供該第二尾端電流。The folding operational amplifier circuit of claim 4, wherein the second differential input unit comprises:
a differential unit receives the input signal and controls the current according to the input signal; and a tail current source coupled to the differential unit and provides the second tail according to whether the differential unit is turned on or off Terminal current.
一第一電流鏡，耦接該第一差動輸入單元，並依據該第一尾端電流而產生該第一鏡電流與該第二鏡電流；以及
一第二電流鏡，耦接該第二差動輸入單元，並依據該第二尾端電流而產生該第一鏡電流與該第二鏡電流。The folding operational amplifier circuit of claim 4, wherein the current mirror circuit comprises:
a first current mirror coupled to the first differential input unit, and generating the first mirror current and the second mirror current according to the first tail current; and a second current mirror coupled to the second And inputting the first mirror current and the second mirror current according to the second tail current.
一第一開關模組，耦接於該差動輸入級電路與該電流鏡電路之間；以及
一第二開關模組，耦接於該差動輸入級電路與該電流鏡電路之間；
其中，該第一開關模組與該第二開關模組依據該珈瑪電路之該珈瑪訊號而導通或截止。The folding operational amplifier circuit of claim 1, wherein the control switch circuit comprises:
a first switch module coupled between the differential input stage circuit and the current mirror circuit; and a second switch module coupled between the differential input stage circuit and the current mirror circuit;
The first switch module and the second switch module are turned on or off according to the gamma signal of the gamma circuit.
一第一電晶體，耦接該電流鏡電路；
一第二電晶體，耦接該電流鏡電路與該第一電晶體，該第一電晶體與該第二電晶體依據該第二鏡電流，產生該輸出電流。
The folding operational amplifier circuit of claim 1, wherein the output stage circuit comprises:
a first transistor coupled to the current mirror circuit;
a second transistor coupled to the current mirror circuit and the first transistor, the first transistor and the second transistor generating the output current according to the second mirror current.
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