TWI492542B - Input interface circuit - Google Patents

Description

Input interface circuit

The present disclosure relates to a signal input interface, and more particularly to an input interface circuit.

The display is an integral part of the electronic device. By means of the display, the electronic device can display the data thereon for viewing by the user. A source driver is often provided in the display to provide a data signal to the corresponding pixel unit for display. In the source driver, an input interface circuit is required to receive the data signal, and after receiving, the serial signal is converted into a parallel signal or other subsequent processing steps. Therefore, whether the input interface circuit can operate efficiently will affect the quality of the data signal.

However, in general, the input interface circuit is often limited by the signal swing or the size of the circuit voltage source, so that the range in which it can work becomes smaller. In the case of high frequencies, small changes make it easier to limit the working range and not make the most efficient use.

Therefore, how to design a new input interface circuit to overcome the above problems is an urgent problem to be solved in the industry.

Accordingly, one aspect of the present disclosure is to provide an input interface circuit comprising: a first differential input pair, a first active load, a second differential input pair, and two second active loads. The first differential input pair contains two P-type gold The oxygen semiconductors each include: a first gate, a first source, and a first drain. The first gate receives one of a pair of differential inputs. The first source is used to connect the first current source. The first drain is connected to one of a pair of differential outputs. The first active load 俾 is connected between the pair of differential outputs and the first voltage source. The second differential input pair includes two N-type MOS transistors, each of which includes: a second gate, a second source, and a second drain. The second gate receives one of the pair of differential inputs. The second source is coupled to the second current source. The second active load is respectively connected between one of the pair of differential output terminals and the second drain of the one of the two N-type MOS transistors and the second voltage source.

According to an embodiment of the present disclosure, the input interface circuit further includes a third active load and a switching element, wherein the third active load is connected between the first current source and the second current source, and the voltage of the switching element is at the differential input end. When the value causes the first differential input pair to stop operating, the third active load is activated to cause the current of the first current source to be directed to the second differential input pair.

According to another embodiment of the present disclosure, the input interface circuit further includes a fourth active load and a switching element, wherein the fourth active load is connected between the first current source and the second current source, and the switching element is at the pair of differential inputs When the voltage value causes the second differential input pair to stop operating, the fourth active load is activated to cause the current of the second current source to be introduced into the first differential input pair.

According to still another embodiment of the present disclosure, the input interface circuit further includes a gain enhancement stage coupled to the pair of differential outputs.

According to still another embodiment of the present disclosure, the first drains of the two P-type MOS transistors are each connected to the third current source, and the current value of the third current source is smaller than the first current source.

According to the disclosure, there is an embodiment in which two N-type gold oxides The second drain of the semi-transistor is each further connected to the fourth current source, and the current value of the fourth current source is smaller than the second current source.

The advantage of the application of the present disclosure is that the design of the second differential input pair and the second active load allows the input interface circuit to continue to operate when the voltage of the supply voltage or the differential input changes. Easily achieve the above objectives.

Please refer to Figure 1. FIG. 1 is a circuit diagram of an input interface circuit 1 in an embodiment of the disclosure. The input interface circuit 1 includes: a first differential input pair including two P-type MOS transistors P1 and P2, a first active load including two N-type MOS transistors N1 and N2, and a second N-type gold oxide The second differential input pair of the semi-transistors N3 and N4 and the second second active load 10.

The two P-type MOS transistors P1 and P2 of the first differential input pair each include a first gate, a first source, and a first drain. The first gates of the P-type MOS transistors P1 and P2 receive voltages of one of the pair of differential inputs IN+ and IN-, respectively. The first source of the P-type MOS transistors P1 and P2 is used to connect the first current source 12. The first drain of the P-type MOS transistors P1 and P2 is connected to one of a pair of differential output terminals VP and VN. A first active load including two N-type MOS transistors N1 and N2 is coupled between the pair of differential output terminals VP and VN and between the first voltage source GND. In this embodiment, the first voltage source GND is a ground potential.

The second differential input pair includes two N-type MOS transistors N3 and N4 each including a second gate, a second source, and a second drain. N-type gold oxide semi-electric The second gates of crystals N3 and N4 also receive the voltage of one of the pair of differential input terminals IN+ and IN-. The second source of the N-type MOS transistors N3 and N4 is connected to the second current source 14. One of the second active loads 10 is connected between the differential output terminal VP and the second drain of the N-type MOS transistor N3 and the second voltage source VDD. The other second active load 10 is connected between the differential output terminal VN and the second drain of the N-type MOS transistor N4, and the second voltage source VDD.

Therefore, when the differential input terminals IN+ and IN- receive the differential input voltage, if the voltage level thereof is low, only the two P-type MOS transistors P1 of the first differential input pair and P2 is turned on and the first current source 12 is drawn to generate a differential output voltage at the differential output terminals VP and VN. When the differential input voltages received by the differential input terminals IN+ and IN- are slightly increased, the two P-type MOS transistors P1 and P2 and the second differential input of the first differential input pair are aligned. The two N-type MOS transistors N3 and N4 operate simultaneously to generate a differential output voltage. When the differential input voltages received by the differential input terminals IN+ and IN- are increased to turn off the two P-type MOS transistors P1 and P2 in the first differential input pair, and the second differential input pair The two N-type MOS transistors N3 and N4 will continue to operate to produce a differential output voltage. Therefore, the operating range of the input interface circuit 1 will be greatly improved.

On the other hand, if the second voltage source VDD changes due to environmental changes or other factors, it is also possible to shorten or increase the voltage difference between the differential input voltage and the P-type MOS transistor or the N-type MOS half. The transistor is turned on or off. However, since the operating range of the input interface circuit 1 is greatly improved, the input interface circuit 1 cannot be operated due to the change of the second voltage source VDD.

In this embodiment, after the differential output voltages are generated, the differential output terminals VP and VN are further transmitted to the gain enhancement stage 16 for signal enhancement of the differential output voltage.

Please refer to Figure 2. 2 is a diagram showing the relationship between the equivalent transconductance (gm) of the first and second differential input pairs of the input interface circuit 1 and the differential output voltage Vcm in an embodiment of the disclosure. In the above circuit structure, when the differential output voltage Vcm is too low or too high, only the first differential input pair or the second differential input operates on one of them, wherein only the first differential input The transduction for operation is gmp, and only the transduction of the second differential input pair is gmn. However, when the differential output voltage Vcm is in the middle range, the first differential input pair and the second differential input pair will start to operate, and the equivalent transduction is gmn+gmp, which causes the differential output voltage Vcm. The equivalent transduction is not the same when it is too low or too high. Such an effect will easily cause delays in signal timing or duty cycles, which may affect the lack of signal transmission results. Especially when the circuit is operated at high frequencies, this loss will have a more serious impact.

So please refer to Figure 3. FIG. 3 is a circuit diagram of an input interface circuit 3 in another embodiment of the disclosure. The components of the input interface circuit 3 in this embodiment are substantially the same as the input interface circuit 1 of FIG. 1. However, in the embodiment, the input interface circuit 1 further includes a third active load 30, a fourth active load 32, and a switching element. 34 and 36.

The third active load 30 and the fourth active load 32 are both connected between the first current source 12 and the second current source 14. In the present embodiment, the third active load 30 is formed of an N-type MOS device, and the fourth active load 32 is formed of a P-type MOS device. Switching elements 34 and 36 respectively The three active loads 30 and the fourth active load 32 are connected. When the voltage of the differential input terminals IN+ and IN- causes the first differential input pair to stop, the third active load 30 is activated to introduce the current of the first current source 12 into the second differential input. Correct. Since the transduction is proportional to the result of the current opening number, when the first differential input pair stops operating, the current of the second differential input pair will be quadrupled due to the current introduced into the first current source 12, which can be maintained. The transduction is stable.

Similarly, when the voltage value of the differential input terminals IN+ and IN- causes the second differential input pair to stop operating, the fourth active load 32 is activated to cause the current of the second current source 14 to be introduced into the first difference. Dynamic input pair to achieve stable transduction. Please also refer to Figure 4. Figure 4 is a diagram showing the relationship between the equivalent transconductance of the first and second differential input pairs of the input interface circuit 1' and the differential output voltage Vcm in an embodiment of the present disclosure. It can be seen from FIG. 4 that after the setting of the third active load 30 and the fourth active load 32, the equivalent transduction will exhibit a relatively stable state under the variation of the differential output voltage Vcm, without Affect the quality of the signal.

Please refer to Figure 5. FIG. 5 is a circuit diagram of an input interface circuit 5 in still another embodiment of the disclosure. In the present embodiment, the input interface circuit 5 further includes third current sources 50, 52 and fourth current sources 54, 56. The third current sources 50 and 52 are respectively connected to the first drains of the two P-type MOS transistors P1 and P2, and the fourth current sources 54 and 56 are respectively connected to the two N-type MOS transistors N1 and N2. The second drain is connected. The current values of the third current source 50, 52 and the fourth current source 54, 56 are smaller than the current values of the first current source and the second current source.

Since the differential input IN+ and IN- can swing very large, making the first One of the second differential input pair or the second differential input pair enters a cut-off region due to no current, and returns to the saturation region until a signal is input (saturation region) ). However, when the MOS transistor returns from the cut-off region to the saturation region, it will cause a delay, and the circuit cannot be operated in a high-frequency environment. Therefore, by the arrangement of the third current source 50, 52 and the fourth current source 54, 56, the P-type MOS transistors P1 and P2 and the N-type MOS transistors N1 and N2 can always pass current. And always maintain the state of the saturation zone.

Therefore, the input interface circuit of the present disclosure is designed to continue to operate when the voltage of the supply voltage or the differential input changes due to the design of the second differential input pair and the second active load.

The present disclosure has been disclosed in the above embodiments, but it is not intended to limit the disclosure, and any person skilled in the art can make various changes and refinements without departing from the spirit and scope of the disclosure. The scope of protection of the disclosure is subject to the definition of the scope of the patent application.

1, 3, 5‧‧‧ input interface circuit

10‧‧‧Second active load

12‧‧‧First current source

14‧‧‧second current source

16‧‧‧ Gain enhancement level

30‧‧‧ Third active load

32‧‧‧fourth active load

34, 36‧‧‧Switching elements

50, 52‧‧‧ third current source

54, 56‧‧‧ fourth current source

The above and other objects, features, advantages and embodiments of the present disclosure will be more apparent and understood. The description of the drawings is as follows: FIG. 1 is a circuit diagram of an input interface circuit according to an embodiment of the disclosure; 2 is a diagram showing the relationship between the equivalent transconductance and the differential output voltage of the first and second differential input pairs of the input interface circuit in an embodiment of the disclosure; 3 is a circuit diagram of an input interface circuit in another embodiment of the disclosure; FIG. 4 is an equivalent diagram of first and second differential input pairs of an input interface circuit according to an embodiment of the disclosure A diagram of the relationship between the transconductance and the differential output voltage; and FIG. 5 is a circuit diagram of an input interface circuit in still another embodiment of the present disclosure.

1‧‧‧Input interface circuit

10‧‧‧Second active load

12‧‧‧First current source

14‧‧‧second current source

16‧‧‧ Gain enhancement level

Claims (6)

An input interface circuit comprising: a first differential input pair comprising two P-type MOS transistors, each comprising: a first gate for connecting one of a pair of differential input terminals; a source for connecting to a first current source; and a first drain for directly connecting to one of a pair of differential outputs; a first active load coupled to the pair of differential outputs And a second differential input pair comprising: two N-type MOS transistors, each comprising: a second gate for receiving one of the pair of differential input terminals; a second source for connecting a second current source; a second drain; and two second active loads respectively connected to one of the pair of differential outputs and the two N-type MOS transistors One of the second drains and a second voltage source. The input interface circuit of claim 1, further comprising a third active load and a switching element, wherein the third active load is connected between the first current source and the second current source, the switching element is in the pair Differential transmission When the voltage value of the input terminal stops the operation of the first differential input pair, the third active load is activated to introduce the current of the first current source into the second differential input pair. The input interface circuit of claim 1, further comprising a fourth active load and a switching element, wherein the fourth active load is connected between the first current source and the second current source, the switching element is in the pair When the voltage value of the differential input terminal stops the operation of the second differential input pair, the fourth active load is activated to introduce the current of the second current source into the first differential input pair. The input interface circuit of claim 1, further comprising a gain enhancement stage coupled to the pair of differential outputs. The input interface circuit of claim 1, wherein the first drain of the two P-type MOS transistors is further connected to a third current source, and the current value of the third current source is less than the first Battery. The input interface circuit of claim 1, wherein the second drain of the two N-type MOS transistors is further connected to a fourth current source, and the current value of the fourth current source is less than the second Battery.