TWI667788B - Semiconductor structures and fabrication method thereof - Google Patents

Abstract

The present disclosure provides a semiconductor structure including: a substrate having a surface; a first doped region formed in the substrate; a second doped region formed in the substrate; and a third doped region formed In the substrate, the third doped region is located between the first doped region and the second doped region, and electrically isolates the first doped region from the second doped region; a doped region is formed in the substrate and surrounded by the second doped region; a gate doped region is formed in the substrate and surrounded by the fourth doped region; a source doped region, Formed in the substrate, located in the second doping region; a drain doped region formed in the substrate, located in the second doped region; and a plurality of isolation structures formed in the substrate The gate doped region and the source doped region are located between the gate doped region and the drain doped region.

Description

Semiconductor structure and method of manufacturing same

The present disclosure relates to a semiconductor structure, and more particularly to a junction field effect transistor (JFET) having a low pinch-off voltage and a method of fabricating the same.

In the classification of field effect transistors, there are two basic types, namely, a gold oxide half field effect transistor (MOSFET) and a junction field effect transistor (JFET). The main difference between the two field effect transistors is that the gold oxide half field effect transistor is provided with a layer of insulating material commonly referred to as gate oxide between the gate and the other electrodes. The channel current of the MOSFET is controlled by the electric field applied to the channel to increase or decrease the channel area according to operational needs. The gate of the junction field effect transistor forms a PN junction with other electrodes, and the gate current is changed to change the range of the depletion region, thereby controlling the channel current.

However, conventional junction field effect transistors (JFETs) require additional mask steps to define the channels, which have significantly increased the cost of fabrication and the complexity of the process, and need to be improved.

Therefore, it has been desired to develop a junction field effect transistor having a low clamping voltage and a simple process.

In accordance with an embodiment of the present disclosure, a semiconductor structure is provided. The semiconductor structure includes: a substrate having a surface; a first doped region formed in the substrate; a second doped region formed in the substrate; and a third doped region formed In the substrate, the third doped region is located between the first doped region and the second doped region, and electrically isolates the first doped region from the second doped region; a doped region is formed in the substrate and surrounded by the second doped region; a gate doped region is formed in the substrate and surrounded by the fourth doped region; a source doped region, Formed in the substrate, located in the second doping region; a drain doped region formed in the substrate, located in the second doped region; and a plurality of isolation structures formed in the substrate The gate doped region and the source doped region are located between the gate doped region and the drain doped region.

According to some embodiments, the substrate is a P-type germanium substrate or an N-type germanium substrate.

According to some embodiments, when the substrate is a P-type germanium substrate, the first doped region, the second doped region, the source doped region, and the drain doped region are N-type doped regions. And the third doped region, the fourth doped region, and the fifth doped region are P-type doped regions.

According to some embodiments, when the substrate is an N-type germanium substrate, the first doped region, the second doped region, the source doped region, and the drain doped region are P-type doped regions. And the third doped region, the fourth doped region, and the fifth doped region are N-type doped regions.

According to some embodiments, the thickness of the third doped region ranges from about 200 to 300 nm.

According to some embodiments, the width of the third doped region is greater than or equal to The width of the second doped region.

According to some embodiments, the third doped region has a bottom portion and a top portion, the bottom portion contacting the first doping region, the top portion contacting the second doping region, and the top portion of the third doping region is The surface of the substrate has a distance of between about 5 and 7 microns.

According to some embodiments, the second doped region between the third doped region and the fourth doped region defines a channel.

According to some embodiments, the isolation structures are shallow trench spacers.

According to an embodiment of the present disclosure, a method of fabricating a semiconductor structure is provided. The manufacturing method includes: providing a substrate; performing a first implantation process to form a first doped region in the substrate; forming a plurality of isolation structures in the substrate; and performing a second implantation process to Forming a second doped region in the substrate; performing a third implant process to form a third doped region in the substrate, wherein the third doped region is located in the first doped region and the second Between the doped regions, electrically isolating the first doped region and the second doped region; performing a fourth implant process to form a fourth doped region in the second doped region; a fifth implantation process for forming a gate doping region in the fourth doping region; and performing a sixth implantation process to form a source doping region in the second doping region A drain doped region is disposed between the gate doped region and the source doped region and between the gate doped region and the drain doped region.

According to some embodiments, when the substrate is a P-type germanium substrate, the first implanting process, the second implanting process, and the sixth implanting process are implanted with N-type dopants, and the third Clothing process, the fourth planting process, and the The fifth planting process is carried out by P-type doping.

According to some embodiments, when the substrate is an N-type germanium substrate, the first implanting process, the second implanting process, and the sixth implanting process are implanted with a P-type dopant, and the third The planting process, the fourth planting process, and the fifth planting process are implanted with an N-type dopant.

According to some embodiments, the implanting dose of the third implanting process is between 1 x 10 ¹³ and 8 x 10 ¹³ .

According to some embodiments, the implanting energy of the third implant process is between 20 and 60 KeV.

The invention utilizes a general CMOS or Bipolar-CMOS-DMOS (BCD) process to fabricate a junction field effect transistor (JFET), and implants a P-type or N-type dopant in the implantation process (depending on the product needs to be adjusted). The specific depth position of the substrate forms a doped region having a specific size (for example, a specific thickness and width) as an electrical isolation structure of the upper and lower doped regions, and defines a channel of a junction field effect transistor (JFET). When the component is actuated, by adjusting the magnitude of the gate voltage, the size of the depletion region on the channel can be further affected. When the applied negative bias voltage is larger, the range of the depletion region is enlarged, and finally the channel is depleted. The region is pinched off and the current is stopped. The magnitude of the gate voltage applied at this time is the pinch-off voltage of the junction field effect transistor (JFET). Therefore, in the present invention, the magnitude of the pinch-off voltage can be changed by simply adjusting the size of the doping region as the electrical isolation structure in the substrate. The process of the invention is simple and does not require an additional mask step to define the channel, and the fabricated junction field effect transistor (JFET) has a low clamping voltage and a high breakdown voltage, which is quite beneficial for various switching applications and ESD protection.

The above described objects, features and advantages of the present invention will become more apparent and understood.

10‧‧‧Semiconductor structure

12‧‧‧Substrate

14‧‧‧First doped area

16‧‧‧Second doped area

18‧‧‧ Third doped area

20‧‧‧fourth doping zone

22‧‧‧ gate doping area

24‧‧‧ source doped area

26‧‧‧汲Doped area

28‧‧‧Isolation structure

30‧‧‧ bottom of the third doped area

32‧‧‧Top of the third doped area

34‧‧‧ Surface of the substrate

36‧‧‧ channel

38‧‧‧First planting process

40‧‧‧Second planting process

42‧‧‧ Third planting process

44‧‧‧ Fourth planting process

46‧‧‧The fifth planting process

48‧‧‧The sixth planting process

D‧‧‧Distance of the top of the third doped region from the surface of the substrate

Thickness of T‧‧‧ third doped zone

W1‧‧‧Width of the third doped region

W2‧‧‧ width of the second doped region

1 is a schematic cross-sectional view of a semiconductor structure in accordance with an embodiment of the present disclosure; and FIG. 2A-2E is a cross-sectional view showing a method of fabricating a semiconductor structure in accordance with an embodiment of the present disclosure.

3 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure; 4A-4E is a cross-sectional view showing a method of fabricating a semiconductor structure according to an embodiment of the present disclosure; and FIG. 5 is a cross-sectional view according to the present disclosure. An embodiment of an electrical test chart of a semiconductor structure; and FIG. 6 is an electrical test chart of a semiconductor structure in accordance with an embodiment of the present disclosure.

Referring to FIG. 1, a semiconductor structure 10 is provided in accordance with an embodiment of the present disclosure. FIG. 1 is a schematic cross-sectional view of a semiconductor structure 10.

As shown in FIG. 1 , in the embodiment, the semiconductor structure 10 includes a substrate 12 , a first doped region 14 , a second doped region 16 , a third doped region 18 , and a fourth doped region formed in the substrate 12 . The impurity region 20, the gate doped region 22, the source doped region 24, the drain doped region 26, and the plurality of isolation structures 28. It is worth noting that the third blend The impurity region 18 is located between the first doping region 14 and the second doping region 16 and electrically isolates the first doping region 14 from the second doping region 16. The fourth doped region 20 is surrounded by the second doped region 16. The gate doped region 22 is surrounded by a fourth doped region 20. Source doped region 24 and drain doped region 26 are located within second doped region 16. The isolation structure 28 is between the gate doped region 22 and the source doped region 24 and between the gate doped region 22 and the gate doped region 26.

According to some embodiments, the substrate 12 may be a P-type germanium substrate or an N-type germanium substrate.

In this embodiment, the substrate 12 is a P-type germanium substrate, and when the substrate 12 is a P-type germanium substrate, the first doped region 14, the second doped region 16, the source doped region 24, and the drain doping The region 26 is an N-type doped region, and the third doped region 18, the fourth doped region 20, and the gate doped region 22 are P-type doped regions.

According to some embodiments, the thickness T of the third doped region 18 ranges from about 200 to 300 nanometers.

According to some embodiments, the width W1 of the third doped region 18 is greater than or equal to the width W2 of the second doped region 16.

In accordance with some embodiments, where effective electrical isolation is formed between the first doped region 14 and the second doped region 16, the width W1 of the third doped region 18 can be any suitable size.

According to some embodiments, the third doped region 18 has a bottom 30 and a top 32, the bottom 30 contacts the first doped region 14, the top 32 contacts the second doped region 16, and the top 32 of the third doped region 18 and the substrate The distance D of the surface 34 of 12 is approximately between 5 and 7 microns.

According to some embodiments, the top 32 of the third doped region 18 and the substrate The distance D of the surface 34 of 12 is approximately 6.13 microns.

According to some embodiments, the second doped region 16 between the third doped region 18 and the fourth doped region 20 defines a channel 36.

According to some embodiments, the isolation structure 28 can be a shallow trench isolation (STI).

In the present embodiment, the semiconductor structure 10 is a vertical junction field effect transistor (JFET).

Referring to FIGS. 2A-2E, a method of fabricating a semiconductor structure 10 is provided in accordance with an embodiment of the present disclosure. 2A-2E is a schematic cross-sectional view showing a method of fabricating the semiconductor structure 10.

As shown in FIG. 2A, a substrate 12 is provided.

In some embodiments, the substrate 12 can be a P-type germanium substrate or an N-type germanium substrate.

In the present embodiment, the substrate 12 is a P-type germanium substrate.

Thereafter, a first implant process 38 is performed to form a first doped region 14 in the substrate 12.

In the present embodiment, the first implant process 38 is implanted with an N-type dopant such as nitrogen, phosphorus or arsenic to form a first doped region 14 of the N-type doped region.

According to some embodiments, the first implant process 38 has a implant dose of between about 1 x 10 ¹³ and 8 x 10 ¹³ .

According to some embodiments, the first implant process 38 has an implant energy of between about 20 and 60 KeV.

Thereafter, as shown in FIG. 2B, a plurality of isolation structures 28 are formed on the base. In the board 12.

In some embodiments, the isolation structure 28 can be fabricated by any suitable deposition process.

According to some embodiments, the isolation structure 28 can be a shallow trench isolation (STI).

Thereafter, a second implant process 40 is performed to form a second doped region 16 in the substrate 12.

In the present embodiment, the second implant process 40 is implanted with an N-type dopant such as nitrogen, phosphorus or arsenic to form a second doped region 16 of the N-type doped region.

According to some embodiments, the second implant process 40 has a implant dose of between about 1 x 10 ¹³ and 8 x 10 ¹³ .

According to some embodiments, the implanting energy of the second implant process 40 is between about 20 and 60 KeV.

Thereafter, as shown in FIG. 2C, a third implant process 42 is performed to form a third doped region 18 in the substrate 12. The third doped region 18 is located between the first doped region 14 and the second doped region 16 and electrically isolates the first doped region 14 from the second doped region 16.

In the present embodiment, the third implant process 42 is implanted with a P-type dopant such as boron, aluminum, gallium, or indium to form a third doped region 18 of the P-type doped region.

According to some embodiments, the implanting dose of the third implanting process 42 is approximately between 1 x 10 ¹³ and 8 x 10 ¹³ .

According to some embodiments, the third implanting process 42 has a large implant energy About 20 to 60 KeV.

According to some embodiments, the thickness T of the third doped region 18 ranges from about 200 to 300 nanometers.

According to some embodiments, the width W1 of the third doped region 18 is greater than or equal to the width W2 of the second doped region 16.

In accordance with some embodiments, where effective electrical isolation is formed between the first doped region 14 and the second doped region 16, the width W1 of the third doped region 18 can be any suitable size.

According to some embodiments, the third doped region 18 has a bottom 30 and a top 32, the bottom 30 contacts the first doped region 14, the top 32 contacts the second doped region 16, and the top 32 of the third doped region 18 and the substrate The distance D of the surface 34 of 12 is approximately between 5 and 7 microns.

According to some embodiments, the distance D between the top 32 of the third doped region 18 and the surface 34 of the substrate 12 is approximately 6.13 microns.

Thereafter, as shown in FIG. 2D, a fourth implant process 44 is performed to form a fourth doped region 20 in the second doped region 16.

In the present embodiment, the fourth implant process 44 is implanted with a P-type dopant such as boron, aluminum, gallium, or indium to form a fourth doped region 20 of the P-type doped region.

According to some embodiments, the fourth implant process 44 has a implant dose of between about 1 x 10 ¹³ and 8 x 10 ¹³ .

According to some embodiments, the fourth implant process 44 has an implant energy of between about 20 and 60 KeV.

Thereafter, as shown in FIG. 2E, the fifth implantation process 46 is implemented to A gate doping region 22 is formed in the fourth doping region 20.

In the present embodiment, the fifth implant process 46 is implanted with a P-type dopant such as boron, aluminum, gallium, or indium to form a gate doped region 22 of the P-type doped region.

According to some embodiments, the implanting dose of the fifth implanting process 46 is approximately between 1 x 10 ¹³ and 8 x 10 ¹³ .

According to some embodiments, the implanting energy of the fifth implant process 46 is between about 20 and 60 KeV.

Thereafter, a sixth implantation process 48 is performed to form a source doped region 24 and a drain doped region 26 in the second doped region 16. At this time, the isolation structure 28 is located between the gate doped region 22 and the source doped region 24, and between the gate doped region 22 and the drain doped region 26.

In the present embodiment, the sixth implant process 48 is implanted with an N-type dopant such as nitrogen, phosphorus or arsenic to form a source doped region 24 and a drain doped region 26 of the N-type doped region. .

According to some embodiments, the implanting dose of the sixth implanting process 48 is approximately between 1 x 10 ¹³ and 8 x 10 ¹³ .

According to some embodiments, the implanting energy of the sixth implant process 48 is between about 20 and 60 KeV.

According to some embodiments, the second doped region 16 between the third doped region 18 and the fourth doped region 20 defines a channel 36.

Thereafter, on the substrate 12, for example, a metal telluride process and an electrical connection process are continued.

Thus, the fabrication of the semiconductor structure 10 of the present embodiment is completed.

In the present embodiment, the semiconductor structure 10 is a vertical junction field effect transistor (JFET).

Referring to FIG. 3, in accordance with an embodiment of the present disclosure, a semiconductor structure 10 is provided. FIG. 3 is a schematic cross-sectional view of the semiconductor structure 10.

As shown in FIG. 3, in the embodiment, the semiconductor structure 10 includes a substrate 12, a first doping region 14, a second doping region 16, a third doping region 18, and a fourth doping formed in the substrate 12. The impurity region 20, the gate doped region 22, the source doped region 24, the drain doped region 26, and the plurality of isolation structures 28. It should be noted that the third doping region 18 is located between the first doping region 14 and the second doping region 16 and electrically isolate the first doping region 14 from the second doping region 16. The fourth doped region 20 is surrounded by the second doped region 16. The gate doped region 22 is surrounded by a fourth doped region 20. Source doped region 24 and drain doped region 26 are located within second doped region 16. The isolation structure 28 is between the gate doped region 22 and the source doped region 24 and between the gate doped region 22 and the gate doped region 26.

According to some embodiments, the substrate 12 may be a P-type germanium substrate or an N-type germanium substrate.

In this embodiment, the substrate 12 is an N-type germanium substrate, and when the substrate 12 is an N-type germanium substrate, the first doped region 14, the second doped region 16, the source doped region 24, and the drain doping The region 26 is a P-type doped region, and the third doped region 18, the fourth doped region 20, and the gate doped region 22 are N-type doped regions.

According to some embodiments, the thickness T of the third doped region 18 ranges from about 200 to 300 nanometers.

According to some embodiments, the width W1 of the third doped region 18 is greater than or equal to the width W2 of the second doped region 16.

In accordance with some embodiments, where effective electrical isolation is formed between the first doped region 14 and the second doped region 16, the width W1 of the third doped region 18 can be any suitable size.

According to some embodiments, the third doped region 18 has a bottom 30 and a top 32, the bottom 30 contacts the first doped region 14, the top 32 contacts the second doped region 16, and the top 32 of the third doped region 18 and the substrate The distance D of the surface 34 of 12 is approximately between 5 and 7 microns.

According to some embodiments, the distance D between the top 32 of the third doped region 18 and the surface 34 of the substrate 12 is approximately 6.13 microns.

According to some embodiments, the second doped region 16 between the third doped region 18 and the fourth doped region 20 defines a channel 36.

According to some embodiments, the isolation structure 28 can be a shallow trench isolation (STI).

In the present embodiment, the semiconductor structure 10 is a vertical junction field effect transistor (JFET).

Referring to FIGS. 4A-4E, a method of fabricating a semiconductor structure 10 is provided in accordance with an embodiment of the present disclosure. 4A-4E is a schematic cross-sectional view showing a method of fabricating the semiconductor structure 10.

As shown in Fig. 4A, a substrate 12 is provided.

In some embodiments, the substrate 12 can be a P-type germanium substrate or an N-type germanium substrate.

In the present embodiment, the substrate 12 is an N-type germanium substrate.

Thereafter, a first implant process 38 is performed to form a first doped region 14 in the substrate 12.

In the present embodiment, the first implant process 38 is implanted with a P-type dopant such as boron, aluminum, gallium, or indium to form a first doped region 14 of the P-type doped region.

According to some embodiments, the first implant process 38 has a implant dose of between about 1 x 10 ¹³ and 8 x 10 ¹³ .

According to some embodiments, the first implant process 38 has an implant energy of between about 20 and 60 KeV.

Thereafter, as shown in FIG. 2B, a plurality of isolation structures 28 are formed in the substrate 12.

In some embodiments, the isolation structure 28 can be fabricated by any suitable deposition process.

According to some embodiments, the isolation structure 28 can be a shallow trench isolation (STI).

Thereafter, a second implant process 40 is performed to form a second doped region 16 in the substrate 12.

In the present embodiment, the second implant process 40 is implanted with a P-type dopant such as boron, aluminum, gallium, or indium to form a second doped region 16 of the P-type doped region.

According to some embodiments, the second implant process 40 has a implant dose of between about 1 x 10 ¹³ and 8 x 10 ¹³ .

According to some embodiments, the implanting energy of the second implant process 40 is between about 20 and 60 KeV.

Thereafter, as shown in FIG. 2C, a third implant process 42 is performed to form a third doped region 18 in the substrate 12. The third doping region 18 is located in the first doping region 14 and the second doping region 16 are electrically isolated from the first doping region 14 and the second doping region 16.

In the present embodiment, the third implant process 42 is implanted with an N-type dopant such as nitrogen, phosphorus or arsenic to form a third doped region 18 of the N-type doped region.

According to some embodiments, the implanting dose of the third implanting process 42 is approximately between 1 x 10 ¹³ and 8 x 10 ¹³ .

According to some embodiments, the implanting energy of the third implant process 42 is between about 20 and 60 KeV.

According to some embodiments, the thickness T of the third doped region 18 ranges from about 200 to 300 nanometers.

According to some embodiments, the width W1 of the third doped region 18 is greater than or equal to the width W2 of the second doped region 16.

In accordance with some embodiments, where effective electrical isolation is formed between the first doped region 14 and the second doped region 16, the width W1 of the third doped region 18 can be any suitable size.

According to some embodiments, the third doped region 18 has a bottom 30 and a top 32, the bottom 30 contacts the first doped region 14, the top 32 contacts the second doped region 16, and the top 32 of the third doped region 18 and the substrate The distance D of the surface 34 of 12 is approximately between 5 and 7 microns.

According to some embodiments, the distance D between the top 32 of the third doped region 18 and the surface 34 of the substrate 12 is approximately 6.13 microns.

Thereafter, as shown in FIG. 2D, a fourth implant process 44 is performed to form a fourth doped region 20 in the second doped region 16.

In the present embodiment, the fourth implant process 44 is implanted with an N-type dopant such as nitrogen, phosphorus or arsenic to form a fourth doped region 20 of the N-type doped region.

According to some embodiments, the fourth implant process 44 has a implant dose of between about 1 x 10 ¹³ and 8 x 10 ¹³ .

According to some embodiments, the fourth implant process 44 has an implant energy of between about 20 and 60 KeV.

Thereafter, as shown in FIG. 2E, a fifth implant process 46 is performed to form a gate doped region 22 in the fourth doped region 20.

In the present embodiment, the fifth implant process 46 is implanted with an N-type dopant such as nitrogen, phosphorus or arsenic to form a gate doped region 22 of the N-type doped region.

According to some embodiments, the implanting dose of the fifth implanting process 46 is approximately between 1 x 10 ¹³ and 8 x 10 ¹³ .

According to some embodiments, the implanting energy of the fifth implant process 46 is between about 20 and 60 KeV.

Thereafter, a sixth implantation process 48 is performed to form a source doped region 24 and a drain doped region 26 in the second doped region 16. At this time, the isolation structure 28 is located between the gate doped region 22 and the source doped region 24, and between the gate doped region 22 and the drain doped region 26.

In the present embodiment, the sixth implant process 48 is implanted with a P-type dopant such as boron, aluminum, gallium, or indium to form a source doped region 24 and a drain doped region of the P-type doped region. Miscellaneous area 26.

According to some embodiments, the implanting dose of the sixth implanting process 48 is approximately between 1 x 10 ¹³ and 8 x 10 ¹³ .

According to some embodiments, the implanting energy of the sixth implant process 48 is between about 20 and 60 KeV.

According to some embodiments, the second doped region 16 between the third doped region 18 and the fourth doped region 20 defines a channel 36.

Thereafter, on the substrate 12, for example, a metal telluride process and an electrical connection process are continued.

Thus, the fabrication of the semiconductor structure 10 of the present embodiment is completed.

In the present embodiment, the semiconductor structure 10 is a vertical junction field effect transistor (JFET).

Example

Example 1

The relationship between the gate voltage and the drain current of the field effect transistor in this embodiment

The electrical test was performed with a junction field effect transistor (JFET) structure as shown in Fig. 1 to measure the relationship between the gate voltage (VG) and the drain current (ID). Figure 5 shows. In the case of a fixed source/drain voltage, different gate voltages (negative bias voltages) (from 0 to -8 V) are applied to the junction field effect transistors of this embodiment. It can be seen from the test results that when the gate voltage is not applied, the drain current is 0.27 mA, and when the gate voltage of -5 V is applied, the drain current is reduced to 0, which means the junction field of this embodiment. The pinch-off voltage of the effect transistor is -5 V, and it is apparent that the junction field effect transistor of this embodiment has a relatively low clamping voltage.

Example 2

The relationship between the source/drain voltage and the drain current of the junction field effect transistor of this embodiment

Conductive testing with a junction field effect transistor (JFET) structure as shown in Figure 1 to measure the relationship between source/drain voltage (VDS) and drain current (ID), The result is shown in Figure 6. The relationship between the source/drain voltage (VDS) and the drain current (ID) is measured without applying a gate voltage. It can be seen from the test results that when the gate voltage (Vg = 0 V) is not applied, the breakdown voltage of the junction field effect transistor of this embodiment is 33.6 V, which is apparently high in the junction field effect transistor of this embodiment. Crash voltage.

The invention utilizes a general CMOS or Bipolar-CMOS-DMOS (BCD) process to fabricate a junction field effect transistor (JFET), and implants a P-type or N-type dopant in the implantation process (depending on the product needs to be adjusted). The specific depth position of the substrate forms a doped region having a specific size (for example, a specific thickness and width) as an electrical isolation structure of the upper and lower doped regions, and defines a channel of a junction field effect transistor (JFET). When the component is actuated, by adjusting the magnitude of the gate voltage, the size of the depletion region on the channel can be further affected. When the applied negative bias voltage is larger, the range of the depletion region is enlarged, and finally the channel is depleted. The region is pinched off and the current is stopped. The magnitude of the gate voltage applied at this time is the pinch-off voltage of the junction field effect transistor (JFET). Therefore, in the present invention, the magnitude of the pinch-off voltage can be changed by simply adjusting the size of the doping region as the electrical isolation structure in the substrate. The process of the invention is simple and does not require an additional mask step to define the channel, and the fabricated junction field effect transistor (JFET) has a low clamping voltage and a high breakdown voltage, which is quite beneficial for various switching applications and ESD protection.

While the invention has been described above in terms of several preferred embodiments, it is not intended to limit the scope of the present invention, and any one of ordinary skill in the art can make any changes without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims.

Claims (10)

A semiconductor structure comprising: a substrate having a surface; a first doped region formed in the substrate; a second doped region formed in the substrate; and a third doped region formed on the substrate The third doped region is located between the first doped region and the second doped region, and electrically isolates the first doped region from the second doped region; a fourth doped region Formed in the substrate, surrounded by the second doped region; a gate doped region formed in the substrate and surrounded by the fourth doped region; a source doped region formed in the The substrate is located in the second doping region; a drain doped region is formed in the substrate and located in the second doped region; and a plurality of isolation structures are formed in the substrate at the gate Between the doped region and the source doped region, and between the gate doped region and the drain doped region, wherein the substrate is an N-type germanium substrate, the first doped region, the first The doped region, the source doped region, and the drain doped region are P-type doped regions, the third doped region, the fourth doped region, and the Doping region is N-type doped region. The semiconductor structure of claim 1, wherein the third doped region has a thickness of 200 to 300 nm. The semiconductor structure of claim 1, wherein the third doped region has a width greater than or equal to a width of the second doped region. The semiconductor structure of claim 1, wherein the third doping The region has a bottom and a top, the bottom contacting the first doped region, the top contacting the second doped region. The semiconductor structure of claim 4, wherein the top of the third doped region is at a distance of 5-7 microns from the surface of the substrate. The semiconductor structure of claim 1, wherein the second doped region between the third doped region and the fourth doped region defines a channel. The semiconductor structure of claim 1, wherein the isolation structures are shallow trench spacers. A method for fabricating a semiconductor structure, comprising: providing a substrate, wherein the substrate is an N-type germanium substrate; performing a first implant process to form a first doped region in the substrate; forming a plurality of isolation structures In the substrate, a second implantation process is performed to form a second doped region in the substrate; and a third implant process is performed to form a third doped region in the substrate, wherein the third The doped region is located between the first doped region and the second doped region, and electrically isolates the first doped region from the second doped region; and a fourth implant process is performed to Forming a fourth doping region in the two doping regions; performing a fifth implantation process to form a gate doping region in the fourth doping region; and implementing a sixth implantation process to Forming a source doped region and a drain doped region in the second doped region such that the isolation structures are located between the gate doped region and the source doped region, and are located at the gate doping Between the region and the drain doping region, wherein the first implanting process, the second implanting process, And the sixth planting process is carried out by P-type dopant, the third planting process, the fourth planting process, and the fifth planting process are implanted with N-type dopants. The method of fabricating a semiconductor structure according to claim 8, wherein the implanting dose of the third implanting process is between 1×10 ¹³ and 8×10 ¹³ . The method of fabricating a semiconductor structure according to claim 8, wherein the third implant process has a implantation energy of 20 to 60 KeV.