KR20230109458A - Circular ldmos device and method of manufacturing the same - Google Patents

Abstract

A circular LDMOS device includes a substrate of a first conductivity type, a lower drift layer formed on the substrate, a drain region formed on the lower drift layer, a source region having an annular ring shape surrounding the drain region and spaced apart from the drain region, An upper drift layer formed on the lower drift layer and having a conductivity type different from that of the lower drift layer, a field insulating film formed on the upper drift layer and electrically separating the drain region and the source region from each other, and the upper drift layer and a reverse bias region of the first conductivity type provided to extend a depletion region when reverse bias is applied to the substrate and the upper drift layer.

Description

Circular LDMOS device and its manufacturing method {CIRCULAR LDMOS DEVICE AND METHOD OF MANUFACTURING THE SAME}

Embodiments of the present invention relate to a high voltage semiconductor device and a manufacturing method thereof. More specifically, embodiments of the present invention relate to a circular LDMOS (Lateral Double Diffused Metal Oxide Semiconductor) device and a manufacturing method of the circular LDMOS device.

In general, an LDMOS device used as a high voltage semiconductor device may have advantages such as fast switching speed, high input impedance, and low power consumption. Accordingly, display driver ICs, power converters, motor controllers, automotive power supplies, etc. It can be widely used in various power devices. The LDMOS device may include a drift region extending in a horizontal direction between a channel region and a drain region, and an on-resistance and a breakdown voltage of the LDMOS device may be determined by a length of the drift region and an impurity concentration.

For example, a circular LDMOS device includes a drift region formed on a substrate, a drain region formed on a central portion of the drift region, a circular ring-shaped body region formed to surround the drift region, and the body region It may include a source region formed thereon. The on-resistance of the circular LDMOS device may be reduced by increasing the impurity concentration of the drift region, and the circular LDMOS device may have an increased breakdown voltage when the drift region is sufficiently converted to a depletion state.

Also, when the drift length of the drift region along the horizontal direction is increased, the horizontal electric field may be reduced. As a result, the breakdown voltage may increase. However, when the drift length increases, the channel width increases, which may cause an on-state breakdown voltage (On-BV) to decrease.

Embodiments of the present invention provide a circular LDMOS device with increased breakdown voltage.

Embodiments of the present invention provide a method of fabricating a circular LDMOS device with increased breakdown voltage.

A circular LDMOS device according to embodiments of the present invention has a substrate of a first conductivity type, a lower drift layer formed on the substrate, a drain region formed on the lower drift layer, and an annular ring shape surrounding the drain region. A source region spaced apart from the drain region, an upper drift layer formed on the lower drift layer and having a conductivity type different from that of the lower drift layer, and formed on the upper drift layer, wherein the drain region and the source region are electrically connected to each other. The reverse bias region of the first conductivity type penetrates the separating field insulating layer and the upper drift layer and the lower drift layer and is provided to expand a depletion region when a reverse bias is applied to the substrate and the upper drift layer. include

In one embodiment of the present invention, the reverse bias region may have the first conductivity type.

In one embodiment of the present invention, the reverse bias region extends downward from a high-concentration reverse bias layer and a high-concentration reverse bias pattern that isolate the field insulating layer into first and second field insulating layer patterns on the upper drift layer. and may include a pair of first slits spaced apart from each other along the horizontal direction.

Here, the reverse bias region may additionally include second slits spaced apart from the slits, penetrating the upper drift layer and the lower drift layer downward, and electrically connected to the upper drift layer.

In one embodiment of the present invention, an epitaxial layer formed on the substrate and having the same conductivity type as the lower drift layer, the substrate having the same first conductivity type as the upper drift layer, The lower drift layer may be formed on the epitaxial layer.

Here, the field insulating layer and the upper drift layer may each have a circular ring shape, and the lower drift layer and the epitaxial layer may each have a disk shape.

In one embodiment of the present invention, a first well region having a circular ring shape surrounding the upper drift layer and having the same first conductivity type as the upper drift layer is formed on the lower drift layer and the lower drift layer A second well region having the same second conductivity type may be additionally provided, the source region may be formed on the first well region, and the drain region may be formed on the second well region.

Here, the upper drift layer and the first well region may be separated by a predetermined distance.

In addition, a third well region formed in the first well region and having the first conductivity type and a well contact region formed on the third well region and having the first conductivity type are additionally formed.

Meanwhile, a deep well region formed under the first well region and having the first conductivity type and a buried layer formed under the deep well region and having the first conductivity type may be additionally provided.

Here, the filling layer may include a ring region having a circular ring shape and a plurality of protrusions protruding inward from the ring region.

In one embodiment of the present invention, a first field electrode disposed on the field insulating film and having a circular ring shape is additionally provided.

Here, a plurality of second field electrodes are formed having a circular ring shape surrounding the first field electrode and disposed in a concentric circle shape.

Also, the first field electrode may be electrically connected to the drain region, and the second field electrodes may be electrically isolated.

In the manufacturing method of a circular LDMOS device according to embodiments of the present invention, a lower drift layer is formed on a substrate of a first conductivity type, and an upper portion of a circular ring shape having the first conductivity type is formed on the lower drift layer form a drift layer. A field insulating layer having a circular ring shape is formed on the upper drift layer, a drain region is formed inside the field insulating layer, and a source region having a circular ring shape surrounding the field insulating layer and spaced apart from the drain region is formed. . In addition, a reverse bias region of the first conductivity type is formed to pass through the upper drift layer and the lower drift layer and to expand a depletion region when a reverse bias is applied to the substrate and the upper drift layer.

In one embodiment of the present invention, the reverse bias region may have the first conductivity type.

In one embodiment of the present invention, in order to form the reverse bias region, a high-concentration reverse bias layer is formed on the upper drift layer to isolate the field insulating film with first and second field insulating film patterns, and the high-concentration reverse bias layer is formed on the upper drift layer. A pair of first slits extending downward from the bias pattern and spaced apart from each other in a horizontal direction may be formed. In this case, the first slits may be formed through an ion implantation process.

According to the embodiments of the present invention as described above, the reverse bias region passes through the upper drift layer and the lower drift layer. In this case, the reverse bias region is provided to expand a depletion region when a reverse bias is applied to the substrate and the upper drift layer. Accordingly, when a reverse bias voltage is applied to the reverse bias region, reverse bias is applied to the upper drift layer and the substrate. As a result, as the depletion region is expanded, the current path is reduced. Furthermore, the amount of current can be easily controlled by adjusting the depletion width by adjusting the reverse bias value.

1 is a plan view for explaining a circular LDMOS device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along line II-II′ shown in FIG. 1 .
3 is a cross-sectional view for explaining a circular LDMOS device according to an embodiment of the present invention.
4 to 9 are cross-sectional views for explaining a manufacturing method of the circular LDMOS device shown in FIG. 1 .

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention does not have to be configured as limited to the embodiments described below and may be embodied in various other forms. The following examples are not provided to fully complete the present invention, but rather to fully convey the scope of the present invention to those skilled in the art.

In the embodiments of the present invention, when one element is described as being disposed on or connected to another element, the element may be directly disposed on or connected to the other element, and other elements may be interposed therebetween. It could be. Alternatively, when an element is described as being directly disposed on or connected to another element, there cannot be another element between them. The terms first, second, third, etc. may be used to describe various items such as various elements, compositions, regions, layers and/or parts, but the items are not limited by these terms. will not

Technical terms used in the embodiments of the present invention are only used for the purpose of describing specific embodiments, and are not intended to limit the present invention. In addition, unless otherwise limited, all terms including technical and scientific terms have the same meaning as can be understood by those skilled in the art having ordinary knowledge in the technical field of the present invention. The above terms, such as those defined in conventional dictionaries, shall be construed to have a meaning consistent with their meaning in the context of the relevant art and description of the present invention, unless expressly defined, ideally or excessively outwardly intuition. will not be interpreted.

Embodiments of the present invention are described with reference to schematic illustrations of idealized embodiments of the present invention. Accordingly, variations from the shapes of the illustrations, eg, variations in manufacturing methods and/or tolerances, are fully foreseeable. Accordingly, embodiments of the present invention are not to be described as being limited to specific shapes of regions illustrated as diagrams, but to include variations in shapes, and elements described in the drawings are purely schematic and their shapes is not intended to describe the exact shape of the elements, nor is it intended to limit the scope of the present invention.

1 is a plan view for explaining a circular LDMOS device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line II-II′ shown in FIG. 1 .

1 and 2, a circular LDMOS device 100 according to an embodiment of the present invention includes a substrate 102, a lower drift layer 130, a source region 152, a drain region 154, and an upper drift A region 134 , a field insulating layer 140 and a reverse bias region 160 are included.

The substrate has a first conductivity type. For example, the first substrate may have P-type conductivity.

A lower drift layer 130 is formed over the substrate 102 . The lower drift layer 130 may have a second conductivity type different from the first conductivity type. For example, the lower drift layer 130 may have N-type conductivity.

A drain region 154 is formed on the lower drift layer 130 . Meanwhile, a source region 152 having a circular ring shape and spaced apart from the drain region 154 is provided to surround the drain region.

A field insulating film is formed on the lower drift layer. A field insulating layer is formed between the drain region 154 and the source region 152 . Thus, the field insulating layer electrically separates the drain region and the source region from each other. The field insulating layer may be made of, for example, silicon oxide.

An upper drift layer 134 is formed between the lower drift layer 130 and the field insulating layer 140 . The upper drift layer 134 may have a conductivity type different from that of the lower drift layer 130, that is, a first conductivity type.

The reverse bias region 160 passes through the upper drift layer 134 and the lower drift layer 130 . The reverse bias region 160 is provided to expand a depletion region when a reverse bias is applied to the substrate 102 and the upper drift layer 134 . The reverse bias region 160 may have the first conductivity type.

When a reverse bias voltage is applied to the reverse bias region 160 , a reverse bias is applied to the upper drift layer 134 and the substrate 105 . As a result, the current path is reduced by extending the depletion region.

Furthermore, the amount of current can be easily controlled by adjusting the depletion width by adjusting the reverse bias value.

In one embodiment of the present invention, the reverse bias region 160 may include a high concentration reverse bias layer 161 and a pair of slits 162 .

The high-concentration reverse bias layer 161 may isolate the field insulating layer 140 into a first field insulating layer pattern 141 and a second field insulating layer pattern 140 on the upper drift layer 134 . The high concentration reverse bias layer 161 may have a first conductivity type.

The pair of slits 162 extend downward from the high-concentration reverse bias layer 161 and are spaced apart from each other in a horizontal direction. Meanwhile, the number of slits 162 may be adjusted.

Meanwhile, the circular LDMOS device 100 may include an epitaxial layer 104 formed on the substrate 102, and the lower drift layer 130 may be formed on the epitaxial layer 104 there is.

In particular, the substrate 102 may have a first conductivity type, and the epitaxial layer 104 and the lower drift layer 130 may have a second conductivity type. For example, the substrate 102 may be a P-type substrate, and an N-type epitaxial layer 104 may be formed on the P-type substrate 102 . In addition, an N-type impurity region functioning as the lower drift layer 130 may be formed on the N-type epitaxial layer 104 . The N-type epitaxial layer 104 may be formed on the P-type substrate 102 through an epitaxial growth process, and the lower drift layer 130 is ion implanted into the N-type epitaxial layer 104 It may be formed by implanting N-type impurities through a process.

The upper drift layer 134 may be formed on the lower drift layer 130 . The upper drift layer 134 may have the first conductivity type in order to sufficiently implement the depletion state of the lower drift layer 130 . For example, the upper drift layer 134 may be a P-type impurity region, and may be formed by implanting P-type impurities into the upper portion of the lower drift layer 130 through an ion implantation process. In particular, by forming the upper drift layer 134 , the impurity concentration of the lower drift layer 130 may be increased, thereby reducing the on-resistance of the circular LDMOS device 100 .

The circular LDMOS device 100 is formed on a central portion adjacent to the drain region 154 of the first well region 136 having a circular ring shape surrounding the upper drift layer 134 and the lower drift layer 130. A formed second well region 138 may be further included.

The upper drift layer 134 may be formed in a circular ring shape between the first well region 136 and the second well region 138 . The first well region 136 may have the same conductivity type as the upper drift layer 134 and the first conductivity type, and the second well region 138 may have the same conductivity as the lower drift layer 130 . type, that is, may have the second conductivity type.

For example, the first well region 136 may be a P-type impurity region, and the second well region 138 may be an N-type impurity region. The first well region 136 may be formed on an upper portion of an edge of the lower drift layer 130 through an ion implantation process, and the second well region 138 may be formed at the center of the lower drift layer 130. It may be formed through an ion implantation process on top of the site. In this case, the lower drift layer 130 may have a higher impurity concentration than the epitaxial layer 104, and the second well region 138 may have a higher impurity concentration than the lower drift layer 130. there is.

The source region 152 may be formed on the first well region 136 , and the drain region 154 may be formed on the second well region 138 . The source region 152 and the drain region 154 may have the second conductivity type. For example, the source region 152 may be formed by implanting N-type impurities into an upper portion of the first well region 136 through an ion implantation process, and the drain region 154 may be formed by implanting an N-type impurity into the upper portion of the first well region 136 . It can be formed by implanting an N-type impurity on top of (138).

In addition, a well contact region 156 may be formed on the first well region 136 . The well contact region 156 may have the first conductivity type and may be formed in a circular ring shape surrounding the source region 152 . Optionally, as shown in FIG. 2 , a third well region 158 having the first conductivity type may be formed in the first well region 136, and an upper portion of the third well region 158 may be formed. The well contact region 156 may be formed. For example, the third well region 158 may be formed by implanting P-type impurities into the first well region 136 through an ion implantation process, and the well contact region 156 may be formed by an ion implantation process. It may be formed by injecting P-type impurities into the upper portion of the third well region 158 through As a result, the third well region 158 may have a higher impurity concentration than the first well region 136 , and the well contact region 156 may have a higher impurity concentration than the third well region 158 . there is.

According to an embodiment of the present invention, a deep well region 132 having the same conductivity type as the first well region 136, that is, the first conductivity type may be formed below the first well region 136. A buried layer 110 having the same conductivity type as the deep well region 132 , ie, the first conductivity type, may be formed below the deep well region 132 . The deep well region 132 may be used for device isolation, and the buried layer 110 may be used to sufficiently deplete the lower drift layer 130 and the epitaxial layer 104 .

For example, the deep well region 132 may have a circular ring shape surrounding the lower drift layer 130 and may be a P-type impurity region formed through an ion implantation process. The buried layer 110 may have a circular ring shape surrounding the epitaxial layer 104 and may be a P-type impurity region formed through an ion implantation process. As a result, the epitaxial layer 104 may have a substantially disk shape defined by the buried layer 110, and the lower drift layer 130 may have a shape of the first well region 136 and the deep well region 132. ) may have an approximately circular ring shape defined by

Referring back to FIGS. 1 and 2 , the field insulating layer 140 may be formed between the source region 152 and the drain region 154 . In particular, the outer portion of the field insulating layer 140 is formed on the upper drift layer 134 to be spaced apart from the first well region 136 by a predetermined distance, and the inner portion of the field insulating layer 140 is formed on the second well region 136. It may be formed on an edge portion of the well region 138 .

For example, the field insulating layer 140 may be formed in a circular ring shape through a LOCOS (Local Oxidation of Silicon) process. In this case, the outer portion of the upper drift layer 134 is spaced apart from the first well region 136 by a predetermined interval, and the inner portion of the upper drift layer 134 is spaced apart from the second well region 138 by a predetermined interval. It can be. Therefore, as shown in FIG. 2 , the field insulating film 140 is formed between the upper drift layer 134 and the lower drift layer (between the upper drift layer 134 and the second well region 138). 130) and an outer portion of the second well region 138 in a circular ring shape. In this case, the drain region 154 may be formed inside the field insulating layer 140 .

Meanwhile, the circular LDMOS device 100 may include a device isolation layer 142 surrounding the well contact region 156 . As an example, the device isolation layer 142 may be formed simultaneously with the field insulating layer 140 . As another example, although not shown, the circular LDMOS device 100 may include a device isolation region (not shown) surrounding the well contact region 156, and the device isolation region is STI (Shallow Trench Isolation) It can be formed through a process.

A gate insulating layer 144 may be formed on an inner portion of the first well region 136, an outer portion of the lower drift layer 130, and an outer portion of the upper drift layer 134, and the gate insulating layer 144 may be formed. A gate electrode 146 may be formed on an outer portion of the insulating layer 144 and the field insulating layer 140 .

Referring back to FIG. 2 , a first field electrode 148 having a circular ring shape (not shown in FIG. 1 ) may be formed on an inner portion of the field insulating layer 140 . In addition, a plurality of second field electrodes 150 (not shown in FIG. 1) are formed on the field insulating film 140 to have a circular ring shape surrounding the first field electrode 148 and are arranged in a concentric circle. can The first field electrode 148 and the second field electrodes 150 may be formed to prevent an electric field from being concentrated on the drain region 154 or an area adjacent to the drain region 154 . In particular, the first field electrode 148 may be electrically connected to the drain region 154 and the second field electrodes 150 may be electrically isolated.

3 is a cross-sectional view for explaining a circular LDMOS device according to an embodiment of the present invention.

Referring to FIG. 3, a circular LDMOS device according to an embodiment of the present invention includes a substrate 102, a lower drift layer 130, a source region 152, a drain region 154, an upper drift region 134, a field It includes an insulating layer 140 and a reverse bias region 160 .

The reverse bias region 160 is spaced apart from the first slits 161 and penetrates the upper drift layer 134 and the lower drift layer 130 downwardly, and is electrically connected to the upper drift layer 134. The second slits 163 may be further included.

That is, the first slits 162 apply a first reverse bias to the substrate 105, while the second slits 163 apply a second reverse bias different from the first reverse bias to the upper drift layer ( 134) can be applied.

4 to 8 are cross-sectional views for explaining a manufacturing method of the circular LDMOS device shown in FIG. 1 .

Referring to FIG. 4 , an epitaxial layer 104 may be formed on the substrate 100 . For example, the substrate 102 may have a first conductivity type and the epitaxial layer 104 may have a second conductivity type. Specifically, the N-type epitaxial layer 104 may be formed on the P-type silicon substrate 102 through an epitaxial growth process.

Referring to FIG. 5 , a buried layer 110 having a circular ring shape and surrounding the epitaxial layer 104 may be formed on the substrate 102 . For example, the buried layer 110 may have the first conductivity type, and by implanting P-type impurities into the surface portion of the substrate 102 and the epitaxial layer 104 through an ion implantation process, the buried layer 110 may have the first conductivity type. (110) may be formed. The ion implantation process may be performed using the ion implantation mask 10 shown in FIG. 4 . The filling layer 100 may include a ring region 112 having a circular ring shape and a plurality of protrusions 114 protruding inward from the ring region 112 . That is, the protrusions 114 may protrude toward the center of the filling layer 100 .

In addition, a lower drift layer 130 may be formed on the epitaxial layer 104 . For example, the lower drift layer 130 may have the second conductivity type, and by implanting N-type impurities into the epitaxial layer 104 through an ion implantation process, on the epitaxial layer 104 The lower drift layer 130 may be formed.

Referring to FIG. 6 , a deep well region 132 having a circular ring shape may be formed on the buried layer 110 . For example, the deep well region 132 may have the first conductivity type, and the deep well region 132 is formed by implanting P-type impurities into the lower drift layer 130 through an ion implantation process. can do.

An upper drift layer 134 having a circular ring shape may be formed on the lower drift layer 130 . For example, the upper drift layer 134 may have the first conductivity type, and the upper drift layer 134 is formed by implanting P-type impurities into the upper part of the lower drift layer 130 through an ion implantation process. can be formed.

A first well region 136 having a circular ring shape may be formed on the deep well region 132 . For example, the first well region 136 may have the first conductivity type, and by implanting P-type impurities into the upper part of the lower drift layer 130 through an ion implantation process, the first well region ( 136) can be formed.

A second well region 138 may be formed on the lower drift layer 130 . For example, the second well region 138 may have the second conductivity type, and by implanting N-type impurities into the upper part of the lower drift layer 130 through an ion implantation process, the second well region ( 138) can be formed.

In this case, the upper drift layer 134 may have a circular ring shape surrounding the second well region 138, and the first well region 136 may have a circular ring shape surrounding the upper drift layer 134. can have Also, the upper drift layer 134 may be spaced apart from the first well region 138 by a predetermined distance, and the second well region 136 may be spaced apart from the upper drift layer 134 by a predetermined distance.

Referring to FIG. 7 , a field insulating layer 140 having a circular ring shape may be formed on the upper drift layer 134 . An outer portion of the field insulating layer 140 is formed on the upper drift layer 134 to be spaced apart from the first well region 136 by a predetermined distance, and an inner portion of the field insulating layer 140 is formed on the second well region. (138) may be formed on the edge portion.

For example, the field insulating layer 140 may be formed in a circular ring shape through a LOCOS (Local Oxidation of Silicon) process. Specifically, the field insulating film 140 includes the upper drift layer 134, a part of the lower drift layer 130 between the upper drift layer 134 and the second well region 138, and the first It may be formed in a circular ring shape on the outer portion of the 2 well region 138 . That is, the inner diameter of the field insulating film 140 may be smaller than the inner diameter of the upper drift layer 134 , and the outer diameter of the field insulating film 140 may be smaller than the outer diameter of the upper drift region 134 .

Meanwhile, a device isolation layer 142 may be formed to electrically isolate the circular LDMOS device 100 from adjacent devices. As an example, the device isolation layer 142 may be formed simultaneously with the field insulating layer 140 .

As another example, the device isolation layer 142 may be formed on the epitaxial layer 104 through a LOCOS process after forming the epitaxial layer 104 .

Referring to FIG. 8 , a gate insulating layer 144 may be formed, and a gate electrode 146 may be formed on the gate insulating layer 144 . For example, the gate insulating film 144 may be formed through a thermal oxidation process, and the gate electrode 146 is a polysilicon layer doped with impurities on the gate insulating film 144 and the field insulating film 140 ( (not shown) may be formed by patterning the impurity-doped polysilicon layer. In particular, the gate electrode 146 may have a circular ring shape. Specifically, an outer portion of the gate electrode 146 may be spaced apart from the device isolation layer 142, and an inner portion of the gate electrode 146 may be positioned on an outer portion of the field insulating layer 140. .

In addition, a first field electrode 148 having a circular ring shape may be formed on the inner portion of the field insulating film 140, and the first field electrode 148 has a circular ring shape on the field insulating film 140 and is arranged in a concentric circle shape. A plurality of second field electrodes 150 may be formed. That is, the second field electrodes 150 may be formed between the first gate electrode 146 and the first field electrode 148 .

The first field electrode 148 and the second field electrodes 150 may be formed simultaneously with the gate electrode 146, and although not shown, side surfaces of the gate electrode 146 and the first field electrode 146 may be formed simultaneously. Spacers (not shown) made of an insulating material, for example, silicon oxide or silicon nitride, may be formed on side surfaces of the field electrode 148 and the second field electrodes 150 .

Referring back to FIG. 8 , a source region 152 having the second conductivity type is formed on the first well region 136, and a source region 152 having the second conductivity type is formed on the second well region 138. A drain region 154 may be formed. The source region 152 and the drain region 154 may be formed by implanting N-type impurities into an upper portion of the first well region 136 and an upper portion of the second well region 138 through an ion implantation process. And, the source region 152 may have a circular ring shape.

In addition, a well contact region 156 having the first conductivity type may be formed outside the source region 152 . For example, the well contact region 156 may be formed by implanting P-type impurities into the upper portion of the first well region 136 through an ion implantation process. In addition, the well contact region 156 may be positioned between the source region 152 and the isolation layer 142 and may have a circular ring shape.

Optionally, a third well region 158 having the first conductivity type may be formed in the first well region 136, and the well contact region 156 may be formed on the third well region 158. can be formed in The third well region 158 may be formed through an ion implantation process after forming the first well region 136 or the gate electrode 146 .

Referring to FIG. 9 , when a reverse bias passes through the upper drift layer 134 and the lower drift layer 130 and is applied to the substrate 102 and the upper drift layer 134, the depletion region can be expanded. A reverse bias region 160 of the first conductivity type is formed. In this case, the reverse bias region 160 may have the first conductivity type.

In one embodiment of the present invention, the reverse bias region 160 isolates the field insulating film 140 with first and second field insulating film patterns 140 and 141 on the upper drift layer 134. A high-concentration reverse bias layer 161 is formed. Subsequently, a pair of first slits 162 extending downward from the high-concentration reverse bias layer 161 and spaced apart from each other in a horizontal direction are formed. In this case, the first slits 162 may be formed through an ion implantation process.

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art can variously modify and change the present invention without departing from the spirit and scope of the present invention described in the claims below. You will understand that there is

10: ion implantation mask 12: opening
100: circular LDMOS element 102: substrate
104: epitaxial layer 110: buried layer
112: ring area 114: protrusion
120: buried layer 122: first buried area
124: second buried area 130: lower drift layer
132: deep well region 134: upper drift layer
136: first well region 138: second well region
140: field insulating film 142: element isolation film
144: gate insulating film 146: gate electrode
148: first field electrode 150: second field electrode
152: source region 154: drain region
156: well contact area 158: third well area
160: reverse bias region 161: high concentration reverse bias layer
162: first slit

Claims (18)

a substrate of a first conductivity type;
a lower drift layer formed on the substrate;
a drain region formed on the lower drift layer;
a source region having an annular ring shape surrounding the drain region and spaced apart from the drain region;
an upper drift layer formed on the lower drift layer and having a conductivity type different from that of the lower drift layer;
a field insulating layer formed on the upper drift layer and electrically separating the drain region and the source region from each other; and
a reverse bias region of the first conductivity type passing through the upper drift layer and the lower drift layer and extending a depletion region when a reverse bias is applied to the substrate and the upper drift layer;
A toroidal LDMOS device comprising a. The ring-type LDMOS device according to claim 1, wherein the reverse bias region has the first conductivity type. The method of claim 1, wherein the reverse bias region,
a high-concentration reverse bias layer on the upper drift layer, isolating the field insulating film into first and second field insulating film patterns; and
and a pair of first slits extending downward from the high-concentration reverse bias pattern and spaced apart from each other in a horizontal direction. 4. The method of claim 3 , wherein the reverse bias region further comprises second slits spaced apart from the first slits, penetrating the upper drift layer and the lower drift layer downward, and electrically connected to the upper drift layer. Characterized in that the annular LDMOS device. The method of claim 1, further comprising an epitaxial layer formed on the substrate and having the same conductivity type as the lower drift layer,
The circular LDMOS device according to claim 1 , wherein the substrate has the same first conductivity type as the upper drift layer, and the lower drift layer is formed on the epitaxial layer. The method of claim 5, wherein the field insulating film and the upper drift layer each have a circular ring shape,
Circular LDMOS device, characterized in that each of the lower drift layer and the epitaxial layer has a disk shape. The method of claim 1 , further comprising: a first well region having a circular ring shape surrounding the upper drift layer and having the same first conductivity type as the upper drift layer;
a second well region formed on the lower drift layer and having a second conductivity type identical to that of the lower drift layer;
The circular LDMOS device according to claim 1 , wherein the source region is formed on the first well region, and the drain region is formed on the second well region. 8. The circular LDMOS device according to claim 7, wherein the upper drift layer and the first well region are separated by a predetermined distance. The method of claim 7 , further comprising: a third well region formed in the first well region and having the first conductivity type;
and a well contact region formed on the third well region and having the first conductivity type. The method of claim 7 , further comprising: a deep well region formed under the first well region and having the first conductivity type;
and a buried layer formed below the deep well region and having the first conductivity type. 11. The circular LDMOS device of claim 10, wherein the filling layer includes a ring region having a circular ring shape and a plurality of protrusions protruding inward from the ring region. The circular LDMOS device of claim 1 , further comprising a first field electrode disposed on the field insulating film and having a circular ring shape. 13. The circular LDMOS device of claim 12, further comprising a plurality of second field electrodes having a circular ring shape surrounding the first field electrode and arranged in a concentric circle. 14. The circular LDMOS device according to claim 13, wherein the first field electrode is electrically connected to the drain region, and the second field electrodes are electrically isolated from each other. forming a lower drift layer on a substrate of a first conductivity type;
forming an upper drift layer having a circular ring shape having the first conductivity type on the lower drift layer;
forming a field insulating layer having a circular ring shape on the upper drift layer;
forming a drain region inside the field insulating film;
forming a source region spaced apart from the drain region and having a circular ring shape surrounding the field insulating layer; and
forming a reverse bias region of the first conductivity type passing through the upper drift layer and the lower drift layer and extending a depletion region when a reverse bias is applied to the substrate and the upper drift layer;
Method of manufacturing a circular LDMOS device comprising a. 16. The method of claim 15, wherein the reverse bias region has the first conductivity type. 16. The method of claim 15, wherein forming the reverse bias region comprises:
forming a high-concentration reverse bias layer on the upper drift layer to isolate the field insulating film into first and second field insulating film patterns; and
Forming a pair of first slits extending downward from the high-concentration reverse bias layer and spaced apart from each other in a horizontal direction:
Method for manufacturing a ring-shaped LDMOS device comprising a. 18. The method of claim 17, wherein the first slits are formed through an ion implantation process.

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