TWI615968B - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

A semiconductor device comprising: a substrate having a first conductivity type, a first well region having a second conductivity type, a first doping region having a first conductivity type, a second well region having a second conductivity type, having a first At least one second doped region of one conductivity type, at least one third doped region having a second conductivity type, and a fourth doped region having a second conductivity type. The first well zone is located in the substrate. The first doped region is located in the first well region. The second well region is located in the first well region and is located between the first doped region and the substrate. At least one second doped region is located in the first doped region. At least one third doped region is located in the first well region of the first side of the first doped region. The fourth doped region is located in the first well region on the second side of the first doped region.

Description

Semiconductor component and method of manufacturing same

The present invention relates to an integrated circuit and a method of fabricating the same, and more particularly to a semiconductor device and a method of fabricating the same.

High-voltage semiconductor components are widely used in the fields of high-voltage AC-DC converters and LED drivers. As environmental awareness rises, high-voltage semiconductor components with high conversion efficiency and low standby power consumption are receiving increasing attention. Therefore, it is common to integrate a HV start-up circuit and a Pulse Width Modulation (PWM) circuit in a single chip to achieve energy saving.

In the prior art, a power resistor is often used as a high voltage starting circuit. However, the power resistor continues to dissipate energy after the pulse width circuit is activated, resulting in increased energy consumption and is not suitable for green energy products. In recent years, it has been changed to a high-voltage junction field-effect transistor (HV JFET) or a depletion mode double-diffused metal Oxide semiconductor (Depletion mode DMOS). Come as a high voltage start circuit. The high voltage junction field effect transistor is turned off after the pulse width circuit is activated, which reduces energy consumption. However, in order to withstand voltages of up to several hundred volts, the high voltage junction field effect transistor has a large size, which limits the design flexibility of the saturation current of the high voltage junction field effect transistor. Therefore, how to provide a high voltage junction field effect transistor that provides an adjustable and wide saturation current to meet different circuit requirements without changing any process conditions is an important issue.

The present invention provides a semiconductor device and a method of fabricating the same that can provide an adjustable and wide saturation current while maintaining the size of the semiconductor device and its breakdown voltage to meet different circuit requirements.

The present invention provides a semiconductor device and a method of fabricating the same that can change a pinch-off voltage without changing any process and without adding an additional mask.

The present invention provides a semiconductor device comprising: a substrate having a first conductivity type, a first well region having a second conductivity type, a first doping region having a first conductivity type, and a second well region having a second conductivity type At least one second doped region having a first conductivity type, at least one third doped region having a second conductivity type, and a fourth doped region having a second conductivity type. The first well zone is located in the substrate. The first doped region is located in the first well region. The second well region is located in the first well region and is located between the first doped region and the substrate. At least one second doped region is located in the first doped region. At least one third doped region is located in the first well region of the first side of the first doped region. The fourth doped region is located in the first well region on the second side of the first doped region.

In an embodiment of the invention, the at least one second doped region is a gate. At least one third doped region is a source. The fourth doped region is a drain. The gate and source surround the bungee.

In an embodiment of the invention, the semiconductor device further includes at least one channel located in the first well region and the second well region below the first doped region, and electrically connected to the source and the drain.

In an embodiment of the invention, the at least one second doped region includes a plurality of gates. The at least one third doped region includes a plurality of sources. The fourth doped region is a drain. The gates correspond to the source and surround the drain.

In an embodiment of the invention, the gate and the source are symmetrically distributed with a center of the circle.

In an embodiment of the invention, the gate and the source are asymmetrically distributed with a center of the circle.

In an embodiment of the invention, the semiconductor device further includes a plurality of channels respectively located in the first well region and the second well region below the first doped region, and electrically connected to the source and the drain.

In an embodiment of the invention, the semiconductor device further includes at least one body region having a first conductivity type between adjacent two sources.

In an embodiment of the invention, the doping concentration of the second well region is lower than the doping concentration of the first well region.

In an embodiment of the invention, the second well region has a width of between 0.5 μm and 5 μm.

In an embodiment of the invention, the first doped region comprises a heavily doped region, a field region, a well region, or a combination thereof.

In an embodiment of the invention, the first doped region does not directly contact the substrate.

In an embodiment of the invention, the semiconductor device further includes: an isolation structure and a conductor structure. The isolation structure is located on the first well region on the second side of the first doped region. The conductor structure is located on the first well region and extends to cover a portion of the isolation structure.

In an embodiment of the invention, the semiconductor device further includes: a top doped region having a first conductivity type and a lightly doped region having a second conductivity type. The top doped region is located in the first well region below the isolation structure. The lightly doped region is located between the isolation structure and the top doped region.

In an embodiment of the invention, the shape of the semiconductor element includes a circle, an ellipse, and an octagon or a combination thereof.

The present invention provides a method of manufacturing a semiconductor device, the steps of which are as follows. A substrate having a first conductivity type is provided. A first well region having a second conductivity type is formed in the substrate. A first doped region having a first conductivity type is formed in the first well region. A second well region having a second conductivity type is formed in the first well region such that the second well region is located between the first doped region and the substrate. Forming at least one second doped region having a first conductivity type in the first doped region. Forming at least one third doped region having a second conductivity type in the first well region on the first side of the first doped region. A fourth doped region having a second conductivity type is formed in the first well region on the second side of the first doping region.

In an embodiment of the invention, the at least one second doped region includes a plurality of gates. The at least one third doped region includes a plurality of sources. The fourth doped region is a drain. The gates correspond to the source and surround the drain.

In an embodiment of the invention, the method of manufacturing the semiconductor device further includes the following steps. A plurality of channels are formed in the first well region and the second well region below the first doped region. The above channels are electrically connected to the source and the drain, respectively. At least one body region is formed between two adjacent sources.

In an embodiment of the invention, the step of forming the second well region comprises the following steps. A patterned mask is formed on the substrate. A patterned mask exposes the top surface of the first well zone. An ion implantation process is performed to form a first well region in the substrate. The first well zone has a first portion and a second portion. The first part is separated from the second part by a distance. A thermal annealing process is performed to thermally diffuse ions implanted in the first portion and the second portion of the first well region to a region between the first portion and the second portion to form a second well region.

In an embodiment of the invention, the doping concentration of the second well region is lower than the doping concentration of the first well region.

Based on the above, the present invention may surround the first doped region (which may be, for example, a drain) by a plurality of third doped regions (which may be, for example, sources) or a plurality of second doped regions (which may be, for example, gates). In order to adjust the saturation current. Additionally, the present invention can vary the pinch voltage by controlling the doping concentration or width of the second well region. As such, the present invention can adjust the saturation current and the pinch-off voltage to meet the needs of customization while maintaining the size of the semiconductor component (which can be, for example, an HV JFET) and its breakdown voltage. In addition, the present invention can also be used to adjust the saturation current and the clamping voltage without changing any process without adding an additional mask.

The above described features and advantages of the invention will be apparent from the following description.

In the following embodiments, when the first conductivity type is N type, the second conductivity type is P type; when the first conductivity type is P type, and the second conductivity type is N type. The P-type doping is, for example, boron; the N-type doping is, for example, phosphorus or arsenic. In the present embodiment, the first conductivity type is a P type, and the second conductivity type is an N type. However, the present invention is not limited thereto. In addition, the same or similar component symbols represent the same or similar components.

1 is a top plan view of a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1 , the present embodiment provides a semiconductor device 100 including: a substrate 102 having a first conductivity type, a first well region 104 having a second conductivity type, and a first doping region 108 having a first conductivity type. a second well region 106 having a second conductivity type, a second doping region 110 having a first conductivity type, a third doping region 112 having a second conductivity type, and a fourth doping region 114 having a second conductivity type And a top doping region 119 having a first conductivity type. In one embodiment, semiconductor component 100 can be, for example, a high voltage junction field effect transistor (HV JFET) that can withstand voltages from 100 V to 800 V and is used as a high voltage startup circuit. Although the semiconductor device 100 illustrated in FIG. 1 is circular, the invention is not limited thereto. In other embodiments, the shape of the semiconductor component 100 can be elliptical, octagonal, or a combination thereof.

In an embodiment, the substrate 102 can be, for example, a P-type semiconductor substrate, such as a P-type substrate. The material of the semiconductor substrate is, for example, at least one material selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. Substrate 102 can also be, for example, an epitaxial layer (EPI), a non-epitaxial layer (non-EPI), an insulating layer overlying (SOI) substrate, or a combination thereof.

The first well region 104 is located in the substrate 102. As shown in the enlarged view of FIG. 1, the first well region 104 can include a first portion 104a and a plurality of second portions 104b. The shape of the first portion 104a can be, for example, gear-like. In detail, the first portion 104a has a plurality of protrusions which are respectively disposed on a perimeter of a circular body portion. The shape of the second portion 104b can be, for example, curved. The second portion 104b corresponds to the protrusion of the first portion 104a, respectively. Each of the second portions 104b is spaced from the projection of the corresponding first portion 104a by a distance. In one embodiment, each of the second portions 104b sandwiches a second well region 106 with a projection of the corresponding first portion 104a.

The first doped region 108 is located in the first well region 104. In detail, a portion of the first doped region 108 overlaps the first portion 104a of the first well region 104. Another portion of the first doped region 108 overlaps the second well region 106. The first doped region 108 has an opposing first side S1 (which may be, for example, the outer side) and a second side S2 (which may be, for example, the inner side).

The second well region 106 is located between the first portion 104a and the second portion 104b of the first well region 104. The second doped region 110 is located in the first doped region 108. In an embodiment, the first doped region 108 completely encapsulates the second doped region 110. The third doped region 112 is located in the second portion 104b of the first well region 104 of the first side S1 of the first doped region 108. In an embodiment, the second portion 104b of the first well region 104 completely encapsulates the third doped region 112. The fourth doped region 114 is located in the first portion 104a of the first well region 104 of the second side S2 of the first doped region 108. In an embodiment, the first portion 104a of the first well region 104 completely encapsulates the fourth doped region 114.

The top doped region 119 is located in the first portion 104a of the first well region 104. In an embodiment, the top doped region 119 can be, for example, a plurality of strip doped regions. The plurality of strip doped regions are radially outwardly distributed around the fourth doping region 114 and surround the fourth doping region 114. The strip doped regions may have the same pitch or different pitches.

In an embodiment, the second doping region 110 can be, for example, a doped region or a plurality of doped regions. The third doping region 112 can be, for example, a doped region or a plurality of doped regions. The semiconductor device 100 further includes a body region 116 having a first conductivity type between adjacent two second doping regions 110 (or third doping regions 112). When the second doping region 110 and the third doping region 112 are, for example, a plurality of doping regions, as shown in FIG. 1 , the second doping regions 110 (eg, gates) respectively correspond to the third doping regions 112 ( For example, the source is included, and the second doping region 110 and the third doping region 112 both surround the fourth doping region 114 (eg, a drain). In an embodiment, the second doping region 110 and the third doping region 112 are symmetrically distributed with the fourth doping region 114 as a center. However, the present invention is not limited thereto. In other embodiments, the second doping region 110 and the third doping region 112 may also be asymmetrically distributed at the center of the fourth doping region 114 (as shown in FIG. 3E).

Although eight second doped regions 110, eight third doped regions 112, and eight body regions 116 are illustrated in FIG. However, the present invention is not limited thereto. In other embodiments, the number of the second doping region 110, the third doping region 112, and the body region 116 can be adjusted as needed (as shown in FIGS. 3A to 3D). It is worth mentioning that the present embodiment can adjust the saturation current by changing the number of the second doping region 110 and the third doping region 112 to meet the customization requirements. For example, when the number of the second doping region 110 and the third doping region 112 is increased, and the area of the third doping region 112 corresponding to the fourth doping region 114 is also increased, which makes the semiconductor device 100 The drain current or saturation current increases. On the contrary, when the path or channel of the fourth doping region 114 to the third doping region 112 is decreased, the gate current or saturation current of the semiconductor element 100 is also lowered. Therefore, the present embodiment can adjust or change the gate current or saturation current of the semiconductor device 100 while maintaining the size or breakdown voltage of the semiconductor device 100 to meet the different needs of the customer.

Fig. 2A is a schematic cross-sectional view taken along line A-A' of Fig. 1; Fig. 2B is a schematic cross-sectional view taken along line C-C' of Fig. 1.

Referring to FIG. 1 , FIG. 2A and FIG. 2B , the semiconductor device 100 of the present embodiment further includes a channel 130 located in the first well region 104 and the second well region 106 below the first doping region 108 . In particular, the channel 130 can extend along the bottom surface of the first doped region 108. As shown in FIG. 2A, the first well region 104, the second well region 106, and the channel 130 are located between the first doped region 108 and the substrate 102 such that the first doped region 108 does not directly contact the substrate 102. When the high voltage startup circuit is turned on, the channel 130 can allow the drain current to flow from the fourth doped region 114 (eg, drain D) to the third doped region 112 (eg, source S). In other words, the channel 130 can be electrically connected to the source S and the drain D. Alternatively, a gate voltage can be applied to the second doped region 110 (eg, gate G) and a body voltage applied to the body region 116 (eg, body B) such that between the first doped region 108 and the substrate 102 A pinch channel (not shown) is formed in the second well region 106 to pinch off the channel 130, thereby turning off the high voltage starting circuit. In an embodiment, the pinch channel in the second well region 106 can extend from the first doped region 108 to the substrate 102.

It is worth mentioning that the doping concentration of the second well region 106 may be smaller than the doping concentration of the first well region 104. Therefore, the pinch channel is easily generated in the second well region 106 when the high voltage starting circuit is turned off. In addition, the present embodiment can change the clamping voltage by controlling the doping concentration or width W of the second well region 106. For example, as the doping concentration of the second well region 106 is greater or the width W is wider, the clamping voltage is greater. Conversely, as the doping concentration of the second well region 106 is smaller or the width W is narrower, the pinch voltage is smaller. Therefore, the present embodiment can adjust or change the clamping voltage of the semiconductor device 100 without changing any process conditions and without adding an additional mask to meet the different needs of the customer.

In one embodiment, the second well region 106 can be formed by, for example, disposing a patterned mask (not shown) on the substrate 102 when the first well region 104 is formed. The patterned mask exposes the top surface of the first well region 104. Thereafter, an ion implantation process is performed to form the first well region 104 in the substrate 102. At this time, the first portion 104a of the first well region 104 is spaced apart from the second portion 104b by a distance. In an embodiment, the distance may be, for example, the width W of the second well region 106, which may be between 0.5 μm and 5 μm. Next, a thermal annealing process is performed to thermally diffuse ions implanted by the first portion 104a and the second portion 104b of the first well region 104 into the region of the second well region 106. In an alternate embodiment, a second well region 106 having a lighter doping concentration may be formed between the first portion 104a and the second portion 104b of the first well region 104 using a lithography and ion implantation process.

In an embodiment, the first well region 104 includes an epitaxial layer or a non-epitaxial layer. The non-epitaxial layer can be, for example, a well, a drift layer, a buffer layer, a deep well, a doped layer, or a combination thereof. In the present embodiment, the first well region 104 may be an N-type deep well region, and the implanted dopant may be, for example, phosphorus or arsenic, and the doping concentration may be, for example, 1 ́10 ¹³ /cm ³ to 5 ́. 10 ¹⁵ /cm ³ . The doping concentration of the second well region 106 may be, for example, 1 ́10 ¹³ /cm ³ to 5 ^{́10 15} /cm ³ .

In an embodiment, the first doped region 108 can be, for example, a heavily doped region, a field region, a well region, or a combination thereof. The method of forming the first doping region 108 may be, for example, performing a lithography and ion implantation process, and the implanted dopant may be, for example, boron, and the doping concentration thereof may be, for example, 1 ^{́10 15} /cm ³ to 5 ́. 10 ¹⁷ /cm ³ .

In addition, the semiconductor device 100 of the present embodiment further includes isolation structures 124, 126, 128, a conductor structure 120, a top doping region 119 having a first conductivity type, and a lightly doped region 118 having a second conductivity type. As shown in FIG. 2A, isolation structure 124 is located on first portion 104a of first well region 104 of second side S2 of first doped region 108. The isolation structure 126 is located on the substrate 102 between the second doped region 110 and the third doped region 112. As shown in FIG. 2B, isolation structure 128 is located on substrate 102 between second doped region 110 and body region 116. The material of the isolation structure 124, 126, 128 is, for example, doped or undoped yttrium oxide, low stress tantalum nitride, ytterbium oxynitride or a combination thereof, and the formation method thereof may be, for example, local area thermal oxidation (LOCOS), shallow Ditch isolation method or deep trench isolation method. In an embodiment, the isolation structures 124, 126, 128 may be, for example, a field oxide structure (FOX), a shallow trench isolation structure (STI), and a deep trench isolation structure (DTI), or a combination thereof.

The conductor structure 120 is located on the first portion 104a of the first well region 104 and extends over a portion of the isolation structure 124. In detail, the conductor structure 120 has a dielectric layer 122 between the first portion 104a of the first well region 104 and the conductor structure 120 and the first doped region 108. In an embodiment, the conductor structure 120 can be used as a field plate. The field plate can uniform the electric field distribution within the semiconductor component 100 to increase the breakdown voltage of the semiconductor component 100. In an embodiment, the material of the conductor structure 120 comprises polysilicon. The method of forming the conductor structure 120 may be a chemical vapor deposition method. The material of the dielectric layer 122 includes ruthenium oxide, which may be formed by chemical vapor deposition.

The top doped region 119 is located in the first portion 104a of the first well region 104 below the isolation structure 124. The top doping region 119 has the effect of reducing the surface electric field (RESURF), thereby increasing the breakdown voltage of the semiconductor device 100. In an embodiment, the doping implanted in the top doping region 119 may be, for example, boron, and the doping concentration may be, for example, 1 ́10 ¹⁶ /cm ³ to 5 ^{́10 17} /cm ³ . The lightly doped region 118 is between the isolation structure 124 and the top doped region 119. The lightly doped region 118 can be used as another current path to reduce the on-resistance of the semiconductor device 100. In one embodiment, the dopant implanted in the lightly doped region 118 can be, for example, phosphorous or arsenic, and the doping concentration can be, for example, from 1 ́10 ¹⁶ /cm ³ to 5 ^{́10 17} /cm ³ . In an embodiment, a top doped region 119 and a lightly doped region 118 are selectively formed. In other words, a semiconductor element having no top doped region 119 and a lightly doped region 118 or a semiconductor element having only one of the top doped region 119 and the lightly doped region 118 is also within the scope of the present invention.

In an embodiment, the second doping region 110, the third doping region 112, the fourth doping region 114, and the body region 116 may be formed by, for example, performing a lithography and ion implantation process. The dopant implanted in the second doped region 110 and the body region 116 can be, for example, boron. The doping concentration of the second doping region 110 may be, for example, 1 ́10 ¹⁸ /cm ³ to 5 ^{́10 19} /cm ³ . The doping concentration of the body region 116 may be, for example, 1 ́10 ¹⁸ /cm ³ to 5 ^{́10 19} /cm ³ . The dopant implanted in the third doping region 112 and the fourth doping region 114 may be, for example, phosphorus or arsenic. The doping concentration of the third doping region 112 may be, for example, 1 ́10 ¹⁸ /cm ³ to 5 ^{́10 19} /cm ³ . The doping concentration of the fourth doping region 114 may be, for example, 1 ́10 ¹⁸ /cm ³ to 5 ^{́10 19} /cm ³ .

In an alternative embodiment, another conductor structure (not shown) may be simultaneously formed to cover a region other than the third doping region 112 (eg, a region covering the body region 116) when the conductor structure 120 is formed. In other words, the top surface of the third doped region 112 is exposed to the conductor structure. Therefore, the conductor structure can be used as a mask to perform the ion implantation process of the third doping region 112.

The description will be made below for the different number and different configurations of the third doped region 112 and the body region 116.

Fig. 3A is a top plan view showing a semiconductor device according to a first embodiment of the present invention. Fig. 3B is a top plan view showing a semiconductor device according to a second embodiment of the present invention. Fig. 3C is a top plan view showing a semiconductor device according to a third embodiment of the present invention. Fig. 3D is a top plan view showing a semiconductor device according to a fourth embodiment of the present invention. Fig. 3E is a top plan view showing a semiconductor device according to a fifth embodiment of the present invention. For the sake of clarity, FIGS. 3A to 3E only indicate the third doping region 112, the fourth doping region 114, and the body region 116, and other components are similar to FIG. 1, and thus will not be described again.

Referring to FIG. 3A, the semiconductor device 100a of the first embodiment has two third doping regions 112 and eight body regions 116. The two third doping regions 112 are symmetrically distributed with the fourth doping region 114 as a center. The eight body regions 116 are evenly distributed between the two third doping regions 112. Specifically, the semiconductor device 100a of the first embodiment has two channels extending from the two third doping regions 112 (eg, source) to the fourth doping region 114 (eg, a drain).

Referring to FIG. 3B, the semiconductor device 100b of the second embodiment is similar to the semiconductor device 100a of the first embodiment. The difference between the above two is that the semiconductor device 100b of the second embodiment has four third doping regions 112. The four third doping regions 112 are symmetrically distributed with the fourth doping region 114 as a center. Specifically, the semiconductor device 100b of the second embodiment has four channels extending from the four third doping regions 112 (eg, source) to the fourth doping region 114 (eg, a drain).

Referring to FIG. 3C, the semiconductor device 100c of the third embodiment is similar to the semiconductor device 100a of the first embodiment. The difference between the above two is that the semiconductor device 100c of the third embodiment has six third doping regions 112. The six third doping regions 112 are symmetrically distributed with the fourth doping region 114 as a center. Specifically, the semiconductor device 100c of the third embodiment has six channels extending from the six third doping regions 112 (eg, source) to the fourth doping region 114 (eg, a drain).

Referring to FIG. 3D, the semiconductor device 100d of the fourth embodiment is similar to the semiconductor device 100a of the first embodiment. The difference between the above two is that the semiconductor device 100d of the fourth embodiment has eight third doping regions 112. The eight third doping regions 112 are symmetrically distributed with the fourth doping region 114 as a center. Specifically, the semiconductor device 100d of the fourth embodiment has eight channels extending from the eight third doping regions 112 (eg, source) to the fourth doping region 114 (eg, a drain).

Referring to FIG. 3E, the semiconductor device 100e of the fifth embodiment is similar to the semiconductor device 100b of the second embodiment. The difference between the two is that the four third doping regions 112 of the semiconductor device 100e of the embodiment of the fifth embodiment are asymmetrically distributed with the fourth doping region 114 as a center. The semiconductor device 100e of the fifth embodiment still has four channels extending from the four third doping regions 112 (eg, source) to the fourth doping region 114 (eg, a drain).

In summary, the present invention may surround the first doped region by a plurality of third doped regions (which may be, for example, sources) or a plurality of second doped regions (which may be, for example, gates) (which may be, for example, germanium) Pole), thereby adjusting the bucker current or saturation current. Additionally, the present invention can vary the pinch voltage by controlling the doping concentration or width of the second well region. As such, the present invention can adjust the saturation current and the pinch-off voltage to meet the needs of customization while maintaining the size of the semiconductor component (which can be, for example, an HV JFET) and its breakdown voltage. In addition, the present invention can also be used to adjust the saturation current and the clamping voltage without changing any process without adding an additional mask.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100, 100a, 100b, 100c, 100d, 100e‧‧‧ semiconductor components
102‧‧‧Base
104‧‧‧First Well Area
104a‧‧‧Part 1
104b‧‧‧Part II
106‧‧‧Second well area
108‧‧‧First doped area
110‧‧‧Second doped area
112‧‧‧ Third doped area
114‧‧‧fourth doping zone
116‧‧‧ Main area
118‧‧‧lightly doped area
119‧‧‧top doped area
120‧‧‧Conductor structure
122‧‧‧ dielectric layer
124, 126, 128‧‧‧ isolation structure
130‧‧‧ channel
B‧‧‧ Subject
D‧‧‧汲
G‧‧‧ gate
S‧‧‧ source
S1‧‧‧ first side
S2‧‧‧ second side
W‧‧‧Width

1 is a top plan view of a semiconductor device in accordance with an embodiment of the present invention. Fig. 2A is a schematic cross-sectional view taken along line A-A' of Fig. 1; Fig. 2B is a schematic cross-sectional view taken along line C-C' of Fig. 1. Fig. 3A is a top plan view showing a semiconductor device according to a first embodiment of the present invention. Fig. 3B is a top plan view showing a semiconductor device according to a second embodiment of the present invention. Fig. 3C is a top plan view showing a semiconductor device according to a third embodiment of the present invention. Fig. 3D is a top plan view showing a semiconductor device according to a fourth embodiment of the present invention. Fig. 3E is a top plan view showing a semiconductor device according to a fifth embodiment of the present invention.

Claims (10)

A semiconductor device comprising: a substrate having a first conductivity type; a first well region having a second conductivity type, located in the substrate; a first doped region having the first conductivity type, located in the a second well region having the second conductivity type, located in the first well region and located between the first doped region and the substrate; having at least one of the first conductivity type a second doped region located in the first doped region; at least one third doped region having the second conductivity type, located in the first well region of a first side of the first doped region; A fourth doped region having the second conductivity type is located in the first well region on a second side of the first doped region. The semiconductor device of claim 1, wherein the at least one second doped region is a gate, the at least one third doped region is a source, and the fourth doped region is a drain The gate and the source surround the drain. The semiconductor device of claim 2, further comprising at least one channel in the first well region and the second well region below the first doped region, and electrically connecting the source and the anode pole. The semiconductor device of claim 1, wherein the at least one second doped region comprises a plurality of gates, the at least one third doped region comprises a plurality of sources, and the fourth doped region is a The bungee poles respectively correspond to the source and surround the drain, and the gates and the sources are symmetrically distributed in a center of the circle. The semiconductor device of claim 4, further comprising at least one body region having the first conductivity type, located between adjacent two sources. The semiconductor device of claim 1, wherein the second well region has a width of between 0.5 μm and 5 μm. A method of manufacturing a semiconductor device, comprising: providing a substrate having a first conductivity type; forming a first well region having a second conductivity type in the substrate; forming the first well region in the first well region a first doped region of the conductivity type; forming a second well region having the second conductivity type in the first well region such that the second well region is located between the first doped region and the substrate; Forming at least one second doping region having the first conductivity type in the first doping region; forming the second conductivity type in the first well region of a first side of the first doping region At least one third doped region; and a fourth doped region having the second conductivity type formed in the first well region of a second side of the first doped region. The method of fabricating a semiconductor device according to claim 7, wherein the at least one second doped region comprises a plurality of gates, the at least one third doped region comprises a plurality of sources, the fourth doping The area is a drain, and the gates respectively correspond to the source and surround the drain. The manufacturing method of the semiconductor device of claim 8, further comprising: forming a plurality of channels in the first well region and the second well region below the first doping region, wherein the channels are respectively Electrically connecting the source and the drain; forming at least one body region between adjacent two sources. The method of manufacturing a semiconductor device according to claim 7, wherein the forming of the second well region comprises: forming a patterned mask on the substrate, the patterned mask exposing the first a top surface of the well region; performing an ion implantation process to form the first well region in the substrate, wherein the first well region has a first portion and a second portion, the first portion being separated from the second portion a distance; and performing a thermal annealing process to thermally diffuse the first portion and the second portion implanted ions of the first well region to a region between the first portion and the second portion to form the Second well area.