TWI443835B - Semiconductor structure and method for manufacturing and manipulating the same - Google Patents

Description

Semiconductor structure, manufacturing method and operating method thereof

The present invention relates to a semiconductor structure, a method of fabricating the same, and a method of fabricating the same, and more particularly to a semiconductor structure incorporating an active device and a polysilicon resistor, and a method of fabricating the same.

In recent years, the green energy industry has attracted attention, and the green energy industry needs high conversion efficiency and low standby power consumption. The high press range has been widely used in Power Management (PM) Integrated Circuits (ICs) and Switch Mode Power Supplies (SMPS). The SMPS has a start-up circuit with a wide range of high input voltages (eg, 40 volts (V) to 750V).

The switching mode power IC needs to be combined with a startup circuit and a Pulse Width Modulation (PWM) circuit. In general, the startup circuit used in the high voltage device uses a resistor to provide a charging current to the capacitor until the voltage on the capacitor reaches the startup voltage of the PWM circuit, and the startup circuit stops functioning. However, the conventional high-voltage starting circuit uses a power resistor (Power Resistor), so that after the starting circuit stops, the power is still continuously consumed by the power resistor, and the power saving effect cannot be achieved.

The present invention relates to a semiconductor structure, a method of fabricating the same, and a method of fabricating the same, which combines an active device and a polysilicon resistor to save component volume and to be manufactured without increasing process complexity.

According to a first aspect of the invention, a semiconductor structure is provided comprising a substrate, an active device, a field oxide layer and a polysilicon resistor. The active device is formed in a surface region of the substrate, the active device has a first doped region, a second doped region and a third doped region, and the second doped region is disposed on the first doped region, a doped region is interposed between the second and third doped regions, the first doped region has a first conductivity type, and the third doped region has a second conductivity type, a first conductivity type and a second conductivity type different. A field oxide layer is disposed on a portion of the third doped region. The polysilicon resistor is disposed on the field oxide layer and electrically connected to the third doping region.

According to a second aspect of the present invention, a method of fabricating a semiconductor structure is provided, the method comprising the following steps. A substrate is provided. Forming an active component in a surface region of the substrate, the active component has a first doped region, a second doped region, and a third doped region, and the second doped region is disposed on the first doped region The first doped region is between the second and third doped regions, the first doped region has a first conductivity type, and the third doped region has a second conductivity type, the first conductivity type and the second conductivity type Different types. A field oxide layer is formed on a portion of the third doped region. A polysilicon resistor is formed on the field oxide layer and electrically connected to the third doped region.

According to a third aspect of the present invention, a method for operating a semiconductor structure is provided. The semiconductor structure includes a substrate, an active device, a field oxide layer, and a polysilicon resistor. The active device has a gate, a drain, and a source. The oxide layer is disposed on a portion of the active device, the polysilicon resistor is disposed on a portion of the field oxide layer, and the polysilicon resistor includes a plurality of electrical contacts, and the method of operation includes the following steps. A gate voltage is applied to the gate, a drain voltage is applied to the drain, and a source voltage is applied to the source. The source is electrically connected to an electrical contact. The other electrical contact is coupled to a reference voltage. The other electrical contact is coupled to a ground voltage, and a potential difference is formed between the other electrical contact and the other electrical contact.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

First embodiment

1 is a schematic view of a semiconductor structure in accordance with an embodiment of the present invention. As shown in FIG. 1, the semiconductor structure 10 includes a substrate 100, and an active device 103 is formed in a surface region of the substrate 100. The substrate 100 is, for example, a substrate and has a first conductivity type, for example, a P-type conductivity type. The active device 103 has a doped region 106a, a doped region 106b, a doped region 107, a doped region 108a, a doped region 108b, a doped region 110, a doped region 112, a doped region 114, a doped region 116, and a doped region The impurity region 118 and the doping region 120. The doped region 116 is disposed on the doped region 106a, and the doped region 106a is interposed between the doped region 107 and the doped region 116.

The doped region 106a, the doped region 106b, the doped region 112, the doped region 116, and the doped region 120 have a first conductivity type, a doped region 107, a doped region 108a, a doped region 108b, and a doped region 110 The doped region 114 and the doped region 118 have a second conductivity type, and the first conductivity type is different from the second conductivity type. For example, the doped region of the first conductivity type is, for example, a boron-doped P-type conductivity type ion, and the doped region of the second conductivity type is, for example, doped with Arsenic or Phosphorus. Type conductivity type ions.

In one embodiment, the doping region 114, the doping region 116, the doping region 118, and the doping region 120 are, for example, heavily doped regions having a relatively high concentration of ion doping, doped regions 106a, doped regions 106b The doped region 107 and the doped region 108a and the doped region 108b are, for example, lightly doped regions having a lower concentration of ion doping. In one embodiment, the doped region 106a and the doped region 106b have, for example, a well region of a first conductivity type, and the doped region 107 is, for example, a high voltage (HV) well region, a doped region 108a, and a doped region. 108b is, for example, Deep Well. The doped region 108a and the doped region 108b are disposed adjacent to the side of the doped region 106a, for example, respectively disposed on the bottom side and the adjacent side of the doped region 106a, and the doped region 108a and the doped region 108b have a second conductivity type. The spacing and spacing between the doped regions 108b are related to a clamping voltage of the active device 103, and the spacing between the two adjacent doping regions 108a and between the doping region 108b and the doping region 108a. The spacing is related to a clamping voltage of the active component 103.

The doped region 110 is formed in the doped region 107, for example, as a first top doped region, and the doped region 112 is formed, for example, as a second top doped region. The doped region 110 is opposite to the conductive type of the doped region 112. In one embodiment, the doped region 110 has a second conductivity type and the doped region 112 has a first conductivity type. In another embodiment, the doped region 110 has a first conductivity type and the doped region 112 has a second conductivity type.

In one embodiment, the doping region 114 of FIG. 1 is, for example, a drain region, the doping region 116 is, for example, a gate, and the doping region 118 is, for example, a source (Source Region). The doped region 120 is, for example, a Bulk Region. The Field Oxide (FOX) structure 104 includes a field oxide layer 104a, a field oxide layer 104b, and a field oxide layer 104c. The field oxide layer 104a and the field oxide layer 104b are formed, for example, and disposed on a portion of the doped region 107. The polysilicon resistor 102 is formed, for example, and disposed on the field oxide layer 104a and the field oxide layer 104b.

The polysilicon resistor 102 includes a plurality of segments, which may correspond to a plurality of electrical contacts, such as electrical contacts 102a, electrical contacts 102b, and electrical contacts 102c. The electrical contacts 102a are used. The electrical contact 102b is electrically connected to an internal circuit (having a reference voltage), and the electrical contact 102c is electrically connected to a ground. There is a voltage dividing resistor between the electrical contact 102b and the electrical contact 102c. Therefore, when operating the semiconductor structure 10, a gate voltage can be applied to the gate, a drain voltage is applied to the drain, and a source voltage is applied to the source. Moreover, the coupling of the electrical contact 102b and a reference voltage, coupled to the other electrical contact 102c and a ground voltage, due to the presence of a voltage dividing resistor between the electrical contact 102b and the electrical contact 102c, There is a potential difference between the electrical contacts 102b and the electrical contacts 102c.

In one embodiment, the active component 103 is, for example, a high voltage component. Further, the active device 103 is, for example, an N-type junction field effect transistor (NJFET). Of course, the active component 103 can also be other possible semiconductor components without limitation. In one embodiment, the active device 103 can utilize a local Oxidation of Silicon (LOCOS), an epitaxial germanium (EPI) process, a non-epi process (non-EPI) process, or a field oxide (FOX) process. , Shallow Trench Isolation (STI), Deep Trench Isolation (DTI) process and / or Silicon-on-Insulator (SOI) process. The contour of the active element 103 may be a Circle Structure, an Ellipse Structure or an Octagon Structure, or other possible shapes. In one embodiment, a buried layer of a second conductivity type (eg, an N-type buried layer) is used as a channel for the NJFET. In an embodiment, the N-type channel can be formed by an N-type well, an N-type drift region, an N-type buffer layer, and/or an N-type deep well. The clamping voltage of the NJFET can be modulated by the spacing of the N-type buried layers.

The semiconductor structure is combined with the polysilicon resistor 102 and the active device 103. For example, the polysilicon resistor 102 is embedded in the field oxide layer (FOX) of the doped layer 107 (for example, a drift region), which not only saves volume, but also uses a high voltage process. Manufactured without the need for additional masks and processes. In addition, the embedded polysilicon resistor 102 can be a high resistance resistor and can be applied to a Voltage Division Circuit and a Voltage Reduce Circuit.

Fig. 2A is a plan view showing an embodiment of the semiconductor structure as shown in Fig. 1. Referring to FIG. 2A, the polysilicon resistor 102-1 is an embodiment of the polysilicon resistor 102 of FIG. 1. The polysilicon resistor 102-1 includes, for example, a plurality of concentric ring structures having different radii of curvature. In other embodiments, the polysilicon resistor 102-1 may also be a plurality of octagonal structures (for example, an octagonal ring structure), a plurality of semi-annular structures, a plurality of elliptical ring structures, or an irregular semicircular structure, without limitation. The method of forming the polysilicon resistor 102-1 is, for example, first forming a polysilicon material layer on the field oxide layer 104 (shown in FIG. 1). The polycrystalline germanium material layer is then patterned to form a plurality of semi-annular structures, a plurality of elliptical ring structures, an irregular semi-circular structure, a plurality of concentric ring structures, or a plurality of octagonal structures.

Referring to FIGS. 1 and 2A simultaneously, the doped region 114 of FIG. 1 corresponds to the region 1022 of FIG. 2A (eg, a drain), and the region 1022 may include a contact, such as a doped region 116. Corresponding to the region 1036 of FIG. 2A (eg, a gate), the doped region 118 corresponds to, for example, the region 1034 of FIG. 2A (eg, source), and the doped region 120 corresponds to, for example, the region of FIG. 2A. 1032 (for example, the base).

In this embodiment, the polysilicon resistor 102-1 may have a plurality of semi-annular structures, an elliptical ring structure, an irregular semicircular structure, a concentric ring structure or an octagonal structure, and is disposed substantially in a center. The polysilicon resistor 102-1 has an open region 1028. The open region 1028 includes a plurality of conductive layers of a metal material or a polysilicon material, thereby connecting the turns to the next turn of the polysilicon resistor 102-1.

The polysilicon resistor 102-1 can be electrically connected by a conductive layer 1024 and a conductive layer 1026. The conductive layer 1024 can be connected to the ground. The conductive layer 1026 can be connected to an internal circuit (for example, having a reference voltage), and the conductive layer 1024. The conductive layer 1026 includes, for example, a metal material, a polysilicon material, or other conductive materials. The polysilicon resistor 102-1 between the conductive layer 1024 and the conductive layer 1026 may be a voltage dividing resistor, and the voltage dividing resistor and the polysilicon resistor 102-1 of the outermost ring other than the voltage dividing resistor may have a proportional relationship. For example, the resistance of the voltage dividing resistor is R, and the resistance of the outermost polysilicon resistor 102-1 other than the voltage dividing resistor is 100R, and the two exhibit a 100-fold proportional relationship.

2B is a top plan view showing another embodiment of the semiconductor structure as shown in FIG. 1. Referring to FIG. 2B, the polysilicon resistor 102-2 is another embodiment of the polysilicon resistor 102 of FIG. The structure, material, shape, forming method and embodiment of the polysilicon resistor 102-2 may be the same as or similar to the respective structures, materials, shapes and embodiments of the polysilicon resistor 102-1, and will not be described here. The difference lies in the polysilicon resistor 102. The region 1022 of -2 (eg, a bungee pole) may include a larger metal field plate that reduces the electric field effect of the drain region.

2C is a plan view showing still another embodiment of the semiconductor structure as shown in FIG. 1. Referring to FIG. 2C, the polysilicon resistor 102-3 is another embodiment of the polysilicon resistor 102 of FIG. As shown in FIG. 2C, the polysilicon resistor 102-3 may include a plurality of half-circle structures having different radii of curvature, the semi-annular structures being centered on the region 1022 (eg, a bungee pole), mirrored or Symmetrically set to piece together a plurality of structures that approximate the ring. The method of forming the polysilicon resistor 102-3 may be the same as the method of forming the polysilicon resistor 102-1 of FIG. 2A, and will not be described again. In the concentric half-rings on the same side of the region 1022, the adjacent two concentric semi-rings are electrically connected by a conductive layer made of a conductive material such as metal or polysilicon.

In this embodiment, in the polysilicon layer structure of each turn of the polysilicon resistor 102-3, the polysilicon layer of the same ring may be equal in voltage. Moreover, the outermost polysilicon layer of the polysilicon resistor 102-3 may be connected to a conductive layer 1024a, the other end of the conductive layer 1024a may be connected to another polysilicon resistor 1020, and the polysilicon resistor 1020 is connected to the ground via the conductive layer 1024b. In this way, the resistance characteristic of the polysilicon resistor 102-3 is more precisely controlled.

In Fig. 2C, the structure of the polysilicon resistor 102-3 includes a plurality of concentric ring structures in which a plurality of semi-annular structures having different radii of curvature are arranged to be substantially center-circumscribed. Of course, in other embodiments, an elliptical ring structure, a concentric ring structure, or an octagonal structure may also be used to surround the crucible, which is not limited.

2D is a plan view showing still another embodiment of the semiconductor structure as shown in FIG. 1. Referring to FIG. 2D, the polysilicon resistor 102-4 is another embodiment of the polysilicon resistor 102 of FIG. As shown in Fig. 2D, the polysilicon resistor 102-4 may include an irregular semicircular structure surrounded by a crucible. This irregular semi-circular structure is formed by an offset every half turn when it is bent, which is more convenient for the layout process. If the 汲 is extremely central, these concentric semi-rings are not mirrored. The potential of each of the polysilicon resistive layers of the irregular semicircular structure formed is not equal. Also, the potential can be changed by adjusting the pitch of the polysilicon resistive layers of each turn. For example, the distance between the polysilicon resistor layers can be extended to prevent the voltage drop of the potential from being too severe, so that the withstand voltage capability of the component is better. In addition, the conductive layer 1024a, the other polysilicon resistor 1020 and the conductive layer 1024b function in the same manner as in FIG. 2C, and are used to more precisely control the characteristics of the polysilicon resistor 102-4, and details are not described herein again.

2E is a plan view showing still another embodiment of the semiconductor structure as shown in FIG. 1. Referring to FIG. 2E, the polysilicon resistor 102-5 is another embodiment of the polysilicon resistor 102 of FIG. As shown in FIG. 2E, the polysilicon resistor 102-5 may include a plurality of concentric ring structures that are bent and surrounded by a region 1022 (eg, a drain). The conductive layer 1024a, the other polysilicon resistor 1020 and the conductive layer 1024b function in the same manner as in FIG. 2C, and are used to more precisely control the characteristics of the polysilicon resistor 102-5, which will not be described herein.

In Fig. 2E, the structure of the polysilicon resistor 102-5 is described by way of an annular concentric ring structure. Of course, in other embodiments, an elliptical ring structure or an octagonal ring structure may be used to surround the crucible, which is not limited.

Second embodiment

3 is a cross-sectional view showing a semiconductor structure in accordance with another embodiment of the present invention. As shown in FIG. 3, the semiconductor structure 20 includes a substrate 200, and an active device 203 is formed in a surface region of the substrate 200. The substrate 200 is, for example, a substrate and has a first conductivity type, for example, a P-type conductivity type. The active device 203 has a doped region 206a, a doped region 206b, a doped region 207, a doped region 208, a doped region 209a, a doped region 209b, a doped region 210, a doped region 212, a doped region 214, and a doped region The impurity region 216, the doping region 218, and the doping region 220. The doped region 216 is disposed on the doped region 206a, and the doped region 206a is interposed between the doped region 207 and the doped region 216.

The doped region 206a, the doped region 206b, the doped region 212, the doped region 216, and the doped region 220 have a first conductivity type, a doped region 207, a doped region 208, a doped region 210, and a doped region 214. The doped region 218 has a second conductivity type, the first conductivity type is different from the second conductivity type, the first conductivity type is, for example, a P-type conductivity type, and the second conductivity type is, for example, an N-type conductivity type.

In one embodiment, the doping region 214, the doping region 216, the doping region 218, and the doping region 220 are, for example, heavily doped regions having a higher concentration of ion doping, doped regions 206a, doped regions 206b. The doped region 207 and the doped region 208 are, for example, lightly doped regions having a lower concentration of ion doping. In one embodiment, the doping region 206a and the doping region 206b are, for example, a high-voltage deep well region having a first conductivity type (for example, a high-voltage P-type deep well region), and the doping region 207 has, for example, a second conductivity type. High pressure well zone (for example, a high pressure N-type well zone). The doped region 208 is disposed adjacent to the side of the doped region 206a, and the doped region 209a and the doped region 209b are disposed, for example, on the bottom side of the doped region 206a. The doped region 209a and the doped region 209b are, for example, a second conductivity type buried layer (NBL). The distance between the doped region 209a and the doped region 209b is related to a clamping voltage of the active device 203. The doped region 210 and the doped region 212 formed in the doped region 207 may be the same as or similar to the doped region 110 and the doped region 112 of FIG. 1 and will not be further described herein.

The Field Oxide (FOX) structure 204 includes a field oxide layer 204a, a field oxide layer 204b, and a field oxide layer 204c. The field oxide layer 204a and the field oxide layer 204b are formed, for example, and disposed on a portion of the doped region 207. The polysilicon resistor 202 is formed, for example, on the field oxide layer 204a and the field oxide layer 204b, and may include different embodiments of the second to second embodiments. The polysilicon resistor 202 includes a plurality of segments, which may correspond to a plurality of electrical contacts, such as electrical contacts 202a, electrical contacts 202b, and electrical contacts 202c, electrical contacts 202a-electric The connection manner of the contact 202c is the same as or similar to that of the electrical contact 102a to the electrical contact 102c of FIG. 1 and will not be described again.

In one embodiment, the active component 203 is, for example, a high voltage component. Further, the active device 203 is, for example, an N-type junction field effect transistor (NJFET), and the active device 203 can be used in the same manner as the active device 103 in FIG. Of course, the active component 203 can also be other possible semiconductor components, and is not limited. In one embodiment, the buried layer 209a of the second conductivity type and the buried layer 209b (for example, an N-type buried layer) are used as the channels of the NJFET. The clamping voltage of the NJFET can be modulated by the spacing of the N-type buried layers.

The semiconductor structure combines the polysilicon resistor 202 with the active device 203, for example, by embedding the polysilicon resistor 202 on the field oxide layer (FOX) of the doped layer 207 (eg, a drift region), which not only saves volume, but also uses a general high voltage. The process can be manufactured without the need for additional masks and processes. In addition, the embedded polysilicon resistor 202 can be a high resistance resistor and can be applied to a Voltage Division Circuit and a Voltage Reduce Circuit.

Third embodiment

4 is a cross-sectional view showing a semiconductor structure in accordance with another embodiment of the present invention. As shown in FIG. 4, the semiconductor structure 30 includes a substrate 300, and an active device 303 is formed in a surface region of the substrate 300. The substrate 300 is, for example, a substrate and has a first conductivity type, for example, a P-type conductivity type. The active device 303 has a doped region 306a, a doped region 306b, a doped region 307, a doped region 310, a doped region 312, a doped region 314, a doped region 318a, a doped region 318b, and a doped region 320. The doped region 318a and the doped region 318b are disposed on the doped region 306a, and the doped region 306a is interposed between the doped region 307 and the doped region 318a and the doped region 318b.

The doped region 306a, the doped region 306b, the doped region 312, the doped region 318b, and the doped region 320 have a first conductivity type, a doped region 307, a doped region 310, a doped region 314, and a doped region 318a There is a second conductivity type, the first conductivity type is different from the second conductivity type, the first conductivity type is, for example, a P-type conductivity type, and the second conductivity type is, for example, an N-type conductivity type.

In one embodiment, the doped region 314, the doped region 318a, the doped region 318b, and the doped region 320 are, for example, heavily doped regions having a higher concentration of ion doping. The doped region 306a, the doped region 306b, and the doped region 307 are, for example, lightly doped regions having a lower concentration of ion doping. In one embodiment, the doped region 306a and the doped region 306b have, for example, a well region of a first conductivity type (eg, a P-type well region), and the doped region 307 is, for example, a high-voltage well region of a second conductivity type ( For example, it is a high pressure N-type well area). The doped region 310 and the doped region 312 formed in the doped region 307 may be the same as or similar to the doped region 110 and the doped region 112 of FIG. 1 and will not be described herein.

The Field Oxide (FOX) structure 304 includes a field oxide layer 304a, a field oxide layer 304b, and a field oxide layer 304c. The field oxide layer 304a, the field oxide layer 304b, and the field oxide layer 304c are formed, for example, and disposed in the doped region 307. Part of it. The polysilicon resistor 302 is formed, for example, on the field oxide layer 304a and the field oxide layer 304b, and may include different embodiments of the second to second embodiments. The polysilicon resistor 302 includes a plurality of segments, which may correspond to a plurality of electrical contacts, such as electrical contacts 302a, electrical contacts 302b, and electrical contacts 302c, electrical contacts 302a-electric The connection manner of the contact 302c is the same as or similar to that of the electrical contact 102a to the electrical contact 102c of FIG. 1 and will not be described again.

In one embodiment, the active component 303 is, for example, a high voltage component. Further, the active device 303 is, for example, an N-type Laterally Diffused Metal Oxide Semiconductor (LDMOS), and the laterally diffused metal oxide semiconductor can be fabricated by, for example, an Ultra High Voltage (UHV) process. The doped region 314 is, for example, a drain, and the gate structure region 316 is a gate region, for example, including a gate layer and a gate oxide layer. The doped region 318a and the doped region 318b are, for example, a source and a base electrically connected. Of course, the active component 303 can also be other possible semiconductor components without limitation.

The semiconductor structure combines the polysilicon resistor 302 with the active device 303, for example, by embedding the polysilicon resistor 302 on the field oxide layer (FOX) of the doped layer 307 (eg, a drift region), which not only saves volume, but also uses a general high voltage. The process can be manufactured without the need for additional masks and processes. In addition, the embedded polysilicon resistor 302 can be a high resistance resistor and can be applied to a Voltage Division Circuit and a Voltage Reduce Circuit.

In summary, the semiconductor structure of the above embodiment of the present invention can be combined with a polysilicon resistor and an active component, and can be applied to a high voltage semiconductor structure, which not only saves the overall volume of the semiconductor structure, but also can be manufactured using a high voltage process without additional Photomask and process. In addition, the polysilicon resistor can be a high resistance resistor and can be applied to a voltage divider circuit and a step-down circuit. The semiconductor structure in some embodiments of the present invention can replace the conventional power resistor to achieve energy saving effect.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

10, 20, 30. . . Semiconductor structure

100, 200, 300. . . Base

102, 202, 302, 102-1, 102-2, 102-3, 102-4, 102-4, 1020. . . Polysilicon resistor

102a, 102b, 102c, 202a, 202b, 202c, 302a, 302b, 302c. . . Electrical contact

103, 203, 303. . . Active component

104, 204, 304. . . Field oxidation structure

104a, 104b, 104c, 204a, 204b, 204c, 304a, 304b, 304c. . . Field oxide layer

106a, 106b, 206a, 206b, 306a, 306b, 107, 207, 307, 108, 108a, 108b, 208, 110, 210, 310, 112, 212, 312, 114, 214, 314, 116, 216, 118, 218, 318a, 318b, 120, 220, 320. . . Doped layer

316. . . Gate structure

1024, 1026. . . Conductive layer

1024a, 1024b. . . Conductive layer

1028. . . Open area

1032, 1034, 1036. . . region

1 is a schematic view of a semiconductor structure in accordance with an embodiment of the present invention.

2A-2E are top views showing different embodiments of the semiconductor structure as shown in FIG. 1.

3 is a schematic view of a semiconductor structure in accordance with another embodiment of the present invention.

4 is a schematic view of a semiconductor structure in accordance with yet another embodiment of the present invention.

10. . . Semiconductor structure

100. . . Base

102. . . Polysilicon resistor

102a, 102b, 102c. . . Electrical contact

103. . . Active component

104. . . Field oxidation structure

104a, 104b, 104c. . . Field oxide layer

106a, 106b, 107, 108, 108a, 108b, 110, 112, 114, 116, 118, 120. . . Doped layer

Claims (10)

A semiconductor structure includes: a substrate; an active device formed in a surface region of the substrate, the active device having a first doped region, a second doped region, and a third doped region, the first a second doped region is disposed on the first doped region, the first doped region is between the second doped region and the third doped region, the first doped region has a first conductivity type, the first doped region The three doped region has a second conductivity type and a drain, the first conductivity type is different from the second conductivity type; a field oxide layer is disposed on a portion of the third doping region; and a polysilicon resistor is disposed The polysilicon resistor includes at least three electrical contacts coupled to the drain, an internal circuit, and a ground, and the polysilicon resistor is electrically connected to the third doped region. The semiconductor structure of claim 1, wherein the first doped region comprises a first lightly doped region having the first conductivity type, and the second doped region is a first heavily doped region Having at least one of the first and second conductivity types, and the third doped region includes a second lightly doped region and a second heavily doped region, and the conductive type of the second lightly doped region And the conductivity type of the second heavily doped region has the second conductivity type. The semiconductor structure of claim 1, wherein the polysilicon resistor has a plurality of semi-annular structures, a plurality of elliptical ring structures, a plurality of irregular semicircular structures, a plurality of concentric ring structures or a plurality An octagonal structure. The semiconductor structure of claim 3, wherein the second heavily doped region is the drain, the semi-annular structures, the elliptical annular structures, the irregular semicircular structures, and the concentric rings. The structure or the octagonal structures are arranged with the crucible extremely centered. The semiconductor structure of claim 4, wherein the semi-annular structures, the elliptical annular structures or the concentric ring structures comprise a plurality of annular structures having different radii of curvature. A method of fabricating a semiconductor structure, comprising: providing a substrate; forming an active device in a surface region of the substrate, the active device having a first doped region, a second doped region, and a third doped region The second doped region is disposed on the first doped region, the first doped region is between the second and third doped regions, and the first doped region has a first conductivity type The third doped region has a second conductivity type and a drain, the first conductivity type being different from the second conductivity type; forming a field oxide layer on a portion of the third doping region; and forming a polysilicon Resisting the field oxide layer and electrically connecting the polysilicon resistor to the third doping region, wherein the polysilicon resistor comprises at least three electrical contacts respectively coupled to the drain, an internal circuit, and a ground end. The method of fabricating a semiconductor structure according to claim 6, wherein the step of forming the polysilicon resistor comprises: forming a polysilicon material layer on the field oxide layer; and patterning the polysilicon material layer to form a plurality of layers a ring structure, a plurality of elliptical ring structures, a plurality of irregular semicircular structures, a plurality of concentric ring structures or a plurality of octagon structures. The method of fabricating a semiconductor structure according to claim 7 , wherein the third doped region comprises a second lightly doped region and a second heavily doped region, wherein the second heavily doped region is a drain, the formation of the polysilicon resistor includes forming the semi-annular structures, the elliptical annular structures, the irregular semicircular structures, the concentric ring structures or the octagonal structures surrounding the crucible Extreme setting. The method of fabricating a semiconductor structure according to claim 8, wherein the forming of the polysilicon resistor comprises forming the semi-annular structures having different radii of curvature, the elliptical ring structures or the concentrics at a center of the crucible. Ring structure. A semiconductor structure operating method, the semiconductor structure comprising a substrate, an active device, a field oxide layer and a polysilicon resistor, the active device having a gate, a drain and a source, the field oxide layer being disposed on the active a portion of the device, the polysilicon resistor is disposed on a portion of the field oxide layer, and the polysilicon resistor includes at least three electrical contacts coupled to the drain, an internal circuit, and a ground terminal, respectively. package And applying a gate voltage to the gate, applying a drain voltage to the drain, and applying a source voltage to the source; electrically connecting the source and one of the electrical contacts a further electrical contact coupled to the electrical contacts and a reference voltage; and another electrical contact coupled to the electrical contacts and the ground, wherein the other electrical There is a potential difference between the sexual contact and the other electrical contact.