TWI662661B - Fan-out semiconductor package - Google Patents

Abstract

A fan-out type semiconductor package includes: a first interconnecting component having a through hole; a semiconductor wafer disposed in the through hole; an encapsulation body encapsulating at least a portion of the first interconnecting component and the semiconductor wafer; a second An interconnecting component disposed on the first interconnecting component and the semiconductor wafer and including a redistribution layer electrically connected to the semiconductor wafer; and a passivation layer disposed on the second interconnecting component and having exposed second interconnects At least part of the opening of the redeployment layer of the component; and a sub-bump metal layer disposed on the passivation layer and filling at least part of the opening. In the metal layer under the bump. The number of conductor layers formed on the surface of the passivation layer is different from the number of conductor layers formed on the exposed redistribution layer and the wall of the opening.

Description

Fan-out semiconductor package [Cross Reference to Related Applications]

This application claims Korean Patent Application No. 10-2016-0070900 filed with the Korean Intellectual Property Office on June 8, 2016 and Korean Patent Application No. 10-2016 with the Korean Intellectual Property Office on August 24, 2016 -0107687, the disclosure of the Korean patent application is incorporated herein by reference in its entirety.

The present invention relates to a semiconductor package, and more particularly, to a fan-out type semiconductor package in which a connection terminal may extend outside a region where a semiconductor wafer is disposed.

Recently, a recent important trend in the development of technology related to semiconductor wafers is to reduce the size of semiconductor wafers. Therefore, in the field of packaging technology, according to a rapid increase in demand for a small semiconductor wafer or the like, a device having a semiconductor package having a compact size and containing a plurality of pins at the same time is required.

One type of packaging technology proposed to meet the technical needs as described above is fan-out packaging. This fan-out package has a compact size (compact size), and may allow multiple pins to be implemented by relocating the connection terminals outside the area where the semiconductor wafer is placed.

Aspects of the present invention can provide a fan-out type semiconductor package capable of ensuring sufficient close adhesion of a metal layer under a bump.

According to an aspect of the present invention, there can be provided a fan-out type semiconductor package in which a metal layer under a bump is formed on a surface of a passivation layer using a laminate to which a conductor layer is attached.

According to an aspect of the present invention, a fan-out type semiconductor package may include: a first interconnection member having a through hole; and a semiconductor wafer disposed in the through hole of the first interconnection member and having an upper portion disposed thereon. An active surface with a connection pad and a non-active surface opposite to the active surface; an encapsulation body that encapsulates at least a portion of the first interconnecting component and the non-active surface of the semiconductor wafer; a second An interconnection member disposed on the first interconnection member and the active surface of the semiconductor wafer and including a redistribution layer electrically connected to the connection pad of the semiconductor wafer; a passivation layer disposed on The second interconnect member has an opening exposing at least a portion of the redistribution layer of the second interconnect member; and a sub-bump metal layer disposed on the passivation layer and filling the opening At least part of it. The first interconnection component includes a redistribution layer electrically connected to the connection pad of the semiconductor wafer, and in the under bump metal layer, the number of conductor layers formed on a surface of the passivation layer. It is different from the number of conductor layers formed on the exposed redistribution layer and the wall of the opening.

100‧‧‧Semiconductor Package

100A‧‧‧fan-out semiconductor package

100B‧‧‧fan-out semiconductor package

100C‧‧‧fan-out semiconductor package

110‧‧‧first interconnecting component

110H‧‧‧through hole

111‧‧‧ Insulation

111a‧‧‧First insulation layer

111b‧‧‧Second insulation layer

111c‧‧‧Third insulation layer

112a‧‧‧First layer

112b‧‧‧ Third layer

112c‧‧‧Second layer

112d‧‧‧Fourth layer

113‧‧‧Interstitial hole

120‧‧‧Semiconductor wafer

121‧‧‧ Ontology

122‧‧‧Connecting pad

123‧‧‧ passivation layer

130‧‧‧ Capsule

131‧‧‧ opening

140‧‧‧second interconnecting component

141a‧‧‧Insulation

141b‧‧‧Insulation

142a‧‧‧heavy cloth layer

142b‧‧‧ Heavy cloth

143a‧‧‧Interstitial hole

143b‧‧‧Interstitial hole

160‧‧‧ metal layer under bump

161‧‧‧Second conductor layer

162‧‧‧Third conductor layer

170‧‧‧connection terminal

200‧‧‧The first laminated film

201‧‧‧ release film

201'‧‧‧ release film

202‧‧‧Passivation layer

202'‧‧‧ passivation layer

202p‧‧‧ chemical reaction group

202’p‧‧‧Chemical Reactive Group

202H‧‧‧Open

300‧‧‧ Laminate

301‧‧‧ carrier film

302‧‧‧release layer

303‧‧‧first conductor layer

303p‧‧‧metal

401‧‧‧ separable membrane

402‧‧‧metal layer

403‧‧‧metal layer

404‧‧‧ dry film

405‧‧‧adhesive film

501‧‧‧ reel

502‧‧‧ Reel

1000‧‧‧ electronic device

1010‧‧‧ Motherboard

1020‧‧‧Chip-related components

1030‧‧‧Network related components

1040‧‧‧Other components

1050‧‧‧ Camera Module

1060‧‧‧antenna

1070‧‧‧ display device

1080‧‧‧ battery

1090‧‧‧Signal cable

1100‧‧‧Smartphone

1101‧‧‧Body

1110‧‧‧ Motherboard

1120‧‧‧Electronic components

1130‧‧‧ Camera Module

2100‧‧‧fan-out semiconductor package

2120‧‧‧Semiconductor wafer

2121‧‧‧ Ontology

2122‧‧‧Connecting pad

2130‧‧‧ Capsule

2140‧‧‧interconnect

2141‧‧‧Insulation

2142‧‧‧ Heavy cloth

2143‧‧‧ via

2150‧‧‧ passivation layer

2160‧‧‧Under bump metal layer

2170‧‧‧Solder Ball

2200‧‧‧fan-in semiconductor package

2220‧‧‧Semiconductor wafer

2221‧‧‧ Ontology

2222‧‧‧Connecting pad

2223‧‧‧ passivation layer

2240‧‧‧interconnect

2241‧‧‧Insulation

2242‧‧‧Wiring pattern

2243‧‧‧Interstitial hole

2243h‧‧‧Interstitial hole

2250‧‧‧ passivation layer

2251‧‧‧ opening

2260‧‧‧Under bump metal layer

2270‧‧‧Solder Ball

2280‧‧‧underfill resin

2290‧‧‧Molding material

2301‧‧‧Plug-in base

2302‧‧‧Plug-in base

2500‧‧‧ Motherboard

Area A‧‧‧

I-I'‧‧‧ line

II-II'‧‧‧line

The above and other aspects, features, and advantages of the present invention will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

FIG. 1 is a schematic block diagram illustrating an example of an electronic device system.

FIG. 2 is a schematic perspective view illustrating an example of an electronic device.

3A and 3B are schematic cross-sectional views illustrating a state of a fan-in type semiconductor package before and after being packaged.

FIG. 4 is a schematic cross-sectional view illustrating a packaging process of a fan-in semiconductor package.

5 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is mounted on a plug-in substrate and finally mounted on a main board of an electronic device.

FIG. 6 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is embedded in a plug-in substrate and finally mounted on a main board of an electronic device.

FIG. 7 is a schematic cross-sectional view illustrating a fan-out type semiconductor package.

FIG. 8 is a schematic cross-sectional view illustrating a case where a fan-out type semiconductor package is mounted on a main board of an electronic device.

FIG. 9 is a schematic cross-sectional view illustrating an example of a fan-out type semiconductor package.

FIG. 10 is a schematic plan view taken along a line II ′ of the fan-out semiconductor package of FIG. 9.

11A and 11B are schematic enlarged views illustrating a region A of the fan-out semiconductor package of FIG. 9.

12A to 12G are schematic diagrams illustrating an example of a process of manufacturing the fan-out type semiconductor package of FIG. 9.

FIG. 13 is a schematic diagram illustrating an example of a manufacturing process for manufacturing a laminate used in FIGS. 12A to 12G.

FIG. 14 is a schematic diagram illustrating self-assembly between a passivation layer and a metal layer.

FIG. 15 is a schematic diagram illustrating a normal curing state of the passivation layer.

FIG. 16 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

FIG. 17 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

Hereinafter, exemplary embodiments in the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the shape, size, and the like of the components may be enlarged or reduced for clarity.

The term "exemplary embodiment" used herein does not refer to the same exemplary embodiment, and the term is provided to emphasize a specific feature or characteristic that is different from a specific feature or characteristic of another exemplary embodiment. However, it is considered that the exemplary embodiments provided herein can be implemented by combining one exemplary embodiment with another exemplary embodiment in whole or in part. For example, an element described in a particular exemplary embodiment may be understood as a description related to another exemplary embodiment even if it is not described in another exemplary embodiment, unless an opposite or contradictory description is provided therein .

The meaning of "connected" from a component in the description to another component includes an indirect connection via a third component and a direct connection between two components. In addition, "electrical connection" means the concept of physical connection and physical disconnection. It can be understood that when the components are referred to by "first" and "second", the components are not limited thereby. The "first" and "second" can be used only for the purpose of distinguishing components from other components, and they do not limit the order or importance of the components. In some cases, a first element may be referred to as a second element Without departing from the scope of the patentable scope set forth herein. Similarly, the second element may also be referred to as the first element.

Herein, the upper part, the lower part, the upper side, the lower side, the upper surface, the lower surface, and the like are determined in the drawings. For example, the first interconnection component is disposed at a level higher than the redistribution layer. However, the scope of patent application is not limited to this. In addition, the vertical direction refers to the above upward and downward directions, and the horizontal direction refers to the directions perpendicular to the above upward and downward directions. In this case, the vertical cross-section refers to a case obtained along a plane in the vertical direction, and an example thereof may be a cross-sectional view illustrated in the drawings. In addition, the horizontal cross section refers to a case obtained along a plane in the horizontal direction, and an example thereof may be a plan view illustrated in the drawings.

The terminology used herein is used only to describe exemplary embodiments and not to limit the present invention. In this case, the singular includes the plural unless the context is interpreted otherwise.

Electronic device

FIG. 1 is a schematic block diagram illustrating an example of an electronic device system.

Referring to FIG. 1, the electronic device 1000 may receive a motherboard 1010 therein. The motherboard 1010 may include chip-related components 1020, network-related components 1030, other components 1040, and the like that are physically or electrically connected thereto. These components may be connected to other components to be described below to form various signal lines 1090.

The chip-related component 1020 may include a memory chip such as a volatile memory (for example, dynamic random access memory (DRAM)), a non-volatile memory (for example, read only memory memory; ROM)), flash memory or the like; application processor chips, such as a central processing unit (e.g., central processing unit (CPU)), Graphics processors (e.g., graphics processing unit (GPU)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, or the like; and logic chips such as analog / digital -to-digital (ADC) converter, application-specific integrated circuit (ASIC), or the like. However, the wafer-related component 1020 is not limited thereto, and may include other types of wafer-related components. In addition, the wafer-related components 1020 may be combined with each other.

The network-related component 1030 may include a protocol such as: wireless fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 series or similar), microwave storage Take global interoperability for microwave access (WiMAX) (IEEE 802.16 series or similar), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high-speed packet Access + (high speed packet access +; HSPA +), high speed downlink packet access + (high speed downlink packet access +; HSDPA +), high speed uplink packet access + (high speed uplink packet access +; HSUPA +) , Enhanced data GSM environment (EDGE), global system for mobile communications (GSM), global positioning system (GPS), general package radio service (general package radio service; GPRS), code division multiplex access (CDMA), time division multiple access (time d ivision multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G agreement, 4G agreement, 5G agreement, and any tasks designated after the above agreement Any other wireless and wired protocols. However, the network-related component 1030 is not limited to this, and may include a variety of other wireless or wired standards or protocols. In addition, along with the wafer-related components 1020 described above, the network-related components 1030 may be combined with each other.

Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC), electromagnetic interference (EMI) filtering Device, multilayer ceramic capacitor (MLCC), or the like. However, the other components 1040 are not limited thereto, and may also include passive components or the like used for various other purposes. In addition, together with the wafer-related component 1020 or the network-related component 1030 described above, other components 1040 may be combined with each other.

Depending on the type of the electronic device 1000, the electronic device 1000 may include other components that may or may not be physically connected or electrically connected to the motherboard 1010. These other components may include, for example, a camera module 1050, an antenna 1060, a display device 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown) ), Compass (not shown), accelerometer (not shown), gyroscope (not shown), speaker (not shown), mass storage unit (e.g. hard drive) (not shown), compact Compact disk (CD) player (not shown), digital versatile disk (DVD) player (not shown), or the like. However, these other components are not limited thereto, but may include other components used for various purposes depending on the type of the electronic device 1000 or the like.

The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a mini notebook PC, a television, Video games Phones, smart watches, car components or the like. However, the electronic device 1000 is not limited thereto, and may be any other electronic device that processes data.

FIG. 2 is a schematic perspective view illustrating an example of an electronic device.

Referring to FIG. 2, a semiconductor package may be used in various electronic devices 1000 as described above for various purposes. For example, the motherboard 1110 can be housed in the body 1101 of the smart phone 1100, and various electronic components 1120 can be physically or electrically connected to the motherboard 1110. In addition, other components (such as the camera module 1130) that may or may not be physically or electrically connected to the motherboard 1110 may be housed in the body 1101. Some of the electronic components 1120 may be chip related components, and the semiconductor package 100 may be, for example, an application processor between chip related components, but is not limited thereto. The electronic device is not necessarily limited to the smart phone 1100, but may be other electronic devices as described above.

Semiconductor package

In general, many fine circuits are integrated in a semiconductor wafer. However, the semiconductor wafer itself cannot serve as a completed semiconductor product and may be damaged due to external physical or chemical influences. Therefore, instead of using the semiconductor wafer itself, it can be packaged and used in an electronic device or the like in a packaged state.

Here, a semiconductor package is required due to a difference in circuit width between a semiconductor wafer and a motherboard of an electronic device in terms of electrical connection. In detail, the size of the connection pads of the semiconductor wafer and the spacing between the connection pads of the semiconductor wafer are extremely fine, but the size of the component mounting pads of the motherboard used in electronic devices and the interval between the component mounting pads of the motherboard are significantly larger than The case of semiconductor wafers. Therefore, it may be difficult to directly mount a semiconductor wafer on a motherboard, and a packaging technology for buffering a difference in circuit width between the semiconductor wafer and the motherboard may be required.

A semiconductor package manufactured by a packaging technology may be classified into a fan-in type semiconductor package or a fan-out type semiconductor package depending on a structure and its purpose.

The fan-in type semiconductor package and the fan-out type semiconductor package will be described in more detail below with reference to the drawings.

Fan-in semiconductor package

3A and 3B are schematic cross-sectional views illustrating a state of a fan-in type semiconductor package before and after being packaged.

FIG. 4 is a schematic cross-sectional view illustrating a packaging process of a fan-in semiconductor package.

Referring to the drawings, the semiconductor wafer 2220 may be, for example, an integrated circuit (IC) in a bare state, including: a body 2221 including silicon (Si), germanium (Ge), and gallium arsenide (GaAs) or the like; a connection pad 2222 formed on one surface of the body 2221 and containing a conductive material such as aluminum (Al) or the like; and a passivation layer 2223 such as an oxide film, a nitride film Or the like, which is formed on one surface of the body 2221 and covers at least a part of the connection pad 2222. In this case, since the connection pad 2222 is extremely small, it is difficult to mount an integrated circuit (IC) on an intermediate-level printed circuit board (PCB) and a motherboard of an electronic device or the like.

Therefore, depending on the size of the semiconductor wafer 2220, the interconnection member 2240 may be formed on the semiconductor wafer 2220 so as to redistribute the connection pads 2222. An insulating layer 2241 can be formed on the semiconductor wafer 2220 by using an insulating material such as a photoimagable dielectric (PID) resin, and a via hole 2243h forming an open connection pad 2222 and a wiring pattern 2242 and a dielectric layer can be subsequently formed. Holes 2243 to form interconnecting features 2240. Subsequently, a passivation layer may be formed to protect the interconnect member 2240. 2250, an opening 2251 can be formed, and an under bump metal layer 2260 or the like can be formed. That is, a fan-in semiconductor package 2200 including, for example, a semiconductor wafer 2220, an interconnect member 2240, a passivation layer 2250, and a under bump metal layer 2260 may be manufactured through a series of processes.

As described above, the fan-in type semiconductor package may have all the connection pads (for example, input / output (I / O) terminals) of the semiconductor wafer inside the semiconductor wafer, and may have an excellent form of packaging Electrical characteristics and can be produced at low cost. Therefore, many components mounted in smart phones have been manufactured in the form of fan-in semiconductor packages. In detail, many components installed in smart phones have been developed to implement fast signal transmission while being compact in size.

However, since all the I / O terminals need to be placed inside the semiconductor wafer in the fan-in type semiconductor package, the fan-in type semiconductor package has a large space limitation. Therefore, it is difficult to apply this structure to a semiconductor wafer having a large number of I / O terminals or a semiconductor wafer having a compact size. In addition, due to the disadvantages described above, it is not possible to directly mount and use a fan-in semiconductor package on a motherboard of an electronic device. The reason is that even when the size of the I / O terminals of the semiconductor wafer and the interval between the I / O terminals of the semiconductor wafer are increased by the redistribution process, the size of the I / O terminals of the semiconductor wafer and the I of the semiconductor wafer are increased. The interval between the / O terminals is also not enough to directly mount the fan-in semiconductor package on the motherboard of the electronic device.

5 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is mounted on a plug-in substrate and finally mounted on a main board of an electronic device.

FIG. 6 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is embedded in a plug-in substrate and finally mounted on a main board of an electronic device.

Referring to the drawing, in a fan-in semiconductor package 2200, a semiconductor wafer The connection pads 2222 (ie, I / O terminals) of 2220 can be redistributed via the plug-in substrate 2301, and the fan-in semiconductor package 2200 can be finally mounted on the motherboard of an electronic device in a state where it is mounted on the plug-in substrate 2301. 2500 on. In this case, the solder ball 2270 and the like may be fixed by the underfill resin 2280 or the like, and the outside of the semiconductor wafer 2220 may be covered by the molding material 2290 or the like. Alternatively, the fan-in semiconductor package 2200 may be embedded in a separate plug-in substrate 2302, and the connection pads 2222 (ie, I / O terminals) of the semiconductor wafer 2220 may be embedded in the fan-in semiconductor package 2200 on the plug-in substrate 2302. In the middle state, the plug-in substrate 2302 is redistributed, and the fan-in semiconductor package 2200 can be finally mounted on the motherboard 2500 of the electronic device.

As described above, it may be difficult to directly mount and use a fan-in semiconductor package on a motherboard of an electronic device. Therefore, the fan-in type semiconductor package may be mounted on a separate plug-in substrate and then on a main board of an electronic device through a packaging process, or may be mounted on a main board of an electronic device in a state where it is embedded in the plug-in substrate And use.

Fan-out semiconductor package

FIG. 7 is a schematic cross-sectional view illustrating a fan-out type semiconductor package.

Referring to the drawings, in the fan-out type semiconductor package 2100, for example, the outside of the semiconductor wafer 2120 may be protected by the encapsulation body 2130, and the connection pads 2122 of the semiconductor wafer 2120 may be redistributed outside the semiconductor wafer 2120 by the interconnection member 2140. In this case, the passivation layer 2150 may be further formed on the interconnection part 2140, and the under bump metal layer 2160 may be further formed in the opening of the passivation layer 2150. The solder ball 2170 may be further formed on the under bump metal layer 2160. The semiconductor wafer 2120 may be an integrated circuit (IC) including a body 2121, a connection pad 2122, and a blunt circuit. Chemical layer (not shown) and the like. The interconnect member 2140 may include: an insulating layer 2141; a redistribution layer 2142 formed on the insulating layer 2141; and a via hole 2143 that electrically connects the connection pad 2122 and the redistribution layer 2142 to each other.

As described above, the fan-out type semiconductor package may have a form in which I / O terminals of a semiconductor wafer are rearranged and disposed outside the semiconductor wafer via interconnect members formed on the semiconductor wafer. As described above, in a fan-in semiconductor package, all I / O terminals of a semiconductor wafer need to be placed inside the semiconductor wafer. Therefore, when the size of the semiconductor wafer is reduced, it is necessary to reduce the size and pitch of the balls, so that the standardized ball layout cannot be used in a fan-in semiconductor package. On the other hand, a fan-out type semiconductor package has a form in which I / O terminals of a semiconductor wafer are rearranged and disposed outside the semiconductor wafer via interconnect members formed on the semiconductor wafer, as described above. Therefore, even when the size of the semiconductor wafer is reduced, the standardized ball layout can be used as it is in a fan-out semiconductor package, so that the fan-out semiconductor package can be mounted on the motherboard of an electronic device without using a separate plug-in type Substrate, as described below.

FIG. 8 is a schematic cross-sectional view illustrating a case where a fan-out type semiconductor package is mounted on a main board of an electronic device.

Referring to the drawings, the fan-out type semiconductor package 2100 may be mounted on the motherboard 2500 of the electronic device via the solder ball 2170 or the like. That is, as described above, the fan-out type semiconductor package 2100 includes an interconnection member 2140 formed on the semiconductor wafer 2120 and capable of re-arranging the connection pads 2122 to a fan-out area exceeding the size of the semiconductor wafer 2120 such that The standardized ball layout may be used as it is in a fan-out type semiconductor package 2100. Therefore, the fan-out type semiconductor package 2100 can be mounted on the motherboard 2500 of the electronic device without using a separate plug-in substrate or the like.

As described above, since the fan-out type semiconductor package can be mounted on a motherboard of an electronic device without using a separate plug-in substrate, the fan-out type semiconductor package can be implemented with a thickness smaller than that of the fan-in type semiconductor package using the plug-in substrate. Therefore, the fan-out type semiconductor package can be miniaturized and thinned. In addition, fan-out semiconductor packages have excellent thermal and electrical characteristics, making them particularly suitable for mobile products. Therefore, a printed circuit board (PCB) can be used to implement a fan-out type semiconductor package in a more compact form than a general package-on-package (POP) type, and the fan-out type The semiconductor package can solve the problem attributed to the occurrence of bending phenomenon.

Meanwhile, the fan-out type semiconductor package refers to a packaging technology for mounting a semiconductor wafer on a motherboard of an electronic device or the like as described above and protecting the semiconductor wafer from external influences, and is similar to a plug-in substrate or the like Concept of a printed circuit board (PCB) of the present invention, which has a scale, purpose, and the like different from that of a fan-out type semiconductor package, and the like, and is embedded therein There are fan-in semiconductor packages.

A fan-out type semiconductor package that can ensure a sufficient close adhesion of the metal layer under the bump will be described below with reference to the drawings.

FIG. 9 is a schematic cross-sectional view illustrating an example of a fan-out type semiconductor package.

FIG. 10 is a schematic plan view taken along a line II ′ of the fan-out semiconductor package of FIG. 9.

11A and 11B are schematic enlarged views illustrating a region A of the fan-out semiconductor package of FIG. 9.

Referring to the drawings, a fan-out type semiconductor package 100A according to an exemplary embodiment of the present invention may include: a first interconnection part 110 having a through hole 110H; a semiconductor The body wafer 120 is disposed in the through hole 110H of the first interconnection member 110 and has an active surface on which the connection pad 122 is disposed and a non-active surface opposite to the active surface; and an encapsulation body 130 that encapsulates the first At least part of the inactive surface of the interconnecting component 110 and the semiconductor wafer 120; the second interconnecting component 140, which is disposed on the active surfaces of the first interconnecting component 110 and the semiconductor wafer 120 and includes a weight electrically connected to the connection pad 122 Cloth layers 142a and 142b; a passivation layer 202 disposed on the second interconnection member 140 and having at least a portion of the opening 202H exposing the redistribution layer 142b of the second interconnection member 140; a metal layer 160 under the bump, which is disposed On the passivation layer 202 and filling at least a portion of the opening 202H; and a connection terminal 170 disposed on the under bump metal layer 160 and electrically connected to the connection pad 122. The under bump metal layer 160 may include: a first conductor layer 303 formed on the surface of the passivation layer 202; a second conductor layer 161 formed on the exposed redistribution layer 142b and the opening 202H of the second interconnection member 140 And a third conductor layer 162 formed on the second conductor layer 161. That is, in the under bump metal layer 160, the number of the first conductor layer 303, the second conductor layer 161, and the third conductor layer 162 formed on the surface of the passivation layer 202 may be different from those formed on the second interconnection member. The number of the second conductive layer 161 and the third conductive layer 162 on the wall of the exposed redistribution layer 142b and the opening 202H of 140. The number of the first conductor layer 303, the second conductor layer 161, and the third conductor layer 162 formed on the surface of the passivation layer 202 may be larger than the exposed redistribution layer 142b and the wall of the opening 202H formed on the second interconnection member 140. The number of the second conductor layers 161 and the third conductor layers 162 on the substrate.

In this case, when the first conductor layer 303 formed on the surface of the passivation layer 202 and surrounding the edge of the opening 202H is disposed as in the fan-out type semiconductor package 100A according to the exemplary embodiment, the first conductor layer may be used 303 as the base seed Layer to form the under bump metal layer 160. In this case, the passivation layer 202 and the first conductor layer 303 may have sufficient tight adhesion therebetween by self-assembly or the like, as described below. Therefore, the under-bump metal layer 160 formed by using the first conductor layer 303 as the seed layer can also ensure a sufficient tight adhesion.

Meanwhile, in the fan-out type semiconductor package 100A according to an exemplary embodiment, an outermost circuit such as a metal layer under a bump may be formed on a surface of the passivation layer 202 using a laminate to which the first conductor layer 303 is attached. 160 or similar. In this case, the first conductor layer 303 can serve as a protective layer before being patterned, and thus suppresses several side effects that may occur during the circuit formation process, for example, spots on the surface of the outermost layer, due to high Surface roughness makes it difficult to implement fine circuits, and the like. In addition, when a connection terminal 170 such as a solder ball is formed, a circuit such as an outermost layer of a metal layer under a bump formed using a laminate may be beneficial to a manufacturing process. In addition, as described below, a laminate may be applied to both surfaces of the outermost layer in a process of manufacturing a fan-out type semiconductor package. Therefore, a bending problem or the like which may occur in a process of manufacturing a fan-out type semiconductor package can be suppressed.

The respective components included in the fan-out type semiconductor package 100A according to the exemplary embodiment will be described in more detail below.

The first interconnection member 110 may include redistribution layers 112 a and 112 c, and the redistribution layers 112 a and 112 c may redistribute the connection pads 122 of the semiconductor wafer 120, thereby reducing the number of layers of the second interconnection member 140. If necessary, the first interconnection member 110 may maintain the hardness of the fan-out type semiconductor package 100A depending on certain materials, and is used to ensure the thickness uniformity of the encapsulation body 130. In some cases, due to the first interconnection part 110, the fan-out type semiconductor package 100A according to an exemplary embodiment may be used as a part of a stacked package. The first interconnection part 110 may have a through hole 110H. The through hole 110H may have The semiconductor wafer 120 disposed therein is spaced apart from the first interconnection part 110 by a predetermined distance. A side surface of the semiconductor wafer 120 may be surrounded by the first interconnection part 110. However, this form is merely an example and may be modified in different ways to have other forms, and the fan-out type semiconductor package 100A may perform another function depending on this form.

The first interconnection part 110 may include: an insulation layer 111 that is in contact with the second interconnection part 140; a first redistribution layer 112a that is in contact with the second interconnection part 140 and embedded in the insulation layer 111; and a second The redistribution layer 112c is disposed on the other surface of the insulating layer 111 opposite to one surface of the insulating layer 111 in which the first redistribution layer 112a is embedded. The first interconnection part 110 may include a via hole 113 that penetrates the insulating layer 111 and electrically connects the first redistribution layer 112 a and the second redistribution layer 112 c to each other. The first redistribution layer 112 a and the second redistribution layer 112 c may be electrically connected to the connection pad 122. When the first redistribution layer 112a is embedded in the insulating layer 111, the stepped portion due to the thickness of the first redistribution layer 112a may be significantly reduced, and the insulation distance of the second interconnection member 140 may be changed accordingly. Got constant. That is, the difference between the distance from the redistribution layer 142a of the second interconnecting member 140 to the lower surface of the insulating layer 111 and the distance from the redistribution layer 142a of the second interconnecting member 140 to the connection pad 122 may be less than the first The thickness of a redistribution layer 112a. Therefore, a high-density wiring design of the second interconnection part 140 may be easy.

The material of the insulating layer 111 is not particularly limited. For example, an insulating material may be used as a material of the insulating layer 111. In this case, the insulating material may be a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide resin), a thermosetting resin, or a thermoplastic resin impregnated with an inorganic filler such as glass cloth (or glass fabric) Resin in core materials, such as prepreg, Ajinomoto Build up Film (ABF), FR-4, bismaleimide triazine (BT) or similar . Alternatively, light can also be used Photoimagable dielectric (PID) resin is used as the insulating material.

The redistribution layers 112a and 112c can be used to redistribute the connection pads 122 of the semiconductor wafer 120. The material of each of the redistribution layers 112a and 112c may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The redistribution layers 112a and 112c may perform various functions depending on the design of their corresponding layers. For example, the redistribution layers 112a and 112c may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal (S) pattern may include various signals other than a ground (GND) pattern, a power (PWR) pattern, and the like, such as a data signal and the like. In addition, the redistribution layers 112a and 112c may include via hole pads, connection terminal pads, and the like. As a non-limiting example, both the redistribution layers 112a and 112c may include a ground pattern. In this case, the number of ground patterns formed on the redistribution layers 142a and 142b of the second interconnection member 140 can be significantly reduced, so that the degree of freedom in wiring design can be improved.

If necessary, a surface treatment layer (not shown) may be further formed on a portion of the redistribution layer 112 c exposed through the opening 131 formed in the encapsulation body 130. The surface treatment layer (not shown) is not particularly limited as long as it is known in the prior art, and may be, for example, electrolytic gold plating, electroless gold plating, organic solderability preservative (OSP) ) Or electroless tin, electroless silver, electroless nickel / replaced gold plating, direct immersion gold (DIG) plating, hot air solder leveling (HASL), or similar methods .

The via hole 113 may electrically connect the redistribution layers 112 a and 112 c formed on different layers to each other, thereby generating an electrical path in the first interconnection part 110. Vias Each of 113 may also be formed of a conductive material. Each of the via holes 113 may be completely filled with a conductive material, as illustrated in FIG. 10, or a conductive material may also be formed along the wall of each of the via holes 113. In addition, each of the via holes 113 may have all shapes known in the prior art, such as a tapered shape, a cylindrical shape, and the like. Meanwhile, as can be seen from a process to be described below, when forming holes for the via hole 113, some of the pads of the first redistribution layer 112 a may serve as stoppers, and each of the via holes 113 A tapered shape having an upper surface width greater than a lower surface width may therefore be advantageous in a manufacturing process. In this case, the via hole 113 may be integrated with a part of the second redistribution layer 112c.

The semiconductor wafer 120 may be an integrated circuit (IC) provided in an amount of hundreds to millions of elements or more stoppers integrated in a single wafer. The IC may be, for example, an application processor chip, such as a central processing unit (e.g., a CPU), a graphics processor (e.g., a GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or the like Similar, but not limited to this. The semiconductor wafer 120 may be formed based on an active wafer. In this case, the base material of the body 121 may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits may be formed on the body 121. The connection pad 122 may electrically connect the semiconductor wafer 120 to other components. The material of the connection pad 122 may be a conductive material such as aluminum (Al) or the like. The passivation layer 123 exposing the connection pad 122 may be formed on the body 121 and may be an oxide film, a nitride film or the like, or a double layer of an oxide layer and a nitride layer. The lower surface of the connection pad 122 may have a stepped portion passing through the passivation layer 123 with respect to the lower surface of the encapsulation body 130. Therefore, the phenomenon in which the encapsulation body 130 penetrates into the lower surface of the connection pad 122 can be prevented to a certain extent. The insulating layer (not shown) and the like can be further disposed in other desired positions.

The non-active surface of the semiconductor wafer 120 may be disposed at a level lower than an upper surface of the second redistribution layer 112 c of the first interconnection part 110. For example, the non-active surface of the semiconductor wafer 120 may be disposed at a level lower than the upper surface of the insulating layer 111 of the first interconnection part 110. The height difference between the non-active surface of the semiconductor wafer 120 and the upper surface of the second redistribution layer 112c of the first interconnection part 110 may be 2 μm or more, for example, 5 μm or more. In this case, it is possible to effectively prevent cracks from being generated in the corners of the inactive surface of the semiconductor wafer 120. In addition, the deviation of the insulation distance on the non-active surface of the semiconductor wafer 120 when the encapsulation body 130 is used can be significantly reduced.

The encapsulation body 130 may protect the first interconnection part 110 and / or the semiconductor wafer 120. The encapsulation form of the encapsulation body 130 is not particularly limited, but may be a form in which the encapsulation body 130 surrounds at least a portion of the first interconnection part 110 and / or the semiconductor wafer 120. For example, the encapsulation body 130 may cover the inactive surfaces of the first interconnecting component 110 and the semiconductor wafer 120, and fill a space between the wall of the through hole 110H and the side surface of the semiconductor wafer 120. In addition, the encapsulation body 130 may also fill at least a part of a space between the passivation layer 123 of the semiconductor wafer 120 and the second interconnection member 140. At the same time, the encapsulation body 130 may fill the through hole 110H, thus acting as an adhesive and reducing buckling of the semiconductor wafer 120 depending on certain materials.

Certain materials of the encapsulation body 130 are not particularly limited. For example, an insulating material may be used as some materials of the encapsulation body 130. In this case, the insulating material may be a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide resin), a reinforcing material (such as an inorganic filler impregnated in the thermosetting resin and the thermoplastic resin) Resin such as ABF, FR-4, BT, PID resin or the like. Alternatively, a known molding material such as EMC or the like may be used. Alternatively, a resin in which a thermosetting resin or a thermoplastic resin is impregnated together with an inorganic filler in a core material such as glass cloth (or glass fabric) may be used as the insulating material.

The encapsulation body 130 may include a plurality of layers formed of a variety of materials. For example, the space in the through hole 110H may be filled by the first encapsulation body, and the first interconnecting component 110 and the semiconductor wafer 120 may be covered by the second encapsulation body. Alternatively, the first encapsulation body may cover the first interconnection part 110 and the semiconductor wafer 120 while filling the space in the through hole 110H with a predetermined thickness, and the second encapsulation body may also cover the first encapsulation body with a predetermined thickness. In addition to the forms described above, various forms can be used.

If desired, the encapsulation body 130 may include conductive particles in order to block electromagnetic waves. For example, the conductive particles can be any material that can block electromagnetic waves, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb ), Titanium (Ti), solder or the like. However, this is only an example, and the conductive particles are not particularly limited thereto.

The second interconnecting member 140 may be configured to redistribute the connection pads 122 of the semiconductor wafer 120. Dozens to hundreds of connection pads 122 having various functions may be redistributed by the second interconnection member 140, and may be physically or electrically connected to an external source via a connection terminal 170 to be described below depending on the function. The second interconnection member 140 may include: insulation layers 141a and 141b; redistribution layers 142a and 142b, which are disposed on the insulation layers 141a and 141b; and via holes 143a and 143b, which penetrate the insulation layers 141a and 141b and The redistribution layers 142a and 142b are connected to each other. In the fan-out type semiconductor package 100A according to the exemplary embodiment, the second interconnection member 140 may include a plurality of redistribution layers 142a and 142b, but may also include a single layer. In addition, the second interconnection member 140 may include a different number of layers.

An insulating material may be used as a material of each of the insulating layers 141a and 141b. In this case, a photosensitive insulating material such as a photoimagable dielectric (PID) resin may also be used as the insulating material. In this case, each of the insulating layers 141a and 141b may be formed to have a smaller thickness, and a fine pitch of each of the via holes 143a and 143b may be more easily achieved. The materials of the insulating layers 141a and 141b may be the same as each other or may be different from each other as necessary. The insulating layers 141a and 141b may be integrated with each other depending on a process, so that a boundary therebetween may not be easily visible.

The redistribution layers 142 a and 142 b may be substantially used to redeploy the connection pads 122. The material of each of the redistribution layers 142a and 142b may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), Lead (Pb), titanium (Ti), or an alloy thereof. The redistribution layers 142a and 142b may perform various functions depending on the design of their corresponding layers. For example, the redistribution layers 142a and 142b may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal (S) pattern may include various signals other than a ground (GND) pattern, a power (PWR) pattern, and the like, such as a data signal and the like. In addition, the redistribution layers 142a and 142b may include via hole pads, connection terminal pads, and the like.

If necessary, a surface treatment layer (not shown) may be further formed on the exposed portions of the self-weighting layers 142a and 142b of the redistribution layer 142b. The surface treatment layer (not shown) is not particularly limited as long as it is known in the prior art, and may be, for example, electrolytic gold plating, electroless gold plating, OSP or electroless tin, electroless silver, electroless plating Nickel / substituted gold plating, DIG plating, HASL or similar methods.

Interlayer holes 143a and 143b can be redistribution layers formed on different layers 142a and 142b, the connection pad 122, or the like are electrically connected to each other, thereby generating an electrical path in the fan-out type semiconductor package 100A. The material of each of the via holes 143a and 143b may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), Lead (Pb), titanium (Ti), or an alloy thereof. Each of the via holes 143a and 143b may be completely filled with a conductive material, or a conductive material may be formed along a wall of each of the via holes 143a and 143b. In addition, each of the via holes 143a and 143b may have all shapes known in the prior art, such as a tapered shape, a cylindrical shape, and the like.

The thicknesses of the redistribution layers 112a and 112c of the first interconnecting component 110 may be greater than the thickness of the redistribution layers 142a and 142b of the second interconnecting component 140. Since the thickness of the first interconnection part 110 may be equal to or greater than the thickness of the semiconductor wafer 120, the redistribution layers 112a and 112c formed in the first interconnection part 110 may be formed as Has a large size. On the other hand, since the second interconnection member 140 is thin, the redistribution layers 142 a and 142 b of the second interconnection member 140 may form a relatively smaller size than the size of the redistribution layers 112 a and 112 c of the first interconnection member 110. .

The passivation layer 202 may be configured to protect the second interconnection part 140 from external physical or chemical damage. The passivation layer 202 may have an opening 202H that exposes at least a portion of one of the redistribution layers 142 a and 142 b of the second interconnection part 140. Each of the openings 202H may expose all or only a portion of the surface of the redistribution layer 142b. In some cases, each of the openings 202H may expose a side surface of the redistribution layer 142b.

The material of the passivation layer 202 is not particularly limited, and may be, for example, a photosensitive insulating material. Alternatively, a solder resist may also be used as a material of the passivation layer 202. Substitute As the material of the passivation layer 202, an insulating resin (for example, ABF including an inorganic filler and an epoxy resin, or the like) containing no core material but containing a filler may be used. Compared with the general case, the surface roughness of the passivation layer 202 may be lower. When the surface roughness is as low as the case described above, it is possible to suppress several side effects that may occur next in the circuit formation process, such as generating spots on the surface, difficulty in implementing fine circuits, and the like.

The under bump metal layer 160 may be additionally configured to improve the connection reliability of the connection terminal 170 to improve the board level reliability. The under bump metal layer 160 may include: a first conductor layer 303 formed on the surface of the passivation layer 202; and a second conductor layer 161 formed on the heavy layer exposed through the opening 202H, the wall of the opening 202H, and the first conductor 303. On the cloth layer 142b; and a third conductor layer 162, which is formed on the second conductor layer 161.

The first conductor layer 303 and the passivation layer 202 may form a self-assembly therebetween, as described below, and thus have sufficient tight adhesion therebetween. The first conductor layer 303 may be used as a base seed layer for forming the under bump metal layer 160. Therefore, the under-bump metal layer 160 can also have sufficient close adhesion. The first conductor layer 303 can serve as a protective layer for the outermost layer of the fan-out semiconductor package before being patterned, thereby suppressing several side effects that may occur during the circuit formation process, such as generating spots on the surface of the outermost layer, making it difficult Implement fine circuits, and the like. The first conductor layer 303 may include a known conductive material, preferably copper (Cu), such as electrolytic copper.

The second conductor layer 161 may serve as a seed layer, and the third conductor layer 162 may substantially serve as the under bump metal layer 160. The second conductor layer 161 and the third conductor layer 162 may include a known conductive material, and preferably include electroless copper and electrolytic copper, respectively. The first conductor layer 303 contains electrolytic copper, the second conductor layer 161 contains electroless copper, and the third conductor layer In the case where 162 includes electrolytic copper, the first conductor layer 303, the second conductor layer 161, and the third conductor layer 162 are distinguishable layers, because any adjacent layers are formed by different processes. The second conductor layer 161 may serve as a seed layer, and thus has an extremely thin thickness. That is, the thickness of the second conductor layer 161 may be lower than the thickness of the first conductor layer 303 and the third conductor layer 162. The thickness of the third conductor layer 162 may be thicker than that of the first conductor layer 303, and the thickness of the first conductor layer 303 may be thicker than that of the second conductor layer 161. That is, the thickness of the third conductor layer 162 may be the thickest, and the thickness of the second conductor layer 161 may be the thinnest. However, the thicknesses of the first to third conductor layers are not necessarily limited thereto.

The connection terminal 170 may be additionally configured to physically or electrically connect the fan-out type semiconductor package 100A externally. For example, the fan-out semiconductor package 100A can be mounted on a motherboard of an electronic device via a connection terminal 170. Each of the connection terminals 170 may be formed of a conductive material such as solder or the like. However, this is only an example, and the material of each of the connection terminals 170 is not particularly limited thereto. Each of the connection terminals 170 may be a pad, a ball, a pin, or the like. The connection terminal 170 may be formed in a multilayer structure or a single-layer structure. When the connection terminal 170 is formed in a multilayer structure, the connection terminal 170 may include a copper pillar and solder. When the connection terminal 170 is formed in a single layer structure, the connection terminal 170 may include tin-silver solder or copper. However, this is only an example, and the connection terminal 170 is not limited thereto. The number, interval, placement, or the like of the connection terminals 170 are not particularly limited, and may be sufficiently modified by those skilled in the art depending on design details. For example, the connection terminal 170 may be provided in an amount of tens to thousands according to the number of the connection pads 122 of the semiconductor wafer 120, but is not limited thereto, and may also be tens to thousands or more or tens to thousands The connection terminal 170 is provided in an amount of or less.

At least one of the connection terminals 170 may be disposed in the fan-out area. Fan-out area It is a region other than a region where the semiconductor wafer 120 is placed. That is, the fan-out type semiconductor package 100A according to an exemplary embodiment may be a fan-out type package. Compared with the fan-in package, the fan-out package can have excellent reliability, can implement multiple input / output (I / O) terminals, and can promote 3D interconnection. In addition, compared with a ball grid array (BGA) package, a land grid array (LGA) package, or the like, the fan-out package can be used without a separate board. It is mounted on the electronic device. Therefore, the fan-out type package can be manufactured to have a small thickness and can be price competitive.

Although not shown in the drawings, the metal layer may be further disposed on the inner wall of the through hole 110H of the first interconnecting component 110 as required. That is, the side surface of the semiconductor wafer 120 may also be surrounded by a metal layer. The heat generated by the semiconductor wafer 120 can be efficiently radiated in the upward or downward direction of the fan-out type semiconductor package 100A via the metal layer, and electromagnetic waves can be effectively blocked through the metal layer. In addition, if necessary, a plurality of semiconductor wafers may be disposed in the through holes 110H of the first interconnection member 110, and the number of the through holes 110H of the first interconnection member 110 may be plural, and the semiconductor wafers may be respectively disposed in the through holes. in. In addition, separate passive components such as a condenser, an inductor, and the like may be placed in the through hole 110H together with the semiconductor wafer. In addition, a surface-mounted component may be mounted on the passivation layer 202.

12A to 12G are schematic diagrams illustrating an example of a process of manufacturing the fan-out type semiconductor package of FIG. 9.

Referring to FIG. 12A, a separable membrane 401 may be first prepared. The separable membrane 401 may have metal layers 402 and 403 formed on one surface or both surfaces thereof. Surface treatment may be performed on the bonded surface between the metal layers 402 and 403 to facilitate separation in a subsequent separation process. Alternatively, a release may be provided between the metal layers 402 and 403 Delamination to facilitate separation in subsequent processes. The separable film 401 may be a known insulating substrate, and the material of the separable film 401 may be any material. The metal layers 402 and 403 may be generally copper (Cu) foils, but are not limited thereto. That is, the metal layers 402 and 403 may be thin films formed of other conductive materials. Next, the dry film 404 may be used to perform patterning for forming the first redistribution layer 112a. The first redistribution layer 112a may be formed using a known photolithography method. The dry film 404 may be a known dry film formed of a photosensitive material. Next, a conductive material may fill the patterned space of the dry film 404 to form a first redistribution layer 112a. The first redistribution layer 112a may be formed using a plating method. In this case, the metal film 403 may serve as a seed layer. As the plating method, electroplating, electroless plating, or the like can be used. The plating method can be chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, subtractive method, additive method, semi-additive process (SAP), A modified semi-additive process (MSAP) or a similar method is not limited thereto. Then, the dry film 404 can be removed. The dry film 404 may be removed by a known method such as an etching method or the like.

Referring to FIG. 12B, an insulating layer 111 in which at least a portion of the first redistribution layer 112 a is embedded may be formed on the metal layer 403. Subsequently, a via hole 113 penetrating the insulating layer 111 may be formed. In addition, the second redistribution layer 112c may be formed on the insulating layer 111. It may be through a method of laminating a precursor of the insulating layer 111 by a known lamination method and then hardening the precursor, a method of applying a precursor of the insulating layer 111 by a known application method, and then hardening the precursor, or a similar method The insulating layer 111 is formed. Via holes can be formed by using photolithography, mechanical drilling, laser drilling or the like, patterning can be performed using a dry film or the like, and via holes can be filled by electroplating or the like, and The patterned space method is used to form vias 113 (shown in FIG. 10) and Double cloth layer 112c. Then, the detachable film 401 can be peeled. In this case, the peeling may indicate that the metal layers 402 and 403 are separated. Here, the metal layers 402 and 403 may be separated using a blade, but is not limited thereto. That is, the metal layers 402 and 403 can be separated using all known methods. Meanwhile, the example of forming the first interconnection part 110 before forming the through hole before peeling the separable film 401 has been described in a series of processes, but is not limited thereto. For example, the first interconnection member 110 may be formed after the detachable film 401 is peeled off. That is, the order is not necessarily limited to the order described above.

Referring to FIG. 12C, the remaining metal layer 403 may be removed by a known etching method or the like. In this case, a part of the first redistribution layer 112 a may be removed so that the first redistribution layer 112 a is recessed in the inward direction of the insulating layer 111. In addition, a through hole 110H may be formed in the first interconnection part 110. The through hole 110H may be formed using a mechanical drilling or a laser drilling. However, the through hole 110H is not limited to be formed using mechanical drilling or laser drilling, and may also be formed by a sandblasting method using particles for polishing, a dry etching method using a plasma, or the like. In the case where the through-hole 110H is formed using a mechanical or laser drilling, the resin stain in the through-hole 110H may be removed by performing a desmearing method such as a permanganic acid method or the like. . Then, the adhesive film 405 may be attached to one surface of the first interconnection part 110. In this case, when the first redistribution layer 112a is recessed, one surface of the first redistribution layer 112a may have a stepped portion with respect to one surface of the adhesive film 405. As the adhesive film 405, any material that can fix the insulating layer 111 can be used. As a non-limiting example of this material, a known tape or the like can be used. Examples of known tapes may include a thermosetting adhesive tape whose adhesion is weakened by heat treatment, an ultraviolet curable adhesive tape whose adhesion is weakened by ultraviolet light irradiation, or the like. In addition, the semiconductor wafer 120 may be disposed in the through hole 110H of the insulating layer 111. By way of example, The method of attaching 120 to the adhesive film 405 places the semiconductor wafer 120 in the through hole 110H. The semiconductor wafer 120 may be disposed face down so that the connection pad 122 is attached to the adhesive film 405. If necessary, the connection pad 122 may be attached to the adhesive film 405 such that one surface of the connection pad 122 has a stepped portion relative to the upper surface of the adhesive film 405, that is, after the connection pad 122 is attached to the adhesive film 405, The connection pad 122 is recessed in the inward direction of the semiconductor wafer 120.

Referring to FIG. 12D, an encapsulation body 130 may be used to encapsulate at least a portion of the first interconnecting component 110 and the semiconductor wafer 120. The encapsulation body 130 can cover the inactive surfaces of the first interconnecting component 110 and the semiconductor wafer 120, and can fill the space in the through hole 110H. The encapsulation body 130 may be formed by a known method. For example, the encapsulation body 130 may be formed by a method of laminating a resin for forming the encapsulation body 130 in a non-hardened state and then curing the resin. Alternatively, it may be formed by a method of applying a resin for forming the encapsulation body 130 on the adhesive film 405 in a non-hardened state to encapsulate at least a portion of the first interconnect member and the semiconductor wafer 120 and then hardening the resin Capsular body 130. The semiconductor wafer 120 can be fixed by hardening. As a method of laminating the resin, for example, a hot pressing process that performs pressing of the resin at a high temperature for a predetermined time, a pressure reduction of the resin, and then the resin is cooled to room temperature, a resin is cooled in the cold pressing process, and then a processing tool may be used Method, or a similar method. As a method of applying the resin, for example, a screen printing method in which ink is applied by a squeegee, a spray printing method in which ink is applied in a mist form, or the like can be used. In some cases, one surface of the encapsulation body 130 may have a stepped portion with respect to one surface of the first redistribution layer 112 a and one surface of the connection pad 122 after being hardened. Then, the adhesive film 405 can be peeled. The method of peeling the adhesive film 405 is not particularly limited, but may be a known method. For example, when using a thermosetting adhesive tape that reduces adhesion by heat treatment, In the case of irradiating an ultraviolet curable adhesive tape or the like that weakens the adhesive force as the adhesive film 405, the adhesive film 405 may be peeled off after the adhesive force of the adhesive film 405 is weakened by heat-treating the adhesive film 405, or may It is peeled off after the adhesive force of the adhesive film 405 is weakened by irradiating the adhesive film 405 with ultraviolet rays. Then, the second interconnection member 140 may be formed on the active surfaces of the first interconnection member 110 and the semiconductor wafer 120, and the adhesive film 405 is removed from the active surfaces of the first interconnection member 110 and the semiconductor wafer 120. By the plating method or the like as described above, the insulating layers 141a and 141b can be sequentially formed, and then the redistribution layers 142a and 142b can be formed on the insulating layers 141a and 141b, and the insulating layers 141a and 141b can be formed respectively Via holes 143a and 143b are formed in the layer 141b to form the second interconnection member 140.

Referring to FIG. 12E, the passivation layer 202 and the laminate 300 including the first conductive layer 303, the release layer 302, and the carrier film 301 sequentially stacked may be attached to the second interconnection member 140 such that the passivation layer 202 is connected to the second Interconnect member 140. In addition, the passivation layer 202 and the laminate 300 including the first conductive layer 303, the release layer 302, and the carrier film 301 which are sequentially stacked may be attached to the encapsulation body 130 such that the passivation layer 202 is connected to the encapsulation body 130. Meanwhile, in the case where the first conductor layer 303 is attached to the surface of the passivation layer 202 in the state of the laminate as described above, the self-assembly between the first conductor layer 303 and the passivation layer 202 is described below It is possible that the first conductor layer 303 and the passivation layer 202 can have excellent tight adhesion therebetween. Then, the carrier film 301 may be removed from the laminate attached to one surface of the second interconnection part 140 and the laminate attached to the encapsulation body 130. The method of removing the carrier film 301 may be a known method and is not particularly limited.

Referring to FIG. 12F, in the laminate attached to the second interconnection part 140, it may be An opening 202H is formed that penetrates the passivation layer 202, the laminated first conductor layer 303, and the release layer 302 and exposes at least a portion of the redistribution layer 142b of the second interconnect member 140. The opening 202H may be formed using mechanical drilling or laser drilling. However, the opening 202H is not limited to be formed using mechanical drilling or laser drilling, and may also be formed by a sandblasting method using particles for polishing, a dry etching method using a plasma, or the like. Then, the release layer 302 may be removed from the laminate attached to the second interconnection part 140 and the laminate attached to the encapsulation body 130. The release layer 302 can be removed by a desmearing process. In this case, the first conductor layer 303 in the laminate attached to the second interconnection part 140 and the laminate attached to the encapsulation body 130 can prevent both surfaces of the passivation layer 202 from being decontaminated. Program was damaged. Next, a second conductor layer 161 covering the redistribution layer 142 b exposed through the opening 202H, the wall of the opening 202H, and the first conductor layer 303 may be formed. The second conductor layer 161 may be formed as a base seed layer using the first conductor layer 303 having an excellent tight adhesion as described above, and thus has a better tight adhesion. The second conductor layer 161 may be formed by a known plating method, for example, electroless plating such as sputtering, or the like. Meanwhile, when the second conductor layer 161 is formed on the second interconnecting member 140, a similar conductor layer (not shown) covering the first conductor layer 303 may also be formed on the encapsulation body 130. However, in some cases, a conductor layer (not shown) may not be formed on another surface.

Referring to FIG. 12G, a third conductor layer 162 may be formed on the second conductor layer 161 on the second interconnection part 140. In addition, the first conductor layer 303 and the second conductor layer 161 may be patterned. This process can be performed using a known method such as electroplating by subtractive method, additive method, semi-additive method, modified semi-additive method, or the like. Accordingly, the under bump metal layer 160 may be formed. Meanwhile, although not shown, when the third conductive layer 162 is formed on the second interconnection member 140, the third conductive layer (not shown) may be It is formed on the encapsulation body 130, and the first conductor layer 303, the second conductor layer 161, and the third conductor layer (not shown) formed on the encapsulation body 130 can be removed by a known etching method or the like.示). In addition, an opening 131 may be formed that penetrates the passivation layer 202 attached to the encapsulation body 130 and exposes at least a part of the redistribution layer 112 c formed on the other surface of the first interconnection part 110. The opening 131 may be used as a mark, or the like. In some cases, the opening 131 may be used as a space formed with a connection terminal, a surface mount component, or the like. In the case where the passivation layer 202 is attached to the encapsulation body 130 as described above, the opening 131 may be more easily formed. In addition, in a case where the passivation layer 202 is attached to both sides of the fan-out type semiconductor package as described above in a substantially symmetrical shape, the bending generated during the manufacturing process can be controlled. If necessary, the passivation layer 202 attached to the encapsulation body 130 may be removed as illustrated in the drawing, but the passivation layer 202 may also be used in a state where the passivation layer 202 is attached to the encapsulation body 130. Then, the connection terminal 170 may be formed on the under bump metal layer 160 by a known method. The method of forming the connection terminal 170 is not particularly limited. That is, the connection terminal 170 may be formed by a method well-known in the prior art depending on its structure or form. The connection terminal 170 can be fixed by reflow, and a portion of the connection terminal 170 can be embedded in the passivation layer 202 to enhance the fixing force, and the remaining portion of the connection terminal 170 can be exposed to the outside, thereby improving reliability.

Meanwhile, a series of processes may be to prepare a separable film 401 having a large size, manufacture a plurality of fan-out semiconductor packages 100A through the above-mentioned process, and then singulating the plurality of fan-out semiconductor packages into individual ones by cutting. The fan-out type semiconductor package 100A is to facilitate a mass production process. In this case, productivity can be excellent.

FIG. 13 is a diagram illustrating a method of manufacturing a laminate used in FIGS. 12A to 12G. Schematic illustration of an example process.

Referring to the drawings, a process of manufacturing a laminate may include: preparing a first laminated film 200 including a release film 201 and a passivation layer 202 attached to the release film 201; preparing a carrier film 301; A second laminated film 300 connected to the first conductor layer 303 of the carrier film 301; and attaching the first laminated film 200 and the second laminated film 300 to each other such that the first conductor layer 303 is attached to the passivation layer 202 surface. Attachment of the first laminated film 200 and the second laminated film 300 to each other may be performed using known rolls 501 and 502 (but not limited thereto).

The release film 201 may be, for example, a polyethylene terephthalate (PET) film, and the passivation layer 202 may be, for example, an ABF including a filler and a resin as described above, but the release film 201 and the passivation layer 202 are not limited to this. The carrier film 301 may be, for example, a PET film, but is not limited thereto. The release layer 302 may be, for example, an alkali-soluble resin layer, but is not limited thereto. The first conductor layer 303 may be, for example, an electrolytic copper layer, but is not limited thereto.

FIG. 14 is a schematic diagram illustrating self-assembly between a passivation layer and a metal layer.

Referring to the drawings, the passivation layer 202 may be cured in a state where the first conductor layer 303 is attached to a surface of the passivation layer 202. In this case, when the passivation layer 202 is cured, at least one of the chemically reactive groups 202p included in the insulating resin constituting the passivation layer 202 may self-assemble to the first conductor layer attached to the surface of the passivation layer 202. 303 metal 303p. Therefore, the passivation layer 202 and the first conductor layer 303 can have excellent tight adhesion therebetween. In more detail, the chemically reactive group 202p included in the insulating resin of the passivation layer 202 may be enriched toward the surface of the passivation layer 202 to which the first conductor layer 303 is attached during the curing process, and may be enriched with The metal 303p of the first conductor layer 303 forms a coordination bond or a covalent bond. Therefore, the passivation layer 202 and the first conductor layer 303 may pass through Excellent self-adhesion between them by self-assembly by the keys described above. The chemically reactive group 202p may be a complex compound such as an aromatic compound having a long tail, but is not limited thereto.

FIG. 15 is a schematic diagram illustrating a normal curing state of the passivation layer.

Referring to the drawing, in a case where the passivation layer 202 'is cured only in a state where it is attached to the release film 201', the chemically reactive group 202'p contained in the resin of the passivation layer 202 'may be arbitrarily configured, It may not be possible to achieve an excellent tight adhesion via self-assembly as described above.

FIG. 16 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

Referring to the drawings, in a fan-out type semiconductor package 100B according to another exemplary embodiment of the present invention, the first interconnection part 110 may include: a first insulation layer 111 a that is in contact with the second interconnection part 140; The first redistribution layer 112a is in contact with the second interconnection member 140 and is embedded in the first insulating layer 111a; the third redistribution layer 112b is disposed in contact with the first insulating layer in which the first redistribution layer 112a is embedded. 111a on one surface opposite to the other surface of the first insulating layer 111a; the second insulating layer 111b, which is disposed on the first insulating layer 111a and covers the third redistribution layer 112b; and the second redistribution layer 112c, It is disposed on the second insulating layer 111b. The first redistribution layer 112a, the third redistribution layer 112b, and the second redistribution layer 112c may be electrically connected to the connection pad 122. Meanwhile, although not shown in the drawings, the first redistribution layer 112a, the third redistribution layer 112b, the third redistribution layer 112b, and the second redistribution layer 112c may pass through the first insulating layer 111a and the The first via hole and the second via hole of the two insulating layers 111b are electrically connected to each other.

Since the first redistribution layer 112a is embedded, the The insulation distance of the insulation layer 141a may be substantially constant, as described above. Since the first interconnection part 110 may include a large number of the first redistribution layer 112a, the third redistribution layer 112b, and the second redistribution layer 112c, the second interconnection part 140 may be further simplified. Therefore, a reduction in a yield depending on a defect occurring in a process of forming the second interconnection part 140 can be suppressed. The first redistribution layer 112a may be recessed in the first insulating layer 111a so that there is a stepped portion between the lower surface of the first insulating layer 111a and the lower surface of the first redistribution layer 112a. Therefore, when the encapsulation body 130 is formed, the phenomenon that the material of the encapsulation body 130 permeates and contaminates the first redistribution layer 112a can be prevented.

The lower surface of the first redistribution layer 112 a of the first interconnection part 110 may be disposed at a level higher than the lower surface of the connection pad 122 of the semiconductor wafer 120. In addition, the distance between the redistribution layer 142a of the second interconnection member 140 and the first redistribution layer 112a of the first interconnection member 110 may be greater than the connection between the redistribution layer 142a of the second interconnection member 140 and the semiconductor wafer 120. The distance between the pads 122. The reason is that the first redistribution layer 112 a may be recessed in the insulating layer 111. The third redistribution layer 112 b of the first interconnection part 110 may be disposed on a level between the active surface and the non-active surface of the semiconductor wafer 120. The first interconnection part 110 may be formed in a thickness corresponding to the thickness of the semiconductor wafer 120. Therefore, the third redistribution layer 112 b formed in the first interconnection part 110 may be disposed on a level between the active surface and the non-active surface of the semiconductor wafer 120.

The thicknesses of the first redistribution layer 112a, the third redistribution layer 112b, and the second redistribution layer 112c of the first interconnection part 110 may be greater than the thicknesses of the redistribution layers 142a and 142b of the second interconnection part 140. Since the thickness of the first interconnection member 110 may be equal to or greater than the thickness of the semiconductor wafer 120, the first redistribution layer 112a, the third redistribution layer 112b, and the second redistribution layer 112c may depend on the thickness of the first interconnection member 110. The scale is formed to have a large size. On the other hand, the redistribution layer 142a of the second interconnection member 140 and 142b can be formed to a relatively small size due to its thinness.

The descriptions of the configurations other than the above-mentioned configurations or the like and the manufacturing method overlap with those described above, and therefore are omitted.

FIG. 17 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

Referring to the drawings, in a fan-out type semiconductor package 100C according to another exemplary embodiment of the present invention, the first interconnection part 110 may include: a first insulating layer 111a; a first redistribution layer 112a; The cloth layer 112b is disposed on both surfaces of the first insulating layer 111a; the second insulating layer 111b is disposed on the first insulating layer 111a and covers the first redistribution layer 112a; the second redistribution layer 112c, It is disposed on the second insulation layer 111b; the third insulation layer 111c is disposed on the first insulation layer 111a and covers the third redistribution layer 112b; and the fourth redistribution layer 112d is disposed on the third insulation layer 111c on. The first redistribution layer 112a, the third redistribution layer 112b, the second redistribution layer 112c, and the fourth redistribution layer 112d may be electrically connected to the connection pad 122. Since the first interconnection part 110 may include a larger number of the first redistribution layer 112a, the third redistribution layer 112b, the second redistribution layer 112c, and the fourth redistribution layer 112d, the second interconnection part may be further simplified 140. Therefore, it is possible to suppress a decrease in a yield rate depending on a defect occurring in a process of forming the second interconnection part 140. Meanwhile, although not shown in the drawings, the first redistribution layer 112a, the third redistribution layer 112b, the second redistribution layer 112c, and the fourth redistribution layer 112d may penetrate the first insulating layer 111a, the The first to third vias of the second to third insulating layers 111b to 111c are electrically connected to each other.

The thickness of the first insulating layer 111a may be greater than the thickness of the second insulating layer 111b and the third insulating layer 111c. The first insulating layer 111a may be relatively thick so as to maintain the hardness, and the second insulating layer 111b and the third insulating layer 111c may be introduced so as to form a relatively A large number of second redistribution layers 112c and fourth redistribution layers 112d. The first insulating layer 111a may include an insulating material different from that of the second insulating layer 111b and the third insulating layer 111c. For example, the first insulating layer 111a may be, for example, a prepreg including a core material, an inorganic filler, and an insulating resin, and the second insulating layer 111b and the third insulating layer 111c may be ABF films or include an inorganic filler. And a photosensitive insulating film of an insulating resin. However, the materials of the first insulating layer 111a, the second insulating layer 111b, and the third insulating layer 111c are not limited thereto.

The lower surface of the second redistribution layer 112 c of the first interconnection part 110 may be disposed at a level lower than the lower surface of the connection pad 122 of the semiconductor wafer 120. In addition, the distance between the redistribution layer 142a of the second interconnection member 140 and the second redistribution layer 112c of the first interconnection member 110 may be smaller than the connection between the redistribution layer 142a of the second interconnection member 140 and the semiconductor wafer 120. The distance between the pads 122. The reason is that the second redistribution layer 112c may be disposed on the second insulating layer 111b in a convex form, thereby causing contact with the second interconnection member 140. The first redistribution layer 112 a and the third redistribution layer 112 b of the first interconnection part 110 may be disposed on a level between the active surface and the non-active surface of the semiconductor wafer 120. The first interconnection part 110 may be formed in a thickness corresponding to the thickness of the semiconductor wafer 120. Therefore, the first redistribution layer 112 a and the third redistribution layer 112 b formed in the first interconnection part 110 may be disposed on a level between the active surface and the non-active surface of the semiconductor wafer 120.

The thicknesses of the first redistribution layer 112a, the third redistribution layer 112b, the second redistribution layer 112c, and the fourth redistribution layer 112d of the first interconnecting component 110 may be greater than the redistribution layer 142a and 142b thickness. Since the thickness of the first interconnection part 110 may be equal to or greater than the thickness of the semiconductor wafer 120, the first redistribution layer 112a, the third redistribution layer 112b, the second redistribution layer 112c, and the fourth redistribution layer 112d are also Can be formed to have a large size. On the other hand, the redistribution layers 142a and 142b of the second interconnection part 140 may be formed to a relatively small size due to being thin.

The descriptions of the configurations other than the above-mentioned configurations or the like and the manufacturing method overlap with those described above, and therefore are omitted.

As explained above, according to the exemplary embodiment of the present invention, a fan-out type semiconductor package that can ensure a sufficient close adhesion of the metal layer under the bump can be provided.

Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the invention as defined by the scope of the attached application patents.

Claims (15)

A fan-out type semiconductor package includes a semiconductor wafer having an active surface on which a connection pad is disposed and a non-active surface opposite to the active surface; and an encapsulation body that encapsulates the non-active surface of the semiconductor wafer. At least a portion of an active surface; a second interconnecting component disposed on the active surface of the semiconductor wafer and including a redistribution layer electrically connected to the connection pad of the semiconductor wafer; a passivation layer disposed on The second interconnect member has an opening exposing at least a portion of the redistribution layer of the second interconnect member; and a sub-bump metal layer disposed on the passivation layer and filling the opening At least part of the metal layer, wherein the under-bump metal layer includes: a first conductor layer formed on a surface of the passivation layer; and a second conductor layer formed on the exposed redistribution layer and the opening. And a third conductor layer formed on the second conductor layer, the number of conductor layers formed on the surface of the passivation layer is greater than that formed on the exposed Said A cloth layer and the number of conductor layers on the wall of the opening in the passivation layer, the first conductor layer includes a metal layer consisting only of metal, and the thickness of the second conductor layer is less than A conductor layer and a thickness of the third conductor layer, wherein the first conductor layer includes electrolytic copper, the second conductor layer includes electroless copper, and the third conductor layer includes electrolytic copper. The fan-out semiconductor package according to item 1 of the patent application scope, further comprising a connection terminal disposed on the metal layer under the bump and electrically connected to the connection pad of the semiconductor wafer, wherein the connection At least one of the terminals is disposed in the fan-out area. The fan-out type semiconductor package according to item 1 of the patent application scope, further comprising a first interconnection part having a through hole, wherein the semiconductor wafer is disposed in the through hole of the first interconnection part, The encapsulation body fills at least a portion of the through hole of the first interconnection component, the first interconnection component includes: a first insulating layer; a first redistribution layer, which is interconnected with the second A component is in contact with and embedded in the first insulation layer; and a second redistribution layer is disposed on the first opposed to one surface of the first insulation layer in which the first redistribution layer is embedded On the other surface of the insulating layer, the first redistribution layer and the second redistribution layer are electrically connected to the connection pad. The fan-out type semiconductor package according to item 3 of the scope of patent application, wherein the first interconnecting component further includes: a second insulating layer disposed on the first insulating layer and covering the second redistribution layer And a third redistribution layer disposed on the second insulating layer, and the third redistribution layer is electrically connected to the connection pad. The fan-out type semiconductor package according to item 3 of the patent application scope, wherein a distance between the redistribution layer and the first redistribution layer of the second interconnecting component is greater than the second interconnecting component The distance between the redistribution layer and the connection pad. The fan-out type semiconductor package according to item 3 of the scope of patent application, wherein a thickness of the first redistribution layer is greater than a thickness of the redistribution layer of the second interconnect component. The fan-out type semiconductor package according to item 3 of the patent application scope, wherein a lower surface of the first redistribution layer is disposed at a level higher than a lower surface of the connection pad. The fan-out type semiconductor package according to item 4 of the patent application scope, wherein the second redistribution layer is disposed on a level between the active surface and the non-active surface of the semiconductor wafer. The fan-out type semiconductor package according to item 1 of the patent application scope, further comprising a first interconnection part having a through hole, wherein the semiconductor wafer is disposed in the through hole of the first interconnection part, The encapsulation body fills at least a portion of the through hole of the first interconnecting component, wherein the first interconnecting component includes: a first insulating layer; a first redistribution layer and a second redistribution layer, Respectively disposed on opposite surfaces of the first insulation layer; a second insulation layer disposed on the first insulation layer and covering the first redistribution layer; and a third redistribution layer disposed on On the second insulating layer, and the first redistribution layer to the third redistribution layer are electrically connected to the connection pad. The fan-out type semiconductor package according to item 9 of the patent application scope, wherein the first interconnecting component further includes: a third insulating layer disposed on the first insulating layer and covering the second redistribution layer A fourth redistribution layer disposed on the third insulating layer, and the fourth redistribution layer is electrically connected to the connection pad. The fan-out type semiconductor package according to item 9 of the scope of patent application, wherein a thickness of the first insulating layer is greater than a thickness of the second insulating layer. The fan-out type semiconductor package according to item 9 of the scope of patent application, wherein a thickness of the third redistribution layer is greater than a thickness of the redistribution layer of the second interconnect component. The fan-out type semiconductor package according to item 9 of the scope of patent application, wherein the first redistribution layer is disposed on a level between the active surface and the non-active surface of the semiconductor wafer. The fan-out type semiconductor package according to item 9 of the scope of the patent application, wherein a lower surface of the third redistribution layer is disposed at a level lower than a lower surface of the connection pad. A fan-out type semiconductor package includes a semiconductor wafer having an active surface on which a connection pad is disposed and a non-active surface opposite to the active surface; and an encapsulation body that encapsulates the non-active surface of the semiconductor wafer. At least a portion of an active surface; a second interconnecting component disposed on the active surface of the semiconductor wafer and including a redistribution layer electrically connected to the connection pad of the semiconductor wafer; a passivation layer disposed on The second interconnect member has an opening exposing at least a portion of the redistribution layer of the second interconnect member; and a sub-bump metal layer disposed on the passivation layer and filling the opening At least part of the metal layer, wherein the under-bump metal layer includes: a first conductor layer formed on a surface of the passivation layer; and a second conductor layer formed on the exposed redistribution layer and the opening. And a third conductor layer formed on the second conductor layer, the number of conductor layers formed on the surface of the passivation layer is greater than that formed on the exposed Said The number of conductor layers on the wall of the opening in the passivation layer and the passivation layer, the first conductor layer includes a metal layer consisting only of metal, and the thickness of the second conductor layer is smaller than the thickness of the conductor layer The thickness of the first conductor layer and the third conductor layer, the passivation layer includes an inorganic filler and an insulating resin, and at least one of chemically reactive groups included in the insulating resin of the passivation layer is The metal assembled to the first conductor layer.