JP2011114079A - Semiconductor apparatus, semiconductor package, and method of manufacturing semiconductor apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To alleviate the stress to be added to a bump and the periphery thereof in a cooling process after a semiconductor apparatus and a substrate are connected. <P>SOLUTION: A semiconductor apparatus (chip 10) has an insulating film 9, an electrode pad (for example, an electrode pad body 1 and an adhesion layer 18) formed on a part of one side of the insulating film 9, and a coating insulating film 2 formed on one side of the insulating film 9 and to which an opening 2a for exposing the electrode pad is formed. Further, the semiconductor apparatus has a metal layer (for example, first and second barrier metals 4 and 5) formed to be in contact with the electrode pad via the opening 2a such that its periphery resides over the coating insulating film 2 outside the opening 2a, and a bump 6 provided on the metal layer. Furthermore, the semiconductor apparatus has an intervention layer (for example, an intervention metal layer 3) that is disposed between the part (a rising-up part 11) rising up over the coating insulating film 2 in the metal layer and the coating insulating film 2. The adhesion of the intervention layer with the coating insulating film 2 is weaker than that with the metal layer. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device, a semiconductor package, and a method for manufacturing a semiconductor device.

As a semiconductor device in which a semiconductor chip (hereinafter simply referred to as a chip) is mounted on a substrate, there is a type in which the chip and the substrate are electrically connected to each other via a bump (so-called flip chip connection). An example of this type of semiconductor device is FCBGA (Flip Chip Ball Grid Array).
In the semiconductor device having such a configuration, a stress due to a difference in thermal expansion coefficient between the chip and the substrate is applied to the bump.

A semiconductor device configured to relieve such stress is described in Patent Document 1, for example.
The semiconductor device includes a first insulating film formed on the electrode pad of the chip and having an opening, a second insulating film formed on the first insulating film and having an opening, and formed on the electrode pad and the first insulating film. And a bump which is provided on the base metal layer and electrically connects the base metal layer and the electrode land of the wiring board to each other.
In this semiconductor device, the diameter of the underlying metal layer is smaller than the diameter of the electrode pad and larger than the opening diameter of the first insulating film, and the opening diameter of the second insulating film is larger than the diameter of the underlying metal layer. Is also made up of large.
Furthermore, the gap between the chip and the wiring board is filled with underfill resin.
In Patent Document 1, since the opening diameter of the second insulating film surrounding the outer periphery of the bump is larger than the diameter of the base metal layer to which the bump is directly bonded, the gap between the base portion of the bump and the second insulating film is disclosed. There is a description that a relatively large gap can be secured, and the gap is sufficiently filled with the underfill resin. Further, in Patent Document 1, since the underfill resin is sufficiently filled in the gap, the stress relaxation effect by the underfill resin is sufficiently exerted, and as a result, cracks and peeling occur in the circuit portion around the electrode pad. There is a description that generation | occurrence | production of is suppressed.

JP 2009-064812 A

In the structure of Patent Document 1, it is considered that the stress relaxation effect of the underfill resin is exhibited after the underfill resin is filled.
However, the stress applied to the bumps is also generated in a process in which the chip and the substrate are connected by melting the bumps and then cooled to room temperature, that is, in a process before filling with the underfill resin.

Here, a mechanism in which stress is applied to the bumps in the step before filling with the underfill resin will be described.
First, when the chip and the substrate are connected by the bump at a temperature equal to or higher than the melting point of the bump, since the bump is in a molten state, even if the chip and the substrate are expanded by their respective thermal expansion coefficients, Some bumps are not stressed.
However, after that, when cooled to room temperature, the chip and the substrate shrink with their respective thermal expansion coefficients, but after the bumps become solid at the melting point, the difference between the thermal expansion coefficients of the chip and the substrate Stress is applied to the bump.
FIG. 8 is a diagram for explaining the adverse effects caused by the stress applied to the bumps 106 in the process in which the chip and the substrate (the substrate is not shown in the figure, but is located above FIG. 8) are contracted by cooling after the flip chip connection. It is sectional drawing and has shown the bump 106 and its periphery. A first barrier metal 104 and a second barrier metal 105 are formed under the bump 106, and the lower first barrier metal 104 is formed on the electrode pad 101 through an opening formed in the coating insulating film 102. It is connected.
FIG. 8 shows an example in which the first and second barrier metals 104 and 105 are N-SMD (Non-Soldermask Defined) types. In FIG. 8, the direction of arrow C is the direction of the center of the semiconductor package including the chip and the substrate.
In the process in which the chip and the substrate contract due to cooling, for example, stress is applied to the bump 106, the first barrier metal 104, and the second barrier metal 105 in the direction of peeling the first barrier metal 104 from the chip. Here, generally, as the material of the first and second barrier metals 104 and 105, a metal material such as Ti or Ta that has good adhesion to the coating insulating film 102 is used. For this reason, the first and second barrier metals 104 and 105 and the covering insulating film 102 behave integrally. Therefore, due to this stress, for example, cracks 107 may be generated from the end portions of the first and second barrier metals 104 and 105 to the covering insulating film 102 or the electrode pad 101 and further to the underlying wiring layer (not shown). Yes (FIG. 8 (a)). Alternatively, this stress may cause a crack 108 in the bump 106 (FIG. 8B).

  As described above, it is difficult to relieve the stress applied to the bump and its periphery in the cooling process after the chip (semiconductor device) and the substrate are connected.

The present invention includes an insulating film,
An electrode pad formed on a part of one surface of the insulating film;
A coating insulating film formed on the one surface and having an opening for exposing the electrode pad;
A metal layer formed so as to be in contact with the electrode pad through the opening and having a peripheral portion riding on the insulating film for coating outside the opening; and a bump provided on the metal layer;
An intervening layer interposed between the portion of the metal layer riding on the covering insulating film and the covering insulating film;
Have
The intervening layer is formed of a material whose adhesion to the covering insulating film is weaker than that of the metal layer.

According to this semiconductor device, the intervening layer is interposed between the portion of the metal layer that runs on the covering insulating film (hereinafter referred to as the riding-up portion) and the covering insulating film, and the intervening layer Is made of a material whose adhesion to the covering insulating film is weaker than that of the metal layer.
For this reason, when stress is applied to the bump, for example, an operation occurs in which the intervening layer is peeled off from the insulating film together with the rising portion of the metal layer, and the stress applied to the bump and its periphery can be relaxed.

The present invention also includes an insulating film,
An electrode pad formed on a part of one surface of the insulating film;
A coating insulating film formed on the one surface and having an opening for exposing the electrode pad;
A metal layer formed so as to be in contact with the electrode pad through the opening and having a peripheral portion riding on the insulating film for coating outside the opening; and a bump provided on the metal layer;
An intervening layer interposed between the portion of the metal layer riding on the covering insulating film and the covering insulating film;
Have
The intervening layer has a semiconductor device made of a material whose adhesion with the covering insulating film is weaker than that of the metal layer;
A substrate having a larger coefficient of thermal expansion than the semiconductor device;
Have
A semiconductor package is provided in which the semiconductor device is connected to the substrate through the bumps.

The present invention also includes a step of forming an electrode pad on a portion of one surface of the insulating film;
Forming a coating insulating film having an opening exposing the electrode pad on the one surface;
Forming an intervening layer at an edge of the opening on the insulating film for covering;
A metal layer is formed so as to be in contact with the electrode pad through the opening, and so that a peripheral portion of the metal layer runs on the coating insulating film outside the opening and covers the intervening layer. Process,
Have
The intervening layer is formed of a material whose adhesion to the covering insulating film is weaker than that of the metal layer.

  According to the present invention, it is possible to relieve the stress applied to the bump and its periphery during the cooling process after connecting the semiconductor device and the substrate.

It is a figure which shows the semiconductor device which concerns on embodiment, among these, (a) is sectional drawing of a bump and its periphery, (b) is a top view of an electrode pad. It is sectional drawing which shows a series of processes in the manufacturing method of the semiconductor device which concerns on embodiment. It is sectional drawing which shows a series of processes in the manufacturing method of the semiconductor device which concerns on embodiment. It is sectional drawing which shows a series of processes in the manufacturing method of the semiconductor device which concerns on embodiment. It is a series of process diagrams showing a method for mounting a semiconductor device according to an embodiment on a substrate. It is a series of process diagrams showing a method for mounting a semiconductor device according to an embodiment on a substrate. It is a figure explaining operation | movement of the semiconductor device which concerns on embodiment, and shows the cross section of a bump and its periphery. It is a figure for demonstrating the bad effect by the stress added to a bump in the process in which a chip | tip and a board | substrate shrink | contract by the cooling after flip-chip connection, and shows the cross section of a bump and its periphery.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same components are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

[First Embodiment]
1A and 1B are diagrams showing a semiconductor device (semiconductor chip 10; hereinafter simply referred to as a chip 10) according to the embodiment, in which (a) is a sectional view of the bump 6 and its periphery, and (b) is a plan view.
In addition, Fig.1 (a) is AA arrow sectional drawing of FIG.1 (b).
In FIG. 1B, the illustration of the bump 6 is omitted. In FIG. 1B, the intervening metal layer 3 is actually hidden behind the second barrier metal 5 (and the first barrier metal 4), but the arrangement region of the intervening metal layer 3 is easy to understand. It is shaded.

The semiconductor device (chip 10) according to the present embodiment includes an insulating film 9 and electrode pads (for example, the electrode pad main body 1 and the adhesion layer 18) formed on a part of one surface of the insulating film 9. ) And a covering insulating film 2 formed on one surface of the insulating film 9 and having an opening 2a for exposing the electrode pad.
Further, the chip 10 is formed so as to be in contact with the electrode pad through the opening 2a, and a metal layer (for example, the first and second barrier metals) whose peripheral part runs on the coating insulating film 2 outside the opening 2a. 4 and 5) and bumps 6 provided on the metal layer.
Further, the chip 10 includes an intervening layer (for example, an intervening metal layer 3) interposed between a portion of the metal layer that rides on the coating insulating film 2 (climbing portion 11) and the coating insulating film 2. )have.
The intervening layer is made of a material whose adhesion to the covering insulating film 2 is weaker than that of the metal layer.
Details will be described below.

The chip 10 according to the present embodiment includes, for example, an element such as a transistor formed on one surface (circuit formation surface) side of a substrate (not shown), and a multilayer wiring layer formed on the circuit formation surface of the substrate. And have. The multilayer wiring layer has a plurality of electrode pad bodies 1 on the uppermost layer. For example, the electrode pad main body 1 is arranged along the four outer peripheral sides of the chip 10 or arranged in a matrix on the entire surface of the chip 10. The electrode pad body 1 can be made of Al, Al alloy, Cu, Cu alloy, or the like.
On the electrode pad main body 1, an adhesion layer 18 having a strong adhesion such as TiN and an insulating thin film 19 such as SiON having an opening 19 a for exposing the adhesion layer of the electrode pad are provided.
Further, the chip 10 is formed on, for example, a multilayer wiring layer, and a plurality of metal layers (configured by the first barrier metal 4 and the second barrier metal 5) that are electrically connected to the electrode pads, respectively. And bumps 6 respectively provided on these metal layers.
The chip 10 can be mounted on the substrate 20 (see FIGS. 5 and 6) via the bumps 6 by so-called flip chip connection.

Further, an insulating film 9 is interposed between the electrode pad main body 1 and a wiring (not shown) that is one layer lower than the electrode pad main body 1. The insulating film 9 can be made of, for example, SiO ₂ .
A coating insulating film (chip cover film) 2 is formed on the insulating thin film 19. The covering insulating film 2 is formed with a plurality of openings 2a for exposing at least a part of the adhesion layer 18 of each electrode pad. The size of the opening of the covering insulating film 2 can be the same as or larger than the opening 19 a of the insulating thin film 19. The opening 2a is inclined in a mortar shape so as to spread upward, for example.

First and second barrier metals 4 and 5 serving as bases for the bumps 6 are formed in the opening 2a and the peripheral edge thereof. The first barrier metal 4 is formed so as to be in contact with the electrode pad through the opening 2a, and the peripheral portion of the first barrier metal 4 runs on the insulating film 2 for coating outside the opening 2a. On the first barrier metal 4, for example, a second barrier metal 5 is formed in the same range as the first barrier metal 4.
The materials of the first and second barrier metals 4 and 5 will be described later.
Note that the metal layer climbing portion 11 constituted by the first and second barrier metals 4 and 5 runs on the coating insulating film 2 outside the opening 2a.

Further, the chip 10 has an intervening metal layer 3 interposed between the metal layer riding portion 11 and the covering insulating film 2. The intervening metal layer 3 is made of a material that has a weaker adhesive force (adhesive force per unit area) with the coating insulating film 2 than that with the metal layer (for example, the first barrier metal 4). That is, the adhesion force (adhesion force per unit area) between the intervening metal layer 3 and the covering insulating film 2 is greater than the adhesion force between the first barrier metal 4 and the interposition metal layer 3 (adhesion force per unit area). weak.
The intervening metal layer 3 can be made of a metal material other than Ti and Ta having good adhesion to the coating insulating film 2. Specifically, for example, the intervening metal layer 3 is preferably made of at least one of Al, Cu, Al alloy, and Cu alloy that are easy to process.

Further, bumps 6 are provided on the metal layer (for example, on the second barrier metal 5). The bump 6 is made of, for example, lead-free solder or other solder.
The bump 6 is preferably in contact with the outer peripheral end face of the metal layer (first and second barrier metals 4 and 5), for example.
Furthermore, it is more preferable that the bump 6 is in contact with the outer peripheral end surface of the intervening metal layer 3, for example.

  The planar shapes of the metal layers (first and second barrier metals 4 and 5) and the intervening metal layer 3 are arbitrary, such as polygonal and circular, but for example, as shown in FIG. it can. That is, in the example of FIG. 1, the shape of the opening 2 a of the covering insulating film 2, the shape of the opening 19 a of the insulating thin film 19, the outer peripheral shape of the first barrier metal 4, the outer peripheral shape of the second barrier metal 5, and the intervening metal layer 3. The outer peripheral shape and the inner peripheral shape of the intervening metal layer 3 are octagonal.

  Next, a method for manufacturing the semiconductor device according to the embodiment will be described. 2 to 4 are sectional views showing a series of steps for explaining this manufacturing method.

The manufacturing method of the semiconductor device according to the present embodiment includes a step of forming an electrode pad on a part of one surface of the insulating film 9 and a coating having an opening 2a exposing the electrode pad on one surface of the insulating film 9. Forming the insulating film 2 for use.
Further, this manufacturing method includes a step of forming an intervening layer (for example, intervening metal layer 3) at the edge of the opening 2a on the covering insulating film 2.
Furthermore, this manufacturing method includes a step of forming a metal layer (for example, composed of the first and second barrier metals 4 and 5). In this step, the metal layer is in contact with the electrode pad through the opening 2a, and the peripheral portion of the metal layer runs on the coating insulating film 2 outside the opening 2a to cover the intervening layer. A metal layer is formed.
The intervening layer is formed of a material whose adhesion to the covering insulating film 2 is weaker than that of the metal layer.
Details will be described below.

  First, the electrode pad body 1 is formed on the insulating film 9. A film of a material (for example, Al, Al alloy, Cu, and Cu alloy) of the electrode pad main body 1 is formed on the insulating film 9 by about 1 μm, for example, by sputtering. Next, a mask pattern (not shown) that covers a portion where the electrode pad body 1 is formed is formed on the material film of the electrode pad body 1. That is, after forming a photosensitive resist film, the resist film is exposed and developed to form a mask pattern. Next, after etching the material film of the electrode pad body 1 using this mask pattern as a mask, the electrode pad body 1 is formed by removing the mask pattern.

  Thereafter, an adhesion layer 18 (for example, TiN) is similarly formed on the electrode pad body 1. The thickness of the adhesion layer 18 is about 200 nm, and the dimensions are the same as or slightly larger than those of the electrode pad body 1.

  Next, an insulating thin film 19 such as SiON is formed in the same manner. The insulating thin film 19 has a thickness of about 300 nm and has an opening 19 a that exposes the adhesion layer 18 on the electrode pad body 1, and rides on the peripheral edge of the adhesion layer 18.

  Next, a coating insulating film 2 made of photosensitive polyimide or the like is formed. Further, an opening 2a for forming a metal layer is formed in the covering insulating film 2 by exposure and development. Thereafter, a heat treatment at about 350 ° C. is performed to cure the coating insulating film 2 (FIG. 2A).

  Next, an intervening metal layer 3 made of a metal material having a weak adhesion with the coating insulating film 2 such as Cu is formed on the coating insulating film 2, the insulating thin film 19, and the electrode pad adhesion layer 18. The intervening metal layer 3 is formed to a thickness of about 30 nm by, for example, sputtering. Next, a mask pattern 12 is formed on the intervening metal layer 3 to cover a portion where the metal layer run-up portion 11 (see FIG. 1) is formed in the subsequent process. That is, after forming a photosensitive resist film, the mask pattern 12 is formed by exposing and developing the resist film (FIG. 2B).

  Next, the intervening metal layer 3 is etched using the mask pattern 12 as a mask, so that the intervening metal layer 3 remains in the formation range of the landing portion 11 (see FIG. 1). Next, the mask pattern 12 is removed (FIG. 2C).

  Next, the first barrier metal 4 as a seed layer of the second barrier metal 5 is formed on the covering insulating film 2, the intervening metal layer 3, the insulating thin film 19, and the electrode pad adhesion layer 18, for example, by sputtering. To do. The first barrier metal 4 is, for example, a laminated structure of a TiW film, a Ti film formed on the TiW film, and a Cu film formed on the Ti film. The film thicknesses of the TiW film, Ti film, and Cu film are, for example, about 200 nm, about 30 nm, and about 300 nm, respectively (FIG. 3A).

  Next, a mask pattern 13 having an opening 13 a corresponding to the formation range of the second barrier metal 5 (see FIG. 1) is formed on the first barrier metal 4. The method for forming the mask pattern 13 is the same as the method for forming the mask pattern 12 (FIG. 3B).

  Next, the second barrier metal 5 is formed on the first barrier metal 4 by electrolytic plating using the mask pattern 13 as a mask. The second barrier metal 5 is, for example, a laminated structure of a Ni film and a Cu film formed on the Ni film. The Ni film has a thickness of, for example, about 3 μm, and the Cu film has a thickness of, for example, about 300 nm (FIG. 3C).

  Next, after removing the mask pattern 13, a mask pattern 14 is formed so as to cover the second barrier metal 5. The formation method of the mask pattern 14 is the same as the formation method of the mask patterns 12 and 13 (FIG. 4A).

  Next, using the mask pattern 14 as a mask, the first barrier metal 4 exposed from the mask pattern 14 is removed by etching. Next, the mask pattern 14 is removed (FIG. 4B).

  Next, a solder paste (not shown) is formed on the second barrier metal 5 by, for example, a printing method, and after heating and melting, flux cleaning is performed to form bumps 6. The bump 6 is, for example, solder containing Pb and Sn, or solder containing Sn, Ag, and Cu. Specifically, for example, the former solder contains 5% by weight of Sn and the balance is Pb, and the latter solder contains 3% by weight of Ag and 0.5% by weight of Cu. And the remainder of them is Sn (FIG. 4C).

  In this way, the chip 10 can be manufactured.

Next, a method for manufacturing the semiconductor package (semiconductor module) 30 by flip-chip mounting the chip 10 on the substrate (wiring substrate) 20 will be described with reference to FIGS.
5 and 6 are a series of process diagrams showing a method of mounting the chip 10 on the substrate 20.
5, (a), (c), and (e) are plan views, (b) is a sectional view taken along the line BB in (a), and (d) is a view taken along the line BB in (c). Sectional drawing and (f) are BB arrow sectional drawings of (e). Similarly, in FIG. 6, (a) and (c) are plan views, (b) is a cross-sectional view taken along the line BB in (a), and (d) is a cross-sectional view taken along the line BB in (c). is there.
5 and 6, the top and bottom of the chip 10 are reversed from those in FIGS. 1 and 4.

The semiconductor package 30 according to the present embodiment includes the chip 10 according to the present embodiment as described above and the substrate 20 having a larger thermal expansion coefficient than the chip 10, and the chip 10 is a substrate via the bumps 6. 20 is connected.
Details will be described below.

  The chip 10 is mounted on the substrate 20 by a known mounting machine (not shown). First, for example, the chip 10 and the substrate 20 are placed with the circuit forming surface (the surface on which the bump 6 is provided) of the chip 10 on which flux (not shown) is applied to the tip of the bump 6 facing the substrate 20 side. They are arranged opposite to each other (FIGS. 5A and 5B).

  Next, for example, the chip 10 is lowered relative to the substrate 20 by the mounting machine, and the substrate 20 and the chip 10 are pressed against each other via the bumps 6. At this time, the bumps 6 are brought into contact with electrode pads (both not shown) on the wiring of the substrate 20. Then, for example, the substrate 20 and the chip 10 are heated so that the bump 6 has a temperature equal to or higher than the melting point. As a result, the chip 10 is flip-chip connected to the substrate 20 via the bumps 6 (FIGS. 5C and 5D).

Due to the heating at the time of mounting, as shown in FIGS. 5C and 5D, the chip 10 and the substrate 20 are thermally expanded. Here, in general, since the substrate 20 has a larger coefficient of thermal expansion than the chip 10, as shown in FIGS. 5C and 5D, the substrate 20 is more heated than the chip 10 during heating. The rate of expansion is large.
However, when the bump 6 is at a temperature equal to or higher than the melting point, the bump 6 is in a molten state. Therefore, even if the chip 10 and the substrate 20 are expanded by their respective thermal expansion coefficients, No stress is applied.

Thereafter, when the chip 10 and the substrate 20 are cooled to room temperature, the chip 10 and the substrate 20 are contracted to a size before heating (FIGS. 5E and 5F).
In this cooling process, the chip 10 and the substrate 20 contract at their respective thermal expansion coefficients. Therefore, after the bump 6 becomes solid at the melting point, the stress due to the difference in the thermal expansion coefficient between the chip 10 and the substrate 20 is bumped. Join 6
As described above, since the substrate 20 generally has a larger thermal expansion coefficient than the chip 10, if the chip 10 is on the upper side in the stage after cooling, the substrate 20 exhibits a convex warp upward. .

Next, the gap between the chip 10 and the substrate 20 is filled with the underfill resin 15 and cured by heating or the like (FIGS. 6A and 6B).
Next, a BGA (Ball Grid Array) ball 16 is formed on the surface of the substrate 20 opposite to where the chip 10 is provided.
Thereafter, if necessary, each semiconductor package 30 is separated into pieces by cutting the substrate 20 by dicing. Thereby, the semiconductor package 30 shown in FIGS. 6C and 6D can be obtained.
If necessary, the chip 10 and the underfill resin 15 may be sealed with a sealing resin (not shown) after the underfill resin 15 is filled and cured. This sealing may be performed so as to cover the upper surface of the chip 10 or may be performed so that the upper surface of the chip 10 is exposed.

Next, the operation of this embodiment will be described.
FIG. 7 is a view for explaining the operation of the chip 10 according to the embodiment, and shows a cross section of the bump 6 and its periphery. In FIG. 7, the arrow C direction is the central direction of the semiconductor package 30.

As described above, in the cooling process after the chip 10 is flip-chip mounted on the substrate 20 (the process from FIG. 5C and FIG. 5D to FIG. 5E and FIG. 5F), the chip 10 and the substrate Stress due to the difference in thermal expansion coefficient from 20 is applied to the bump 6. Further, as described above, since the substrate 20 generally has a larger thermal expansion coefficient than the chip 10, the chip 10 is on the upper side in the stage after cooling (stages (e) and (f) in FIG. 5). Then, the board | substrate 20 exhibits a convex curvature.
Therefore, specifically, for example, in each bump 6, stress in a direction in which the bump 6 and the electrode pad are peeled from the chip 10 is applied to the end portion far from the center of the semiconductor package 30.
Under such circumstances, the chip 10 according to the present embodiment includes an intervening metal layer 3 interposed between the riding-up portion 11 of the first and second barrier metals 4 and 5 and the covering insulating film 2. have. The intervening metal layer 3 has weaker adhesion with the covering insulating film 2 than that with the first barrier metal 4.
For this reason, for example, as shown in FIG. 7, the intervening metal layer 3 is integrally formed with the bump 6 and the riding-up portion 11 due to the stress applied to the bump 6 in the cooling process after the chip 10 is flip-chip mounted on the substrate 20. Peel from the covering insulating film 2. A clearance 17 having a size corresponding to the stress is formed between the covering insulating film 2 and the intervening metal layer 3.
That is, by causing such peeling and clearance 17, stress acts on the bump 6, the coating insulating film 2, the adhesion layer 18, the electrode pad main body 1, or the wiring (not shown) underneath. Can be suppressed, and damage to them can be suppressed.

According to the embodiment as described above, there is an intervening metal between the climbing portion 11 riding on the coating insulating film 2 in the first and second barrier metals 4 and 5 and the coating insulating film 2. Layer 3 is interposed. The intervening metal layer 3 is made of a material whose adhesion to the covering insulating film 2 is weaker than that of the first barrier metal 4.
For this reason, when stress is applied to the bump 6, for example, an operation occurs in which the intervening metal layer 3 is peeled off from the covering insulating film 2 together with the riding-up portion 11, and the stress applied to the bump 6 and its periphery can be relaxed.
Therefore, it is possible to suppress the occurrence of damage such as cracks in the bump 6 and its periphery.

  Since the bumps 6 are in contact with the outer peripheral end faces of the metal layers (first and second barrier metals 4 and 5), the integrity of the bumps 6 and the metal layers can be improved. Therefore, the possibility of cracks occurring between the bumps 6 and the metal layer can be reduced, and peeling at the interface between the intervening metal layer 3 and the coating insulating film 2 can be easily caused. Furthermore, when the bump 6 is also in contact with the outer peripheral end surface of the intervening metal layer 3, the integrity of the bump 6 and the metal layer can be further enhanced, and these effects can be further enhanced.

In the above embodiment, the example in which the intervening layer is the intervening metal layer 3 has been described. However, the present invention is not limited to this example, and the intervening layer may be, for example, an organic film containing siloxane or a fluororesin (Teflon (registered trademark)). Etc.).
In the above embodiment, the example in which the metal layer serving as the base of the bump 6 is composed of two metal layers (first and second barrier metals 4 and 5) has been described. You may comprise by a layer or you may comprise by one metal layer.

DESCRIPTION OF SYMBOLS 1 Electrode pad main body 2 Covering insulating film 2a Opening 3 Intervening metal layer 4 1st barrier metal 5 2nd barrier metal 6 Bump 9 Insulating film 10 Semiconductor chip 11 Riding part 12 Mask pattern 13 Mask pattern 13a Opening 14 Mask pattern 15 Underfill Resin 16 BGA ball 17 Clearance 18 Adhesion layer 19 Insulating thin film 19a Opening 20 Substrate 30 Semiconductor package 101 Electrode pad 102 Covering insulating film 104 First barrier metal 105 Second barrier metal 106 Bump 107 Crack 108 Crack

Claims (7)

An insulating film;
An electrode pad formed on a part of one surface of the insulating film;
A coating insulating film formed on the one surface and having an opening for exposing the electrode pad;
A metal layer formed so as to be in contact with the electrode pad through the opening and having a peripheral portion riding on the insulating film for coating outside the opening; and a bump provided on the metal layer;
An intervening layer interposed between the portion of the metal layer riding on the covering insulating film and the covering insulating film;
Have
The semiconductor device is characterized in that the intervening layer is made of a material whose adhesion to the covering insulating film is weaker than that of the metal layer.   The semiconductor device according to claim 1, wherein the intervening layer is made of metal.   The semiconductor device according to claim 2, wherein the metal constituting the intervening layer is at least one of Al, Cu, an Al alloy, and a Cu alloy.   The semiconductor device according to claim 1, wherein the bump is in contact with an outer peripheral end surface of the metal layer.   The semiconductor device according to claim 4, wherein the bump is also in contact with an outer peripheral end surface of the intervening layer. An insulating film;
An electrode pad formed on a part of one surface of the insulating film;
A coating insulating film formed on the one surface and having an opening for exposing the electrode pad;
A metal layer formed so as to be in contact with the electrode pad through the opening and having a peripheral portion riding on the insulating film for coating outside the opening; and a bump provided on the metal layer;
An intervening layer interposed between the portion of the metal layer riding on the covering insulating film and the covering insulating film;
Have
The intervening layer has a semiconductor device made of a material whose adhesion with the covering insulating film is weaker than that of the metal layer;
A substrate having a larger coefficient of thermal expansion than the semiconductor device;
Have
A semiconductor package, wherein the semiconductor device is connected to the substrate through the bumps. Forming an electrode pad on a portion of one surface of the insulating film;
Forming a coating insulating film having an opening exposing the electrode pad on the one surface;
Forming an intervening layer at an edge of the opening on the insulating film for covering;
A metal layer is formed so as to be in contact with the electrode pad through the opening, and so that a peripheral portion of the metal layer runs on the coating insulating film outside the opening and covers the intervening layer. Process,
Have
The method of manufacturing a semiconductor device, wherein the intervening layer is formed of a material whose adhesion to the covering insulating film is weaker than that of the metal layer.

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