TWI658546B - Fan-out semiconductor package - Google Patents

Fan-out semiconductor package Download PDF

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Publication number
TWI658546B
TWI658546B TW106105515A TW106105515A TWI658546B TW I658546 B TWI658546 B TW I658546B TW 106105515 A TW106105515 A TW 106105515A TW 106105515 A TW106105515 A TW 106105515A TW I658546 B TWI658546 B TW I658546B
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TW
Taiwan
Prior art keywords
layer
fan
semiconductor package
redistribution layer
disposed
Prior art date
Application number
TW106105515A
Other languages
Chinese (zh)
Other versions
TW201803046A (en
Inventor
金恩實
李斗煥
邊大亭
高泰昊
金暎阿
Original Assignee
三星電機股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to ??10-2016-0036258 priority Critical
Priority to KR20160036258 priority
Priority to KR20160083565 priority
Priority to ??10-2016-0083565 priority
Priority to ??10-2016-0107713 priority
Priority to KR1020160107713A priority patent/KR101999625B1/en
Application filed by 三星電機股份有限公司 filed Critical 三星電機股份有限公司
Publication of TW201803046A publication Critical patent/TW201803046A/en
Application granted granted Critical
Publication of TWI658546B publication Critical patent/TWI658546B/en

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Abstract

A fan-out type semiconductor package may include: a first interconnecting member having a through hole; and a semiconductor wafer disposed in the through hole of the first interconnecting member and having an active surface and a surface opposite to the active surface. A passive surface with a connection pad disposed on the active surface; an encapsulation body encapsulating at least some portions of the first interconnecting member and at least some portions of the passive surface of the semiconductor wafer; a second interaction A connection member is disposed on the first interconnection member and the active surface of the semiconductor wafer; and a reinforcing layer is disposed on the encapsulation body. The first interconnection member and the second interconnection member each include a redistribution layer, and the redistribution layer is electrically connected to the connection pad of the semiconductor wafer.

Description

Fan-out semiconductor package [Cross Reference to Related Applications]

This application claims the priority of Korean Patent Application No. 10-2016-0036258, filed with the Korean Intellectual Property Office on March 25, 2016, and South Korea, which filed with the Korean Intellectual Property Office on July 1, 2016 Priority of Patent Application No. 10-2016-0083565 and Priority of Korean Patent Application No. 10-2016-0107713 filed at the Korean Intellectual Property Office on August 24, 2016, each of which is described in Korean Patent Application The full disclosure of the case is incorporated in this case for reference.

The present invention relates to a semiconductor package, and more particularly, to a fan-out type semiconductor package in which connection terminals can extend outside a region in which a semiconductor wafer is placed.

A recent significant trend in technological developments related to semiconductor wafers is the reduction in the size of semiconductor wafers. Therefore, in the case of packaging technology, with the rapid increase in demand for small-sized semiconductor wafers, etc., it has been necessary to implement it to include multiple pins At the same time, it has a compact semiconductor package.

One packaging technology proposed to meet the above technical requirements is a fan-out package. Such a fan-out type package has a compact size and can implement a plurality of pins by rewiring the connection terminals outside the area where the semiconductor wafer is placed.

Aspects of the present invention can provide a fan-out type semiconductor package in which a warpage problem can be effectively solved.

According to an aspect of the present invention, it is possible to provide a fan-out type semiconductor package in which a reinforcing layer capable of controlling warpage of the fan-out type semiconductor package is attached to an encapsulant that encapsulates a semiconductor wafer.

According to an aspect of the present invention, a fan-out semiconductor package may include: a first interconnection member having a through hole; and a semiconductor wafer disposed in the through hole of the first interconnection member and having An active surface and a passive surface opposite to the active surface, a connection pad is disposed on the active surface; an encapsulation body encapsulating at least some portions of the first interconnection member and the passive surface of the semiconductor wafer At least some portions of the surface; a second interconnecting member disposed on the first interconnecting member and on the active surface of the semiconductor wafer; and a reinforcing layer disposed on the encapsulation body. The first interconnection member and the second interconnection member each include a redistribution layer, and the redistribution layer is electrically connected to the connection pad of the semiconductor wafer.

100‧‧‧ semiconductor package

100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, 100J, 2100‧‧‧fan-out semiconductor packages

110, 510‧‧‧ first interconnecting member

110H, 510H‧‧‧through hole

111a‧‧‧First insulation layer

111b‧‧‧Second insulation layer

111c‧‧‧Third insulation layer

112a‧‧‧First redistribution layer

112b‧‧‧Second redistribution layer

112c‧‧‧ Third wiring layer

112d‧‧‧Fourth wiring layer

113a‧‧‧First interlayer window

113b‧‧‧Second interlayer window

120, 520, 2120, 2220‧‧‧ semiconductor wafers

121, 521, 1101, 2121, 2221‧‧‧ main body

122, 2122, 2222‧‧‧ connecting pad

123, 150, 2150, 2223, 2250‧‧‧

130, 530, 540, 2130 ‧ ‧ capsules

140‧‧‧Second interconnecting component

141a, 141b, 511, 2141, 2241‧‧‧ insulating layer

142, 142a, 142b, 512a, 512b, 2142‧‧‧ Redistribution layer

143a, 143b, 513, 2143, 2243

150H, 181H, 182H, 185H, 2251‧‧‧ opening

160, 2160, 2260‧‧‧ metal layer under bump

170‧‧‧connection terminal

181, 183, 184, 185, 186‧‧‧reinforcement

182‧‧‧resin layer

183P, 184P, 186P‧‧‧ Curved part

184a‧‧‧One side of reinforcement layer 184

184b‧‧‧ the other side of the reinforcement layer 184

184c‧‧‧Core Materials

301‧‧‧ carrier film

302, 303‧‧‧metal layer

304‧‧‧ dry film

305‧‧‧adhesive film

522‧‧‧electrode pad

1000‧‧‧ electronic device

1010, 1110, 2500‧‧‧ Motherboard

1020‧‧‧Chip-related components

1030‧‧‧Network related components

1040‧‧‧Other components

1050, 1130‧‧‧ Camera Module

1060‧‧‧antenna

1070‧‧‧Display device

1080‧‧‧ battery

1090‧‧‧Signal line

1100‧‧‧Smartphone

1120‧‧‧Electronic components

2140, 2240‧‧‧ interconnecting components

2170, 2270‧‧‧solder ball

2200‧‧‧fan-in semiconductor package

2242‧‧‧ Redistribution Layer

2243h‧‧‧Interlayer window

2280‧‧‧ underfill resin

2290‧‧‧Molding material

2301, 2302‧‧‧ interposer

t1, t2, t3‧‧‧thickness

W1, W2‧‧‧Warping

I-I'‧‧‧ line

The above and other aspects, features, and advantages of the present invention will be more clearly understood by reading the following detailed description in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic block diagram illustrating an example of an electronic device system.

FIG. 2 is a schematic perspective view illustrating an example of an electronic device.

3A and 3B are schematic cross-sectional views illustrating states of a fan-in semiconductor package before and after being packaged.

FIG. 4 is a schematic cross-sectional view illustrating a packaging process of a fan-in semiconductor package.

5 is a schematic cross-sectional view illustrating a situation in which a fan-in semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic device.

FIG. 6 is a schematic cross-sectional view illustrating a case where a fan-in type semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic device.

FIG. 7 is a schematic cross-sectional view illustrating a fan-out type semiconductor package.

8 is a schematic cross-sectional view illustrating a situation in which a fan-out type semiconductor package is mounted on a main board of an electronic device.

FIG. 9 is a schematic cross-sectional view illustrating an example of a fan-out type semiconductor package.

FIG. 10 is a schematic plan view taken along a line I-I 'of the fan-out type semiconductor package shown in FIG. 9.

11A to 11D are schematic cross-sectional views illustrating various forms of a via window formed in a first interconnection member of the fan-out type semiconductor package shown in FIG. 9.

12 to 16 are diagrams illustrating an example of a process of manufacturing the fan-out type semiconductor package shown in FIG. 9.

FIG. 17 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

FIG. 18 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

FIG. 19 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

FIG. 20 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

FIG. 21 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

22 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

FIG. 23 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

FIG. 24 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

FIG. 25 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

FIG. 26 is a schematic diagram illustrating a situation in which warpage occurs in a fan-out type semiconductor package.

FIG. 27 is a schematic diagram illustrating a case in which warpage of a fan-out type semiconductor package is suppressed.

FIG. 28 is a diagram illustrating other problems occurring in FIG. 27.

FIG. 29 is a graph for comparing the effects of suppressing warpage between the fan-out semiconductor packages.

Hereinafter, exemplary embodiments in the present invention will be explained with reference to the drawings. In the drawings, the shape, size, etc. of each component may be exaggerated or omitted for clarity.

The term "exemplary embodiment" used herein does not refer to the same exemplary embodiment, but is provided to emphasize a particular feature or characteristic that is different from a particular feature or characteristic of another exemplary embodiment. However, the exemplary embodiments provided herein are considered to be able to be implemented by being combined with each other in whole or in part. For example, even if an element set forth in a particular exemplary embodiment is not set forth in another exemplary embodiment, the element can be understood as a contrary unless a contrary or contradictory description is provided herein. A description related to another exemplary embodiment.

In the description, the meaning of "connection" between one component and another component includes an indirect connection through a third component and a direct connection between two components. In addition, "electrical connection" means the concept of physical connection and physical disconnection. It should be understood that when an element is referred to by "first" and "second", the element is not limited thereby. The use of "first" and "second" may only be used to combine the described components with Other elements are distinguished for purposes and may not limit the order or importance of the elements. In some cases, a first element may be referred to as a second element without departing from the scope of the patentable scope set forth herein. Similarly, the second element may also be referred to as the first element.

Herein, the upper part, the lower part, the upper side, the lower side, the upper surface, the lower surface, and the like are determined in the drawings. For example, the first interconnection member is disposed at a level higher than the height of the heavy wiring layer. However, the scope of this application patent is not limited to this. In addition, the vertical direction refers to the above upward and downward directions, and the horizontal direction refers to the directions perpendicular to the above upward and downward directions. In this case, the vertical cross-section refers to a case of being taken along a plane in the vertical direction, and an example of the vertical cross-section may be a cross-sectional view shown in a drawing. In addition, the horizontal cross section refers to a case of being taken along a plane in the horizontal direction, and an example of the horizontal cross section may be a plan view shown in a drawing.

The terminology used herein is for the purpose of illustrating exemplary embodiments only and not limiting the present invention. In this case, the singular includes the plural unless otherwise explained in context.

Electronic device

FIG. 1 is a schematic block diagram illustrating an example of an electronic device system.

Referring to FIG. 1, a motherboard 1010 can be housed in the electronic device 1000. The motherboard 1010 may include a chip-related component 1020, a network-related component 1030, other components 1040, etc. that are physically connected or electrically connected to the motherboard 1010. These components can be connected to other components described below to form various signal lines 1090.

The chip-related component 1020 may include a memory chip such as a volatile memory (for example, dynamic random access memory (DRAM)), a non-volatile memory (for example, read only memory (read only) memory (ROM)), flash memory, etc .; application processor chips, such as a central processing unit (for example, a central processing unit (CPU)), a graphics processor (for example, a graphics processing unit (graphic processing unit, GPU)), digital signal processor, cryptographic processor, microprocessor, microcontroller, etc .; and logic chips, such as analog-to-digital (ADC) converters, application-specific integrated products Circuit (application-specific integrated circuit, ASIC), etc. However, the wafer-related component 1020 is not limited to this, and may include other types of wafer-related components. In addition, the wafer-related components 1020 may be combined with each other.

The network related component 1030 can be compatible with, for example, the following protocols: wireless fidelity (Wi-Fi) (Institute of Electrical And Electronics Engineers (IEEE) 802.11 family, etc.), global interoperable microwave access (worldwide interoperability for microwave access, WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high-speed packet access + ( high speed packet access + (HSPA +), high speed downlink packet access + (HSDPA +), high speed uplink packet access + (HSUPA +), enhanced data GSM environment (enhanced data GSM environment (EDGE), global system for mobile communications (GSM), global positioning system (GPS), general packet radio service (GPRS), code division multiple access (code division multiple access (CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G agreement, 4G agreement, and 5G agreement, and following the above Any other wireless and wire protocols specified after the agreement. However, the network related component 1030 is not limited to this, but may include various other wireless standards or protocols or wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020 described above.

Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC), electromagnetic interference (electromagnetic interference) , EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, other components 1040 are not limited to this, but may include passive components and the like used for various other purposes. In addition, other components 1040 may be combined with each other together with the chip-related component 1020 or the network-related component 1030 described above.

Depending on the type of the electronic device 1000, the electronic device 1000 may include other components that may be physically connected to or electrically connected to the motherboard 1010 or may be physically connected or not electrically connected to the motherboard 1010. These other components may include, for example, photography Machine module 1050, antenna 1060, display device 1070, battery 1080, audio codec (not shown in the figure), video codec (not shown in the figure), power amplifier (not shown in the figure), compass (Not shown), accelerometer (not shown), gyroscope (not shown), speaker (not shown), mass storage unit (e.g., hard drive) (Not shown), a compact disk (CD) drive (not shown), a digital versatile disk (DVD) drive (not shown), and the like. However, the other components are not limited to this, but the type of the electronic device 1000 and the like may also include other components for various purposes.

The electronic device 1000 can be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet PC, a laptop Personal computers, portable netbook PCs, televisions, video game machines, smart watches, car components, etc. However, the electronic device 1000 is not limited to this, but may be any other electronic device capable of processing data.

FIG. 2 is a schematic perspective view illustrating an example of an electronic device.

Referring to FIG. 2, the semiconductor package may be used in various electronic devices 1000 as described above for various purposes. For example, the motherboard 1110 may be housed in the main body 1101 of the smart phone 1100, and various electronic components 1120 may be physically connected to or electrically connected to the motherboard 1110. In addition, it may be physically connected or electrically connected to the main board 1110 or may not be physically connected or electrically connected to the main board 1110 Other components (for example, the camera module 1130) can be accommodated in the main body 1101. Some electronic components in the electronic component 1120 may be wafer-related components, and the semiconductor package 100 may be, for example, an application processor in a wafer-related component, but is not limited thereto. The electronic device need not be limited to the smart phone 1100, but may be other electronic devices as described above.

Semiconductor package

Generally speaking, many fine circuits are integrated in a semiconductor wafer. However, the semiconductor wafer itself cannot be used as a completed semiconductor product, and may be damaged due to external physical or chemical impact. Therefore, the semiconductor wafer cannot be used alone, but can be packaged in an electronic device or the like and used in a packaged state in the electronic device or the like.

Here, since there is a difference in circuit width between the semiconductor chip and the motherboard of the electronic device in terms of electrical connection, a semiconductor package is required. In detail, the size of the connection pads of the semiconductor wafer and the intervals between the connection pads of the semiconductor wafer are very fine, but the size of the component mounting pads of the motherboard and the component mounting pads of the motherboard are used in electronic devices. Respective intervals are significantly larger than the size of the connection pads of the semiconductor wafer and the intervals between the connection pads. Therefore, it may be difficult to directly mount the semiconductor wafer on the motherboard, and a packaging technology for buffering a difference in circuit width between the semiconductor wafer and the motherboard may be required.

The structure and purpose of the end-view semiconductor package, a semiconductor package manufactured using packaging technology can be divided into a fan-in semiconductor package and a fan-out semiconductor package.

The fan-in type semiconductor package and the fan-out type semiconductor package will be explained in more detail below with reference to the drawings.

Fan-in semiconductor package

3A and 3B are schematic cross-sectional views illustrating states of a fan-in semiconductor package before and after being packaged.

FIG. 4 is a schematic cross-sectional view illustrating a packaging process of a fan-in semiconductor package.

Referring to the drawings, the semiconductor wafer 2220 may be, for example, an integrated circuit (IC) in an exposed state. The semiconductor wafer 2220 includes a main body 2221 including silicon (Si), germanium (Ge), and gallium arsenide ( GaAs) and the like; connection pads 2222 formed on one surface of the main body 2221 and containing a conductive material such as aluminum (Al); and a protective layer 2223 such as an oxide film and a nitride film formed on one surface of the main body 2221 And covers at least some portions of the connection pad 2222. Here, since the connection pad 2222 is very small, it is difficult to mount an integrated circuit (IC) on a printed circuit board (PCB), a motherboard of an electronic device, or the like.

Therefore, depending on the size of the semiconductor wafer 2220, an interconnection member 2240 can be formed on the semiconductor wafer 2220 to rewire the connection pads 2222. The interconnection member 2240 can be formed by the following steps: forming an insulating layer 2241 on the semiconductor wafer 2220 using an insulating material such as a photoimagable dielectric (PID) resin; and forming a dielectric window hole for opening the connection pad 2222 2243h; and then a redistribution layer 2242 and a via window 2243 are formed. Then, can be formed A protective layer 2250 for protecting the interconnection member 2240, an opening 2251 can be formed, and a metal layer 2260 under the bump can be formed. That is, the fan-in type semiconductor package 2200 including, for example, the semiconductor wafer 2220, the interconnect member 2240, the protective layer 2250, and the under bump metal layer 2260 may be manufactured through a series of processes.

As described above, the fan-in type semiconductor package may have a package in which all connection pads of the semiconductor wafer, such as input / output (I / O) terminals, are placed in the semiconductor wafer The form can have excellent electrical characteristics and can be produced at low cost. Therefore, many components mounted in a smart phone have been manufactured in the form of a fan-in semiconductor package. In detail, many components installed in a smart phone have been developed to enable fast signal transfer while having a compact size.

However, since all input / output terminals need to be placed in a semiconductor wafer in a fan-in semiconductor package, the fan-in semiconductor package has a large space limitation. Therefore, it is difficult to apply this structure to a semiconductor wafer having a large number of input / output terminals or a semiconductor wafer having a compact size. In addition, due to the above disadvantages, the fan-in semiconductor package cannot be directly mounted and used on the motherboard of the electronic device. Here, even in a case where the size of the input / output terminals of the semiconductor wafer and the interval between the input / output terminals of the semiconductor wafer are increased by the rewiring process, the size of the input / output terminals of the semiconductor wafer and the The interval between the input / output terminals of the chip may still be insufficient to mount the fan-in semiconductor package directly on the motherboard of the electronic device.

FIG. 5 illustrates a case where a fan-in semiconductor package is mounted on an interposer substrate A schematic cross-sectional view of a state where the electronic device is finally installed on a main board of the electronic device.

FIG. 6 is a schematic cross-sectional view illustrating a case where a fan-in type semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic device.

Referring to the drawings, in the fan-in type semiconductor package 2200, the connection pads 2222 (ie, input / output terminals) of the semiconductor wafer 2220 may be rewired via the interposer substrate 2301, and the fan-in type semiconductor package 2200 may In a state of being mounted on the interposer substrate 2301, it is finally mounted on the main board 2500 of the electronic device. In this case, the solder balls 2270 and the like may be fixed by underfilling the resin 2280 and the like, and the outer surface of the semiconductor wafer 2220 may be covered with a molding material 2290 and the like. Alternatively, the fan-in semiconductor package 2200 may be embedded in a separate interposer substrate 2302, and the connection pads 2222 (ie, input / output terminals) of the semiconductor wafer 2220 may be embedded in the interposer 2200. In the state in the substrate 2302, redistribution is performed again through the interposer substrate 2302, and the fan-in semiconductor package 2200 can be finally mounted on the motherboard 2500 of the electronic device.

As described above, it may be difficult to directly mount and use a fan-in type semiconductor package on a motherboard of an electronic device. Therefore, the fan-in type semiconductor package can be mounted on a separate interposer substrate and then mounted on the main board of the electronic device by a packaging process, or can be mounted on the electronics in a state where the fan-in type semiconductor package is embedded in the interposer substrate. Install and use on the motherboard of the device.

Fan-out semiconductor package

FIG. 7 is a schematic cross-sectional view illustrating a fan-out type semiconductor package.

Referring to the drawings, in the fan-out semiconductor package 2100, for example, In other words, the outer surface of the semiconductor wafer 2120 may be protected by the encapsulation body 2130, and the connection pads 2122 of the semiconductor wafer 2120 may be re-routed outside the semiconductor wafer 2120 through the interconnection member 2140. In this case, a protective layer 2150 may be further formed on the interconnection member 2140, and an under bump metal layer 2160 may be further formed in the opening of the protective layer 2150. A solder ball 2170 may be further formed on the under bump metal layer 2160. The semiconductor wafer 2120 may be an integrated circuit (IC) including a main body 2121, a connection pad 2122, a protective layer (not shown in the figure), and the like. The interconnection member 2140 may include an insulating layer 2141, a redistribution layer 2142 formed on the insulating layer 2141, and a via window 2143 that electrically connects the connection pad 2122 and the redistribution layer 2142 to each other.

As described above, the fan-out type semiconductor package may have a form in which an input / output terminal of a semiconductor wafer is rewired and disposed outside the semiconductor wafer by an interconnection member formed on the semiconductor wafer. . As described above, in a fan-in type semiconductor package, all input / output terminals of a semiconductor wafer need to be placed in the semiconductor wafer. Therefore, when the size of the semiconductor wafer is reduced, it is necessary to reduce the size and pitch of the balls, making it impossible to use a standardized ball layout in a fan-in type semiconductor package. On the other hand, the fan-out type semiconductor package has a form in which the input / output terminals of the semiconductor wafer are rewired and placed outside the semiconductor wafer by the interconnection member formed on the semiconductor wafer as described above. Therefore, even in a case where the size of the semiconductor wafer is reduced, it is actually possible to use a standardized ball layout in a fan-out type semiconductor package, so that the fan-out type semiconductor package can be used without a separate interposer substrate It is installed on the motherboard of the electronic device under the conditions as described below.

8 is a schematic cross-sectional view illustrating a situation in which a fan-out type semiconductor package is mounted on a main board of an electronic device.

Referring to the drawings, the fan-out semiconductor package 2100 can be mounted on the motherboard 2500 of the electronic device through solder balls 2170 and the like. That is, as described above, the fan-out type semiconductor package 2100 includes the interconnection member 2140 formed on the semiconductor wafer 2120 and capable of rewiring the connection pad 2122 to a fan-out area outside the area of the semiconductor wafer 2120. This makes it possible to actually use a standardized ball layout in the fan-out type semiconductor package 2100. Therefore, the fan-out semiconductor package 2100 can be mounted on the motherboard 2500 of the electronic device without using a separate interposer or the like.

As described above, since the fan-out type semiconductor package can be mounted on a main board of an electronic device without using a separate interposer substrate, the fan-out type semiconductor package can be implemented to have a higher use than an interposer substrate. The thickness of the fan-in semiconductor package is small. Therefore, the fan-out semiconductor package can be miniaturized and thinned. In addition, the fan-out semiconductor package has excellent thermal and electrical characteristics, so that the fan-out semiconductor package is particularly suitable for mobile products. Therefore, the fan-out semiconductor package can be implemented in a more compact form than a general-purpose package-on-package (POP) type semiconductor package using a printed circuit board (PCB), and can solve the problem. Problems due to warping.

Meanwhile, the fan-out type semiconductor package refers to a method for mounting a semiconductor wafer on a motherboard of an electronic device or the like as described above and protecting the semiconductor wafer from External impact packaging technology, and the fan-out type semiconductor package is conceptually different from a fan-out type semiconductor package having a scale, purpose, etc. different from that of the fan-out type semiconductor package Printed circuit board (PCB) (for example, interposer, etc.).

Hereinafter, a fan-out type semiconductor package in which the warpage problem can be effectively solved will be explained with reference to the drawings.

FIG. 9 is a schematic cross-sectional view illustrating an example of a fan-out type semiconductor package.

FIG. 10 is a schematic plan view taken along a line I-I 'of the fan-out type semiconductor package shown in FIG. 9.

11A to 11D are schematic cross-sectional views illustrating various forms of a via window formed in a first interconnection member of the fan-out type semiconductor package shown in FIG. 9.

Referring to the drawings, a fan-out type semiconductor package 100A according to an exemplary embodiment of the present invention may include: a first interconnection member 110 having a through hole 110H; and a semiconductor wafer 120 disposed on the first interconnection member 110. The through hole 110H has an active surface and a passive surface opposite to the active surface, and a connection pad 122 is disposed on the active surface; an encapsulation body 130 encapsulates at least some parts of the first interconnection member 110 And at least some parts of the passive surface of the semiconductor wafer 120; the second interconnection member 140 is disposed on the first interconnection member 110 and the active surface of the semiconductor wafer 120; the reinforcing layer 181 is disposed on the encapsulation body 130; A resin layer 182 disposed on the reinforcing layer 181; and an opening 182H penetrating through the resin layer 182, the reinforcing layer 181, and the encapsulant 130 and exposing at least some portions of the third redistribution layer 112c of the first interconnection member 110 . The fan-out type semiconductor package according to an exemplary embodiment 100A may further include: a protective layer 150 disposed on the second interconnection member 140; a under bump metal layer 160 disposed in the opening 150H of the protection layer 150; and a connection terminal 170 disposed on the under bump metal layer 160. . The reinforcing layer 181 may have an elastic modulus larger than the elastic modulus of the encapsulation body 130, and may have a thermal expansion coefficient lower than the coefficient of thermal expansion (CTE) of the encapsulation body 130.

Meanwhile, as shown in FIG. 26, a thermosetting resin film that can firmly fix the first interconnection member 510, the semiconductor wafer 520, and the like may be used to form an encapsulation body 530 that encapsulates the first interconnection member 510, the semiconductor wafer 520, and the like. In detail, the encapsulation body 530 may be formed using a thermosetting resin film having a high thermal expansion coefficient, which generally has good resin fluidity, so that the space of the through hole 510H between the first interconnection member 510 and the semiconductor wafer 520 may be formed. The resin is completely filled and strengthens the close adhesion between the first interconnection member 510 and the semiconductor wafer 520. However, in such a thermosetting resin film, the thermal curing shrinkage of the resin is large, so that severe warpage W1 may occur in the package after the resin is cured. Therefore, it may be difficult to form a fine circuit pattern on the active surface of the semiconductor wafer 520 later.

Meanwhile, as shown in FIG. 27, in order to solve this problem, it may be considered to use a thermosetting resin film having a low thermal expansion coefficient to form the encapsulation body 540. In this case, as compared with a case where a thermosetting resin film having a high thermal expansion coefficient is used, warpage W2 can be suppressed. However, as shown in FIG. 28, in order to reduce the coefficient of thermal expansion, the content of the inorganic filler in the thermosetting resin film is generally increased, so that the resin may not be able to sufficiently fill the fine space due to the decrease in the fluidity of the resin, thereby leading to Cause the formation of voids and so on. In addition, delamination or the like may occur between the first interconnection member and the semiconductor wafer due to a decrease in the close adhesion between the first interconnection member and the semiconductor wafer.

On the other hand, as in the fan-out type semiconductor package 100A according to the exemplary embodiment, in the case where the reinforcing layer 181 having a relatively large elastic modulus or a relatively small thermal expansion coefficient is introduced, the reinforcing layer 181 may be The hardening shrinkage of the material (for example, the thermosetting resin film) of the encapsulation body 130 is suppressed, thereby making it possible to significantly reduce the occurrence of warpage of the fan-out type semiconductor package 100A after the material is hardened. Therefore, a material having a high thermal expansion coefficient can be used as a material of the encapsulation body 130. As a result, problems such as voids and delamination may not occur.

Meanwhile, in the fan-out type semiconductor package 100A according to the exemplary embodiment, the reinforcing layer 181 may include a glass cloth, an inorganic filler, and an insulating resin. In this case, it may not be easy to form an opening in the reinforcing layer 181. However, in the case where the resin layer 182 is disposed on the reinforcing layer 181, this problem can be solved. For example, a material that is the same as or similar to the material of the encapsulation body 130 (for example, an insulating material containing an inorganic filler and an insulating resin but not including a core material such as glass cloth (or glass fiber) (that is, flavor In the case of an Ajinomoto Build-up Film (ABF, etc.)) as the material of the resin layer 182, the opening 182H can be easily formed. The wiring exposed through the opening 182H can be used as a mark, a pad, or the like.

The respective components included in the fan-out type semiconductor package 100A according to the exemplary embodiment will be explained in more detail below.

The first interconnection member 110 may include a redistribution layer 112 a and a redistribution layer 112 b that re-route the connection pads 122 of the semiconductor wafer 120 to thereby reduce the number of layers of the second interconnection member 140. If necessary, the first interconnecting member 110 can maintain the rigidity of the fan-out semiconductor package 100A depending on the material of the encapsulation body 130 and is used to ensure the thickness uniformity of the encapsulation body 130. In some cases, the fan-out type semiconductor package 100A according to an exemplary embodiment may be used as a part of a stacked package semiconductor package due to the first interconnection member 110. The first interconnection member 110 may have a through hole 110H. A semiconductor wafer 120 may be disposed in the through hole 110H to be spaced a predetermined distance from the first interconnection member 110. A side surface of the semiconductor wafer 120 may be surrounded by the first interconnection member 110. However, this form is merely an example and various modifications may be made to the present invention to have other forms, and the fan-out type semiconductor package 100A may perform another function depending on this form.

The first interconnection member 110 may include: a first insulation layer 111a, which contacts the second interconnection member 140; a first redistribution layer 112a, which contacts the second interconnection member 140 and is embedded in the first insulation layer 111a; The wiring layer 112b is disposed on the other surface of the first insulating layer 111a opposite to the surface of the first insulating layer 111a in which the first redistribution layer 112a is embedded; the second insulating layer 111b is disposed on the first insulating layer 111a The second redistribution layer 112b is covered thereon; and the third redistribution layer 112c is disposed on the second insulating layer 111b. The first redistribution layer 112a, the second redistribution layer 112b, and the third redistribution layer 112c may be electrically connected to the connection pad 122. The first interconnection member 110 may include a first redistribution layer 112a and a second redistribution layer 112b, a second redistribution layer 112b, and a third redistribution layer that penetrate the first insulating layer 111a and the second insulating layer 112b, respectively. The layer 112c is electrically connected to the first interlayer window 113a and the second interlayer window 113b. As described above, since the first redistribution layer 112a is embedded, the insulation distance of the insulation layer 141a of the second interconnection member 140 may be substantially constant. Since the first interconnection member 110 may include a large number of redistribution layers 112a, 112b, and 112c, the second interconnection member 140 may be further simplified. Therefore, a decrease in the yield due to a defect occurring in the process of forming the second interconnection member 140 can be improved.

The case where the first interconnection member 110 includes two insulating layers 111a and 111b is illustrated in the drawings, but the number of the insulating layers constituting the first interconnection member 110 may be greater than two. In this case, the number of redistribution layers disposed in the first interconnection member 110 may increase, and additional via windows may be formed to connect the redistribution layers to each other.

The material of each of the insulating layer 111a and the insulating layer 111b is not particularly limited. For example, an insulating material may be used as a material of each of the insulating layer 111a and the insulating layer 111b. In this case, the insulating material may be: a thermosetting resin, such as an epoxy resin; a thermoplastic resin, such as a polyimide resin; wherein the thermosetting resin or the thermoplastic resin is dipped into, for example, a glass cloth (or glass) together with an inorganic filler. Resins in core materials such as prepreg, prepreg, ABF, FR-4, and Bisaleimide Triazine (BT). Alternatively, a photosensitive imaging dielectric (PID) resin may be used as the insulating material. The first insulating layer 111a and the second insulating layer 111b may include the same insulating material, and the boundary between the first insulating layer 111a and the second insulating layer 111b may not be obvious. However, the first insulating layer 111a and the second insulating layer 111b are not limited to this.

The redistribution layer 112a, redistribution layer 112b, and redistribution layer 112c may be used to redistribute the connection pads 122 of the semiconductor wafer 120, and the material of each of the redistribution layer 112a, redistribution layer 112b, and redistribution layer 112c The conductive material may be, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c may have various functions depending on the design of the corresponding layers. For example, the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal (S) pattern may include various signal patterns other than a ground (GND) pattern, a power (PWR) pattern, and the like, such as a data signal pattern. In addition, the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c may include a via window pad, a connection terminal pad, and the like. As a non-limiting example, both of the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c may include a ground pattern. In this case, the number of ground patterns formed on the redistribution layer 142a and the redistribution layer 142b of the second interconnection member 140 can be significantly reduced, and the degree of freedom in wiring design can be improved.

If necessary, a surface treatment layer (not shown in the figure) may be further formed on the third redistribution layer 112c exposed through the opening 182H. The surface treatment layer (not shown in the figure) is not particularly limited as long as the surface treatment layer is known in the related art, and the surface treatment layer may be formed by, for example, electrolytic gold plating or electroless plating. Gold, organic solderability preservative (OSP) Or electroless tin, electroless silver, electroless nickel / replacement gold, direct immersion gold (DIG) plating, hot air solder leveling (HASL), etc.

The vias 113 a and 113 b can electrically connect the redistribution layer 112 a, the redistribution layer 112 b, and the redistribution layer 112 c formed on different layers to each other, thereby forming an electrical path in the first interconnection member 110. . The material of each of the vias 113a and 113b may be a conductive material. As shown in FIGS. 11A to 11D, each of the vias 113a and 113b may be completely filled with a conductive material, or the conductive materials may be formed along the walls of the respective vias. In addition, each of the via window 113a and the via window 113b may have all shapes known in the related art, such as a tapered shape, a cylindrical shape, and the like. At the same time, as can be seen from the process explained below, when forming the holes of the via window 113a, some of the pads of the first redistribution layer 112a can serve as stoppers; and when the second via window is formed 113b, some of the pads of the second redistribution layer 112b may serve as stoppers, and therefore each of the first interlayer window 113a and the second interlayer window 113b has a width that is larger than that of the upper surface. It may be advantageous in a process with a wide tapered shape of the lower surface. In this case, the first via window 113a may be integrated with some portions of the second redistribution layer 112b, and the second via window 113b may be integrated with some portions of the third redistribution layer 112c.

The semiconductor wafer 120 may be an integrated circuit (IC) configured to integrate a number of hundreds to millions of elements or more in a single wafer. For example, the integrated circuit may be an application processor chip, such as a central processing unit (such as For example, a central processing unit), a graphics processor (for example, a graphics processing unit), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, etc., but it is not limited thereto. The semiconductor wafer 120 may be formed based on an active wafer. In this case, the base material of the main body 121 may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits can be formed on the main body 121. The connection pad 122 can electrically connect the semiconductor wafer 120 to other components. The material of the connection pad 122 may be a conductive material such as aluminum (Al). A protective layer 123 exposing the connection pad 122 may be formed on the main body 121, and the protective layer 123 may be an oxide film, a nitride film, or the like, or a double layer formed by an oxide layer and a nitride layer. With the protective layer 123, the lower surface of the connection pad 122 may have a stepped portion with respect to the lower surface of the encapsulation body 130. As a result, a phenomenon in which the encapsulation body 130 penetrates into the lower surface of the connection pad 122 can be prevented to some extent. An insulation layer (not shown in the figure) and the like may be further disposed in other required positions.

The passive surface of the semiconductor wafer 120 may be disposed at a level lower than an upper surface of the third redistribution layer 112 c of the first interconnection member 110. For example, the passive surface of the semiconductor wafer 120 may be disposed at a level lower than the upper surface of the second insulating layer 111 b of the first interconnection member 110. The height difference between the passive surface of the semiconductor wafer 120 and the upper surface of the third redistribution layer 112c of the first interconnection member 110 may be 2 micrometers (μm) or more, for example, 5 micrometers or more. In this case, it is possible to effectively prevent cracks from occurring in the corners of the passive surface of the semiconductor wafer 120. In addition, the deviation of the insulation distance on the passive surface of the semiconductor wafer 120 in the case where the encapsulation body 130 is used can be significantly reduced.

The second redistribution layer 112 b of the first interconnection member 110 may be disposed at a horizontal height between the active surface and the passive surface of the semiconductor wafer 120. The first interconnection member 110 may be formed to a thickness corresponding to the thickness of the semiconductor wafer 120. Therefore, the second redistribution layer 112 b formed in the first interconnection member 110 may be disposed at a level between the active surface and the passive surface of the semiconductor wafer 120.

The encapsulation body 130 may protect the first interconnection member 110 and / or the semiconductor wafer 120. The encapsulation form of the encapsulation body 130 is not particularly limited, but may be in a form in which the encapsulation body 130 surrounds at least some parts of the first interconnection member 110 and / or at least some parts of the semiconductor wafer 120. For example, the encapsulation body 130 may cover the passive surfaces of the first interconnection member 110 and the semiconductor wafer 120 and fill a space between the wall of the through hole 110H and the side surface of the semiconductor wafer 120. In addition, the encapsulation body 130 may also fill at least a part of the space between the protective layer 123 of the semiconductor wafer 120 and the second interconnection member 140. At the same time, the encapsulation body 130 may fill the through-hole 110H so as to view the material of the encapsulation body 130 as an adhesive and reduce buckling of the semiconductor wafer 120.

The material of the encapsulation body 130 is not particularly limited. For example, an insulating material may be used as a material of the encapsulation body 130. In this case, the insulating material may be: a thermosetting resin such as an epoxy resin; a thermoplastic resin such as a polyimide resin; a resin having a reinforcing material such as an inorganic filler immersed in the thermosetting resin and the thermoplastic resin, For example, Ajinomoto constitutes a film, FR-4, bismaleimide triazine, a photosensitive imaging dielectric resin, and the like. In addition, a conventional molding material such as an epoxy molding compound (EMC) can also be used. As another option, As the insulating material, a resin in which a thermosetting resin or a thermoplastic resin is immersed in a core material such as glass cloth (or glass fiber) together with an inorganic filler can also be used.

The encapsulation body 130 may include a plurality of layers formed of a variety of materials. For example, the space within the through hole 110H may be filled with the first encapsulation body, and the first interconnecting member 110 and the semiconductor wafer 120 may be covered with the second encapsulation body. Alternatively, the first encapsulation body may cover the first interconnecting member 110 and the semiconductor wafer 120 with a predetermined thickness while filling the space in the through hole 110H, and the second encapsulation body may cover the first encapsulation body with a predetermined thickness. . In addition to the above, various forms can be used.

If desired, the encapsulation body 130 may include conductive particles to block electromagnetic waves. For example, the conductive particles can be any material that can block electromagnetic waves, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), solder, and the like. However, this is only an example, and the conductive particles are not limited thereto.

The second interconnection member 140 may be configured to rewire the connection pads 122 of the semiconductor wafer 120. Dozens to hundreds of connection pads 122 having various functions may be rewired by the second interconnection member 140, and may be physically connected to or electrically connected via the connection terminals 170 described below in terms of functions. Connected externally. The second interconnection member 140 may include: an insulating layer 141a and an insulating layer 141b; a redistribution layer 142a and a redistribution layer 142b disposed on the insulating layer 141a and the insulating layer 141b; and a via window 143a and a via window 143b. Through the insulating layer 141a and the insulating layer 141b and connecting the redistribution layer 142a and the redistribution layer 142b To each other. In the fan-out type semiconductor package 100A according to the exemplary embodiment, the second interconnection member 140 may include a plurality of redistribution layers 142a and redistribution layers 142b, but is not limited thereto. That is, the second interconnection member 140 may also include a single layer. In addition, the second interconnection member 140 may also include a different number of layers.

An insulating material may be used as a material of each of the insulating layer 141a and the insulating layer 141b. In this case, a photosensitive insulating material such as a photosensitive imaging dielectric (PID) resin may also be used as the insulating material. In this case, each of the insulating layer 141a and the insulating layer 141b can be formed to have a smaller thickness, and the precision of each of the via window 143a and the via window 143b can be more easily achieved. Detail pitch If necessary, the materials of the insulating layer 141a and the insulating layer 141b may be the same as each other or may be different from each other. The insulating layer 141a and the insulating layer 141b may be integrated with each other depending on the manufacturing process, so that the boundary between the insulating layer 141a and the insulating layer 141b may not be easily obvious.

The redistribution layer 142 a and the redistribution layer 142 b may be substantially used for redistribution of the connection pad 122. The material of each of the redistribution layer 142a and the redistribution layer 142b may be, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The redistribution layer 142a and the redistribution layer 142b may have various functions depending on the design of the corresponding layers. For example, the redistribution layer 142a and the redistribution layer 142b may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal (S) pattern may include various signal patterns other than a ground (GND) pattern, a power (PWR) pattern, and the like, such as a data signal pattern. The redistribution layer 142a and redistribution The layer 142b may include a via window pad, a connection terminal pad, and the like.

If necessary, a surface treatment layer (not shown in the figure) may be further formed on the exposed portion of the redistribution layer 142b. The surface treatment layer (not shown in the figure) is not particularly limited as long as the surface treatment layer is known in the related art, and the surface treatment layer may be formed by, for example, electrolytic gold plating or electroless plating. Formed by gold, organic solderability protection or electroless tin, electroless silver, electroless nickel / replacement gold, direct immersion gold plating, hot air solder coating, etc.

The interlayer window 143a and the interlayer window 143b may electrically connect the redistribution layer 142a, the redistribution layer 142b, and the connection pad 122 formed on different layers to each other, thereby generating electricity in the fan-out semiconductor package 100A. Sexual path. The material of each of the vias 143a and 143b may be, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Each of the vias 143a and 143b may be completely filled with the conductive material, or the conductive material may also be formed along the wall of each of the vias. In addition, each of the via window 143a and the via window 143b may have all shapes known in the related art, such as a tapered shape, a cylindrical shape, and the like.

The thicknesses of the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c of the first interconnection member 110 may be larger than the thicknesses of the redistribution layer 142a and the redistribution layer 142b of the second interconnection member 140. Since the first interconnection member 110 may have a thickness equal to or larger than the thickness of the semiconductor wafer 120, depending on the scale of the first interconnection member 110, the weight of the first interconnection member 110 formed in the first interconnection member 110 is large. cloth The line layer 112a, the redistribution layer 112b, and the redistribution layer 112c may be formed to be large. On the other hand, the redistribution layer 142a and the redistribution layer 142b of the second interconnection member 140 may be formed to have a size relatively larger than that of the redistribution layer 112a, redistribution layer 112b, and redistribution layer 112c of the first interconnection member 110 A small size to achieve a thinness of the second interconnection member 140.

The reinforcing layer 181 can suppress warpage generated in the fan-out type semiconductor package 100A. For example, the reinforcing layer 181 can suppress the hardening shrinkage of the material of the encapsulation body 130 such as a thermosetting resin film, so as to suppress the warpage of the fan-out semiconductor package 100A. The reinforcing layer 181 may have an elastic modulus larger than that of the encapsulation body 130, and may have a thermal expansion coefficient smaller than that of the encapsulation body 130. In this case, the warpage suppression effect can be particularly excellent.

The reinforcing layer 181 may include a core material, an inorganic filler, and an insulating resin. For example, the reinforcing layer 181 may be formed of an uncovered copper clad laminate (CCL), a prepreg, or the like. In the case where the reinforcing layer 181 includes a core material such as glass cloth (or glass fiber), the reinforcing layer 181 may be implemented to have a relatively large elastic modulus, and in the case where the reinforcing layer 181 includes an inorganic filler, it may be The reinforcing layer 181 is implemented to have a relatively small thermal expansion coefficient by adjusting the content of the inorganic filler. The reinforcing layer 181 may be attached to the encapsulation body 130 in a hardened state (c-stage). In this case, a boundary surface between the encapsulation body 130 and the reinforcing layer 181 may have an approximately linear shape. Meanwhile, the inorganic filler may be silicon dioxide, alumina, and the like, and the resin may be epoxy resin or the like. However, the inorganic filler and the resin are not limited to this.

A resin layer 182 may be disposed on the reinforcing layer 181. The resin layer 182 may be formed of a material that is the same as or similar to the material of the encapsulation body 130, for example, an insulating material including an inorganic filler and an insulating resin but not including a core material, that is, Ajinomoto constituting film (ABF), or the like. In the case where the reinforcing layer 181 contains a core material or the like, it is difficult to form the opening 182H in the reinforcing layer 181, but in the case where the resin layer 182 is added, the opening 182H can be easily formed. The opening 182H can pass through the encapsulation body 130, the reinforcing layer 181, and the resin layer 182, and can expose at least some portions of the third redistribution layer 112c of the first interconnection member 110. The opening 182H can be used as an opening for marking. Alternatively, the opening 182H may be utilized as an opening for exposing the pad in the stacked package structure. Alternatively, the opening 182H may be utilized as an opening for mounting a surface mounted technology (SMT) component. In the case where the resin layer 182 is disposed, warpage can be suppressed more easily.

The protective layer 150 may be additionally configured to protect the second interconnection member 140 from external physical or chemical damage. The protective layer 150 may have an opening 150H exposing at least some portions of the redistribution layer 142 b of the second interconnection member 140. The opening 150H may expose the entire surface of the redistribution layer 142b or only a portion of the surface of the redistribution layer 142b. The material of the protective layer 150 is not particularly limited, and may be a photosensitive insulating material such as a photosensitive imaging dielectric resin. Alternatively, a solder resist may be used as a material of the protective layer 150. Alternatively, an insulating resin (for example, an Ajinomoto-containing film including an inorganic filler and an epoxy resin) that does not include a core material but includes a filler may be used as the material of the protective layer 150. Use the package in it In the case where an insulating material (for example, Ajinomoto constituting film, etc.) containing an inorganic filler and an insulating resin but not including a core material is used as the material of the protective layer 150, the protective layer 150 and the resin layer 182 may have a symmetrical effect with each other. Control warpage more effectively.

When an insulating material (for example, Ajinomoto constituting film, etc.) containing an inorganic filler and an insulating resin is used as the material of the protective layer 150, the insulating layer 141a and the insulating layer 141b of the second interconnection member 140 may also include an inorganic filler and an insulating material. Resin. In this case, a weight percentage of the inorganic filler included in the protective layer 150 may be greater than a weight percentage of the inorganic filler included in the insulating layer 141 a and the insulating layer 141 b of the second interconnection member 140. In this case, the protective layer 150 may have a relatively low thermal expansion coefficient, and similar to the reinforcing layer 181, may be used to control warpage.

If necessary, the protective layer 150 may be formed of a material satisfying Equations 1 to 4. In this case, the board level reliability of the electronic component package can be improved. The modulus of elasticity is defined as the ratio between stress and deformation, and can be measured by standard tension tests specified in, for example, JIS C-6481, KS M 3001, KS M 527-3, ASTM D882, etc. ) While measuring. The thermal expansion coefficient may refer to a thermal expansion coefficient measured using a thermomechanical analyzer (TMA) or a dynamic mechanical analyzer (DMA). In addition, the thickness refers to the thickness of the protective layer 150 after hardening, and can be measured using a general thickness measuring device. In addition, the surface roughness can be formed by a conventional method such as a surface treatment using cubic zirconia (CZ), and can be measured using a general roughness measuring device. In addition, moisture absorption ratio It can be measured using general measuring equipment.

Equation 1: Elastic modulus × Coefficient of thermal expansion = 230GPa. ppm / ℃

Equation 2: Thickness = 10 microns

Equation 3: Surface roughness = 1 nm

Equation 4: Moisture absorption rate = 1.5%

The under bump metal layer 160 may be additionally configured to improve the connection reliability of the connection terminal 170 to improve the board-level reliability of the fan-out type semiconductor package 100A. The under bump metal layer 160 may be disposed on a wall in the opening 150H of the protective layer 150 and on the exposed redistribution layer 142 b of the second interconnection member 140. The under bump metal layer 160 may be formed by a conventional metallization method using a conventional conductive material (eg, a metal).

The connection terminal 170 may be additionally configured to connect the fan-out semiconductor package 100A physically or electrically externally. For example, the fan-out semiconductor package 100A can be mounted on a motherboard of an electronic device via the connection terminal 170. Each of the connection terminals 170 may be formed of a conductive material such as solder. However, this is only an example, and the material of each of the connection terminals 170 is not limited thereto. Each of the connection terminals 170 may be a land, a ball, a pin, or the like. The connection terminal 170 may be formed as a multilayer structure or a single-layer structure. When the connection terminal 170 is formed into a multilayer structure, the connection terminal 170 may include copper (Cu) pillars and solder. When the connection terminal 170 is formed into a single-layered structure, the connection terminal 170 may include tin-silver solder or copper (Cu). However, this is only an example, and the connection terminal 170 is not limited to this. The number, interval, and configuration of the connection terminals 170 are not particularly limited, but can be sufficiently modified by those skilled in the art depending on the design details. For example, according to The number of the connection pads 122 and the connection terminals 170 of the semiconductor wafer 120 may be set to a number of tens to thousands, but is not limited thereto, and may be set to a number of tens to thousands or more or tens To thousands or less.

At least one of the connection terminals 170 may be disposed in the fan-out area. The fan-out region is a region other than a region in which the semiconductor wafer 120 is disposed. That is, the fan-out type semiconductor package 100A according to an exemplary embodiment may be a fan-out type package. Compared to a fan-in package, the fan-out package can have excellent reliability. The fan-out package can implement multiple input / output (I / O) terminals, and Facilitates 3D interconnection. In addition, compared with a ball grid array (BGA) package, a land grid array (LGA) package, etc., the fan-out package can be used without the need for a separate board. It is mounted on the electronic device. Therefore, the fan-out type package may be manufactured to have a reduced thickness and may be price competitive.

If necessary, a plurality of semiconductor wafers (not shown in the figure) may be placed in the through-holes 110H of the first interconnection member 110, and the number of the through-holes 110H of the first interconnection member 110 may be multiple (in the figure) (Not shown), and semiconductor wafers (not shown in the figure) may be respectively disposed in the through holes. In addition, separate passive components (not shown) such as capacitors and inductors may be encapsulated in the through hole 110H together with the semiconductor wafer. In addition, a surface mount technology component (not shown) may be mounted on the protective layer 150.

12 to 16 are diagrams illustrating an example of a process of manufacturing the fan-out type semiconductor package shown in FIG. 9.

Referring to FIG. 12, a carrier film 301 may be first prepared. The carrier film 301 may have a metal layer 302 and a metal layer 303 formed on one surface or two opposite surfaces of the carrier film. Surface treatment may be performed on a bonding surface between the metal layer 302 and the metal layer 303 to facilitate separation in a subsequent separation process. Alternatively, a release layer may be provided between the metal layer 302 and the metal layer 303 to facilitate separation in subsequent processes. The carrier film 301 may be a conventional insulating substrate, and the material of the carrier film 301 is not particularly limited. The metal layer 302 and the metal layer 303 may be copper (Cu) foils in general, but are not limited thereto. That is, the metal layer 302 and the metal layer 303 may be thin films formed of other conductive materials. Next, patterning for forming the first redistribution layer 112 a may be performed using the dry film 304. The first redistribution layer 112a may be formed using a conventional photolithography method. The dry film 304 may be a conventional dry film formed of a photosensitive material. Next, a conductive material may be disposed in the patterned space of the dry film 304 to form the first redistribution layer 112a. The first redistribution layer 112a may be formed by a plating process. In this case, the metal layer 303 may serve as a seed layer. The plating process may be electroplating or electroless plating, and more specifically, it may be chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, and degrading processes. , Additive process, semi-additive process (SAP), modified semi-additive process (MSAP), etc., but it is not limited to this. Next, the dry film 304 may be removed. The dry film 304 can be removed by a conventional method such as an etching process.

Referring to FIG. 13, next, a first layer may be formed on the metal layer 303. The first insulating layer 111a of at least a part of the double-wiring layer 112a. Next, a first interlayer window 113a may be formed to pass through the first insulating layer 111a. In addition, a second redistribution layer 112b may be formed on the first insulating layer 111a. The precursor of the first insulating layer 111a may be laminated by using a conventional lamination method, and then the precursor is hardened, the precursor of the first insulating layer 111a is applied by a conventional application method, and then The method of hardening the precursor may be used to form the first insulating layer 111a. The first interlayer window 113a and the second redistribution layer 112b can be formed by the following methods: forming a via hole in the first insulating layer 111a by a photolithography method, mechanical drilling, laser drilling, etc .; using Dry film or the like is patterned; and the via window and the patterning space are filled by a plating process or the like. Next, a second insulating layer 111b covering the second redistribution layer 112b may be formed on the first insulating layer 111a. Next, a second interlayer window 113b may be formed to pass through the second insulating layer 111b. In addition, a third redistribution layer 112c may be formed on the second insulating layer 111b. The method of forming the second interlayer window 113b and the third redistribution layer 112c may be the same as the method described above. Next, the carrier film 301 can be peeled off. In this case, the peeling may indicate that the metal layer 302 and the metal layer 303 are separated from each other. Here, the metal layers may be separated from each other by using a blade, but it is not limited to this. That is, all known methods can be used to separate metal layers from each other. Meanwhile, an example in which the first interconnection member 110 is formed before the carrier film 301 is peeled off is explained in a series of processes. However, the present invention is not limited to this. For example, after the carrier film 301 is peeled off, the first interconnection member 110 may be formed according to the above-mentioned process. That is, the order is not necessarily limited to the above-mentioned order.

Referring to FIG. 14, next, the remaining can be removed by a conventional etching method or the like A metal layer 303 and a through hole 110H may be formed in the first interconnection member 110. The through hole 110H may be formed using a mechanical drill or a laser drill. However, the through hole 110H is not limited to this, and the through hole 110H may also be formed by a sand blasting method using abrasive particles, a dry etching method using a plasma, and the like. In a case where the through-hole 110H is formed using mechanical drilling or laser drilling, a desmearing process such as a permanganate method may be performed to remove resin dirt in the through-hole 110H. Next, an adhesive film 305 may be attached to one surface of the first interconnection member 110. As the adhesive film 305, any material that can fix the first interconnection member 110 may be used. As a non-limiting example, a conventional tape or the like can be used. Examples of the conventional adhesive tape may include: a thermosetting adhesive tape whose adhesive force is weakened by heat treatment; an ultraviolet-curable adhesive tape whose adhesive force is weakened by ultraviolet radiation, and the like. Next, the semiconductor wafer 120 may be placed in the through-hole 110H of the first interconnection member 110. For example, the semiconductor wafer 120 may be set by a method of attaching the semiconductor wafer 120 to the adhesive film 305 in the through-hole 110H. The semiconductor wafer 120 may be placed in a face-down manner, so that the connection pad 122 is attached to the adhesive film 305.

15, the encapsulation body 130 may be used to encapsulate the semiconductor wafer 120. The encapsulation body 130 may cover the passive surfaces of the first interconnection member 110 and the semiconductor wafer 120, and may fill a space in the through hole 110H. The encapsulation body 130 can be formed by a conventional method. For example, the encapsulation body 130 may be formed by a method of laminating a resin for forming the encapsulation body 130 in a non-hardened state and then curing the resin. Alternatively, the first interconnecting member 110 and the half may be encapsulated by applying a resin for forming the encapsulation body 130 to the adhesive film 305 in a non-hardened state. The encapsulation body 130 is formed by the conductive wafer 120 and the method of hardening the resin. The semiconductor wafer 120 may be fixed by hardening. As a method of laminating the resin, for example, a method of performing a hot pressing process of compressing the resin at a high temperature for a predetermined time, performing pressure reduction on the resin, and then cooling the resin to room temperature, The resin is cooled in a cold pressing process, and then a work tool or the like is separated. As the method of applying the resin, for example, a screen printing method of applying ink using a squeegee, a spray printing method of applying ink in a mist form, and the like can be used. Next, a reinforcing layer 181 may be formed on the encapsulation body 130. The reinforcing layer 181 may be attached to the encapsulation body 130 in, for example, a hardened state (c-phase) of an uncovered copper-clad laminate or the like. Therefore, after the reinforcement layer 181 is attached to the encapsulation body 130, the boundary surface between the encapsulation body 130 and the reinforcement layer 181 may have an approximately linear form. After the reinforcing layer 181 is attached to the encapsulation body 130, the encapsulation body 130 may be hardened. In this case, the reinforcing layer 181 can control the warpage caused by the hardening contraction of the encapsulation body 130. In addition, in this case, the close adhesion between the reinforcing layer 181 and the encapsulation body 130 may be excellent. Next, the adhesive film 305 can be peeled. The method of peeling the adhesive film is not particularly limited, but may be a conventional method. For example, in the case where a thermosetting adhesive tape whose adhesive force is weakened by heat treatment, a UV-curable adhesive tape whose adhesive force is weakened by ultraviolet radiation are used as the adhesive film 305, it can be weakened by heat-treating the adhesive film 305 After the adhesive force of the adhesive film 305 is peeled off, the adhesive film 305 may be peeled off after the adhesive force of the adhesive film 305 is weakened by radiating the adhesive film 305 with ultraviolet light. Next, a second interconnection member 140 may be formed on the first interconnection member 110 from which the adhesive film 305 is removed and on the active surface of the semiconductor wafer 120. The insulating layer 141a and the insulating layer 141b may be sequentially formed by the above-mentioned plating process and the like, and then a redistribution layer 142a and a redistribution layer 142b are formed on the insulating layer 141a and the insulating layer 141b and the insulating layer 141a and the insulating layer 141b, respectively. And vias 143a and 143b to form the second interconnection member 140. In addition, a resin layer 182 may be formed on the reinforcing layer 181. In addition, a protective layer 150 may be formed on the second interconnection member 140. A method of laminating the precursor of the resin layer 182 and the precursor of the protective layer 150 and then hardening the precursor, applying a material for forming the resin layer 182 and the protective layer 150, and then hardening the material Method to form the resin layer 182 and the protective layer 150.

Referring to FIG. 16, next, an opening 150H may be formed in the protective layer 150 to expose at least some portions of the redistribution layer 142 b of the second interconnection member 140, and may be formed in the opening 150H by a conventional metallization method. Bump metal layer 160. In addition, an opening 182H may be formed that penetrates through the encapsulation body 130, the reinforcing layer 181, and the resin layer 182 and exposes at least some portions of the third redistribution layer 112c of the first interconnection member 110. The opening 182H may be formed by mechanical drilling, laser drilling, sand blasting using abrasive particles, dry etching using plasma, or the like. Next, a connection terminal 170 may be formed on the under bump metal layer 160. The method of forming the connection terminal 170 is not particularly limited. That is, the structure or form of the end-view connection terminal 170 may be formed by a conventional method in the related art. The connection terminal 170 can be fixed by re-soldering, and some parts of the connection terminal 170 can be embedded in the protective layer 150 to enhance the fixing force, and the rest of the connection terminal 170 can be exposed to the outside, so that the reliability can be improved. .

Meanwhile, in order to facilitate mass production, a series of processes may be the following processes: preparing a carrier film 301 having a large size; manufacturing a plurality of fan-out semiconductor packages 100A; and then cutting the plurality by a cutting process. The fan-out semiconductor package is singulated into a single fan-out semiconductor package 100A. In this case, productivity may be excellent.

FIG. 17 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

Referring to the drawings, in the fan-out type semiconductor package 100B according to another exemplary embodiment of the present invention, only the reinforcing layer 181 may be attached to the encapsulation body 130. Even in a case where a separate resin layer 182 or the like is not attached to the reinforcing layer 181 as described above, warpage can be controlled. The reinforcing layer 181 may be formed of, for example, an uncoated copper-clad laminate including a core material, an inorganic filler, and an insulating resin, a prepreg, and the like. The reinforcing layer 181 may have an elastic modulus relatively larger than that of the encapsulation body 130, and may have a thermal expansion coefficient that is smaller than that of the encapsulation body 130. In this case, the warpage suppression effect can be particularly good. The reinforcing layer 181 may be attached to the encapsulation body 130 in a hardened state (c-stage). In this case, a boundary surface between the encapsulation body 130 and the reinforcing layer 181 may have an approximately linear shape.

Explanations of architectures other than the above-mentioned architectures may overlap with the explanations provided above, and therefore will not be described again. In addition, the description of the process of manufacturing the fan-out type semiconductor package 100B in which the resin layer 182 is not formed may overlap with the description provided above, and therefore will not be described again.

FIG. 18 is a schematic cross-section illustrating another example of a fan-out type semiconductor package. view.

Referring to the drawings, in the fan-out type semiconductor package 100C according to another exemplary embodiment of the present invention, only the reinforcing layer 181 may be attached to the encapsulation body 130. In this case, an opening 181H may be formed in the reinforcement layer 181 through the encapsulation body 130 and the reinforcement layer 181 and exposing at least some portions of the third redistribution layer 112c of the first interconnection member 110. Even in a case where a separate resin layer 182 or the like is not attached to the reinforcing layer 181 as described above, the opening 181H can be formed in the reinforcing layer 181. However, in this case, it may be more difficult to form the opening 181H than the case where the resin layer 182 is present due to the characteristics of the material of the reinforcing layer 181 including the core material. In addition, the core material of the reinforcement layer 181 may be exposed to the wall of the opening 181H, and thus an additional process for removing the exposed core material may be required. The reinforcing layer 181 may be attached to the encapsulation body 130 in a hardened state (c-stage). In this case, a boundary surface between the encapsulation body 130 and the reinforcing layer 181 may have an approximately linear shape.

Explanations of architectures other than the above-mentioned architectures may overlap with the explanations provided above, and therefore will not be described again. In addition, the description of the process of manufacturing the fan-out type semiconductor package 100C in which the resin layer 182 is not formed may overlap with the description provided above, and thus will not be described again.

FIG. 19 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

Referring to the drawings, in a fan-out type semiconductor package 100D according to another exemplary embodiment of the present invention, the reinforcing layer 183 may be formed of, for example, a prepreg including a core material, an inorganic filler, and an insulating resin, and the like, and The encapsulation body 130 can be For example, it is formed by an inorganic filler and an insulating resin, but not including a core material of Ajinomoto. In this case, when the weight percentage of the inorganic filler contained in the encapsulant 130 is a1 and the weight percentage of the inorganic filler contained in the reinforcing layer 183 is a2, a1 <a2. For example, 1.10 <a2 / a1 <1.95. That is, the reinforcing layer 183 having a relatively high concentration of the inorganic filler may have a relatively low thermal expansion coefficient, and the encapsulation body 130 having a relatively low concentration of the inorganic filler may have a relatively high thermal expansion coefficient. Therefore, the encapsulation body 130 may have excellent resin fluidity, and the reinforcing layer 183 may be advantageous for controlling warpage. In addition, when the thickness of the reinforcing layer 183 is t1, the thickness of the portion of the encapsulation body 130 covering the first interconnecting member 110 is t2 and the thickness of the portion of the encapsulation body 130 covering the passive surface of the semiconductor wafer 120 is t3, t2 <t1, and t3 <t1. For example, 0.2 <t2 / t1 <0.6, and 0.2 <t3 / t1 <0.6. That is, the thickness of the reinforcing layer 183 may be greater than the thickness of the portion of the encapsulation body 130 that covers the first interconnection member 110 and the portion that covers the passive surface of the semiconductor wafer 120, which may be more beneficial for controlling warpage.

Meanwhile, the reinforcing layer 183 may be attached to the encapsulation body 130 in a non-hardened state and then hardened. Therefore, the material of the reinforcing layer 183 having a relatively small thermal expansion coefficient may infiltrate into the through-hole 110H due to mixing between heterogeneous materials in contact with each other or movement of a boundary surface. For example, a prepreg including a core material, an inorganic filler, and an insulating resin may be attached to the encapsulant 130 in a b-stage in a semi-hardened state, and may then be hardened by a subsequent process in a c-stage, So that the reinforcing layer 183 can be formed. In this case, the mixing or boundary surface between materials may be caused by the concentration of the inorganic filler in the reinforcing layer 183 and the concentration of the inorganic filler in the encapsulant 130. The difference while moving. As a result, the boundary surface between the encapsulation body 130 and the reinforcing layer 183 may have a non-linear shape. For example, a boundary surface between the encapsulation body 130 and the reinforcing layer 183 may have a bent portion 183P bent toward a space between the wall of the through hole 110H of the first interconnection member 110 and the wall of the semiconductor wafer 120. In this case, the contact area between the reinforcement layer 183 and the encapsulation body 130 can be increased, so that the close adhesion between the reinforcement layer 183 and the encapsulation body 130 can be further improved.

Architectural explanations and the like other than the above-mentioned architectures may overlap with the explanations provided above, and therefore will not be described again. In addition, the description of the manufacturing process for manufacturing the fan-out semiconductor package 100D in which the resin layer 182 is not formed, and the material and hardened state of which are different from those of the above-mentioned reinforcing layer 181 and the hardened state of the reinforcing layer 183 overlap with the description provided above, and Therefore, they will not be described in detail.

FIG. 20 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

Referring to the drawings, in a fan-out type semiconductor package 100E according to another exemplary embodiment of the present invention, the reinforcing layer 184 may be formed of, for example, an asymmetric prepreg including a core material, an inorganic filler, and an insulating resin. And the weight percentage of the inorganic filler contained in one side 184a of the reinforcing layer 184 that is in contact with the encapsulation body 130 and the other side 184b of the reinforcing layer 184 opposite to the one side 184a of the core material 184c The weight percentages of the inorganic fillers are different from each other. The encapsulation body 130 may be formed of, for example, a film made of Ajinomoto, which contains an inorganic filler and an insulating resin, but does not include a core material. In this case, when the weight percentage of the inorganic filler contained in the encapsulant 130 is a1, none of the inorganic filler contained in one side 184a of the reinforcing layer 184 is When the weight percentage of the organic filler is a2, and when the weight percentage of the inorganic filler contained in the reinforcing layer 184 on the other side 184b opposite to the one side 184a is a3, a1 <a2 <a3. For example, 1.10 <a3 / a1 <1.95. That is, the thermal expansion coefficient of the other side 184b of the reinforcing layer 184 may be the lowest, the thermal expansion coefficient of one side 184a of the reinforcing layer 184 may be the intermediate value, and the thermal expansion coefficient of the encapsulant 130 may be the highest. Therefore, the encapsulation body 130 can have excellent resin fluidity, one side 184a of the reinforcement layer 184 can ensure excellent tight adhesion with the encapsulation body 130, and the other side 184b of the reinforcement layer 184 can effectively control warpage. In addition, when the thickness of the reinforcing layer 184 is t1, the thickness of the portion of the encapsulation body 130 covering the first interconnecting member 110 is t2 and the thickness of the portion of the encapsulation body 130 covering the passive surface of the semiconductor wafer 120 is t3, t2 <t1, and t3 <t1. For example, 0.2 <t2 / t1 <0.6, and 0.2 <t3 / t1 <0.6. In this case, warpage can be controlled more easily.

Meanwhile, the reinforcing layer 184 may be attached to the encapsulation body 130 in a semi-hardened state in a non-hardened state and then hardened. Therefore, the material of the reinforcing layer 184 having a relatively small thermal expansion coefficient may infiltrate into the through-hole 110H due to mixing between heterogeneous materials in contact with each other or movement of a boundary surface. That is, for example, an asymmetric prepreg including a core material, an inorganic filler, and an insulating resin, etc. may be attached to the encapsulation body 130 in the b-stage, and may then be subjected to subsequent processes in the c stage Hardened, which in turn makes it possible to form a reinforcing layer 184. In this case, the mixture or boundary surface between the materials may move due to the difference between the weight percentage of the inorganic filler on one side 184a of the reinforcing layer 184 and the weight percentage of the inorganic filler of the encapsulant 130. As a result, the boundary surface between the encapsulation body 130 and the reinforcing layer 184 may have a non-linear shape. For example, some portions of one side 184a of the reinforcing layer 184 may face the encapsulation body 130 that fills the space between the first interconnection member 110 and the semiconductor wafer 120 located in the through hole 110H of the first interconnection member 110. Recessed, which in turn makes it possible to form a curved portion 184P. In this case, the contact area between the reinforcement layer 184 and the encapsulation body 130 can be increased, so that the close adhesion between the reinforcement layer 184 and the encapsulation body 130 can be further improved.

Explanations of architectures other than the above-mentioned architectures may overlap with the explanations provided above, and therefore will not be described again. In addition, the description of the process for manufacturing the fan-out semiconductor package 100E in which the resin layer 182 is not formed, and the material and hardened state of which is different from that of the above-mentioned reinforcing layer 181 and the hardened state of the reinforcing layer 184 overlaps the description provided above, and Therefore, they will not be described in detail.

FIG. 21 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

Referring to the drawings, in the fan-out type semiconductor package 100F according to another exemplary embodiment of the present invention, only the reinforcing layer 185 may be attached to the encapsulation body 130. In this case, the reinforcing layer 185 may be formed of, for example, a film made of Ajinomoto which contains an inorganic filler and an insulating resin but does not include a core material. In addition, the encapsulant 130 may be formed of, for example, a film made of Ajinomoto, which contains an inorganic filler and an insulating resin, but does not include a core material. However, the reinforcing layer 185 may have an elastic modulus larger than that of the encapsulation body 130 or a thermal expansion coefficient smaller than that of the encapsulation body 130 to suppress warpage. The reinforcing layer 185 may be attached to the encapsulation body 130 in a hardened state (stage c). In this case, the boundary surface between the encapsulation body 130 and the reinforcing layer 185 may have a near Like linear shape.

The description of the frame type other than the above-mentioned structure may overlap with the description provided above, and therefore will not be described again. In addition, the description of the manufacturing process for manufacturing the fan-out semiconductor package 100F in which the resin layer 182 is not formed, and the material and hardened state of which are different from those of the above-mentioned reinforcing layer 181 and the hardened state of the reinforcing layer 185 are overlapped with those provided above, Therefore, they will not be described in detail.

22 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

Referring to the drawings, in the fan-out type semiconductor package 100G according to another exemplary embodiment of the present invention, only the reinforcing layer 185 may be attached to the encapsulation body 130. In this case, an opening 185H may be formed in the reinforcing layer 185 through the reinforcing layer 185 and exposing at least some portions of the third redistribution layer 112c of the first interconnection member 110. In the case where the reinforcing layer 185 does not contain a core material, the opening 185H can be easily formed. The reinforcement layer 185 may be attached to the encapsulation body 130 in a hardened state (c-stage), and the boundary surface between the encapsulation body 130 and the reinforcement layer 185 may therefore have an approximately linear shape.

Explanations of architectures other than the above-mentioned architectures may overlap with the explanations provided above, and therefore will not be described again. In addition, the description of the process of manufacturing the fan-out semiconductor package 100G in which the resin layer 182 is not formed, and the material and hardened state of which is different from the material of the reinforced layer 181 and the reinforced layer 185 in the hardened state overlap with the description provided above, and Therefore, they will not be described in detail.

FIG. 23 is a schematic cross-section illustrating another example of a fan-out type semiconductor package. view.

Referring to the drawings, in a fan-out type semiconductor package 100H according to another exemplary embodiment of the present invention, the reinforcing layer 186 may be formed of, for example, an Ajinomoto film that includes an inorganic filler and an insulating resin but does not include a core material. And the like, and the encapsulation body 130 may be formed of, for example, a film made of Ajinomoto which contains an inorganic filler and an insulating resin but does not include a core material. In this case, when the weight percentage of the inorganic filler contained in the encapsulant 130 is a1 and the weight percentage of the inorganic filler contained in the reinforcing layer 186 is a2, a1 <a2. For example, 1.10 <a2 / a1 <1.95. That is, the reinforcing layer 186 having a relatively high concentration of the inorganic filler may have a relatively low thermal expansion coefficient, and the encapsulation body 130 having a relatively low concentration of the inorganic filler may have a relatively high thermal expansion coefficient. Therefore, the encapsulation body 130 may have excellent resin fluidity, and the reinforcing layer 186 may be advantageous for controlling warpage. In addition, when the thickness of the reinforcing layer 186 is t1, the thickness of the portion of the encapsulation body 130 covering the first interconnecting member 110 is t2 and the thickness of the portion of the encapsulation body 130 covering the passive surface of the semiconductor wafer 120 is t3, t2 <t1, and t3 <t1. For example, 0.2 <t2 / t1 <0.6, and 0.2 <t3 / t1 <0.6. That is, the thickness of the reinforcing layer 186 may be greater than the thickness of the portion of the encapsulation body 130 that covers the first interconnecting member 110 and the passive surface of the semiconductor wafer 120, which may be more beneficial for controlling warpage.

Meanwhile, the reinforcing layer 186 may be attached to the encapsulation body 130 in a semi-hardened state in a non-hardened state and then hardened. Therefore, the material of the reinforcing layer 186 having a relatively small thermal expansion coefficient may infiltrate into the through-hole 110H due to mixing between heterogeneous materials in contact with each other or movement of a boundary surface. That is, for example, the package The Ajinomoto-containing film containing an inorganic filler and an insulating resin but not including glass cloth can be attached to the encapsulant 130 in the b-stage, and then hardened by a subsequent process in the c-stage, so that a reinforcing layer can be formed. 186. In this case, the mixing or boundary surface between the materials may move due to a difference between the weight percentage of the inorganic filler of the reinforcing layer 186 and the weight percentage of the inorganic filler of the encapsulant 130. As a result, the boundary surface between the encapsulation body 130 and the reinforcing layer 186 may have an approximately non-linear shape. For example, some portions of the reinforcing layer 186 may be recessed toward the encapsulation body 130 that fills a space between the first interconnection member 110 and the semiconductor wafer 120 located in the through-hole 110H of the first interconnection member 110, and further, This makes it possible to form the bent portion 186P. In this case, the contact area between the reinforcement layer 186 and the encapsulation body 130 can be increased, so that the close adhesion between the reinforcement layer 186 and the encapsulation body 130 can be further improved.

Explanations of architectures other than the above-mentioned architectures may overlap with the explanations provided above, and therefore will not be described again. In addition, the description of the process for manufacturing the fan-out semiconductor package 100H in which the resin layer 182 is not formed, and the material and hardened state of which is different from the material of the reinforced layer 181 and the hardened state of the reinforcing layer 186 overlap with the description provided above, Therefore, they will not be described in detail.

FIG. 24 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

Referring to the drawings, in a fan-out type semiconductor package 1001 according to another exemplary embodiment of the present invention, the first redistribution layer 112a may be recessed in the first insulating layer 111a, so that the first insulating layer The lower surface of 111a may have a stepped portion with respect to the lower surface of the first redistribution layer 112a. As a result, the encapsulation body 130 is formed At this time, a phenomenon in which the material of the encapsulation body 130 oozes out and contaminates the first redistribution layer 112a can be prevented. Meanwhile, since the first redistribution layer 112 a is recessed in the first insulating layer 111 a as described above, the first interconnection member 110 may be disposed at a level higher than the lower surface of the connection pad 122 of the semiconductor wafer 120. The lower surface of the one-layer wiring layer 112a. In addition, the distance between the redistribution layer 142a of the second interconnection member 140 and the first redistribution layer 112a of the first interconnection member 110 may be greater than the connection between the redistribution layer 142a of the second interconnection member 140 and the semiconductor wafer 120. The distance between the pads 122.

Explanations of architectures other than the above-mentioned architectures may overlap with the explanations provided above, and therefore will not be described again. In addition, a description of a process of manufacturing a fan-out type semiconductor package 1001 in which a stepped portion is formed by partially removing the first redistribution layer 112a when the metal layer 303 is removed may overlap the description provided above, and therefore does not I will repeat them later. Meanwhile, the features of the fan-out semiconductor package 100B to the fan-out semiconductor package 100H can also be applied to the fan-out semiconductor package 100I.

FIG. 25 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

Referring to the drawings, in a fan-out type semiconductor package 100J according to another exemplary embodiment of the present invention, the first interconnection member 110 may include: a first insulating layer 111a; a first redistribution layer 112a and The second redistribution layer 112b is respectively disposed on two opposite surfaces of the first insulating layer 111a; the second insulating layer 111b is disposed on the first insulating layer 111a and covers the first redistribution layer 112a; Layer 112c is disposed on the second insulating layer 111b; third insulating layer 111c is disposed on the first The second redistribution layer 112b is covered on the insulating layer 111a, and the fourth redistribution layer 112d is disposed on the third insulating layer 111c. The first redistribution layer 112a, the second redistribution layer 112b, the third redistribution layer 112c, and the fourth redistribution layer 112d may be electrically connected to the connection pads 122 of the semiconductor wafer 120. Since the first interconnection member 110 may include a larger number of redistribution layers 112a, redistribution layers 112b, redistribution layers 112c, and redistribution layers 112d, the second interconnection member 140 may be further simplified. Therefore, a decrease in the yield due to a defect occurring in a process of forming the second interconnection member 140 can be improved. Meanwhile, although not shown in the drawings, the first redistribution layer 112a, the second redistribution layer 112b, the third redistribution layer 112c, and the fourth redistribution layer 112d may pass through the first insulating layer 111a, The first to third interlayer windows of the second insulating layer 111b and the third insulating layer 111c are electrically connected to each other.

The first insulating layer 111a may have a thickness larger than that of the second insulating layer 111b and the third insulating layer 111c. The first insulating layer 111a may be relatively thick to maintain rigidity, and the second insulating layer 111b and the third insulating layer 111c may be introduced to form a larger number of redistribution layers 112c and 112d. The first insulating layer 111a may include an insulating material different from that of the second insulating layer 111b and the third insulating layer 111c. For example, the first insulating layer 111a may be, for example, a prepreg including a core material, an inorganic filler, and an insulating resin, and the second insulating layer 111b and the third insulating layer 111c may be an Ajinomoto including an inorganic filler and an insulating resin. A film or a photosensitive insulating film. However, the materials of the first insulating layer 111a and the materials of the second insulating layer 111b and the third insulating layer 111c are not limited thereto.

Can be at a level lower than the lower surface of the connection pad 122 of the semiconductor wafer 120 The lower surface of the third redistribution layer 112c of the first interconnection member 110 is disposed at a height. In addition, the distance between the redistribution layer 142 of the second interconnection member 140 and the third redistribution layer 112c of the first interconnection member 110 may be smaller than the connection between the redistribution layer 142 of the second interconnection member 140 and the semiconductor wafer 120. The distance between the pads 122. Here, the third redistribution layer 112c may be disposed on the second insulating layer 111b in a protruding form so as to contact the second interconnection member 140. The first redistribution layer 112a and the second redistribution layer 112b of the first interconnection member 110 may be disposed at a level between the active surface and the passive surface of the semiconductor wafer 120. The first interconnection member 110 may be formed to a thickness corresponding to the thickness of the semiconductor wafer 120. Therefore, the first redistribution layer 112 a and the second redistribution layer 112 b formed in the first interconnection member 110 may be disposed at a level between the active surface and the passive surface of the semiconductor wafer 120.

The thicknesses of the redistribution layer 112a, the redistribution layer 112b, the redistribution layer 112c, and the redistribution layer 112d of the first interconnection member 110 may be greater than the thickness of the redistribution layer 142 of the second interconnection member 140. Since the first interconnection member 110 may have a thickness equal to or larger than the thickness of the semiconductor wafer 120, the redistribution layer 112a, redistribution layer 112b, redistribution layer 112c, and redistribution layer 112d may also be Formation is large. On the other hand, the redistribution layer 142 of the second interconnection member 140 may be formed to have a relatively small size to achieve a thinness.

Explanations of architectures other than the above-mentioned architectures may overlap with the explanations provided above, and therefore will not be described again. In addition, in addition to the structure of the first interconnection member 110, the description of the process of manufacturing the fan-out type semiconductor package 100J may overlap with the description provided above, and therefore will not be described again. Meanwhile, fan-out semiconductors The features of the package 100B to the fan-out type semiconductor package 100H can also be applied to the fan-out type semiconductor package 100J.

FIG. 26 is a schematic diagram illustrating a situation in which warpage occurs in a fan-out type semiconductor package.

Referring to the drawings, a thermosetting resin film capable of firmly fixing the first interconnection member 510 and the semiconductor wafer 520 can be used as a material for encapsulating the first interconnection member 510 and the semiconductor wafer 520, and the first mutual The connecting member 510 includes an insulating layer 511, a redistribution layer 512a and a redistribution layer 512b, a via window 513, and the like, and the semiconductor wafer 520 includes a main body 521, an electrode pad 522, and the like. In detail, the encapsulation body 530 may be formed using a thermosetting resin film having a high thermal expansion coefficient, which generally has good resin fluidity, so that the space of the through hole 510H between the first interconnection member 510 and the semiconductor wafer 520 may be formed. The resin is completely filled and strengthens the close adhesion between the first interconnection member 510 and the semiconductor wafer 520. However, it can be understood that in such a thermosetting resin film, the thermal curing shrinkage of the resin is large, which further causes severe warpage W1 in the package after the resin is cured. Therefore, it may be difficult to form a fine circuit pattern later.

FIG. 27 is a schematic diagram illustrating a case in which warpage of a fan-out type semiconductor package is suppressed.

FIG. 28 is a diagram illustrating other problems occurring in FIG. 27.

Referring to the drawings, a thermosetting resin film having a low thermal expansion coefficient can be considered as a material for encapsulating the first interconnecting member 510 and the encapsulating body 540 of the semiconductor wafer 520. The first interconnecting member 510 includes an insulating layer 511, Redistribution layer 512a The redistribution layer 512b, the interlayer window 513, and the like, and the semiconductor wafer 520 includes a main body 521, an electrode pad 522, and the like. It can be understood that, in a case where a thermosetting resin film having a low thermal expansion coefficient is used as a material of the encapsulation body 540, compared to a case where a thermosetting resin film having a high thermal expansion coefficient is used, warpage W2 is suppressed. However, in order to reduce the coefficient of thermal expansion, the content of the inorganic filler in the thermosetting resin film is generally increased, so that the resin cannot sufficiently fill the fine spaces due to the decrease in resin fluidity, which may cause voids and the like. In addition, delamination and the like between the first interconnection member and the semiconductor wafer may occur due to a decrease in the close adhesion between the first interconnection member and the semiconductor wafer.

FIG. 29 is a graph for comparing the effects of suppressing warpage between the fan-out semiconductor packages.

Referring to the drawings, Comparative Example 1 refers to a case where a thermosetting resin film having a high thermal expansion coefficient having good resin fluidity is used as a material of the encapsulation body as shown in FIG. 26. It is understood that, in Comparative Example 1, severe warpage occurred due to the high thermosetting shrinkage of the encapsulation body. Comparative Example 2 refers to a case where a thermosetting resin having a low thermal expansion coefficient is used as a material of the encapsulation body as shown in FIG. 27 to suppress warpage. In Comparative Example 2, warpage may be suppressed due to the low thermosetting shrinkage of the encapsulated body, but the above-mentioned problems such as voids and delamination also occur. The example of the present invention refers to a case in which a thermosetting resin film having a high thermal expansion coefficient having good resin fluidity as in the present invention is used as the material of the encapsulation body, and the elasticity of the encapsulation body which is more elastic than that of the encapsulation body is introduced. In the case of a reinforcing layer having a large modulus of elasticity and a coefficient of thermal expansion smaller than that of the encapsulated body. In the present invention However, the warpage can be suppressed to a level similar to that of Comparative Example 2 without causing problems such as voids and delamination.

As described above, according to the exemplary embodiment of the present invention, a fan-out type semiconductor package in which a warpage problem can be effectively solved can be provided.

Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and changes may be made without departing from the scope of the invention as defined by the scope of the accompanying patent application. transform.

Claims (29)

  1. A fan-out type semiconductor package includes a semiconductor wafer having an active surface and a passive surface opposite to the active surface, a connection pad is disposed on the active surface, and an encapsulation body encapsulating the semiconductor wafer. At least some portions of a passive surface; a first interconnecting member disposed on the active surface of the semiconductor wafer; and a reinforcing layer disposed on the encapsulation body, wherein the first interconnecting member includes a heavy A wiring layer, the redistribution layer is electrically connected to the connection pad of the semiconductor wafer, the reinforcement layer includes at least an inorganic filler and an insulating resin, and the encapsulation body includes an inorganic filler and an insulating resin, and is contained in The weight percentage of the inorganic filler in the reinforcing layer is greater than the weight percentage of the inorganic filler contained in the encapsulant.
  2. The fan-out type semiconductor package according to item 1 of the scope of patent application, wherein the reinforcing layer has an elastic modulus larger than that of the encapsulation body.
  3. The fan-out type semiconductor package according to item 1 of the patent application scope, wherein the reinforcing layer has a thermal expansion coefficient lower than that of the encapsulation body.
  4. The fan-out type semiconductor package according to item 1 of the patent application scope, wherein the reinforcing layer includes a core material, the inorganic filler, and the insulating resin.
  5. The fan-out semiconductor package according to item 4 of the scope of patent application, further includes a resin layer disposed on the reinforcing layer, wherein the resin layer includes an inorganic filler and an insulating resin.
  6. The fan-out semiconductor package according to item 5 of the patent application scope further includes an opening that penetrates through the resin layer, the reinforcement layer, and the encapsulation body.
  7. The fan-out semiconductor package according to item 5 of the patent application scope further includes a protective layer disposed on the first interconnection member, wherein the protective layer includes an inorganic filler and an insulating resin.
  8. The fan-out type semiconductor package according to item 7 of the scope of patent application, wherein the composition of the resin layer and the composition of the protective layer are the same as each other.
  9. The fan-out type semiconductor package according to item 4 of the scope of patent application, wherein the weight percentage of the inorganic filler contained in the side of the reinforcing layer that is in contact with the encapsulant is included in the reinforcing The weight percentages of the inorganic filler in the other side of the layer opposite to the one side with respect to the core material are different from each other.
  10. The fan-out semiconductor package according to item 9 of the scope of patent application, wherein a1 <a2 <a3, where a1 is the weight percentage of the inorganic filler contained in the encapsulant, and a2 is contained in the reinforcing layer Weight percentage of the inorganic filler in the one side in contact with the encapsulant, and a3 is the inorganic contained in the other side of the reinforcing layer opposite to the one side Filler weight percentage.
  11. The fan-out type semiconductor package according to item 1 of the patent application scope, wherein the reinforcing layer includes an inorganic filler and an insulating resin and does not include a core material.
  12. The fan-out type semiconductor package according to item 1 of the patent application scope, further comprising: a second interconnection member having a through hole, wherein the semiconductor wafer is disposed in the through hole of the second interconnection member. Wherein the second interconnection member includes a first insulation layer, a first redistribution layer, and a second redistribution layer, the first redistribution layer is in contact with the first interconnection member and is embedded in the first In the insulation layer, the second redistribution layer is disposed on another surface of the first insulation layer opposite to a surface of the first insulation layer in which the first redistribution layer is embedded, and the The first redistribution layer and the second redistribution layer are electrically connected to the connection pad.
  13. According to the fan-out type semiconductor package of claim 12, wherein the second interconnection member further includes a second insulation layer and a third redistribution layer, the second insulation layer is disposed on the first insulation layer. The second redistribution layer is covered on the insulating layer, the third redistribution layer is disposed on the second insulating layer, and the third redistribution layer is electrically connected to the connection pad.
  14. The fan-out type semiconductor package according to item 13 of the patent application scope, wherein the second redistribution layer is disposed at a horizontal height between the active surface and the passive surface of the semiconductor wafer.
  15. The fan-out type semiconductor package according to item 12 of the patent application scope, wherein a distance between the redistribution layer and the first redistribution layer of the first interconnection member is greater than the first interconnection The distance between the redistribution layer of the component and the connection pad.
  16. According to the fan-out type semiconductor package of claim 12, the first redistribution layer has a thickness larger than a thickness of the redistribution layer of the first interconnection member.
  17. The fan-out type semiconductor package according to item 12 of the application, wherein the lower surface of the first redistribution layer is disposed at a level higher than the lower surface of the connection pad.
  18. The fan-out type semiconductor package according to item 1 of the patent application scope, further comprising: a second interconnection member having a through hole, wherein the semiconductor wafer is disposed in the through hole of the second interconnection member. Wherein the second interconnection member includes a first insulation layer, a first redistribution layer and a second redistribution layer respectively disposed on two opposite surfaces of the first insulation layer, and is disposed on the first A second insulation layer on the insulation layer and covering the first redistribution layer and a third redistribution layer disposed on the second insulation layer, and the first redistribution layer to the third redistribution layer Electrically connected to the connection pad.
  19. The fan-out type semiconductor package as described in claim 18, wherein the second interconnection member further includes a third insulation layer disposed on the first insulation layer and covering the second redistribution layer. And a fourth redistribution layer disposed on the third insulating layer, and the fourth redistribution layer is electrically connected to the connection pad.
  20. According to the fan-out type semiconductor package of claim 18, wherein the first insulating layer has a thickness larger than a thickness of the second insulating layer.
  21. The fan-out type semiconductor package as described in claim 18, wherein the third redistribution layer has a thickness larger than a thickness of the redistribution layer of the first interconnection member.
  22. The fan-out type semiconductor package as described in claim 18, wherein the first redistribution layer is disposed on a horizontal level between the active surface and the passive surface of the semiconductor wafer.
  23. According to the fan-out type semiconductor package of claim 18, wherein the lower surface of the third redistribution layer is disposed at a lower level than the lower surface of the connection pad.
  24. The fan-out type semiconductor package according to item 1 of the patent application scope, wherein a boundary surface between the encapsulation body and the reinforcement layer has an approximately linear shape.
  25. The fan-out semiconductor package according to item 1 of the scope of patent application, further includes: an insulating member having a through hole, wherein the semiconductor wafer is disposed in the through hole of the insulating member.
  26. The fan-out type semiconductor package according to item 1 of the patent application scope, further comprising: a second interconnection member having a through hole, wherein the semiconductor wafer is disposed in the through hole of the second interconnection member. Wherein the second interconnection member includes an insulating layer, a first redistribution layer disposed on a first surface of the insulating layer, and a second surface of the insulating layer opposite to the first surface. A second redistribution layer, and the first redistribution layer and the second redistribution layer are electrically connected to the connection pad.
  27. A fan-out type semiconductor package includes a semiconductor wafer having an active surface and a passive surface opposite to the active surface, a connection pad is disposed on the active surface, and an encapsulation body encapsulating the semiconductor wafer. At least some parts of a passive surface; a first interconnecting member disposed on the active surface of the semiconductor wafer; and a reinforcing layer disposed on the encapsulation body and a protective layer disposed on the first interactive member On the connection member, wherein the first interconnection member includes a redistribution layer, the redistribution layer is electrically connected to the connection pad of the semiconductor wafer, the protective layer includes an inorganic filler and an insulating resin, and the first An interconnection member includes an insulating layer including an inorganic filler and an insulating resin, and a weight percentage of the inorganic filler included in the protective layer is greater than the weight of the insulating layer included in the first interconnection member. Weight percentage of inorganic filler.
  28. A fan-out type semiconductor package includes a semiconductor wafer having an active surface and a passive surface opposite to the active surface, a connection pad is disposed on the active surface, and an encapsulation body encapsulating the semiconductor wafer. At least some parts of a passive surface; a first interconnecting member disposed on the active surface of the semiconductor wafer; and a reinforcing layer disposed on the encapsulation body and a protective layer disposed on the first interactive member A connecting member, and an insulating member having a through hole, wherein the first interconnecting member includes a redistribution layer, the redistribution layer is electrically connected to the connection pad of the semiconductor wafer, and the semiconductor wafer is disposed on In the through hole of the insulating member, a boundary surface between the reinforcement layer and the encapsulation body has a bent portion that is bent toward a space between the inner wall of the through hole and the semiconductor wafer. .
  29. The fan-out type semiconductor package according to claim 28, wherein the reinforcing layer has a thickness larger than that of the first portion of the encapsulation body covering the insulating member and the encapsulation body covers the The second portion of the passive surface of the semiconductor wafer has a large thickness.
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KR101933421B1 (en) 2017-10-27 2018-12-28 삼성전기 주식회사 Fan-out semiconductor package module
KR101939046B1 (en) * 2017-10-31 2019-01-16 삼성전기 주식회사 Fan-out semiconductor package
KR102029101B1 (en) * 2017-12-28 2019-10-07 삼성전자주식회사 Semiconductor package
KR20190082604A (en) 2018-01-02 2019-07-10 삼성전자주식회사 Semiconductor package
KR102111302B1 (en) * 2018-07-27 2020-05-15 삼성전자주식회사 Electronic component package

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