TWI658553B - Fan-out semiconductor package - Google Patents

Abstract

The present invention provides a fan-out type semiconductor package including: a first semiconductor wafer; a first encapsulation body; a connecting member including a first through hole and a first redistribution layer; a second semiconductor wafer; a first encapsulation body; A double wiring layer; a second via and a third via. The length of the longest side of the first cutting surface of the second through-hole is shorter than the length of the longest side of the second cutting surface of the third through-hole. The first cutting surface of the second through-hole and the second cutting surface of the third through-hole are formed by It is formed by cutting a plane at any horizontal height parallel to the second active surface.

Description

Fan-out semiconductor package

The present disclosure relates to a semiconductor package, and more particularly, to a fan-out type semiconductor package in which a connection terminal can extend beyond an area where a semiconductor wafer is disposed.

[Cross-reference to related applications]

This application claims the priority of Korean Patent Application No. 10-2017-0000799, filed with the Korean Intellectual Property Office on January 03, 2017, and South Korea, which filed with the Korean Intellectual Property Office on March 22, 2017 The priority of Patent Application No. 10-2017-0036054, the disclosure content of each of the Korean patent applications mentioned herein is incorporated in its entirety for reference.

Recently, a recent significant trend in technological developments related to semiconductor wafers has been reducing the size of semiconductor wafers. Therefore, in the field of packaging technology, with the rapid increase in demand for small-sized semiconductor wafers and the like, it has been necessary to implement small-sized semiconductor packages including multiple pins at the same time.

Fan-out semiconductor packaging is a packaging technology proposed to meet the above technical requirements. This fan-out type semiconductor package has a small size and can be A plurality of pins are realized by rewiring the connection terminals outside the area where the semiconductor wafer is arranged.

One aspect of the present disclosure can provide a fan-out semiconductor package. Although a plurality of semiconductor wafers are used, the fan-out semiconductor package can still be thinned and has improved performance and excellent reliability.

According to one aspect of the present disclosure, a fan-out type semiconductor package can be provided, in which a plurality of semiconductor wafers are stacked and packaged, and the plurality of semiconductor wafers are configured in a special form so as to be electrically charged through vias instead of wires. Connect to the redistribution layer.

According to an aspect of the present disclosure, the fan-out semiconductor package may include a first semiconductor wafer having a first active surface having a first connection pad configuration thereon and a first non-active surface opposite to the first active surface. A first encapsulation body that covers at least a portion of the first semiconductor wafer; a connecting member that is disposed on the first encapsulation body and the first active surface of the first semiconductor wafer, and includes a first through hole and A through-hole electrically connected to the first redistribution layer of the first connection pad; the second semiconductor wafer has a second active surface on which a plurality of second connection pads are arranged, and is opposite to and attached to the second active surface To the second non-active surface of the connecting member; the second encapsulating body covering at least part of the connecting member and covering at least part of the second semiconductor wafer; the second redistribution layer disposed on the second encapsulating body and the second A second active surface of the semiconductor wafer; a second through hole penetrating through the second encapsulation body and electrically connecting the second connection pad and the second redistribution layer to each other And a third through hole penetrating through the second encapsulation body and electrically connecting the first redistribution layer and the second redistribution layer to each other. The length of the longest side of the first cutting surface of the second through-hole is shorter than the length of the longest side of the second cutting surface of the third through-hole. The first cutting surface of the second through-hole and the second cutting surface of the third through-hole are formed by It is formed by cutting a plane at any horizontal height parallel to the second active surface.

100‧‧‧Semiconductor Package

100A, 100B, 100C, 100D, 100E, 100F‧‧‧ fan-out semiconductor packages

110‧‧‧ support member

111a‧‧‧First insulation layer

111b‧‧‧Second insulation layer

111c‧‧‧Third insulation layer

112a‧‧‧First redistribution layer

112b‧‧‧Second redistribution layer

112c‧‧‧ Third wiring layer

112d‧‧‧Fourth wiring layer

113a‧‧‧First through hole

113b‧‧‧Second through hole

113c‧‧‧Third through hole

120B‧‧‧Semiconductor wafer

120P‧‧‧Connecting pad

120P’‧‧‧Reconnected connection pad

120R‧‧‧ Redistribution Layer

120RP‧‧‧ Redistribution pattern

121‧‧‧First semiconductor wafer

121a‧‧‧ Ontology

121b‧‧‧first connection pad

121c‧‧‧ passivation layer

122‧‧‧Second semiconductor wafer

122a‧‧‧ Ontology

122b‧‧‧Second connection pad

122c‧‧‧ passivation layer

123‧‧‧Third semiconductor wafer

123a‧‧‧ Ontology

123b‧‧‧Third connection pad

123c‧‧‧ passivation layer

124‧‧‧ Fourth semiconductor wafer

124a‧‧‧ Ontology

124b‧‧‧Fourth connection pad

124c‧‧‧ passivation layer

125‧‧‧ Adhesive members

130‧‧‧ the first envelope

140‧‧‧ connecting member

141a‧‧‧First insulation layer

141b‧‧‧Second insulation layer

142‧‧‧First redistribution layer

143‧‧‧The first through hole

150‧‧‧ second envelope

152‧‧‧Second redistribution layer

153‧‧‧Second through hole

155‧‧‧Third through hole

155a‧‧‧metal pillar

155b‧‧‧through-hole conductor

155h‧‧‧through hole

160‧‧‧ passivation layer

170‧‧‧ metal layer under bump

180‧‧‧Connecting terminal

1000‧‧‧ electronic device

1010‧‧‧Motherboard

1020‧‧‧Chip-related components

1030‧‧‧Network related components

1040‧‧‧Other components

1050‧‧‧ Camera Module

1060‧‧‧antenna

1070‧‧‧ display device

1080‧‧‧ battery

1090‧‧‧Signal cable

1100‧‧‧Smartphone

1110‧‧‧ Motherboard

1101‧‧‧Body

1120‧‧‧Electronic components

1130‧‧‧ Camera Module

2120‧‧‧Semiconductor wafer

2121‧‧‧ Ontology

2122‧‧‧Connecting pad

2130‧‧‧Encapsulation body

2140‧‧‧Connecting member

2141‧‧‧Insulation

2142‧‧‧ Redistribution Layer

2143‧‧‧through hole

2150‧‧‧ passivation layer

2200‧‧‧fan-in semiconductor package

2220‧‧‧Semiconductor wafer

2221‧‧‧ Ontology

2222‧‧‧Connecting pad

2223‧‧‧ passivation layer

2240‧‧‧Connecting member

2241‧‧‧Insulation

2242‧‧‧Wiring pattern

2243‧‧‧through hole

2243h‧‧‧Through Hole

2250‧‧‧ passivation layer

2251‧‧‧ opening

2260‧‧‧Under bump metal layer

2270‧‧‧Solder Ball

2280‧‧‧ underfill resin

2290‧‧‧Molding material

2301, 2302‧‧‧ interposer

2500‧‧‧ Motherboard

The embodiments are exemplified below and described in detail in conjunction with the accompanying drawings. The above and other aspects, features, and advantages of the present invention will be more obvious and easier to understand. In the attached drawings: FIG. Block diagram of an example; FIG. 2 is a perspective view illustrating an example of an electronic device; FIGS. 3A and 3B are cross-sectional schematic views illustrating a state of a fan-in semiconductor package before and after packaging; FIG. 4 is a diagram illustrating a fan-in semiconductor package Figure 5 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic device; and Figure 6 is a diagram illustrating a fan-in semiconductor package embedded in the interposer substrate. FIG. 7 is a schematic cross-sectional view illustrating a fan-out type semiconductor package; and FIG. 8 is a cross-sectional view illustrating a case where a fan-out type semiconductor package is mounted on a main board of an electronic device FIG. 9 is a schematic cross-sectional view illustrating an example of a fan-out semiconductor package; FIGS. 10A and 10B are views illustrating the configuration of the fan-out semiconductor package in FIG. Schematic diagrams of various arrays of the first connection pads on the active surface of the semiconductor wafer; FIGS. 11A to 11D are examples illustrating the manufacturing process of the fan-out type semiconductor package in FIG. 9; and FIG. 12 is a cross-section illustrating another example of the fan-out type semiconductor package 13 is a schematic cross-sectional view illustrating another example of a fan-out semiconductor package; FIG. 14 is a cross-sectional schematic view illustrating another example of a fan-out semiconductor package; and FIG. 15 is a schematic view illustrating another example of a fan-out semiconductor package. 16 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package; FIG. 17 is a schematic view illustrating an effect of a fan-out type semiconductor package according to an exemplary embodiment of the present disclosure; and FIG. 18A and FIG. FIG. 19 is a schematic diagram illustrating a problem of a fan-out type semiconductor package according to the related art.

Hereinafter, exemplary embodiments in the present invention will be described with reference to the drawings. In the drawings, the shape, size, etc. of each component may be exaggerated or reduced for clarity.

The term "exemplary embodiment" used herein does not mean the same exemplary embodiment, but is provided to emphasize a specific feature or characteristic that is different from a specific feature or characteristic of another exemplary embodiment. However, the exemplary embodiments provided herein are considered to be capable of being implemented by combining each other in whole or in part. For example In other words, even if an element described in a specific exemplary embodiment is not described in another exemplary embodiment, the element may be used unless an opposite or contradictory description is provided in another exemplary embodiment. It is understood as a description related to another exemplary embodiment.

The meaning of "connection" between a component and another component in the description includes an indirect connection via a third component and a direct connection between two components. In addition, "electrical connection" means the concept of physical connection and physical disconnection. It should be understood that when an element is referred to by "first" and "second", the element is not limited thereby. The use of "first" and "second" may only be used for the purpose of distinguishing the elements from other elements, and may not limit the order or importance of the elements. In some cases, a first element may be referred to as a second element without departing from the scope of the patentable scope set forth herein. Likewise, the second element may be referred to as a first element.

Herein, the upper part, the lower part, the upper side, the lower side, the upper surface, the lower surface, and the like are illustrated in the attached drawings. For example, the connection member is disposed above the redistribution layer. However, the scope of patents in this application is not limited thereto. In addition, the vertical direction means the above-mentioned upward and downward directions, and the horizontal direction means the directions perpendicular to the above-mentioned upward and downward directions. In this case, the vertical cross-section means a case of being taken along a plane in the vertical direction, and an example of the vertical cross-section may be a cross-sectional view shown in a drawing. In addition, the horizontal cross section means a case of being taken along a plane in a horizontal direction, and an example of the horizontal cross section may be a plan view shown in a drawing.

The terminology used herein is for the purpose of illustrating exemplary embodiments only and is not a limitation on the present disclosure. In this case, unless otherwise explained in the context, singular The form includes most forms.

Electronic device

FIG. 1 is a block diagram illustrating an embodiment of an electronic device system.

Referring to FIG. 1, a motherboard 1010 can be accommodated in the electronic device 1000. The motherboard 1010 may include a chip-related component 1020, a network-related component 1030, other components 1040, and the like, which are physically or electrically connected to the motherboard 1010. These components can be connected to other components described below to form various signal lines 1090.

The chip-related component 1020 may include a memory chip, such as a volatile memory (such as dynamic random access memory (DRAM)), a non-volatile memory (such as read only memory, ROM)), flash memory, etc .; application processor chips, such as a central processing unit (for example, a central processing unit (CPU)), a graphics processor (for example, a graphics processing unit (GPU)) ), Digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc .; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (application-specific integrated circuit, ASIC). However, the wafer-related component 1020 is not limited thereto, and may include other types of wafer-related components. In addition, the wafer-related components 1020 may be combined with each other.

The network-related component 1030 may include, for example, the following protocols: wireless fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers Electrical And Electronics Engineers (IEEE) 802.11 family, etc.), worldwide interoperability for microwave access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, long term evolution (LTE), data-only Evolution data only (Ev-DO), high speed packet access + (HSPA +), high speed downlink packet access + (HSDPA +), high speed uplink packet access + ( high speed uplink packet access + (HSUPA +), enhanced data GSM environment (EDGE), global system for mobile communications (GSM), global positioning system (GPS), universal General packet radio service (GPRS), code division multiple access (CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications , DECT), Bluetooth, 3G agreement, 4G agreement, 5G agreement, and following the above Any other wireless and wire protocols specified after the agreement. However, the network related component 1030 is not limited thereto, and may include various other wireless standards or protocols or wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020 described above.

Other components 1040 may include a high-frequency inductor, a ferrite inductor, a power inductor, a ferrite bead, and a low temperature co-fired ceramic; (LTCC), electromagnetic interference (EMI) filters, multilayer ceramics Multilayer ceramic capacitor (MLCC) or a combination thereof. However, other components 1040 are not limited to this, and may include passive components used for various other purposes and the like. In addition, other components 1040 may be combined with each other together with the chip-related component 1020 or the network-related component 1030 described above.

Depending on the type of the electronic device 1000, the electronic device 1000 may include other components that may be physically or electrically connected to the motherboard 1010, or other components that may not be physically or electrically connected to the motherboard 1010. These other components may include, for example, camera module 1050, antenna 1060, display device 1070, battery 1080, audio codec (not shown), video codec (not shown), power amplifier (not shown), compass (Not shown), accelerometer (not shown), gyroscope (not shown), speaker (not shown), mass storage unit (e.g. hard drive) (not shown), compact disk , CD) drive (not shown), digital versatile disk (DVD) drive (not shown), and so on. However, these other components are not limited thereto, but may include other components for various purposes depending on the type of the electronic device 1000 and the like.

The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet PC, and a notebook. Personal computer, netbook PC, TV, video game machine, smart watch or car component, etc. However, the electronic device 1000 is not limited thereto, and may be any other electronic device that processes data.

FIG. 2 is a schematic perspective view illustrating an example of an electronic device.

Referring to FIG. 2, the semiconductor package 100 may be used for various purposes in the electronic device 1000 described above. For example, the motherboard 1110 can be accommodated in the body 1101 of the smart phone 1100, and various electronic components 1120 can be physically connected to or electrically connected to the motherboard 1110. In addition, other components that can be physically connected or electrically connected to the motherboard 1110, or other components that cannot be physically connected or electrically connected to the motherboard 1110 (eg, the camera module 1130) can be housed in the body 1101. Some electronic components in the electronic component 1120 may be chip related components, and the semiconductor package 100 may be, for example, an application processor between chip related components, but is not limited thereto. The electronic device need not be limited to the smart phone 1100, but may be the other electronic devices described above.

Semiconductor package

Generally speaking, many fine circuits are integrated in a semiconductor wafer. However, the semiconductor wafer itself cannot serve as a completed semiconductor product, and may be damaged due to external physical or chemical influences. Therefore, the semiconductor wafer cannot be used alone, but can be packaged in an electronic device or the like and used in a packaged state in the electronic device or the like.

Here, a semiconductor package is required due to a difference in circuit width in terms of electrical connection between the semiconductor chip and the motherboard of the electronic device. In detail, the size of the connection pads of the semiconductor wafer and the interval between the connection pads of the semiconductor wafer are extremely fine, but the size of the component mounting pads of the motherboard and the interval between the component mounting pads of the motherboard are significantly Connection pads larger than semiconductor wafers Size and spacing. Therefore, it may be difficult to directly mount a semiconductor wafer on a motherboard, and a packaging technology for buffering a difference in circuit width between the semiconductor wafer and the motherboard may be required.

Depending on the structure and purpose of the semiconductor package, the semiconductor package manufactured by the packaging technology can be classified into a fan-in semiconductor package or a fan-out semiconductor package.

The fan-in type semiconductor package and the fan-out type semiconductor package will be described in more detail below with reference to the drawings.

Fan-in semiconductor package

3A and 3B are schematic cross-sectional views illustrating states of a fan-in semiconductor package before and after packaging.

FIG. 4 is a schematic cross-sectional view illustrating a packaging process of a fan-in semiconductor package.

Referring to the drawings, the semiconductor wafer 2220 may be, for example, an integrated circuit (IC) in an exposed state. The semiconductor wafer 2220 includes a body 2221 including silicon (Si), germanium (Ge), and gallium arsenide (GaAs). Connection pad 2222 is formed on one surface of the body 2221 and includes a conductive material such as aluminum (Al); and a passivation layer 2223 is, for example, an oxide film or a nitride film, and is formed on one surface of the body 2221 And cover at least a part of the connection pad 2222. In this case, since the connection pad 2222 is significantly small in size, it is difficult to mount an integrated circuit (IC) on a middle-level printed circuit board (PCB), a motherboard of an electronic device, and the like.

Therefore, the size of the connecting member 2240 can be seen at half the size of the semiconductor wafer 2220. The conductor wafer 2220 is formed with a redistribution connection pad 2222. The connecting member 2240 can be formed by the following steps: forming an insulating layer 2241 on the semiconductor wafer 2220 using an insulating material such as a photoimagable dielectric (PID) resin; forming a through-hole hole 2243h that opens the connection pad 2222; and then A wiring pattern 2242 and a through hole 2243 are formed. Next, a passivation layer 2250 for protecting the connection member 2240 may be formed, an opening 2251 may be formed, and a metal layer 2260 under the bump may be formed. That is, the fan-in type semiconductor package 2200 including, for example, the semiconductor wafer 2220, the connection member 2240, the passivation layer 2250, and the under bump metal layer 2260 may be manufactured through a series of processes.

As described above, the fan-in semiconductor package may have a packaging form in which all connection pads such as input / output (I / O) terminals of the semiconductor wafer are arranged in the semiconductor wafer, and It can have excellent electrical characteristics and can be produced at low cost. As a result, many components mounted in smart phones have been manufactured in the form of fan-in semiconductor packages. In detail, many components installed in a smart phone have been developed to implement fast signal transmission while having a small size.

However, since all the input / output terminals need to be arranged inside the semiconductor wafer in the fan-in type semiconductor package, the fan-in type semiconductor package has a large space limitation. Therefore, it is difficult to apply this structure to a semiconductor wafer having a large number of input / output terminals or a semiconductor wafer having a smaller size. In addition, due to the above disadvantages, a fan-in semiconductor package cannot be directly mounted and used on a motherboard of an electronic device. Here, even if the size of the input / output terminals of the semiconductor wafer is increased by the rewiring process And the interval between the input / output terminals of the semiconductor wafer, in this case, the size of the input / output terminals of the semiconductor wafer and the interval between the input / output terminals of the semiconductor wafer may not be sufficient for the fan-in semiconductor The package is mounted directly on the motherboard of the electronic device.

5 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic device.

FIG. 6 is a schematic cross-sectional view illustrating a situation where a fan-in semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic device.

Referring to the drawings, in the fan-in type semiconductor package 2200, the connection pads 2222 (ie, input / output terminals) of the semiconductor wafer 2220 can be re-routed through the interposer substrate 2301, and the fan-in type semiconductor package 2200 can be mounted on the intermediary The substrate 2301 is finally mounted on the motherboard 2500 of the electronic device. In this case, the solder balls 2270 and the like can be fixed by underfill resin 2280 and the like, and the outer surface of the semiconductor wafer 2220 can be covered with a molding material 2290 and the like. The fan-in semiconductor package 2200 may be embedded in a separate interposer substrate 2302, and the connection pads 2222 (ie, input / output terminals) of the semiconductor wafer 2220 may be in a state where the fan-in semiconductor package 2200 is embedded in the interposer substrate 2302, The interposer substrate 2302 is rewired, and the fan-in semiconductor package 2200 can be finally mounted on the motherboard 2500 of the electronic device.

As described above, it may be difficult to directly mount and use a fan-in semiconductor package on a motherboard of an electronic device. Therefore, the fan-in semiconductor package can be mounted on a separate interposer substrate and then mounted on the main board of the electronic device through a packaging process; or the fan-in semiconductor package can be embedded in the interposer substrate in a fan-in semiconductor package It is installed and used on the motherboard of the electronic device.

Fan-out semiconductor package

FIG. 7 is a schematic cross-sectional view illustrating a fan-out type semiconductor package.

Referring to the drawings, in a fan-out type semiconductor package, for example, the outer surface of the semiconductor wafer 2120 is protected by the encapsulation body 2130, and the connection pads 2122 of the semiconductor wafer 2120 may be directed outside the semiconductor wafer 2120 by the connection member 2140. Perform rewiring. In this case, a passivation layer 2150 may be further formed on the connection member 2140, and an under bump metal layer 2160 may be further formed in the opening of the passivation layer 2150. A solder ball 2170 may be further formed on the under bump metal layer 2160. The semiconductor wafer 2120 may be an integrated circuit including a body 2121, a connection pad 2122, a passivation layer (not shown), and the like. The connection member 2140 may include an insulating layer 2141, a redistribution layer 2142 formed on the insulating layer 2141, and a through hole 2143 for electrically connecting the connection pad 2122 and the redistribution layer 2142 to each other.

As described above, the fan-out type semiconductor package may have a form in which an input / output terminal of a semiconductor wafer is rewired via a connection member formed on the semiconductor wafer and is disposed outside the semiconductor wafer. As described above, in a fan-in type semiconductor package, all input / output terminals of a semiconductor wafer need to be arranged in the semiconductor wafer. Therefore, when the size of the semiconductor wafer is reduced, the size and pitch of the balls need to be reduced, thereby making it impossible to use a standardized ball layout in a fan-in semiconductor package. On the other hand, as described above, the fan-out type semiconductor package has a type in which an input / output terminal of a semiconductor wafer is formed by a semiconductor The connection member on the wafer is rewired and arranged outside the semiconductor wafer. Therefore, even when the size of the semiconductor wafer is reduced, the standardized ball layout can still be used in a fan-out semiconductor package, so that the fan-out semiconductor package can be mounted on the motherboard of an electronic device without using a separate interposer substrate. As described below.

8 is a schematic cross-sectional view illustrating a case where a fan-out type semiconductor package is mounted on a motherboard of an electronic device.

Referring to the drawings, the fan-out type semiconductor package 2100 can be mounted on the motherboard 2500 of the electronic device via a solder ball 2170 or the like. That is, as described above, the fan-out type semiconductor package 2100 includes the connection member 2140, which is formed on the semiconductor wafer 2120, and can re-route the connection pad 2122 to a fan-out area outside the semiconductor wafer 2120, thereby actually A standardized ball layout can be used in the fan-out semiconductor package 2100. Therefore, the fan-out semiconductor package 2100 can be mounted on the motherboard 2500 of the electronic device without using a separate interposer or the like.

As described above, since a fan-out type semiconductor package can be mounted on a motherboard of an electronic device without using a separate interposer, the fan-out type semiconductor package can have a thickness smaller than that of a fan-in type semiconductor package using an interposer. Next implementation. Therefore, the fan-out type semiconductor package can be miniaturized and thinned. In addition, the fan-out semiconductor package has excellent thermal and electrical characteristics, thereby making the fan-out semiconductor package particularly suitable for mobile products. Therefore, the fan-out semiconductor package can be implemented in a compact form compared to a general stacked package (POP) type using a printed circuit board (PCB), and can solve the problem caused by warpage. Cause problems.

Meanwhile, a fan-out type semiconductor package means a packaging technology such as the above-mentioned printed circuit board (PCB) for mounting a semiconductor wafer on a motherboard of an electronic device and the like and protecting the semiconductor wafer from external influences, and for example, an interposer substrate, etc. For different concepts, a printed circuit board has a different specification and purpose from a fan-out semiconductor package, and has a fan-in semiconductor package embedded therein.

The fan-out type semiconductor package will be described below with reference to the drawings. Although a plurality of semiconductor wafers are used, the fan-out type semiconductor package can be thinned and has improved performance and excellent reliability.

FIG. 9 is a schematic cross-sectional view illustrating an example of a fan-out type semiconductor package.

10A and 10B are schematic diagrams illustrating various arrays of the first connection pads of the fan-out type semiconductor package disposed on the active surface of the first semiconductor wafer in FIG. 9.

Referring to the drawings, a fan-out semiconductor package 100A according to an exemplary embodiment of the present disclosure may include a first semiconductor wafer 121 having an active surface and a non-active surface opposite to the active surface, the active surface having a first connection pad 121b Configuration; the first encapsulation body 130 covers at least a portion of the first semiconductor wafer 121; the connection member 140 is disposed on the active surface of the first semiconductor wafer 121 and includes a first through hole 143 and a first through hole 143 The second redistribution layer 142 electrically connected to the first connection pad 121b; the second semiconductor wafer 122 is attached to the other surface of the connection member 140 opposite to the surface of the connection member 140 on which the semiconductor wafer 121 is disposed. And has an active surface on which the second connection pad 122b is disposed and an inactive surface opposite to the active surface; the second encapsulation body 150 is disposed opposite to the surface of the connection member 140 on which the first semiconductor wafer 121 is disposed Connection member 140 on the other surface and wraps Covers at least part of the active surface of the second semiconductor wafer 122; the second redistribution layer 152 is disposed on the active surfaces of the second encapsulation body 150 and the second semiconductor wafer 122; and the second through hole 153 penetrates the second package The body 150 and electrically connects the second connection pad 122b and the second redistribution layer 152 to each other; and a third through hole 155 penetrating the second encapsulation body 150 and causes the first redistribution layer 142 and the second redistribution layer 152 Are electrically connected to each other. Here, when the second through hole 153 and the third through hole 155 are formed at the same horizontal height in the surface parallel to the active surface of the second semiconductor wafer, the length of the long side of the cut surface of the third through hole 155 may be The length of the long side of the cut surface of the second through-hole 153 is greater than any length. Here, the length of the long side means the longest distance between any two points in each horizontal cutting plane that pass through the center of the cutting plane and respectively connect to the outer edge of the cutting plane.

At the same time, in recent years, multiple stages stacking technology of multiple memory chips has been developed to increase the memory capacity. For example, as shown in FIG. 19, there may be the following techniques: stacking multiple memory wafers at a second or third stage, mounting the stacked memory wafers on an interposer, and then molding to prepare the interposer The stacked memory chips are mounted on top of each other, using a molding material to form a package. In this case, the stacked memory chips are electrically connected to the interposer substrate by wire bonding. However, in this structure, there is a limitation in thickness due to the significant thickness of the interposer substrate. In addition, when manufacturing an interposer substrate based on silicon, a considerable cost is required. In addition, when reinforcing materials supporting the stacked memory chips are not included separately, reliability problems may occur due to warpage. In particular, because the stacked memory chips are electrically connected to the interposer substrate through wire bonding, the input and output terminals are re-routed. , , as well as It is quite long, so that signal loss often occurs.

In detail, in this wire bonding method, the connection pad is disposed on the center portion of the active surface of the semiconductor wafer, and the connection pad needs to be re-wired intentionally outside the active surface of the semiconductor wafer by forming a redistribution layer to form a semiconductor Wafer stack. For example, as shown in FIG. 18A, the connection pads 120P in the exposed state are arranged in a row on the central portion of the active surface of the semiconductor wafer 120B, and the connection pads 120P may be directed toward the redistribution layer 120R by the redistribution pattern 120RP. The active-plane rewiring of the semiconductor wafer 120B. Alternatively, as shown in FIG. 18B, the connection pads 120P in the exposed state are arranged in two rows on the central portion of the active surface of the semiconductor wafer 120B. The connection pads 120P may be directed toward the semiconductor by the redistribution pattern 120RP of the redistribution layer 120R. The active surface of the wafer 120B is rewired. In any case, the rewiring connection pads 120P 'may be located on both sides of the active surface of the semiconductor wafer 120B. In this case, there are restrictions on the efficient design and configuration of the semiconductor wafer 120B. For example, signal loss can occur due to increased signal paths, etc. In addition, a separate redistribution layer forming process needs to be added, thereby reducing productivity.

On the other hand, in the fan-out type semiconductor package 100A according to the exemplary embodiment, as shown in FIG. 17, the signal path And signal path It can be formed via through-holes instead of wire bonding, and is significantly reduced. Therefore, the occurrence of signal loss can be significantly reduced. That is, the electrical characteristics of the signal can be improved. Specifically, the diameter of the third through hole 155 that connects the redistribution layer 142 and the redistribution layer 152 formed on different layers to each other may be formed to be larger than the diameter of the first through hole 143 and the diameter of the second through hole 153 , Resulting in improved reliability, such as stable transmission of a high-current signal. In addition, as shown in FIGS. 10A and 10B, the first semiconductor wafer 121 disposed on the connection member and the second semiconductor wafer 122 disposed below the connection member may be packaged in an exposed state. That is, the first connection pad 121b of the first semiconductor wafer 121 and the second connection pad 122b of the second semiconductor wafer 122 may be respectively disposed at the central portion of the active surface of the first semiconductor wafer 121 and the active surface of the second semiconductor wafer 122. On the central part. Here, each of the first connection pads 121b may be lined up as shown in FIG. 10A, or may be lined up as shown in FIG. 10B. Although not shown in the drawings, the second connection pad 122 b of the second semiconductor wafer may be configured in the same manner as the first connection pad 121 b of the first semiconductor wafer. For example, the second connection pad 121b may be arranged in a row similar to the configuration of the first connection pad 121b, as shown in FIG. 10A, or may be arranged in two rows similar to the configuration of the first connection pad 121b, as shown in FIG. Shown in 10B. Here, the first semiconductor wafer 121 may be connected to the first redistribution layer 142 of the connection member 140 via the first through hole 143, and the first redistribution layer 142 may be passed through the third via hole penetrating the second encapsulation body 150. 155 is connected to the second redistribution layer 152 formed on the second encapsulation body 150. As described above, it is not necessary to form a rewiring layer in a wafer state in order to redesign the connection pad 121b of the semiconductor wafer 121 and the connection pad 122b of the semiconductor wafer 122, and it can be used in the fan-out semiconductor package 100A for the most effective The connection pad 121 b of the semiconductor wafer 121 and the semiconductor wafer 122 and located at the center of the semiconductor wafer 121 and the connection pad 122 b of the center of the semiconductor wafer 122 are designed because there is no separate change operation.

In addition, in the fan-out type semiconductor package 100A according to the exemplary embodiment, a connection member 140 including a first redistribution layer 142 may be formed, and the second package may be disposed in a second package. The second redistribution layer 152 and the like on the package 150 is not an interposer. Therefore, as shown in FIG. 17, the redistribution layer 142 and the redistribution layer 152 can be routed to various positions, so that the thickness of the connection member 140 can be significantly reduced, and the thickness of the back envelope or the thickness of the stacked wafer can also be reduced. Significantly reduced. In addition, an inactive surface of the second semiconductor wafer 122 may be attached to the connection member 140 using an adhesive member 125 (eg, a die attach film (DAF)), and the attached second semiconductor wafer 122 may be attached. It can be covered by the second encapsulation body 150 to be effectively fixed, so that the reliability can be improved.

Meanwhile, the fan-out type semiconductor package 100A according to an exemplary embodiment may include a support member 110, and the first semiconductor wafer 121 may be disposed in a through hole of the support member 110. In this case, warpage can be controlled via the support member 110, thereby improving reliability. In addition, the fan-out type semiconductor package 100A may further include a passivation layer 160 disposed on the second encapsulation body 150, a under bump metal layer 170 formed in the opening of the passivation layer 160, and formed on the under bump metal layer 170.的 连接 Terminal 180.

Hereinafter, individual components included in the fan-out type semiconductor package 100A according to an exemplary embodiment will be described in more detail.

The first semiconductor wafer 121 may be an integrated circuit (IC) in the number of hundreds to millions of elements or more integrated into a single wafer. The integrated circuit may be volatile memory (such as dynamic random access memory (DRAM)), non-volatile memory (such as read only memory (ROM)), etc., but not This is the limit. The active surface of the first semiconductor wafer 121 means a surface of the first semiconductor wafer 121 on which the first connection pad 121 b is disposed, and the inactive surface of the first semiconductor wafer 121 means a surface opposite to the active surface. the first The semiconductor wafer 121 may be formed on the basis of an active wafer. In this case, the basic material of the body 121a may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits can be formed on the body 121a. The first connection pad 121b can electrically connect the first semiconductor wafer 121 to other components, and a material of each of the first connection pads 121b can be a conductive material, such as aluminum (Al). When necessary, a passivation layer 121c exposing the first connection pad 121b may be formed on the body 121a, and the passivation layer 121c may be an oxide film, a nitride film, or the like, or a double layer composed of an oxide layer and a nitride layer. Other insulation layers (not shown) may be provided.

The first encapsulation body 130 can protect the first semiconductor wafer 121. The encapsulation form of the first encapsulation body 130 is not particularly limited, and the first encapsulation body 130 may be a form in which the first encapsulation body 130 surrounds at least a portion of the first semiconductor wafer 121. For example, the first encapsulation body 130 may cover at least part of the support member 110 and at least part of the inactive surface of the first semiconductor wafer 121, and the first encapsulation body 130 may be filled in the wall surface of the through hole and the first semiconductor. At least part of the space between the side surfaces of the wafer 121. At the same time, the first encapsulation body 130 may be filled in the through hole to serve as an adhesive for fixing the first semiconductor wafer 121, and the buckling of the first semiconductor wafer 121 may be reduced depending on a specific material. The first encapsulation body 130 may include an insulating material. The insulating material may be a material including an inorganic filler and an insulating resin, for example, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide resin, and a reinforcing material such as an inorganic filler immersed in the thermosetting resin and the thermoplastic resin. Resins such as Ajinomoto Build up Film (ABF), FR-4, Bisaleimide Triazine (BT), Photosensitive Imaging Dielectric (PID) resin and the like. In addition, known molding materials such as epoxy rmolding compound (EMC) can also be used. Alternatively, a material made of a thermosetting resin or a thermoplastic resin infused with an inorganic filler and / or a core material such as glass fiber (or glass cloth, glass fabric) can also be used as an insulating material.

The connection member 140 may re-route the first connection pad 121 b of the first semiconductor wafer 121. Dozens to hundreds of first connection pads 121b having various functions can be rewired by the connection member 140, and can be physically or electrically connected to other via the third through hole 155 which will be described below depending on the function. Components. The connection terminal 140 may include a first insulating layer 141a, a first redistribution layer 142 disposed on the first insulating layer 141a, a first penetrating layer that penetrates the first insulating layer 141a and connects the first connection pad 121b to the first redistribution layer 142. A through hole 143 and a second insulating layer 141b disposed on the first insulating layer 141a and covering at least a part of the first redistribution layer 142. Meanwhile, the number of the insulating layers 141a and 141b constituting the connection member 140, the number of the redistribution layers 142, the number of the through holes 143, and the like may be larger than the above-mentioned number.

An insulating material may also be used as a material for each of the insulating layer 141a and the insulating layer 141b. In this case, a photosensitive insulating material such as a photosensitive imaging dielectric (PID) resin may be used as the insulating material. That is, the insulating layer 141a and the insulating layer 141b may be a photosensitive insulating layer. When the insulating layer 141a and the insulating layer 141b have photosensitive characteristics, the insulating layer 141a and the insulating layer 141b can be formed to have a smaller thickness, and the precise pitch of the first through hole 143 can be more easily achieved. The insulating layer 141a and the insulating layer 141b may be a photosensitive insulating layer including an insulating resin and an inorganic filler. When the insulation layer 141a and the insulation When the edge layer 141b is a multilayer, the materials of the insulating layer 141a and the insulating layer 141b may be the same as each other, and may be different from each other when necessary. When the insulating layer 141a and the insulating layer 141b are multiple layers, the insulating layer 141a and the insulating layer 141b may be integrated with each other according to a manufacturing process, so that the boundary between the insulating layers may not be obvious.

The first redistribution layer 142 may be used to redistribute the first connection pad 121b to other regions. The material of the first redistribution layer 142 may be a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof. The first redistribution layer 142 may perform various functions depending on the design of its corresponding layer. For example, the first redistribution layer 142 may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal pattern may include various signals other than a ground pattern, a power pattern, and the like, such as a data signal. In addition, the first redistribution layer 142 may include various pad patterns, such as through-hole pads, connection terminal pads, and the like. When the fan-out semiconductor package is projected in a direction perpendicular to the active surface of the first semiconductor wafer 121, if the projection area of the first semiconductor wafer 121 is the first area and the area surrounding the first area is the second area, all connected to The first connection pad 121 b of the first through hole 143 may be re-routed to the second region through the first re-wiring layer 142. That is, all the first connection pads 121 b connected to the first through holes 143 of the first semiconductor wafer 121 can be re-routed to the fan-out area.

The first through hole 143 can be electrically connected to the first redistribution layer 142, the first connection pad 121b, and the like formed on different layers, thereby generating an electrical path. The material of each of the first through holes 143 may be a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb ), Titanium (Ti), or an alloy thereof. guide An electric material may be completely filled in each of the first through holes 143, or a conductive material may be formed along a wall surface of each of the through hole holes. In addition, each of the first through holes 143 may have all shapes known in the related art, such as a tapered shape, a cylindrical shape, and the like.

Depending on the specific material, the support member 110 can maintain the rigidity of the fan-out type semiconductor package 100A, and the support member 110 can be used to ensure the thickness uniformity of the first encapsulation body 130. In addition, due to the support member 110, the fan-out type semiconductor package 100A according to the exemplary embodiment may be used as part of a package-on-package (POP). The support member 110 may have a through hole. The first semiconductor wafer 121 may be disposed in the through hole to separate the predetermined distance from the self-supporting member 110. A side surface of the first semiconductor wafer 121 may be surrounded by the support member 110. However, this form is merely an example and may be variously modified to have another form, and the supporting member 110 may perform another function depending on the form. In some cases, the support member 110 may also be omitted.

The material of the insulating layer 111 constituting the support member 110 is not particularly limited. For example, an insulating material may be used as the material of the insulating layer. In this case, the insulating material may be: a thermosetting resin such as epoxy resin; a thermoplastic resin such as polyimide resin; an insulating resin in which the thermosetting resin or thermoplastic resin is injected with an inorganic filler or a core material (for example, glass fiber ( Or glass cloth, fiberglass), etc.), such as prepreg, Ajinomoto Build up Film (ABF), FR-4, bismaleimide triazine , BT) and so on. Alternatively, a photosensitive imaging dielectric (PID) resin may be used as the insulating material.

The second semiconductor wafer 122 may also be hundreds to millions of elements or more The number of integrated circuits is integrated in a single chip. The integrated circuit may be volatile memory (such as dynamic random access memory (DRAM)), non-volatile memory (such as read only memory (ROM)), etc., but not This is the limit. The active surface of the second semiconductor wafer 122 means a surface of the second semiconductor wafer 122 on which the second connection pad 122 b is disposed, and the inactive surface of the second semiconductor wafer 122 means a surface opposite to the active surface. The second semiconductor wafer 122 may be formed on the basis of an active wafer. In this case, the basic material of the body 122a may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits can be formed on the body 122a. The second connection pad 122b can electrically connect the second semiconductor wafer 122 to other components, and a material of each of the second connection pads 122b can be a conductive material, such as aluminum (Al). When necessary, a passivation layer 122c may be formed in the body 122a to expose the second connection pad 122b, and the passivation layer 122c may be an oxide film, a nitride film, or the like, or a double layer composed of an oxide layer and a nitride layer. Other insulation layers (not shown) may be provided.

The adhesive member 125 can easily attach the non-active surface of the second semiconductor wafer 122 to the second insulating layer 141 b of the connection member 140. The adhesive member 125 may be a known tape, such as a die attach film. The material of the adhesive member 125 is not particularly limited. The adhesive member 125 may include, for example, an epoxy component, but is not limited thereto. Since the second semiconductor wafer 122 can be mounted more stably through the adhesive member 125, reliability can be improved.

The second encapsulation body 150 can protect the second semiconductor wafer 122. The encapsulation form of the second encapsulation body 150 is not particularly limited, and the second encapsulation body 150 may be a second encapsulation body 130 surrounds at least a part of the form of the second semiconductor wafer 122. For example, the second encapsulation body 150 may cover at least part of the active surface of the second semiconductor wafer 122, and may also cover at least part of the side surface of the second semiconductor wafer 122. The second encapsulation body 150 may include an insulating material. As the insulating material, a photosensitive imaging dielectric (PID) resin or the like can be used. However, the insulating material is not limited to this. That is, the insulating material may include materials including inorganic fillers and insulating resins, such as: thermosetting resins such as epoxy resins; thermoplastic resins such as polyimide resins; or inorganic fillers having injections such as thermosetting resins and thermoplastic resins, etc. More specifically, the resin and the like of the reinforcing material are, for example, Ajinomoto Build Up Film (ABF). In addition, known molding materials such as epoxy molding compound (EMC) can also be used. Alternatively, a material made of a thermosetting resin or a thermoplastic resin impregnated with an inorganic filler and / or a core material such as glass fiber (or glass cloth, glass fabric) can also be used as an insulating material.

The second redistribution layer 152 may be used to redistribute the second connection pad 122b to other regions. The second redistribution layer 152 may be disposed on the active surfaces of the second encapsulation body 150 and the second semiconductor wafer 122. The material of the second redistribution layer 152 may be a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof. The second redistribution layer 152 may perform various functions depending on the design of its corresponding layer. For example, the second redistribution layer 152 may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal pattern may include various signals other than a ground pattern, a power pattern, and the like, such as a data signal. In addition, the second redistribution layer 152 may include Including various pad patterns, such as through-hole pads, connection terminal pads, etc.

The second through hole 153 can be electrically connected to the second redistribution layer 152 and the second connection pad 122 b formed on different layers, thereby generating an electrical path. The second through hole 153 may penetrate the second encapsulation body 150 and may contact the second connection pad 122 b. The material of each of the second through holes 153 may be a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb ), Titanium (Ti), or an alloy thereof. A conductive material may be completely filled in each of the second through holes 153, or a conductive material may be formed along a wall surface of each of the through hole holes. The second through hole 153 may have a reverse tapered shape with a lower diameter larger than the upper diameter, and may be beneficial to a process having the second through hole 153 in this form.

The third through hole 155 can electrically connect the first redistribution layer 142 and the second redistribution layer 152 on different layers, thereby generating an electrical path. The third through hole 155 may penetrate the second encapsulation body 150, and may also penetrate the second insulating layer 141 b of the connection member 140. The material of each of the third through holes 155 may be a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb ), Titanium (Ti), or an alloy thereof. A conductive material may be completely filled in each of the third through holes 155, or a conductive material may be formed along a wall surface of each of the through hole holes. When the third through hole 155 is formed with a predetermined thickness along the wall surface of the through hole hole penetrating the second encapsulation body 150, the space between the third through hole 155 in the through hole hole may be filled by the passivation layer 160. The third through hole 155 may have a tapered shape having a lower diameter than an upper diameter, and may be beneficial to a process of forming the third through hole 155 in this form. That is, when the third through hole 155 is formed in a surface perpendicular to the first active surface, the cutting surface of the third through hole 155 may be a cone shape. The diameter of the third through hole 155 may be larger than the diameter of the second through hole 153. In addition, the height of the third through hole 155 may be greater than the height of the second through hole 153. That is, the through hole 153 and the through hole 155 may have the form of a multi-step through hole capable of stably transmitting a signal or the like.

The passivation layer 160 can protect the second redistribution layer 152 and the like from external physical or chemical damage and the like. The passivation layer 160 may have an opening exposing at least a portion of the second redistribution layer 152. The number of openings formed in the passivation layer 160 may be tens to thousands. The material of the passivation layer 160 is not particularly limited, but may be a photosensitive insulating material such as a photosensitive imaging dielectric (PID) resin. Alternatively, a solder resist may be used as a material of the passivation layer 160. Alternatively, an insulating resin may be used as a material of the passivation layer 160. The insulating resin does not include a core material but includes a filler, such as an Ajinomoto constituting film (ABF) including an inorganic filler and an epoxy resin.

The under bump metal layer 170 can improve the connection reliability of the connection terminals 180 and can improve the board level reliability of the fan-out semiconductor package 100A. The under bump metal layer 170 may be connected to the second redistribution layer 152 exposed through the opening of the passivation layer 160. The under bump metal layer 170 may be formed in the opening of the passivation layer 160 by a known metallization method, which uses a known conductive material (eg, metal), but is not limited thereto.

The connection terminal 180 may be additionally used for external physical connection or external electrical connection of the fan-out semiconductor package 100A. For example, the fan-out semiconductor package 100A can be mounted on a motherboard of an electronic device via a connection terminal 180. Each of the connection terminals 180 may be formed of a conductive material such as solder or the like. However, this is merely an example, and the material of each of the connection terminals 180 is not limited thereto. In connection terminal 180 Each may be a land, a ball, a pin, or the like. The connection terminal 180 may be formed in a multilayer structure or a single-layer structure. When the connection terminal 180 is formed in a multilayer structure, the connection terminal 180 may include a copper pillar and solder. When the connection terminal 180 is formed in a single layer structure, the connection terminal 180 may include tin-silver solder or copper (Cu). However, this is only an example, and the connection terminal 180 is not limited thereto.

The number, interval, or configuration of the connection terminals 180 are not particularly limited, and can be fully modified by those having ordinary knowledge in the technical field depending on design details. For example, the connection terminal 180 may be set to a number of tens to thousands, and may also be set to a number of tens to thousands or more or a number of tens to thousands or less. When the connection terminal 180 is a solder ball, the connection terminal 180 may cover the side surface of the under bump metal layer 170 extending to one surface of the passivation layer 160, and the connection reliability may be more excellent.

At least one of the connection terminals 180 may be configured in the fan-out area. The fan-out area is an area other than the first semiconductor wafer 121 and the second semiconductor wafer 122. That is, the fan-out type semiconductor package 100A according to an exemplary embodiment may be a fan-out type package. Compared with the fan-in package, the fan-out package can have excellent reliability, the fan-out package can implement multiple input / output (I / O) terminals, and the fan-out package can facilitate three-dimensional (3D) )interconnection. In addition, compared to a ball grid array (BGA) package, a land grid array (LGA) package, etc., the fan-out package can be manufactured with a smaller thickness, and Competitive price.

Meanwhile, although not shown in the figure, the metal layer may be further disposed on the Through the wall of the hole. The metal layer can be used to efficiently dissipate the heat generated by the first semiconductor wafer 121. In addition, the metal layer can also be used to block electromagnetic waves. In addition, in addition to the first semiconductor wafer 121, individual passive components (for example, capacitors or inductors) may be further disposed in the through holes. In addition to the structure described above, a structure known in the related art may be applied.

11A to 11D are schematic diagrams illustrating an example of a manufacturing process of the fan-out semiconductor package in FIG. 9.

11A, the supporting member 110 may be prepared in advance. The support member 110 may be formed of an insulating layer 111. The insulating layer 111 may be a copper clad laminate (CCL) without a cover, but is not limited thereto. Then, a through hole may be formed in the support member 110. The through holes can be formed using mechanical drilling, laser drilling, etc., but not limited to this. After the through holes are formed, a desmear process and the like can be additionally performed. Next, the first semiconductor wafer 121 may be disposed in a through-hole of the support member 110 in a face-down manner, and may be covered with the first encapsulation body 130. An adhesive film (not shown) or the like can be used to configure the first semiconductor wafer 121. For example, an adhesive film (not shown) may be attached to the support member 110, the first semiconductor wafer 121 may be attached to an adhesive film (not shown) exposed through the through hole, and a known lamination method or coating may be used. A method of forming the first encapsulation body 130 by a cloth method and removing an adhesive film (not shown).

11B, a first insulating layer 141 a may be formed on the active surfaces of the support member 110 and the first semiconductor wafer 121. The first insulating layer 141a may also be formed by laminating or coating a photosensitive imaging dielectric (PID) resin or the like. Then, a through-hole hole 143h penetrating the first insulating layer 141a may be formed. Lithography (e.g. exposure, Development, etc.) forming through-hole holes 143h. Then, a first redistribution layer 142 and a first through hole 143 may be formed. The first redistribution layer 142 and the first through hole 143 may be formed by a method of forming a pattern using a dry film or the like and then filling the pattern by a plating process. The plating process can be a subtractive process, an additive process, a semi-additive process (SAP), a modified semi-additive process (MSAP), etc., but Not limited to this.

11C, a second insulating layer 141b may be formed on the first insulating layer 141a. The second insulating layer 141b may also be formed by a method such as laminating or coating a photosensitive imaging dielectric (PID) resin. Therefore, the connection member 140 can be formed. Next, the second semiconductor wafer 122 may be attached to the second insulating layer 141 b using an adhesive member 125 or the like. Next, a second encapsulation body 150 covering at least a part of the second semiconductor wafer 122 may be formed by a known lamination method or a coating method.

Referring to FIG. 11D, a through-hole hole penetrating through the second encapsulation body 150 may be formed next. In addition, a through-hole 155h may be formed to penetrate the second encapsulation body 150 and the second insulating layer 141b of the connection member 140. The through-hole holes and the through-hole holes 155h penetrating through the second encapsulation body 150 may be formed by a lithography method using exposure and development. However, depending on the specific material of the second encapsulation body 150, laser drilling, mechanical drilling, etc. may also be used to form through-hole holes and through-hole holes 155h that penetrate the second encapsulation body 150. Then, a second redistribution layer 152, a second via hole 153, and a third via hole 155 can be formed. The second redistribution layer 152, the second through hole 153, and the third through hole 155 can be formed by a method of forming a pattern using a dry film or the like and then filling the pattern by a plating process. The plating process can be a subtractive process, an additive process, or a semi-additive process (semi-additive process (SAP), modified semi-additive process (MSAP), etc., but not limited to this. Then, the passivation layer 160, the under bump metal layer 170, and the connection terminal 180 may be sequentially formed. The passivation layer 160 may be formed by a known lamination method or hardening method, the under bump metal layer 170 may be formed by a known metallization method, and the connection terminal 180 may be formed by a reflow process or the like.

Meanwhile, a series of processes may be the following processes: preparing a support member 110 having a larger size, manufacturing a plurality of fan-out semiconductor packages, and then separating the plurality of fan-out semiconductor packages by a sawing process. Integrated into a separate fan-out type semiconductor package to facilitate mass production. In this case, productivity may be excellent.

FIG. 12 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

Referring to the drawings, in a fan-out type semiconductor package 100B according to an exemplary embodiment, the first semiconductor wafer 121 and the third semiconductor wafer 123 may be arranged side by side in a through hole of the support member 110. The first semiconductor wafer 121 and the third semiconductor wafer 123 may have a first connection pad 121b disposed on the active surface of the body 121a and a third connection pad 123b disposed on the active surface of the body 123a, and the first connection pad 121b Each of the third connection pads 123 b may be re-routed through the first re-wiring layer 142 of the connection member 140. In addition, by using the adhesive member 125, the second semiconductor wafer 122 and the fourth semiconductor wafer 124 can be attached to the connection member 140 side by side. The second semiconductor wafer 122 and the fourth semiconductor wafer 124 may each have a configuration The second connection pad 122b on the active surface of the body 122a and the fourth connection pad 124b disposed on the active surface of the body 124a, and each of the second connection pad 122b and the fourth connection pad 124b can be formed by The second redistribution layer 152 on the second encapsulation body 150 is rewired. The passivation layer 123c and the passivation layer 124c may be disposed on the active surfaces of the third semiconductor wafer 123 and the fourth semiconductor wafer 124, respectively. The descriptions and manufacturing methods of other architectures besides the aforementioned architectures overlap with those described above, and are therefore omitted.

13 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

Referring to the drawings, in the fan-out type semiconductor package 100C according to the exemplary embodiment, the third through hole 155 may have a shape of a metal post. That is, the third through hole 155 may also form the shape of a metal pillar when necessary. The metal pillar may be, for example, a copper pillar, but is not limited thereto. The descriptions and manufacturing methods of other architectures besides the aforementioned architectures overlap with those described above, and are therefore omitted. Meanwhile, the components of the above-mentioned characteristic portions of the fan-out type semiconductor package 100B and the fan-out type semiconductor package 100C according to another exemplary embodiment may be combined with each other.

FIG. 14 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

Referring to the drawings, in a fan-out type semiconductor package 100D according to another exemplary embodiment, the third through hole 155 may include a metal pillar 155a and a through-hole conductor 155b. That is, when necessary, the third through hole 155 may be formed to include the metal pillar 155a and the through hole conductor 155b. In addition to the above architecture description and manufacturing methods and The above content overlaps and is therefore omitted. Meanwhile, the components of the above-mentioned characteristic portions of the fan-out type semiconductor package 100B, the fan-out type semiconductor package 100C, and the fan-out type semiconductor package 100D according to another exemplary embodiment may be combined with each other.

15 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

Referring to the drawings, in a fan-out type semiconductor package 100E according to another example of the present disclosure, the supporting member 110 may include a first insulating layer 111a, a first redistribution layer 112a, a second redistribution layer 112b, and a second insulating layer. 111b and the third redistribution layer 112c, the first insulation layer 111a is in contact with the connection member 140, the first redistribution layer 112a is in contact with the connection member 140 and is embedded in the first insulation layer 111a, and the second redistribution layer 112b is disposed in contact with the On the other surface of the first insulation layer 111a opposite to the surface of the first insulation layer 111a having the first redistribution layer 112a, the second insulation layer 111b is disposed on the first insulation layer 111a and covers the second redistribution layer 112b. The third redistribution layer 112c is disposed on the second insulating layer 111b. Since the support member 110 may include a large number of redistribution layers 112a, 112b, and 112c, the support member 110 may perform some functions of the connection member 140, so that the connection member 140 may be simplified. Therefore, it is possible to suppress a decrease in the yield due to a defect occurring in the process of forming the connection member 140. Since the first redistribution layer 112a is embedded in the first insulation layer 111a, the insulation distance of the insulation layer 141a of the connection member 140 may be relatively fixed. The first redistribution layer 112a may be recessed in the first insulation layer 111, so that a lower surface of the first insulation layer 111a has a step relative to the lower surface of the first redistribution layer 112a. Therefore, it is possible to prevent the first encapsulation body 130 from penetrating into the first redistribution layer 112a. First cloth The line layer 112a, the second redistribution layer 112b, and the third redistribution layer 112c may be electrically connected to each other through the first through hole 113a and the second through hole 113b penetrating the first insulating layer 111a and the second insulating layer 111b.

The lower surface of the first redistribution layer 112 a of the support member 110 may be disposed above the lower surface of the first connection pad 121 b of the first semiconductor wafer 121. In addition, the distance between the first redistribution layer 142 of the connection member 140 and the first redistribution layer 112a of the support member 110 may be greater than the first redistribution layer 142 of the connection member 140 and the first connection pad of the first semiconductor wafer 121. The distance between 121b. Here, the first redistribution layer 112a may be recessed in the first insulating layer 111a. The horizontal height of the second redistribution layer 112 b of the support member 110 may be between the active surface and the non-active surface of the first semiconductor wafer 121. The thickness of the support member 110 may be formed corresponding to the thickness of the first semiconductor wafer 121. Therefore, the horizontal height of the second redistribution layer 112 b formed in the supporting member 110 may be between the active surface and the non-active surface of the first semiconductor wafer 121.

The thicknesses of the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c of the support member 110 may be greater than the thickness of the first redistribution layer 142 of the connection member 140. Since the thickness of the support member 110 may be equal to or greater than the thickness of the first semiconductor wafer 121, the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c may be formed in a larger size according to the specifications of the support member 110. On the other hand, considering the thinness, the first redistribution layer 142 of the connection member 140 may be formed with a relatively small thickness.

The support member 110 can be prepared by, for example, the following steps: preparing a carrier film having a metal layer formed on one surface or an opposite surface of the carrier film; using gold The metal layer serves as a seed layer to form a first redistribution layer 112a; a first insulating layer 111a covering the first redistribution layer 112a on a metal layer; a second redistribution layer 112b to be formed on the first insulating layer 111a; Cover the second insulating layer 111b of the second redistribution layer 112b on the first insulating layer 111a; form a third redistribution layer 112c on the second insulating layer 111b to form a supporting member 110; separate the supporting member 110 from the carrier film ; Then remove the remaining metal layer on the first redistribution layer 112a. When the metal layer is removed, a recessed portion may be formed in the support member 110. The redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c can be formed by patterning using a dry film and filling the pattern by a known plating process. The insulating layer 111a and the insulating layer 111b can be formed by a known laminating method or a coating method and a hardening method. Meanwhile, when the second redistribution layer 112b and the third redistribution layer 112c are formed after the via holes are formed in the first insulating layer 111a and the second insulating layer 111b, the first via hole 113a and the second via hole 113b are also formed. It can be formed by electroplating.

The descriptions and manufacturing methods of other architectures besides the aforementioned architectures overlap with those described above, and are therefore omitted. Meanwhile, components of the above-mentioned characteristic portions of the fan-out semiconductor package 100B, the fan-out semiconductor package 100C, the fan-out semiconductor package 100D, and the fan-out semiconductor package 100E according to another exemplary embodiment may be combined with each other.

FIG. 16 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

Referring to the drawings, in a fan-out type semiconductor package 100F according to another example of the present disclosure, the supporting member 110 may include a first insulating layer 111 a and a first redistribution layer. 112a, the second redistribution layer 112b, the second insulating layer 111b, the third redistribution layer 112c, and the fourth redistribution layer 112d. The first redistribution layer 112a and the second redistribution layer 112b are disposed on the first insulating layer 111a, respectively. On the opposite surface, the second insulation layer 111b is disposed on the first insulation layer 111a and covers the first redistribution layer 112a, the third redistribution layer 112c is disposed on the second insulation layer 111b, and the third insulation layer 111c is disposed on The first insulation layer 111a covers the second redistribution layer 112b, and the fourth redistribution layer 112d is disposed on the third insulation layer 111c. Since the supporting member 110 may include a large number of redistribution layers 112a, redistribution layers 112b, redistribution layers 112c, and redistribution layers 112d, the connection member 140 may be further simplified. The first redistribution layer 112a, the second redistribution layer 112b, the third redistribution layer 112c, and the fourth redistribution layer 112d may pass through the first insulation layer 111a, the second insulation layer 111b, and the third insulation layer 111c. A through hole 113a, a second through hole 113b, and a third through hole 113c are electrically connected to each other.

The thickness of the first insulating layer 111a may be greater than the thickness of the second insulating layer 111b and the thickness of the third insulating layer 111c. Basically, the first insulating layer 111a may be relatively thick to maintain rigidity, and the second insulating layer 111b and the third insulating layer 111c may be introduced to form a larger number of redistribution layers 112c and 112d. The insulating material included in the first insulating layer 111a may be different from the insulating materials included in the second insulating layer 111b and the third insulating layer 111c. For example, the first insulating layer 111a may be, for example, a prepreg including a core material, an inorganic filler, and an insulating resin, and the second insulating layer 111b and the third insulating layer 111c may be films made of Ajinomoto or include an inorganic filler and Photosensitive insulating film of insulating resin. However, the material of the first insulating layer 111a and the material of the second insulating layer 111b The material of the third insulating layer 111c is not limited thereto. Similarly, the diameter of the first through hole 113a may be larger than the diameters of the second through hole 113b and the third through hole 113c.

The thickness of the redistribution layer 112a, the redistribution layer 112b, the redistribution layer 112c, and the redistribution layer 112d of the support member 110 may be greater than the thickness of the first redistribution layer 142 of the connection member 140. Since the thickness of the support member 110 may be equal to or greater than the thickness of the semiconductor wafer 121, the redistribution layer 112a, redistribution layer 112b, redistribution layer 112c, and redistribution layer 112d may also be formed in a larger size. On the other hand, considering the thinness, the first redistribution layer 142 of the connection member 140 may be formed with a relatively small thickness.

The support member 110 may be prepared by, for example, the following steps: preparing a copper clad laminate (CCL) as the first insulating layer 111a, and forming a first redistribution layer 112a and a second redistribution layer on opposite surfaces of the first insulating layer 111a, respectively. 112b. Use a copper layer of a copper clad laminate as a seed layer, a stacked Ajinomoto composition film, etc. as the second insulating layer 111b and the third insulating layer 111c on the opposite surfaces of the first insulating layer 111a, respectively. Then, a third redistribution layer 112c and a fourth redistribution layer 112d are formed on the second insulating layer 111b and the third insulating layer 111c, respectively. The redistribution layer 112a, the redistribution layer 112b, the redistribution layer 112c, and the redistribution layer 112d may be formed by patterning using a dry film and filling a pattern by a known plating process. The insulating layer 111b and the insulating layer 111c can be formed by a known laminating method or a coating method and a hardening method. Meanwhile, when the via holes are formed in the first insulating layer 111a and the second insulating layer 111b, the first redistribution layer 112a, the second redistribution layer 112b, the third redistribution layer 112c, and the fourth redistribution layer 112d are formed. The first through hole 113a, the second through hole 113b, and the third through hole 113c may also be formed by electroplating.

The descriptions and manufacturing methods of other architectures besides the aforementioned architectures overlap with those described above, and are therefore omitted. Meanwhile, the components of the above-mentioned characteristic portions of the fan-out semiconductor package 100B, the fan-out semiconductor package 100C, the fan-out semiconductor package 100D, the fan-out semiconductor package 100E, and the fan-out semiconductor package 100F according to another exemplary embodiment. Can be combined with each other.

As described above, according to the exemplary embodiments of the present disclosure, a fan-out type semiconductor package can be provided. Although a plurality of semiconductor wafers are used, the fan-out type semiconductor package can be thinned with improved efficiency and excellent reliability.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention.

Claims (14)

A fan-out type semiconductor package includes: a first semiconductor wafer having a first active surface on which a first connection pad is disposed and a first non-active surface opposite to the first active surface; a first encapsulation body, Covering at least a part of the first semiconductor wafer; a connecting member, which is disposed on the first encapsulation body and the first active surface of the first semiconductor wafer, and includes a first through hole and via the The first through hole is electrically connected to the first redistribution layer of the first connection pad; the second semiconductor wafer has a second active surface on which the second connection pad is disposed and is opposite to the second active surface And attached to a second non-active surface of the connection member; a second encapsulation body covering at least a portion of the connection member and covering at least a portion of the second semiconductor wafer; a second redistribution layer, configured On the second encapsulation body and the second active surface of the second semiconductor wafer; a second through hole penetrating through the second encapsulation body, and connecting the second connection pad with the first The double wiring layers are electrically connected to each other; and a third via, Penetrate the second encapsulation body and electrically connect the first redistribution layer and the second redistribution layer to each other, wherein the length of the longest side of the first cut surface of the second through hole is shorter than the length The length of the longest side of the second cutting surface of the third through hole, the first cutting surface of the second through hole and the second cutting surface of the third through hole are parallel to the second The active surface is cut by a plane at any horizontal height, the third through hole is formed along the wall surface of the through hole of the second encapsulation body to form a predetermined thickness, and is perpendicular to the first active surface The cutting surface of the through-hole hole cut by the plane of the plane is tapered. The fan-out semiconductor package according to item 1 of the patent application scope, wherein the first region is a projection region where the first semiconductor wafer is projected in a direction perpendicular to the first active surface, and the second region is a region surrounding the projection A region of a first region, and all of the first connection pads connected to the first through hole are re-routed to the second region via the first re-wiring layer. The fan-out type semiconductor package according to item 1 of the scope of patent application, wherein a cutting surface of the third through hole cut in a plane perpendicular to the first active surface is tapered. A fan-out type semiconductor package includes: a first semiconductor wafer having a first active surface on which a first connection pad is disposed and a first non-active surface opposite to the first active surface; a first encapsulation body, Covering at least a part of the first semiconductor wafer; a connecting member, which is disposed on the first encapsulation body and the first active surface of the first semiconductor wafer, and includes a first through hole and via the The first through hole is electrically connected to the first redistribution layer of the first connection pad; the second semiconductor wafer has a second active surface on which the second connection pad is disposed and is opposite to the second active surface And attached to a second non-active surface of the connection member; a second encapsulation body covering at least a portion of the connection member and covering at least a portion of the second semiconductor wafer; a second redistribution layer, configured On the second encapsulation body and the second active surface of the second semiconductor wafer; a second through hole penetrating through the second encapsulation body, and connecting the second connection pad with the first The double wiring layers are electrically connected to each other; and a third via, Penetrate the second encapsulation body and electrically connect the first redistribution layer and the second redistribution layer to each other, wherein the length of the longest side of the first cut surface of the second through hole is shorter than the length The length of the longest side of the second cutting surface of the third through hole, the first cutting surface of the second through hole and the second cutting surface of the third through hole are parallel to the second The plane on any level of the active surface is cut, the first connection pad is arranged on a central portion of the first active surface of the first semiconductor wafer, and the first connection pad directly contacts the The first through hole of the connection member. The fan-out semiconductor package according to item 4 of the patent application scope, further comprising a passivation layer configured on the second encapsulation body and the second active surface of the second semiconductor wafer and Covering at least a portion of the second redistribution layer. The fan-out type semiconductor package according to item 5 of the scope of patent application, wherein the third through hole is formed along a wall surface of the through hole hole penetrating through the second encapsulation body, and the passivation layer is formed. A space between the third through holes filled in the through hole holes. The fan-out semiconductor package according to item 4 of the patent application scope, further comprising a die attach film, and the second non-active surface of the second semiconductor wafer is attached to the die attach film via the die attach film. The connecting member. The fan-out type semiconductor package according to item 4 of the scope of patent application, wherein the connection member includes a first insulating layer, the first redistribution layer, the first through-hole, and a second insulating layer. An insulating layer is disposed on the first active surface of the first encapsulation body and the first semiconductor wafer. The first redistribution layer is disposed on the first insulating layer. A hole penetrates the first insulation layer and electrically connects the first connection pad and the first redistribution layer to each other. The second insulation layer is disposed on the first insulation layer and covers the first insulation layer. At least a portion of the redistribution layer, and the second non-active surface of the second semiconductor wafer is attached to the second insulating layer. A fan-out type semiconductor package includes: a first semiconductor wafer having a first active surface on which a first connection pad is disposed and a first non-active surface opposite to the first active surface; a first encapsulation body, Covering at least a part of the first semiconductor wafer; a connecting member, which is disposed on the first encapsulation body and the first active surface of the first semiconductor wafer, and includes a first through hole and via the The first through hole is electrically connected to the first redistribution layer of the first connection pad; the second semiconductor wafer has a second active surface on which the second connection pad is disposed and is opposite to the second active surface And attached to a second non-active surface of the connection member; a second encapsulation body covering at least a portion of the connection member and covering at least a portion of the second semiconductor wafer; a second redistribution layer, configured On the second encapsulation body and the second active surface of the second semiconductor wafer; a second through hole penetrating through the second encapsulation body, and connecting the second connection pad with the first The double wiring layers are electrically connected to each other; and a third via, Penetrate the second encapsulation body and electrically connect the first redistribution wiring layer and the second redistribution wiring layer to each other, a support member, the support member has a through hole and is disposed on one surface of the connection member Preferably, the first semiconductor wafer is arranged on the surface, wherein the length of the longest side of the first cut surface of the second through hole is smaller than the length of the longest side of the second cut surface of the third through hole, The first cutting surface of the second through-hole and the second cutting surface of the third through-hole are cut from a plane at any horizontal height parallel to the second active surface, and The first semiconductor wafer is disposed in the through hole, and the first encapsulation body fills at least a portion of the through hole. The fan-out type semiconductor package according to item 9 of the patent application scope, wherein the supporting member includes a third redistribution layer electrically connected to the first redistribution layer. The fan-out type semiconductor package according to item 9 of the patent application scope, wherein the supporting member includes a first insulating layer, a third redistribution layer, and a fourth redistribution layer, and the third redistribution layer is connected to the connection A member contacts and is embedded in the first insulating layer, and the fourth redistribution layer is disposed on the first insulating layer opposite to a surface of the first insulating layer in which the third redistribution layer is embedded. On another surface. The fan-out type semiconductor package module according to item 11 of the patent application scope, wherein the supporting member further includes a second insulating layer and a fifth redistribution layer, and the second insulating layer is disposed on the first insulating layer And covers the fourth redistribution layer, and the fifth redistribution layer is disposed on the second insulating layer. The fan-out type semiconductor package according to item 9 of the scope of patent application, wherein the supporting member includes a first insulation layer, a third redistribution layer, a fourth redistribution layer, a second insulation layer, and a fifth redistribution layer, The third redistribution layer and the fourth redistribution layer are respectively disposed on opposite surfaces of the first insulation layer, and the second insulation layer is disposed on the first insulation layer and covers the third insulation layer. A redistribution layer, and the fifth redistribution layer is disposed on the second insulating layer. According to the fan-out type semiconductor package according to item 13 of the patent application scope, wherein the supporting member further includes a third insulating layer and a sixth redistribution layer, the third insulating layer is disposed on the first insulating layer and The fourth redistribution layer is covered, and the sixth redistribution layer is disposed on the third insulating layer.