TWI655883B - Circuit board and method for making thereof - Google Patents
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Abstract
一種線路板結構,其包括一基板、若干導電跡線、至少一焊線手指、一填縫層以及至少一表面電鍍層,導電跡線及焊線手指均形成於基板表面,相鄰導電跡線之間或導線手指與相鄰導電跡線之間具有間隙,填縫層填設於該些間隙,表面電鍍層則形成於焊線手指頂面,其可為鎳層、金層、銀層、鈀層其中一者或其層疊結構,其中表面電鍍層具有一頂面及至少一側面,且所述側面的至少一部分並未接觸填縫層。藉此,本發明的線路板結構焊錫性佳、可相容於打線技術,且導線的密度可得提高。A circuit board structure comprising a substrate, a plurality of conductive traces, at least one wire finger, a seam layer and at least one surface plating layer, wherein the conductive traces and the wire fingers are formed on the surface of the substrate, adjacent conductive traces There is a gap between the wire fingers and the adjacent conductive traces, the gap layer is filled in the gaps, and the surface plating layer is formed on the top surface of the wire bonding finger, which may be a nickel layer, a gold layer, a silver layer, One of the palladium layers or the laminated structure thereof, wherein the surface plating layer has a top surface and at least one side surface, and at least a portion of the side surfaces does not contact the caulking layer. Thereby, the circuit board structure of the present invention has good solderability, is compatible with the wire bonding technology, and can increase the density of the wires.
Description
本發明是關於一種印刷電路板的結構及其製法。The present invention relates to a structure of a printed circuit board and a method of fabricating the same.
隨著電子產品的小型化趨勢,線路板也需製作地更加輕薄,線路板上的導電跡線(trace)及焊線手指(bonding finger)的排列也越來越密集,因此其設計及製造所面臨的挑戰也越來越高。With the trend toward miniaturization of electronic products, circuit boards are also required to be made lighter and thinner, and traces of conductive traces and bonding fingers on the circuit board are increasingly denser, so the design and manufacturing facilities thereof The challenges are also getting higher and higher.
焊線手指之間的間隙越小,製作時越容易發生短路的問題。例如,以往採銅箔限定焊墊設計(Copper Defined Pad Design,又稱Non-Solder Mask Defined,簡稱NSMD)進行加工時,由於防焊層的開窗大於焊墊,因此在銅箔上進行表面電鍍時,鎳、金層1會包覆到銅箔2的三個表面(如第11圖所示),銅箔間隙越小,短路的風險就越高,因而無法滿足精密加工的需求。The smaller the gap between the fingers of the wire, the more likely the short circuit occurs during production. For example, in the past, Copper Defined Pad Design (also known as Non-Solder Mask Defined, NSMD for short) is used for surface plating on copper foil because the window of the solder resist layer is larger than the solder pad. When the nickel and gold layers 1 are coated on the three surfaces of the copper foil 2 (as shown in Fig. 11), the smaller the gap of the copper foil, the higher the risk of short circuit, and thus the demand for precision processing cannot be satisfied.
另有人採用防焊開窗限定技術(Solder Mask Defined,簡稱SMD)將表面電鍍的鎳、金層1限定於防焊層3開窗範圍內(如第12圖所示)。然而,SMD有其先天上的侷限在於,鎳、金層的側邊被防焊層完整包覆,以致於難以利用打線技術(wire bonding)將晶片與基板上的焊線手指以導線連接,導致打線技術的良率偏低。除此之外,採用SMD也會導致焊錫性變差(只有頂面為焊面)並提高走線難度(銅箔2面積通常會大於表面電鍍層的面積)。Another person uses a Solder Mask Defined (SMD) to limit the surface-plated nickel and gold layer 1 to the window of the solder resist layer 3 (as shown in Fig. 12). However, SMD has its inherent limitations in that the sides of the nickel and gold layers are completely covered by the solder mask, so that it is difficult to wire-bond the wafer to the wire fingers on the substrate by wire bonding, resulting in wire bonding. The yield of wire bonding technology is low. In addition, the use of SMD can also lead to poor solderability (only the top surface is the solder joint) and increase the difficulty of routing (copper foil 2 area is usually larger than the surface plating area).
有鑑於此,本發明之主要目的在於提供一種非以SMD技術製作表面電鍍層的線路板結構及製法。In view of the above, the main object of the present invention is to provide a circuit board structure and a manufacturing method for fabricating a surface plating layer without SMD technology.
本發明的另一目的在於提供一種能兼顧導線密度與加工良率的線路板結構及製法。Another object of the present invention is to provide a circuit board structure and a manufacturing method capable of achieving both wire density and processing yield.
為了達成上述及其他目的,本發明提供一種線路板結構,其包括一基板、若干導電跡線、至少一焊線手指、一填縫層以及至少一表面電鍍層,導電跡線及焊線手指均形成於基板表面,相鄰導電跡線之間或導線手指與相鄰導電跡線之間具有間隙,填縫層填設於該些間隙,表面電鍍層則形成於焊線手指頂面,其可為鎳層、金層、銀層、鈀層其中一者或其層疊結構,其中表面電鍍層具有一頂面及至少一側面,且所述側面的至少一部分並未接觸填縫層。In order to achieve the above and other objects, the present invention provides a circuit board structure including a substrate, a plurality of conductive traces, at least one wire finger, a seam layer, and at least one surface plating layer, conductive traces and wire fingers. Formed on the surface of the substrate, between adjacent conductive traces or between the wire fingers and adjacent conductive traces, a gap layer is filled in the gaps, and a surface plating layer is formed on the top surface of the wire bonding finger, which can be It is a nickel layer, a gold layer, a silver layer, a palladium layer or a laminated structure thereof, wherein the surface plating layer has a top surface and at least one side surface, and at least a portion of the side surface does not contact the caulking layer.
為了達成上述及其他目的,本發明提供一種線路板結構的製法,包括:在一基材表面形成若干導電跡線及至少一焊線手指,相鄰所述導電跡線之間具有間隙,該焊線手指與相鄰所述導電跡線之間亦具有間隙;在該基材、導電跡線、焊線手指表面及該些間隙塗布填縫材料;將該些導電跡線、焊線手指表面的填縫材料移除,保留填設於該些間隙內的填縫材料作為一填縫層;以及在該焊線手指頂面形成一表面電鍍層,該表面電鍍層為鎳層、金層、銀層、鈀層其中一者或其層疊結構,該表面電鍍層具有一頂面及至少一側面,且所述側面的至少一部分並未接觸該填縫層。In order to achieve the above and other objects, the present invention provides a method for fabricating a circuit board structure, comprising: forming a plurality of conductive traces on a surface of a substrate and at least one wire bonding finger, and having a gap between adjacent conductive traces, the soldering There is also a gap between the line finger and the adjacent conductive trace; coating the caulking material on the substrate, the conductive trace, the surface of the bonding wire finger and the gap; the conductive trace, the surface of the bonding wire finger The caulking material is removed, and the caulking material filled in the gaps is retained as a caulking layer; and a surface plating layer is formed on the top surface of the bonding wire finger, and the surface plating layer is a nickel layer, a gold layer, and a silver layer. And a laminated structure of the layer or the palladium layer, the surface plating layer having a top surface and at least one side surface, and at least a portion of the side surface does not contact the gap layer.
基於上述設計,表面電鍍層的頂面及至少一側面均可與焊錫接觸,焊錫性佳,表面電鍍層的側面未被遮蔽的特性使得本發明的線路板結構仍可相容於打線技術(wire bonding),而填設於間隙內的填縫層則可以避免以往NSMD易因間隙過小造成短路的問題,導線的密度可望提高。Based on the above design, the top surface and at least one side of the surface plating layer can be in contact with the solder, the solderability is good, and the side surface of the surface plating layer is unshielded, so that the circuit board structure of the present invention can still be compatible with the wire bonding technology (wire Bonding), and the filling layer filled in the gap can avoid the problem that the NSMD is easy to short-circuit due to the small gap, and the density of the wire is expected to increase.
請參考第1圖,所繪示者為本發明線路板結構其中一實施例的剖面圖,該線路板結構包括一基板10、若干導電跡線20、若干焊線手指30、一填縫層40及表面電鍍層50。本實施例的線路板結構例如可為封裝用的IC載板。Please refer to FIG. 1 , which is a cross-sectional view showing an embodiment of a circuit board structure according to the present invention. The circuit board structure includes a substrate 10 , a plurality of conductive traces 20 , a plurality of bonding wire fingers 30 , and a filling layer 40 . And a surface plating layer 50. The circuit board structure of this embodiment can be, for example, an IC carrier board for packaging.
基板10由絕緣材料製成,例如BT樹脂及ABF樹脂,基板10形成有貫通孔11,貫通孔11表面形成銅膜以連接基板10的不同表面。導電跡線(trace)20及焊線手指(bonding finger)30均形成於基板10表面,其中焊線手指30為線路板結構中需與焊錫接觸的部分,導電跡線20原則上不與焊錫接觸,常見用以製作導電跡線20及焊線手指30的材料為銅,相鄰導電跡線20及焊線手指30與其相鄰導電跡線20之間具有間隙,填縫層40填設於該等間隙,表面電鍍層50則形成於焊線手指30頂面,且表面電鍍層50具有一頂面51及至少一側面52,所述側面的至少一部分並未接觸填縫層40。其中,表面電鍍層50可為鎳層、金層、銀層、鈀層其中一者或其層疊結構,例如,表面電鍍層可為鎳金層疊結構、鎳銀金層疊結構、鎳銀層疊結構或鎳鈀金層疊結構。The substrate 10 is made of an insulating material such as BT resin and ABF resin, and the substrate 10 is formed with through holes 11 formed on the surface of the through holes 11 to connect different surfaces of the substrate 10. A conductive trace 20 and a bonding finger 30 are formed on the surface of the substrate 10, wherein the bonding wire finger 30 is a portion of the wiring board structure that needs to be in contact with the solder, and the conductive trace 20 is not in contact with the solder in principle. The material used to make the conductive trace 20 and the wire finger 30 is copper. The adjacent conductive trace 20 and the wire finger 30 have a gap between the adjacent conductive trace 20 and the gap layer 40 is filled in the hole. The surface plating layer 50 is formed on the top surface of the bonding wire finger 30, and the surface plating layer 50 has a top surface 51 and at least one side surface 52, at least a portion of which does not contact the caulking layer 40. The surface plating layer 50 may be one of a nickel layer, a gold layer, a silver layer, and a palladium layer or a laminated structure thereof. For example, the surface plating layer may be a nickel gold laminated structure, a nickel silver gold laminated structure, a nickel silver laminated structure or Nickel palladium gold laminate structure.
為了避免導電跡線20裸露,線路板結構還可包括一防焊層60形成於導電跡線20及部分填縫層40表面。填縫層40及防焊層60兩者均為絕緣層,例如均由防焊材料製成;在其他可能的實施方式中,填縫層40可為異於防焊層60的其他絕緣填充材料,例如環氧樹脂、矽樹脂、聚醯亞胺樹脂、酚類樹脂、氟樹脂、二氧化矽、氧化鋁等材料。In order to avoid the conductive traces 20 from being exposed, the circuit board structure may further include a solder resist layer 60 formed on the surface of the conductive traces 20 and a portion of the fillet layer 40. Both the caulking layer 40 and the solder resist layer 60 are insulating layers, for example, all made of a solder resist material; in other possible embodiments, the caulking layer 40 may be other insulating filling materials different from the solder resist layer 60. For example, epoxy resin, enamel resin, polyimide resin, phenol resin, fluororesin, ceria, alumina, and the like.
在可能的實施方式中,線路板結構的一部分焊線手指的側面可能被防焊層完整包覆,其他部分的焊線手指至少一部分側面裸露而不與防焊層及填縫層接觸。In a possible embodiment, a part of the wire finger of the circuit board structure may be completely covered by the solder resist layer, and at least a part of the side of the wire finger of the other part is exposed without being in contact with the solder resist layer and the caulking layer.
以下針對本發明線路板結構及其製法其中一實施例,參照圖式說明如下。Hereinafter, an embodiment of the circuit board structure and the method of manufacturing the same according to the present invention will be described below with reference to the drawings.
如第2圖所示,以層合有薄銅箔5A的基板10作為起始材料,將該基板10鑽孔,形成若干貫穿基板10不同表面的貫通孔11(如第3圖所示),而後進行鍍銅,於薄銅箔5A及貫通孔11表面形成面銅5B及孔銅5C(如第4圖所示),接著,如第5圖所示,以線路影像轉移技術將面銅5B及薄銅箔5A圖像化,其中一部分面銅5B及薄銅箔5A作為導電跡線20,另一部分則作為焊線手指30,且經圖形化後,導電跡線20之間及焊線手指30與導電跡線20之間具有間隙。As shown in FIG. 2, the substrate 10 on which the thin copper foil 5A is laminated is used as a starting material, and the substrate 10 is drilled to form a plurality of through holes 11 penetrating through different surfaces of the substrate 10 (as shown in FIG. 3). Then, copper plating is performed to form the surface copper 5B and the hole copper 5C on the surface of the thin copper foil 5A and the through hole 11 (as shown in FIG. 4), and then, as shown in FIG. 5, the surface copper 5B is formed by the line image transfer technique. And the thin copper foil 5A is imaged, wherein a part of the surface copper 5B and the thin copper foil 5A are used as the conductive traces 20, and the other part is used as the bonding wire fingers 30, and after being patterned, between the conductive traces 20 and the bonding wire fingers There is a gap between the 30 and the conductive traces 20.
如第6圖所示,以防焊材料6A填平線路間隙,此時防焊材料6A亦覆蓋導電跡線20及焊線手指30的頂面。如第7圖所示,利用刷磨輪7A將導電跡線20及焊線手指30頂面的防焊材料6A刷除,留下位於間隙內的防焊材料作為填縫層40,成為如第8圖所示的狀態。As shown in Fig. 6, the solder resist material 6A fills the line gap, and the solder resist material 6A also covers the conductive trace 20 and the top surface of the bond finger 30. As shown in FIG. 7, the conductive trace 20 and the solder resist 6A on the top surface of the bonding wire finger 30 are brushed off by the brush grinding wheel 7A, and the solder resist material located in the gap is left as the caulking layer 40, which becomes the eighth layer. The state shown in the figure.
如第9圖所示,在導電跡線20及部分填縫層40頂面覆蓋一防焊層60,焊線手指30頂面則保持裸露。As shown in FIG. 9, a solder resist layer 60 is covered on the top surface of the conductive trace 20 and a portion of the fillet layer 40, and the top surface of the solder wire finger 30 remains bare.
接著,進行表面電鍍處理,在焊線手指30頂面形成表面電鍍層50,表面電鍍層50的頂面51及側面52的一部分裸露而未接觸填縫層40及防焊層60,成為如第1圖所示的線路板結構。Next, a surface plating treatment is performed to form a surface plating layer 50 on the top surface of the bonding wire finger 30, and a part of the top surface 51 and the side surface 52 of the surface plating layer 50 is exposed without contacting the caulking layer 40 and the solder resist layer 60. Figure 1 shows the circuit board structure.
基於上述設計,表面電鍍層的頂面及至少一側面均可與焊錫接觸,焊錫性佳,表面電鍍層的側面未被遮蔽的特性使得本發明的線路板結構仍可相容於打線技術(wire bonding),而填設於間隙內的填縫層則可以避免以往NSMD易因間隙過小造成短路的問題,導線的密度可望提高。Based on the above design, the top surface and at least one side of the surface plating layer can be in contact with the solder, the solderability is good, and the side surface of the surface plating layer is unshielded, so that the circuit board structure of the present invention can still be compatible with the wire bonding technology (wire Bonding), and the filling layer filled in the gap can avoid the problem that the NSMD is easy to short-circuit due to the small gap, and the density of the wire is expected to increase.
另外,請參考第10圖及第11圖,其中第10圖揭示本發明另一實施例,第11圖則為利用NSMD技術所製成的習用線路板結構,比較後可以發現,在相同線路間距下,習用NSMD技術非常容易導致相鄰的鎳、金層1等表面電鍍層過於靠近,顯著提高短路的風險,造成不良率增加;相較之下,本發明先以填縫層40填補線路間隙後,再進行表面電鍍,可以避免短路風險。換句話說,相較於NSMD技術,本發明更適用於高線路密度的電路板結構設計,因而更能符合電子產品輕薄短小的設計需求及趨勢。In addition, please refer to FIG. 10 and FIG. 11 , wherein FIG. 10 discloses another embodiment of the present invention, and FIG. 11 is a conventional circuit board structure made by using NSMD technology. After comparison, it can be found that the same line spacing is obtained. Under the NSMD technology, it is very easy to cause the adjacent nickel, gold layer 1 and other surface plating layers to be too close, which significantly increases the risk of short circuit, resulting in an increase in the defect rate. In contrast, the present invention fills the line gap with the filling layer 40 first. After the surface plating, the risk of short circuit can be avoided. In other words, compared with the NSMD technology, the invention is more suitable for the circuit board structure design with high line density, and thus is more suitable for the design requirements and trends of the light and thin electronic products.
1‧‧‧鎳、金層 1‧‧‧ Nickel and gold layers
2‧‧‧銅箔 2‧‧‧ copper foil
3‧‧‧防焊層 3‧‧‧ solder mask
5A‧‧‧薄銅箔 5A‧‧‧thin copper foil
5B‧‧‧面銅 5B‧‧‧ face copper
5C‧‧‧孔銅 5C‧‧‧ hole copper
6A‧‧‧防焊材料 6A‧‧‧solderproof material
7A‧‧‧刷磨輪 7A‧‧‧Brush wheel
10‧‧‧基板 10‧‧‧Substrate
11‧‧‧貫通孔 11‧‧‧through holes
20‧‧‧導電跡線 20‧‧‧ conductive traces
30‧‧‧焊線手指 30‧‧‧welding line fingers
40‧‧‧填縫層 40‧‧‧Seam layer
50‧‧‧表面電鍍層 50‧‧‧Surface plating
51‧‧‧頂面 51‧‧‧ top surface
52‧‧‧側面 52‧‧‧ side
60‧‧‧防焊層 60‧‧‧ solder mask
第1圖為本發明線路板結構其中一實施例的剖面圖。BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing an embodiment of a circuit board structure of the present invention.
第2至9圖為本發明線路板結構其中一實施例的製造過程的剖面圖。2 to 9 are cross-sectional views showing a manufacturing process of one embodiment of the wiring board structure of the present invention.
第10圖為本發明線路板結構另一實施例的剖面圖。Figure 10 is a cross-sectional view showing another embodiment of the circuit board structure of the present invention.
第11圖為以往採用NSMD加工的線路板結構的剖面圖。Figure 11 is a cross-sectional view showing a conventional circuit board structure processed by NSMD.
第12圖為以往採用SMD加工的線路板結構的剖面圖。Fig. 12 is a cross-sectional view showing the structure of a circuit board which has been conventionally processed by SMD.
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