TWI651817B - 電源管理優化熱感知三維晶片封裝 - Google Patents

電源管理優化熱感知三維晶片封裝 Download PDF

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TWI651817B
TWI651817B TW106104339A TW106104339A TWI651817B TW I651817 B TWI651817 B TW I651817B TW 106104339 A TW106104339 A TW 106104339A TW 106104339 A TW106104339 A TW 106104339A TW I651817 B TWI651817 B TW I651817B
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integrated circuit
memory
heat sink
semiconductor package
power region
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TW106104339A
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TW201733045A (zh
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馬杜 克里斯南 艾揚格
泰奎 姜
克里斯多福 格雷戈里 馬隆
諾曼 保羅 約皮
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美商谷歌有限責任公司
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Abstract

一種半導體封裝(100)包含：一基板(110)、一積體電路(120)、一記憶體支撐件(140)、堆疊式記憶體(130)及一罩(150)。該積體電路具有一低功率區(124)及一高功率區(122)。該記憶體支撐件安置於該積體電路之該低功率區上，且經組態以允許穿過其中之一流體流(250)將熱量傳導遠離該積體電路之該低功率區。該罩界定一第一埠(152、152a)、一第二埠(152、152b)及流體連接該第一埠與該第二埠之一罩容積。該罩容積(160)經組態以裝納該積體電路、該記憶體支撐件及該堆疊式記憶體，同時引導該流體流在該積體電路、該記憶體支撐件及該堆疊式記憶體上流動。

Description

電源管理優化熱感知三維晶片封裝
本發明係關於電源管理優化熱感知三維(3D)晶片封裝。
基於互補金屬氧化物半導體(CMOS)之微處理器係用於技術基礎設施之核心技術中之一種。效能縮放之趨勢展示，隨著CMOS微處理器計算能力隨時間增加，電力需求亦增加，從而導致較多熱量產生。除工業標準晶片封裝或基於CMOS之微處理器以外，對特殊用途矽(例如，圖形處理單元(GPU)及定製之特殊應用積體電路(ASIC))之探索亦增加，從而導致較高熱量產生。隨著晶片效能增加，高頻寬記憶體之效能亦需要增加，從而導致額外熱量產生。可需要大電腦資源及處於高密度(諸多伺服器緊密接近)之眾多晶片封裝的服務(諸如成像及人工智慧)進一步增加電力問題。
本發明之一項態樣提供一種半導體封裝。該半導體封裝包含：一基板；一積體電路，其安置於該基板上；一記憶體支撐件，其安置於該積體電路之低功率區上；堆疊式記憶體，其安置於該記憶體支撐件上且與該積體電路通信；及一罩，其連接至該基板。該罩界定一第一埠、一第二埠及流體連接該第一埠與該第二埠之一罩容積。該積體電路具有一低功率區及一高功率區。該記憶體支撐件經組態以允許穿過其中之一流體流將熱量傳導遠離該積體電路之該低功率區。該罩容積經組態以裝納該積體電路、該記憶體支撐件及該堆疊式記憶體，同時引導該流體流在該積體電路、該記憶體支撐件及該堆疊式記憶體上流動。 本發明之實施方案可包含以下選用特徵中之一或多者。在某些實施方案中，該半導體封裝包含安置於該積體電路之該高功率區上之一散熱片。該罩容積可經組態以裝納該散熱片，同時引導該流體流在該散熱片上流動。在此實例中，該散熱片具有複數個鰭狀物。該半導體封裝亦可包含安置於該積體電路之該高功率區上之一導熱材料。該罩容積經組態以裝納該導熱材料，同時引導該流體流在該導熱材料上流動。該導熱材料可包含金剛石及/或銅與碳奈米管或銦之一複合物。 在某些實例中，該半導體封裝包含安置於一導熱材料上之一散熱片。該導熱材料可安置於該積體電路之該高功率區上，且該罩容積經組態以裝納該散熱片，同時引導該流體流在該散熱片上流動。在此實例中，該散熱片具有複數個鰭狀物。該低功率區與該高功率區可不重疊。該記憶體支撐件可包含一多孔材料。該多孔材料可具有規則間隔開之孔。該半導體封裝可進一步包含安置於該積體電路上之一中介層。該記憶體支撐件可經組態以電連接該記憶體與該積體電路。 本發明之另一態樣提供一種用於操作一半導體封裝之方法。該方法包含接收一流體流及將該流體流引導於包含堆疊式記憶體及一積體電路之一半導體封裝之表面上。該積體電路具有一低功率區及一高功率區。該堆疊式記憶體由該積體電路之該低功率區上之一記憶體支撐件支撐。該記憶體支撐件引導該流體流將熱量傳導遠離該積體電路之該低功率區及該高功率區。 此態樣可包含以下選用特徵中之一或多者。該方法可包含利用一罩來引導該流體流，該罩界定一第一埠、一第二埠及流體連接該第一埠與該第二埠之一罩容積。該罩容積可經組態以裝納該積體電路、該記憶體支撐件及該堆疊式記憶體，同時引導該流體流在該積體電路、該記憶體支撐件及該堆疊式記憶體上流動。該方法可進一步包含安置於該積體電路之該高功率區上之一散熱片。該罩容積經組態以裝納該散熱片，同時引導該流體流在該散熱片上流動。在此實例中，該散熱片具有複數個鰭狀物。該方法可進一步包含安置於該積體電路之該高功率區上之一導熱材料。該罩容積經組態以裝納該導熱材料，同時將該流體流引導於該導熱材料上。該導熱材料可包含金剛石及/或銅與碳奈米管或銦之一複合物。 在某些實例中，該方法包含安置於一導熱材料上之一散熱片，該導熱材料安置於該積體電路之該高功率區上。該罩容積經組態以裝納該散熱片，同時引導該流體流在該散熱片上流動。在此實例中，該散熱片具有複數個鰭狀物。該較低功率區與該高功率區可不重疊。該記憶體支撐件可包含一多孔材料，且該多孔材料可具有規則間隔開之孔。該方法可進一步包含安置於該積體電路上之一中介層。該記憶體支撐件可經組態以電連接該記憶體與該積體電路。 在附圖及以下說明中陳述本發明之一或多項實施方案之細節。依據說明及圖式且依據申請專利範圍將明瞭其他態樣、特徵及優點。
圖1展示一半導體封裝100。該半導體封裝包含一基板110。基板110可係一非導電材料或半導電材料以允許安裝、佈線及通過連接。在某些實施方案中，基板110充當一安裝表面及熱分佈表面。常見基板110材料包含但不限於玻璃纖維、FR4、聚醯亞胺、矽、二氧化矽、氧化鋁、藍寶石、鍺、砷化鎵(GaAs)、一種矽鍺合金或磷化銦(InP)。一中介層112安裝於基板110上。一積體電路120及高頻寬記憶體(HBM) 130安裝於中介層112上。一中介層112在一或多個HBM 130與一積體電路120之間提供電連接。中介層112亦在多個連接點之間提供電介面佈線。在某些實施方案中，中介層112將連接擴展至一較寬間距或佈線連接。一中介層112亦可用於在一半導體封裝外側與用於電通信及資料通信之一終端接腳之間提供一電路徑。HBM 130可以一可存取形式儲存資訊或數位資料。HBM 130可係一暫時類型(諸如隨機存取記憶體)或一較長時間儲存類型(諸如長期記憶體或可抹除可程式化唯讀記憶體(EPROM))。HBM 130可包含用於讀取及寫入存取之較寬通信道及較快時脈速度。積體電路120可係位於一個半導體材料(通常為矽)小板上之一組電子電路。積體電路120可係一一般處理單元、一特定類型處理單元(諸如一圖形處理單元)、工業標準電路及/或一特殊應用積體電路。一特殊應用積體電路可係針對一特定用途定製而非意欲用於一般用途之一積體電路(IC)。為執行一給定功能或計算，積體電路120可需要與HBM 130通信以儲存暫時資料或稍後待使用之資料。HBM 130離積體電路120愈遠，積體電路120與HBM 130之間的通信時間可愈長。積體電路120可必須與HBM 130進行多重通信以便存取資料。舉例而言，積體電路120可請求HBM 130中所含有之一資料段，HBM 130可以資料來回覆積體電路120，積體電路120可以一核對和來回覆HBM 130，且HBM 130可在核對和正確時以認可來回覆積體電路120。每當存在一通信時，資料或電力行進HBM 130與積體電路120之間的距離所花費之時間會增加延遲且減緩積體電路120及HBM 130兩者之最大操作速度。將HBM 130更接近積體電路120放置會減少資料行進至HBM 130或積體電路120所需之時間。 圖2A展示安裝至一基板110之具有若干功率區之一積體電路120之一俯視示意圖。在一積體電路120操作或執行計算時，可產生熱量。在積體電路120上放置之半導體之數目及類型可判定所產生熱量。彼此緊密接近放置之高功率半導體或邏輯半導體比稀疏放置之功率半導體或邏輯半導體產生更多熱量。積體電路120包含一高功率區122及一低功率區124。高功率區122可係積體電路120上具有較多熱量之一區域，且低功率區124可係積體電路120上具有較低熱量(相對於高功率區122而言)之一區域。可經由模擬或實際實驗來判定低功率區124及高功率區122。 圖2B展示堆疊於積體電路120上之一或多個HBM 130之一俯視示意圖。藉由將HBM 130放置於積體電路120上，連接長度可比HBM 130緊挨著積體電路120放置時短。HBM 130可係彼此上下堆疊之多個HBM 130。HBM 130放置於積體電路120之低功率區124之頂部上，以防止積聚過多熱量、允許冷卻之一均勻分佈、縮短通信時間及縮短電連接。 圖3A展示基板110、積體電路120、HBM 130及一罩150之一側視示意圖。中介層112連接至基板110之頂部111。積體電路120連接至中介層112且在基板110與中介層112之間提供電連接。一HBM支撐件140在低功率區124上連接至積體電路120。HBM 130連接至HBM支撐件140。HBM支撐件140在積體電路120與HBM 130之間提供電連接，從而允許通信、電力及資料通過HBM支撐件140。HBM支撐件140可係包含HBM支撐件孔142之一多孔材料。HBM支撐件孔142係允許冷卻流體通過HBM支撐件140且增加額外冷卻之材料空隙。HBM支撐件孔142可具有足以允許冷卻流體250通過HBM支撐件孔142之任何形狀。HBM支撐件孔142可具有一規則或不規則形狀，只要在HBM 130與積體電路120之間可進行充分連接且冷卻流體250可流動穿過HBM支撐件140即可。在某些實例中，HBM支撐件140係金剛石、矽及/或銅。HBM支撐件140亦可係一複合金剛石、矽及/或具有碳奈米管及/或銦之複合銅。 一散熱片170連接至積體電路120之高功率區122。散熱片170可包含一底座174以增加自積體電路120吸收之熱量。散熱片170亦可包含一或多個鰭狀物172以增加散熱片之表面積及/或增加散熱片170之熱散逸能力。鰭狀物172可係適於將熱量傳導遠離底座174或積體電路120之任何形狀，包含但不限於圓形、針形、平板形及/或錐形等。散熱片170可由用於傳導熱量之任何適合材料製造，該等材料包含但不限於鋁、含銅物及/或合金等。一導熱材料176可放置於散熱片170與積體電路120之間以促進熱傳遞。在某些實例中，導熱材料176係金剛石及/或銅。導熱材料176亦可係一複合金剛石及/或具有碳奈米管及/或銦之複合銅。 罩150連接至基板110且界定一罩容積160，罩容積160裝納中介層112、積體電路120、HBM支撐件140、HBM 130、散熱片170、鰭狀物172、底座174及導熱材料176。罩150界定包含一第一埠152a及一第二埠152b之一或多個埠152。埠152可係複數個埠152，且不存在對可使用之埠152之數目之限制。 圖3B展示包含一半導體封裝100及一熱交換系統200之一示意圖。熱交換系統200包含連接至一輻射體220及罩150之埠中之一者152、152b之一幫浦210。輻射體220連接至埠中之一者152、152a及幫浦210。輻射體220可係能夠交換熱量之任何裝置，包含但不限於管、帕耳貼(peltier)冷卻件、鰭系統及/或熱塊等。在某些實施方案中，輻射體220包含一風扇240以增加輻射體220至環境之熱散逸。在額外實施方案中，熱交換系統200視需要包含一貯存器230以儲存流體250。貯存器230亦可用於自熱交換系統200散逸熱量。作為一實例，幫浦210自第二埠152b汲取熱流體250且將熱流體250引導至輻射體220。輻射體220冷卻流體250且幫浦210將流體250引導至第一埠152a。經冷卻流體進入第一埠152a且流動穿過罩容積160，從而自積體電路120、散熱片170、HBM 130及HBM支撐件140吸收熱量。含有所吸收熱量之流體250流出第二埠152b且返回至幫浦210，從而完成熱交換系統200。 可藉由模擬或實驗而判定半導體封裝100之總功率容量。判定總功率容量之一種方法可係將HBM 130之Qm HBM功率、積體電路120之高功率區122之Qhigh功率及積體電路120之低功率區122之Qlow功率設定為一低基線值。該方法亦包含：使罩150上之冷卻保持固定以判定或記錄HBM 130、高功率區122及低功率區124之最大接面溫度，及比較所記錄接面值與積體電路120及HBM 130之規格。接下來，調整罩150之冷卻並判定或記錄HBM 130、高功率區122及低功率區124之最大接面溫度。該方法亦包含比較所記錄接面值與積體電路120及HBM 130之規格及先前測試。該方法進一步包含調整高功率區122及低功率區124之位置及大小，且同時使罩150上之冷卻保持固定並判定或記錄HBM 130、高功率區122及低功率區124之最大接面溫度。該方法進一步包含比較所記錄接面值與積體電路120及HBM 130之規格及先前測試，並繼續進行調整直至接面溫度最小化或已達成最大冷卻為止。 圖4係可用於實施此文件中所闡述之裝置及方法之一實例性計算裝置400之一示意圖。計算裝置400意欲表示各種形式之數位電腦，諸如膝上型電腦、桌上型電腦、工作站、個人數位助理、伺服器、刀鋒伺服器、大型電腦及其他適當電腦。此處所展示之組件、組件之連接及關係以及組件之功能僅意欲為例示性的，且並非意欲限制此文件中所闡述及/或所主張之本發明之實施方案。 計算裝置400包含：一半導體封裝100 (或處理器)；記憶體420；一儲存裝置430；一高速介面/控制器440，其連接至記憶體420及高速擴充埠450；及一低速介面/控制器460，其連接至低速匯流排470及儲存裝置430。組件100、420、430、440、450及460中之每一者使用各種匯流排互連，且可安裝於一共同主機板上或視情況以其他方式安裝。半導體封裝100 (或處理器)可處理供在計算裝置400內執行之指令，該等指令包含儲存於記憶體420中或儲存裝置430上以在一外部輸入/輸出裝置(諸如耦合至高速介面440之顯示器480)上顯示用於一圖形使用者介面(GUI)之圖形資訊之指令。在其他實施方案中，可視情況將多個處理器及/或多個匯流排連同多個記憶體及若干類型之記憶體一起使用。此外，可連接多個計算裝置400，其中每一裝置提供必要操作之若干部分(例如，作為一伺服器組、一刀鋒伺服器群組或一多處理器系統)。 記憶體420將資訊非暫時性地儲存於計算裝置400內。記憶體420可係一電腦可讀媒體、一(或若干)揮發性記憶體單元或(若干)非揮發性記憶體單元。非暫時性記憶體420可係用於在一暫時或永久基礎上儲存程式(例如，指令序列)或資料(例如，程式狀態資訊)以供計算裝置400使用之實體裝置。非揮發性記憶體之實例包含但不限於快閃記憶體及唯讀記憶體(ROM)/可程式化唯讀記憶體(PROM)/可抹除可程式化唯讀記憶體(EPROM)/電可抹除可程式化唯讀記憶體(EEPROM) (例如，通常用於韌體，諸如開機程式)。揮發性記憶體之實例包含但不限於隨機存取記憶體(RAM)、動態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(SRAM)、相變記憶體(PCM)以及磁碟或磁帶。 儲存裝置430能夠為計算裝置400提供大容量儲存。在某些實施方案中，儲存裝置430係一電腦可讀媒體。在各種不同實施方案中，儲存裝置430可係一軟碟裝置、一硬碟裝置、一光碟裝置、或一磁帶裝置、一快閃記憶體或其他類似固態記憶體裝置、或包含一儲存區域網路或其他組態中之若干裝置之一裝置陣列。在額外實施方案中，一電腦程式產品有形地體現於一資訊載體中。該電腦程式產品含有在執行時執行一或多種方法(諸如上文所闡述之方法)之指令。該資訊載體係一電腦可讀媒體或機器可讀媒體，諸如記憶體420、儲存裝置430或半導體封裝100 (或處理器)上之記憶體。 高速控制器440管理計算裝置400之頻寬密集型操作，而低速控制器460管理較低頻寬密集型操作。此職責分配僅係例示性的。在某些實施方案中，高速控制器440耦合至記憶體420、顯示器480 (例如，經由一圖形處理器或加速器)，且耦合至可接納各種擴充卡(未展示)之高速擴充埠450。在某些實施方案中，低速控制器460耦合至儲存裝置430及低速擴充埠470。可包含各種通信埠(例如，USB、藍芽、乙太網、無線以太網)之低速擴充埠470可(例如)經由一網路配接器耦合至一或多個輸入/輸出裝置，諸如一鍵盤、一指向裝置、一掃描器或一網路連線裝置(諸如一交換器或路由器)。 如圖中所展示，可以若干不同形式來實施計算裝置400。舉例而言，計算裝置400可實施為一標準伺服器400a或多次實施於此等伺服器400a之一群組中、實施為一膝上型電腦400b、或實施為一機架伺服器系統400c。 圖5展示用於操作一半導體封裝100之一方法500。在方塊502處，方法500包含接收一流體流250。流體250可係適於吸收及傳導熱量之任何流體250。流體250可經由罩150中之一埠152、152a進入至罩容積160。在方塊504處，方法500包含將流體流250引導於堆疊式記憶體或高頻寬記憶體130及一積體電路120之表面上。積體電路120具有一低功率區124及一高功率區122。堆疊式記憶體或HBM 130由積體電路120之低功率區124上之一記憶體支撐件140支撐。記憶體支撐件140引導流體流250將熱量傳導遠離積體電路120之高功率區122及低功率區124。流體250可由罩150引導至罩容積160中於中介層112、積體電路120、HBM 130、HBM支撐件140及散熱片170上。流體250吸收自中介層112、積體電路120、HBM 130、HBM支撐件140及散熱片170產生之熱量。流體可經引導以由熱交換系統200驅逐。 方法500可包含利用一罩150來引導流體流250，罩150界定一第一埠152a、一第二埠152b及流體連接第一埠152a與第二埠152b之一罩容積160。罩容積160可經組態以裝納積體電路120、記憶體支撐件140及堆疊式記憶體130，同時引導流體流250在積體電路120、記憶體支撐件140及堆疊式記憶體130上流動。方法500可進一步包含安置於積體電路120之高功率區122上之一散熱片170。罩容積160經組態以裝納散熱片170，同時引導流體流250在散熱片170上流動。在此實例中，散熱片170可具有複數個鰭狀物172。方法500可進一步包含安置於積體電路120之高功率區122上之一導熱材料176。罩容積160經組態以裝納導熱材料176，同時將流體流250引導於導熱材料176上。導熱材料176可包含金剛石及/或銅與碳奈米管或銦之一複合物。 在某些實例中，方法500包含安置於一導熱材料176上之一散熱片170，導熱材料176安置於積體電路120之高功率區122上。罩容積160經組態以裝納散熱片170，同時引導流體流250在散熱片170上流動。此外，散熱片170可具有複數個鰭狀物172。較低功率區124與高功率區122可不重疊。記憶體支撐件140可包含一多孔材料，且該多孔材料可具有規則間隔開之孔142。方法500可進一步包含安置於積體電路120上之一中介層112。記憶體支撐件140可經組態以電連接記憶體130與積體電路120。 儘管本說明書含有諸多具體細節，但不應將此等具體細節視為對本發明或可主張之範疇之限制，而應將其視為本發明之特定實施方案所特有之特徵之說明。亦可將本說明書中在單獨實施方案之內容脈絡中闡述之某些特徵以組合形式實施於一單項實施方案中。相反地，在一單項實施方案之內容脈絡中闡述之各種特徵亦可單獨地或以任何適合子組合形式實施於多項實施方案中。此外，雖然上文可將特徵闡述為以某些組合形式起作用且甚至最初係如此主張的，但來自一所主張組合之一或多個特徵在某些情形中可自該組合去除，且該所主張組合可針對於一子組合或一子組合之變化形式。 類似地，儘管在圖式中以一特定次序繪示操作，但不應將此理解為需要以所展示特定次序或以順序次序執行此等操作或執行所有所圖解說明操作以達成合意之結果。在某些情況下，多任務及並行處理可係有利的。此外，不應將在上文所闡述實施例中之各種系統組件之分離理解為在所有實施例中需要此分離，且應理解，通常可將所闡述程式組件及系統一起整合於一單個軟體產品中或封裝至多個軟體產品中。 已闡述若干實施方案。然而，將理解，可在不背離本發明之精神及範疇之情況下做出各種修改。因此，其他實施方案亦在隨附申請專利範圍之範疇內。舉例而言，申請專利範圍中所陳述之動作可以一不同次序執行且仍達成合意結果。
100‧‧‧半導體封裝/組件
110‧‧‧基板
111‧‧‧頂部
112‧‧‧中介層
120‧‧‧積體電路
122‧‧‧高功率區
124‧‧‧低功率區/較低功率區
130‧‧‧堆疊式記憶體/高頻寬記憶體/記憶體
140‧‧‧記憶體支撐件/高頻寬記憶體支撐件
142‧‧‧高頻寬記憶體支撐件孔/規則間隔開之孔
150‧‧‧罩
152‧‧‧埠/第一埠/第二埠
152a‧‧‧埠/第一埠
152b‧‧‧埠/第二埠
160‧‧‧罩容積
170‧‧‧散熱片
172‧‧‧鰭狀物
174‧‧‧底座
176‧‧‧導熱材料
200‧‧‧熱交換系統
210‧‧‧幫浦
220‧‧‧輻射體
230‧‧‧貯存器
240‧‧‧風扇
250‧‧‧流體/熱流體/流體流/冷卻流體
400‧‧‧實例性計算裝置/計算裝置
400a‧‧‧標準伺服器/伺服器
400b‧‧‧膝上型電腦
400c‧‧‧機架伺服器系統
420‧‧‧記憶體/組件/非暫時性記憶體
430‧‧‧儲存裝置/組件
440‧‧‧高速介面/高速控制器/組件
450‧‧‧高速擴充埠/組件
460‧‧‧低速控制器/低速介面/組件
470‧‧‧低速匯流排/低速擴充埠
480‧‧‧顯示器
圖1係一實例性半導體封裝之一示意圖。 圖2A係安裝至一基板之具有若干功率區之一實例性積體電路之一俯視示意圖。 圖2B係堆疊於一積體電路上之一或多個高頻寬記憶體(HBM)組件之一俯視示意圖。 圖3A係一基板、一積體電路、一HBM及一罩之一例示性配置之一側視示意圖。 圖3B展示一實例性半導體封裝及一熱交換系統之一示意圖。 圖4係一實例性計算裝置之一示意圖。 圖5展示用於操作一半導體封裝之一方法。 在各圖式中，相同參考編號指示相同元件。

Claims (21)

  1. 一種半導體封裝(100)，其包括：一基板(110)；一積體電路(120)，其安置於該基板(110)上，該積體電路(120)具有一低功率區(124)及一高功率區(122)；一記憶體支撐件(140)，其安置於該積體電路(120)之該低功率區(124)上，該記憶體支撐件(140)經組態以允許穿過其中之一流體流(250)將熱量傳導遠離該積體電路(120)之該低功率區(124)；堆疊式記憶體(130)，其安置於該記憶體支撐件(140)上且與該積體電路(120)通信；及一罩(150)，其連接至該基板(110)且界定一第一埠(152、152a)、一第二埠(152、152b)及流體連接該第一埠(152、152a)與該第二埠(152、152b)之一罩容積(160)，該罩容積(160)經組態以裝納該積體電路(120)、該記憶體支撐件(140)及該堆疊式記憶體(130)，同時引導該流體流(250)在該積體電路(120)、該記憶體支撐件(140)及該堆疊式記憶體(130)上流動。
  2. 如請求項1之半導體封裝(100)，其進一步包括安置於該積體電路(120)之該高功率區(122)上之一散熱片(170)，該罩容積(160)經組態以裝納該散熱片(170)，同時引導該流體流(250)在該散熱片(170)上流動，該散熱片(170)具有複數個鰭狀物(172)。
  3. 如請求項1之半導體封裝(100)，其進一步包括安置於該積體電路(120)之該高功率區(122)上之一導熱材料(176)，該罩容積(160)經組態以裝納該導熱材料(176)，同時引導該流體流(250)在該導熱材料(176)上流動。
  4. 如請求項3之半導體封裝(100)，其中該導熱材料(176)包括金剛石及/或銅與以下材料之一複合物：碳奈米管；或銦。
  5. 如請求項1之半導體封裝(100)，其進一步包括安置於一導熱材料(176)上之一散熱片(170)，該導熱材料(176)安置於該積體電路(120)之該高功率區(122)上，該罩容積(160)經組態以裝納該散熱片(170)，同時引導該流體流(250)在該散熱片(170)上流動，該散熱片(170)具有複數個鰭狀物(172)。
  6. 如請求項1之半導體封裝(100)，其中該低功率區(124)與該高功率區(122)不重疊。
  7. 如請求項1之半導體封裝(100)，其中該記憶體支撐件(140)包括一多孔材料。
  8. 如請求項7之半導體封裝(100)，其中該多孔材料界定規則間隔開之孔(142)。
  9. 如請求項1之半導體封裝(100)，其進一步包括安置於該積體電路(120)上之一中介層(112)。
  10. 如請求項1之半導體封裝(100)，其中該記憶體支撐件(140)經組態以電連接該記憶體(130)與該積體電路(120)。
  11. 一種方法(500)，其包括：接收一流體流(flow of fluid，250)；將該流體流(250)引導於包括堆疊式記憶體(130)及一積體電路(120)之一半導體封裝(100)之表面上，其中該積體電路(120)具有一低功率區(124)及一高功率區(122)，該堆疊式記憶體(130)由該積體電路(120)之該低功率區(124)上之一記憶體支撐件(140)支撐，該記憶體支撐件(140)引導該流體流(250)將熱量傳導遠離該積體電路(120)之該低功率區(124)及該高功率區(122)；及引導該流體流(250)在該積體電路(120)、該記憶體支撐件(140)及該堆疊式記憶體(130)上流動。
  12. 如請求項11之方法(500)，其進一步包括利用一罩(150)來引導該流體流(250)，該罩(150)界定一第一埠(152、152a)、一第二埠(152、152b)及流體連接該第一埠(152、152a)與該第二埠(152、152b)之一罩容積(160)，該罩容積(160)經組態以裝納該積體電路(120)、該記憶體支撐件(140)及該堆疊式記憶體(130)。
  13. 如請求項12之方法(500)，其中該半導體封裝(100)進一步包括安置於該積體電路(120)之該高功率區(122)上之一散熱片(170)，該罩容積(160)經組態以裝納該散熱片(170)，同時引導該流體流(250)在該散熱片(170)上流動，該散熱片(170)具有複數個鰭狀物(172)。
  14. 如請求項12之方法(500)，其中該半導體封裝(100)進一步包括安置於該積體電路(120)之該高功率區(122)上之一導熱材料(176)，該罩容積(160)經組態以裝納該導熱材料(176)，同時引導該流體流(250)在該導熱材料(176)上流動。
  15. 如請求項14之方法(500)，其中該導熱材料(176)包括金剛石及/或銅與以下材料之一複合物：碳奈米管；或銦。
  16. 如請求項12之方法(500)，其中該半導體封裝(100)進一步包括安置於一導熱材料(176)上之一散熱片(170)，該導熱材料(176)安置於該積體電路(120)之該高功率區(122)上，該罩容積(160)經組態以裝納該散熱片(170)，同時引導該流體流(250)在該散熱片(170)上流動，該散熱片(170)具有複數個鰭狀物(172)。
  17. 如請求項11之方法(500)，其中該低功率區(124)與該高功率區(122)不重疊。
  18. 如請求項11之方法(500)，其中該記憶體支撐件(140)包括一多孔材料。
  19. 如請求項18之方法(500)，其中該多孔材料界定規則間隔開之孔(142)。
  20. 如請求項11之方法(500)，其中該半導體封裝(100)進一步包括安置於該積體電路(120)上之一中介層(112)。
  21. 如請求項11之方法(500)，其中該記憶體支撐件(140)經組態以電連接該記憶體(130)與該積體電路(120)。
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