TWI646631B - 在溝槽形成期間運用犧牲阻障層保護貫孔之方法 - Google Patents

在溝槽形成期間運用犧牲阻障層保護貫孔之方法 Download PDF

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TWI646631B
TWI646631B TW106101387A TW106101387A TWI646631B TW I646631 B TWI646631 B TW I646631B TW 106101387 A TW106101387 A TW 106101387A TW 106101387 A TW106101387 A TW 106101387A TW I646631 B TWI646631 B TW I646631B
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barrier layer
sacrificial barrier
layer
trench
holes
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TW201807777A (zh
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夏瑞克 斯蒂奎
法蘭克Ｗ 蒙特
張洵淵
布朗 匹撒拉
道格拉斯Ｍ 崔克特
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格羅方德半導體公司
萬國商業機器公司
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Abstract

一種方法，舉例而言，包括提供中間半導體結構，其包含金屬層、布置於該金屬層上方之可圖型化層、及布置於該可圖型化層上方之硬遮罩，該中間半導體結構包含穿過該硬遮罩延展到該金屬層上之複數個貫孔，在該中間半導體結構上方及該複數個貫孔中沉積犧牲阻障層，移除介於該複數個貫孔間的一部分該犧牲阻障層，同時在該複數個貫孔中維持一部分該犧牲阻障層，在介於該犧牲阻障層之該遭受移除部分與該複數個貫孔間的該可圖型化層中形成溝槽，以及將該犧牲阻障層之該剩餘部分從該複數個貫孔移除。

Description

在溝槽形成期間運用犧牲阻障層保護貫孔之方法
本發明大體上係關於用於製作半導體裝置之方法，並且尤係關於在溝槽形成期間運用犧牲阻障層保護貫孔之方法。
在現代的半導體裝置製作中，在所謂的「前段製程(FEOL)」建立出例如電晶體之裝置後，在所謂的「後段製程(BEOL)」施作連至此等裝置之電連接，亦稱為「金屬化」。金屬化製程包含以導電材料(典型為金屬)填充各種貫孔。然而，在貫孔建立及金屬填充的各種時點，會不經意地引進某些缺陷，影響到使用金屬填充貫孔之連接的終端使用可靠度。
在一項具體實施例中，透過提供一種方法，得以克服先前技術的缺點，並且提供附加優點，該方法舉例而言，包括提供中間半導體結構，其具有金屬層、布置於該金屬層上方之可圖型化層、及布置於該可圖型化 層上方之硬遮罩，該中間半導體結構包括穿過該硬遮罩延展到該金屬層上之複數個貫孔，在該中間半導體結構上方及該複數個貫孔中沉積犧牲阻障層，移除介於該複數個貫孔間的一部分該犧牲阻障層，同時在該複數個貫孔中維持一部分該犧牲阻障層，在介於該犧牲阻障層之該遭受移除部分與該複數個貫孔間的該可圖型化層中形成溝槽，以及將該犧牲阻障層之該剩餘部分從該複數個貫孔移除。
在另一具體實施例中，提供一種方法，其舉例而言，包括提供中間半導體結構，其具有金屬層、布置於該金屬層上方之可圖型化層、及布置於該可圖型化層上方之硬遮罩，該中間半導體結構包括穿過該硬遮罩延展到該金屬層上之複數個貫孔，在該中間半導體結構上方及該複數個貫孔中沉積犧牲阻障層以在該貫孔中界定複數個凹穴，在該犧牲阻障層上方、及該複數個貫孔中該犧牲阻障層所界定之複數個凹穴中沉積填充材料，對一部分該填充材料及該犧牲阻障層介於該複數個貫孔間的一部分進行第一移除，同時在該複數個貫孔中維持一部分該犧牲阻障層及一部分該填充材料，在介於該犧牲阻障層之該遭受移除部分與該複數個貫孔間的該可圖型化層中形成溝槽，以及將該剩餘填充材料及該犧牲阻障層之該剩餘部分從該複數個貫孔進行第二移除。
附加特徵及優點乃透過本揭露之技術來實現。本揭露之其它具體實施例及態樣乃於本文中詳述，並且視為申請專利範圍之一部分。
100‧‧‧中間半導體結構、起始半導體結構
110‧‧‧互連傳導結構
120‧‧‧介電覆蓋層
130‧‧‧可圖型化層
140‧‧‧硬遮罩層
142、144、146‧‧‧硬遮罩
200、220‧‧‧貫孔
210、310‧‧‧凹穴
300‧‧‧溝槽圖型化記憶物、溝槽記憶物
400‧‧‧襯墊、犧牲阻障層
410‧‧‧犧牲阻障層部分
500‧‧‧填充材料
510‧‧‧填充材料部分
600‧‧‧溝槽
1000、2000‧‧‧方法
1100至1500、2100至2600‧‧‧步驟
本說明書之結論部分中特別指出並且明確主張本揭露之專利標的。然後，若要對本揭露有最深刻的理解，可參照以下各項具體實施例之詳細說明及附圖，其中：第1圖根據本揭露之一具體實施例，係中間半導體結構之截面圖；第2至8圖根據本揭露之一具體實施例，係用於在製作半導體裝置之金屬化階段中形成貫孔及溝槽之方法的截面圖；第9圖根據本揭露之一具體實施例，係繪示方法之流程圖；以及第10圖根據本揭露之一具體實施例，係繪示方法之流程圖。
本揭露之態樣及某些特徵、優點、及其細節係引用附圖所示非限制性具體實施例於下文更完整闡釋。省略眾所周知之材料、製作工具、處理技術等之說明以避免非必要地混淆本揭露之詳細說明。然而，應該了解的是，詳細說明及特定實施例雖然指出本揭露之具體實施例，仍係僅舉例來提供，並且非是作為限制。本概念之精神及/或範疇內之各種取代、修改、添加及/或配置經由本揭露對所屬技術領域中具有通常知識者將顯而易見。下文引用為易於了解未依比例繪示的圖式，其中各個不同圖中 所用相同的參考元件符號表示相同或類似組件。
如經由以下說明將會領會者，本說明書提供在溝槽形成期間用來保護中間半導體結構之方法。特別的是，本揭露提供在如所謂後段製程(BEOL)金屬化之電連接中，於溝槽形成期間，用於保護中間半導體結構中之貫孔的方法，例如：避免破壞或斜切貫孔。舉例而言，本揭露可在溝槽形成及溝槽形成後之移除期間，運用非反應性犧牲阻障層保護貫孔，與溝槽形成期間貫孔中僅運用反應性填充材料相比較，用於溝槽微影與圖型化之填充材料與中間半導體基材交互作用，例如：與形成貫孔及/或諸如溝槽形成及移除期間形成貫孔底端之M1層等傳導層之可圖型化材料交互作用。
舉例來說，第1至8圖根據本發明之一具體實施例，繪示用於製作諸如溝槽開口等傳導金屬互連結構同時保護貫孔之方法。
第1圖就一或多個半導體裝置繪示中間半導體結構100之截面圖。舉例而言，所示中間半導體結構100可包括複數個貫孔200及一或多個溝槽圖型化記憶物300(第1圖中僅展示其中一者)。中間半導體結構100可包括互連傳導結構110、介電覆蓋層120、可圖型化層130、以及硬遮罩層140，其可包括含第一保護層或硬遮罩142、第二保護層或硬遮罩144、及第三保護層或硬遮罩146之堆疊。
起始半導體結構100可配合可在前段製程 (FEOL)處理期間建立之個別裝置操作，舉例來說，可在諸如矽基材之基材(未示於第1圖中)上方布置之裝置層(未示於第1圖中)內操作。舉一實施例來說，此等個別裝置舉例來說，可包括諸如FinFET等金屬氧化物半導體場效電晶體(MOSFET)、以及電容器、電阻器與其它半導體裝置。
互連傳導結構110可以是諸如銅層之M1層。介電覆蓋層120可以是氮摻雜碳化矽(NBLOK)，並且可藉由電漿增強型化學氣相沉積(PECVD)來沉積。可圖型化層130可自氣相起使用例如化學氣相沉積(CVD)或物理氣相沉積等任何合適的習知沉積程序、或其它合適的程序來沉積。可圖型化層130可包括介電層，在一項實施例中，或可由超低介電常數(例如：介電常數小於2.7)、或其它合適的材料所製作。
第一硬遮罩142可以是沉積於可圖型化層130上方之硬遮罩，並且在一項特定實施例中，可包括氮，舉例如氮化矽(SiN或SiNH)。此沉積程序可包括任何習知程序，舉例如低溫CVD或電漿增強型CVD。第二硬遮罩144可由金屬或含金屬材料所製作，舉例如包括鈦(Ti)或氮化鈦(TiN)之含金屬材料。第三硬遮罩146可以是沉積於可圖型化層130上方之硬遮罩，並且在一項特定實施例中，可包括氮，舉例如氮化矽(SiN或SiNH)。
貫孔200及溝槽記憶物300可使用微影堆疊與光阻圖型化、及蝕刻程序而以可操作的方式形成在中間半導體結構100中。另外，將會領會的是，中間半導體結 構可根據本揭露具有其它組態及/或由其它材料製作。雖然為了簡單起見，僅展示一部分，仍將了解的是，實際上，同一基材上典型為包括許多此類組件。
如第2圖所示，根據本揭露之一具體實施例，在中間半導體結構100上方布置犧牲阻障層400。舉例而言，犧牲阻障層400可沿著貫孔200及溝槽記憶物300之側壁形成。舉例而言，犧牲阻障層400可界定位在貫孔200中之凹穴210、以及位在溝槽記憶物300中之凹穴310。犧牲阻障層可與形成貫孔之結構不起反應，諸如硬遮罩、可圖型化層及傳導層。可運用諸如有機材料或無機材料等任何合適的材料。合適的原子層沉積可包括氮化鋁(AlN)、氮化鈦(TiN)、鈦(Ti)、鉭(Ta)、氮化鉭(TaN)、鈷(Co)、或釕(Ru)。凹穴可具有高深寬比，諸如介於4比1到12比1之比率。凹穴的高度可為約120奈米而寬度可為約20奈米。
如第3圖所示，填充材料500係沉積於襯墊400上方及凹穴210與310內。犧牲阻障層400保護可圖型化層130免於與填充材料500交互作用，例如：填充材料500未穿透到可圖型化層130內。犧牲阻障層400亦保護互連傳導結構110免於與填充材料500交互作用，例如：填充材料500未穿透到互連傳導結構110內。在本揭露之一些具體實施例中，不需要運用填充材料。舉例而言，犧牲阻障層所界定之凹穴中不需要用填充材料來填充。然而，運用填充材料之效益包括在處理期間對可圖型化層及互連傳導結構提供附加阻障，如下文所述。
請參閱第4圖，移除填充材料500(第3圖)之上部分以曝露犧牲阻障層400之區域，諸如形成於其中之溝槽記憶物300(第1圖)及凹穴310(第2及4圖)上方之區域，同時維持貫孔中犧牲阻障層所形成之部分凹穴210(第2圖)中的填充材料部分510。填充材料之移除可包括電漿蝕刻、濕蝕刻、或電漿蝕刻與濕蝕刻之組合。舉例而言，合適的蝕刻可包括一氧化碳(CO)、二氧化碳(CO2)、二氧化硫(SO2)、有機物用氧(O2)、以及氧化物用氟碳化合物、氟氮化合物。舉例而言，合適的電漿蝕刻氣體可包括氮(N2)、氮/氫(N2/H2)、四氟化碳(CF4)、全氟環丁烷(C4F8)、以及C5HF6。舉例而言，合適的濕蝕刻化學品可包括過氧化氫、氫氟酸、氫氧化銨、或有機溶劑。
在第5圖中，進行犧牲阻障層貫穿以移除犧牲阻障層400(第4圖)對應於用於形成溝槽之區域之部分，同時在貫孔中的凹穴內維持犧牲阻障層部分410及填充材料部分510。舉例而言，可運用合適的選擇性蝕刻，其可操作成將已曝露之犧牲阻障層蝕刻掉，但不會蝕刻填充材料。填充材料部分510保護犧牲阻障層部分410免於犧牲阻障層蝕刻貫穿。
第6圖繪示在可圖型化層130中形成溝槽600，同時在凹穴內之貫孔中維持犧牲阻障層部分410及填充材料部分510。溝槽蝕刻可包括四氟化碳(CF4)、三氟化氮(NF3)、全氟環丁烷(C4F8)、八氟環戊烯(C5F8)、六氟丁二烯(C4F6)、氟代甲烷(CH3F)、氟仿(CHF3)、及/或C5HF6， 氟碳化合物、氬(Ar)、氮(N2)、甲烷(CH4)、一氧化碳(CO)、二氧化碳(CO2)之任何組合。
在第7圖中，自貫孔中之剩餘犧牲阻障層部分410移除剩餘填充材料510(第6圖)。舉例而言，移除可包括使用一氧化碳(CO)、二氧化碳(CO2)、二氧化硫(SO2)、有機物用氧(O2)、以及氧化物用氟碳化合物、氟氮化合物。舉例而言，移除可包括使用諸如氮(N2)、及氮/氫(N2/H2)之合適電漿蝕刻氣體。
在第8圖中，移除剩餘犧牲阻障層部分410(第7圖)。舉例而言，使用濕式TiN移除，諸如SC1(過氧化氫、氫氧化銨、去離子水之混合物)、氫氟酸、或過氧化氫、四元氫氧化銨、去離子水之混合物。可移除填充物材料及犧牲阻障層而不會或限制對貫孔之破壞，諸如硬遮罩、可圖型化層、以及傳導層。之後，硬遮罩142及可圖型化層130之頂端部分可諸如藉由化學機械研磨/平坦化(CMP)來移除。舉例而言，可在裝置開發時調協剩餘犧牲阻障層部分410(第6圖)及剩餘填充材料510(第6圖)，舉例來說，剩餘犧牲阻障層部分410(第6圖)及剩餘填充材料510(第6圖)之上部分可在藉由CMP移除之後，布置於與可圖型化層130之頂端部分之高度相等或更高的高度處。
剩餘貫孔220根據本揭露之一具體實施例，可用諸如金屬之傳導材料來填充。這些貫孔舉例而言，可用鎢來填充，並且可使用一或多種習知程序及技術來完成此填充。溝槽600可根據本揭露之一具體實施例用介電 材料來填充，並且可使用一或多種習知程序及技巧來完成此填充。在其它具體實施例中，這些溝槽舉例而言，可用諸如鎢(W)、鈷(Co)、釕(Ru)、鉭(Ta)、及銅(Cu)等傳導材料來填充，並且可使用一或多種習知程序及技術來完成此填充。
第9圖根據本揭露之一具體實施例，係方法1000之流程圖。方法1000舉例而言，包括於1100提供中間半導體結構，其具有金屬層、布置於該金屬層上方之可圖型化層、及布置於該可圖型化層上方之硬遮罩，該中間半導體結構包括穿過該硬遮罩延展到該金屬層上之複數個貫孔，於1200在該中間半導體結構上方及該複數個貫孔中沉積犧牲阻障層，於1300移除介於該複數個貫孔間的一部分該犧牲阻障層，同時在該複數個貫孔中維持一部分該犧牲阻障層，於1400在介於該犧牲阻障層之該遭受移除部分與該複數個貫孔間的該可圖型化層中形成溝槽，以及於1500將該犧牲阻障層之該剩餘部分從該複數個貫孔移除。
第10圖根據本揭露之一具體實施例，係方法2000之流程圖。方法2000舉例而言，包括於2100提供中間半導體結構，其具有金屬層、布置於該金屬層上方之可圖型化層、及布置於該可圖型化層上方之硬遮罩，該中間半導體結構包括穿過該硬遮罩延展到該金屬層上之複數個貫孔，於2200在該中間半導體結構上方及該複數個貫孔中沉積犧牲阻障層以在該等貫孔中界定複數個凹穴，於2300在該犧牲阻障層上方、及該複數個貫孔中該犧牲阻障 層所界定之複數個凹穴中沉積填充材料，於2400對一部分該填充材料及該犧牲阻障層介於該複數個貫孔間的一部分進行第一移除，同時在該複數個貫孔中維持一部分該犧牲阻障層及一部分該填充材料，於2500在介於該犧牲阻障層之該遭受移除部分與該複數個貫孔間的該可圖型化層中形成溝槽，以及於2600將該剩餘填充材料及該犧牲阻障層之該剩餘部分從該複數個貫孔進行第二移除。
經由本揭露，將會領會的是，運用犧牲阻障層形成之貫孔可與形成此犧牲阻障層之結構不起反應，該結構可具有直線外形且無斜切側邊。舉例而言，本揭露可使得超低介電性可圖型化層在此可圖型化層進行溝槽開挖期間受到保護，並且使諸如鎢(W)、鈷(Co)或銅(Cu)之傳導層受到保護。本揭露可針對較佳之貫孔外形提供優點，以在閘極氧化物崩潰時，達到因時間而變的介電崩潰(TDDB)目標，或舉例來說，使MOSFET中因時間而變的閘極氧化物崩潰降到最小。舉例而言，犧牲阻障層可以是保形沉積於貫孔中及硬遮罩材料上的TiN襯墊。本程序可增大製造程序的程序窗(process window)或穩建性以移除填充材料且不因溝槽形成而破壞可圖型化層。本程序可在使用相同POR濕式化學品(與POR濕式程序流程完全整合)進行填充移除之後，運用濕式可移除襯墊或犧牲阻障層。
本文所用術語的目的僅在於說明特殊具體實施例並且意圖不在於限制本揭露。單數形之「一」(及其變形)及「該」於本文中使用時，用意在於同樣包括複數形， 除非內容另有清楚指示。將再理解術語「包含」(以及包含的任何形式，如單數的「包含」和動名詞的「包含」)、「具有」(以及具有的任何形式，如單數的「具有」和動名詞的「具有」)、「包括」(以及包括的任何形式，如單數的「包括」和動名詞的「包括」)、「含有」(以及含有的任何形式，如單數的「含有」和動名詞的「含有」)為開放式連接動詞。因此，「包含」、「具有」、「包括」或「含有」一或多個步驟或元件的方法或裝置處理那些一或多個步驟或元件，但不受限於僅處理那些一或多個步驟或元件。同樣地，「包含」、「具有」、「包括」或「含有」一或多個特徵之方法的步驟或裝置的元件處理那些一或多個特徵，但不受限於僅處理那些一或多個特徵。此外，以特定方式予以配置的裝置或結構係以至少該方式予以配置，但也可用未列示的方式予以配置。
下文申請專利範圍中所有手段或手段功能元件的相應結構、材料、動作、及均等意，若存在，係有意於包括以明確主張專利權之其它所主張專利權元件共同用於進行功能的任何結構、材料、或動作。已為了描述及說明而呈現本揭露的說明，但無意於具有徹底性或侷限於所揭示形式的揭露。許多修改及變化對於所屬技術領域中具有通常知識者將顯而易知而不脫離本揭露的範疇及精神。具體實施例經選用及說明是為了解釋本揭露一或多項態樣的原理及實際應用，並且令具有所屬技術領域中具有通常知識者憑藉適於所思的特定使用，能夠就具有各種修 改之各項具體實施例理解本揭露的一或多項態樣。

Claims (20)

  1. 一種用於製作半導體裝置的方法，該方法包含：提供中間半導體結構，其包含互連傳導結構、布置於該互連傳導結構上方之介電層及可圖型化層、及布置於該可圖型化層上方之硬遮罩，該中間半導體結構包含延展穿過該硬遮罩、該可圖型化層、該介電層且直接打開到該互連傳導結構上之複數個貫孔；在該中間半導體結構上方及該複數個貫孔中以及在該互連傳導結構上直接地沉積犧牲阻障層；對介於該複數個貫孔間的該犧牲阻障層的上部分進行第一移除，同時在該複數個貫孔中維持直接在該互連傳導結構上的該犧牲阻障層的下部分；在介於該犧牲阻障層之該遭受移除部分與該複數個貫孔間的該可圖型化層中形成溝槽，同時在該複數個貫孔中維持直接在該互連傳導結構上的該犧牲阻障層的該下部分；以及將該犧牲阻障層之該等剩餘下部分從該複數個貫孔進行第二移除以曝露在該複數個貫孔底端的該互連傳導結構。
  2. 如申請專利範圍第1項所述之方法，其中，該犧牲阻障層與形成該複數個貫孔之側邊的可圖型化層不起反應。
  3. 如申請專利範圍第1項所述之方法，其中，該犧牲阻障層與該互連傳導結構不起反應。
  4. 如申請專利範圍第1項所述之方法，其中，該犧牲阻障 層與該在該可圖型化層中形成該溝槽不起反應。
  5. 如申請專利範圍第1項所述之方法，其中，介於該複數個貫孔之其中一者與該溝槽間的間隔小於約20奈米。
  6. 如申請專利範圍第1項所述之方法，其中，該犧牲阻障層包含原子層沉積(ALD)。
  7. 如申請專利範圍第1項所述之方法，其中，該犧牲阻障層包含AlN或TiN。
  8. 如申請專利範圍第1項所述之方法，其中，該中間半導體結構包含對應於該溝槽之溝槽圖型化記憶物。
  9. 如申請專利範圍第7項所述之方法，其中，該犧牲阻障層之該移除部分包含移除對應於該溝槽圖型化記憶物之部分該犧牲阻障層。
  10. 如申請專利範圍第1項所述之方法，其中，該形成該溝槽包含蝕刻。
  11. 如申請專利範圍第1項所述之方法，還包含以傳導材料填充該可圖型化層中之該複數個貫孔。
  12. 如申請專利範圍第1項所述之方法，還包含以傳導或非傳導材料填充該可圖型化層中之該溝槽。
  13. 如申請專利範圍第1項所述之方法，其中：該沉積包含在該犧牲阻障層上方、及該複數個貫孔中由該犧牲阻障層所界定之複數個凹穴中沉積填充材料；該第一移除包含移除一部分該填充材料及該犧牲阻障層介於該複數個貫孔間的該部分，同時在該複數個 貫孔中維持一部分該犧牲阻障層及一部分該填充材料；以及該第二移除包含將該剩餘填充材料及該犧牲阻障層之該剩餘部分從該複數個貫孔移除。
  14. 如申請專利範圍第13項所述之方法，其中，該犧牲阻障層與形成該複數個貫孔之側邊的可圖型化層不起反應。
  15. 如申請專利範圍第13項所述之方法，其中，該犧牲阻障層與該互連傳導結構不起反應。
  16. 如申請專利範圍第13項所述之方法，其中，該犧牲阻障層與該在該可圖型化層中形成該溝槽不起反應。
  17. 如申請專利範圍第13項所述之方法，其中，該犧牲阻障層包含原子層沉積(ALD)。
  18. 如申請專利範圍第17項所述之方法，其中，該犧牲阻障層包含AlN或TiN。
  19. 如申請專利範圍第13項所述之方法，其中，自該貫孔至該溝槽之距離小於約20奈米。
  20. 如申請專利範圍第13項所述之方法，還包含在該複數個貫孔中填充傳導材料並以介電質或傳導材料填充該溝槽。
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US11600519B2 (en) * 2019-09-16 2023-03-07 International Business Machines Corporation Skip-via proximity interconnect

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US20140227872A1 (en) * 2013-02-14 2014-08-14 Globalfoundries Inc. Methods of forming conductive structures using a sacrificial liner layer

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