TWI642204B - 發光二極體元件 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- H—ELECTRICITY
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
- H01L33/42—Transparent materials
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
- H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
Abstract
一種發光二極體元件其包含:導電基板、透明導電層設置在導電基板上、p-型半導體層設置在透明導電層上、主動層設置在p-型半導體層上、n-型半導體層設置在主動層上且p-型半導體層與n-型半導體層之電性相反、緩衝層設置在n-型半導體層上,且緩衝層具有粗糙且凹凸不平的表面以及金屬電極設置在緩衝層之具有粗糙且凹凸不平的表面上,藉由在緩衝層之具有粗糙且凹凸不平的表面來增加光線在發光二極體元件內的反射率,並且藉由減少未摻雜之氮化鎵層(undoped GaN)之厚度,以降低發光二極體元件內部對紫外光的吸收,以增加外部的光萃取效率並提高發光二極體元件的發光效率。
Description
本發明係有關於一種發光二極體元件,更特別的是一種可降低對紫外光之吸收而提高光萃取率之發光二極體元件。
發光二極體(Light emitting diode,LED)在各種電子產品與工業上的應用日益普及,由於所需之能源成本係遠低於傳統之白熱燈或螢光燈,且單一的發光二極體之尺寸非常的輕巧,乃傳統光源所不及,因此在電子產品體積日益輕薄短小的趨勢之下,發光二極體的需求也與日俱增。
發光二極體是一種可以將電能直接轉換為光能之發光元件,由於不需經由將電能轉換成熱能的熱熾發光過程。因此也稱為冷發光元件。發光二極體除了具有高發光效率之外,也是一種微小之固態光源(solid state illuminator),可製作成一半導體晶片形式,具有一半導體p-n接面結構。在此p-n接面之兩端施加電壓以通入電流之後,隨即產生電子與電洞往此p-n接面流動,並結合而釋放出光子。
就發光二極體的亮度方面而言,一般認為現階段的發光二極體,其技術上已經具備冷陰極燈管一半左右的效率,甚至其發光效能可以與冷陰極燈管並駕齊驅,發光二極體的光效率主要與兩者有關:一是與半導體晶片本身的發光效率,另一個係將半導體晶片封裝完成之後的光取出率。關於半導體晶片發光效率的主要發展方向為:電致發光材料的研發、以及提高半導體晶片結晶性的研究,以增加半導體晶片內部的量子效率。
根據習知技術之缺點,本發明的主要目的是揭露一種發光二極體元件,於發光二極體元件中之圖案化藍寶石基板或是奈米級之圖案化藍寶石基板有利於氮化鎵層之成長,且可以降低其缺陷而提高內部量子效率(IQE)以增加磊晶品質。
本發明另一目的係揭露一種發光二極體元件,於發光二極體中之透明導電層可以增加電流分散效率以及降低正向電壓(forward voltage),以提升發光二極體元件之發光效率。
本發明的再一目的係揭露一種發光二極體元件,其係減少未摻雜之氮化鎵層(undoped GaN)之厚度,而降低發光二極體元件內部對紫外光的吸收,以增加外部的光萃取效率以提高發光二極體元件的發光效率。
根據以上所述之目的,本發明揭露一種發光二極體元件其包含:導電基板、透明導電層設置在導電基板上、p-型半導體層設置在透明導電層上、主動層設置在p-型半導體層上、n-型半導體層設置在主動層上且p-型半導體層與n-型半導體層之電性相反、緩衝層設置在n-型半導體層上,且緩衝層具有粗糙且凹凸不平的表面以及金屬電極設置在緩衝層之具有粗糙且凹凸不平的表面上,藉由在緩衝層之具有粗糙且凹凸不平的表面來增加光線在發光二極體元件內的反射率,並且藉由減少未摻雜之氮化鎵層(undoped GaN)之厚度,以降低發光二極體元件內部對紫外光的吸收,以增加外部的光萃取效率以提高發光二極體元件的發光效率。
本發明還揭露一種發光二極體元件之製作方法,其包括:提供基板,且於基板上具有凹凸不平之表面、緩衝層形成在基板上、n-型半導體層形成在緩衝層上、主動層形成在n-型半導體層上、p-型半導體層形成在主動層上、透明導電層形成在p-型半導體層上、導電基板與透明導電層結合、執行剝離步驟,根據基板上之凹凸不平之表面以使基板與緩衝層相互分離,並使得在緩衝層上形成複數個凹凸不平之表面、對緩衝層之凹凸不平之表面執行粗糙化步驟,使得緩衝層之凹凸不平之表面上同時具有粗糙表面以及在緩衝層上形成金屬電極。
10‧‧‧基板
12‧‧‧緩衝層
14‧‧‧n-型半導體層
16‧‧‧主動層
18‧‧‧p-型半導體層
20‧‧‧透明導電層
22‧‧‧導電基板
24‧‧‧金屬電極
102‧‧‧基板之凹凸不平之表面
122‧‧‧緩衝層之凹凸不平之表面
124‧‧‧緩衝層之粗糙化表面
第1圖係根據本發明所揭露之技術,發光二極體元件之截面示意圖。
第2圖係根據本發明所揭露之技術,利用剝離技術將基板與緩衝層分離,並於緩衝層上形成凹凸不平之表面之截面示意圖。
第3圖係根據本發明所揭露之技術,於緩衝層上形成金屬電極之截面示意圖。
首先,請參考第1圖。第1圖係為本發明所揭露之發光二極體元件之截面示意圖。在第1圖中,其結構由下而上依序包括基板10、緩衝層12、n-型半導體層14、主動層16、p-型半導體層18、透明導電層20以及導電基板22。
於本發明的實施例中,其基板10係為經過圖案化藍寶石基板(patterned sapphire substrate)或是奈米級之圖案化藍寶石基板(nano-patterned sapphire substrate),其目的是可以提升在基板10上磊晶成長的氮化鎵層的成長速率以及成長品質並且可以降低氮化鎵層之缺陷(defect),進一步的可以提高內部量子效率(IQE)。且基板10經圖案化之後於其表面係為凹凸不平之表面102。接著,緩衝層12係設置在基板10上,其中緩衝層12係以磊晶成長的方式形成在基板10上,且緩衝層12係為未摻雜之氮化鎵層(un-doped GaN)。於本發明中利用未摻雜之氮化鎵層12做為緩衝層的目的係在於,未摻雜之氮化鎵層12與圖案化藍寶石基板(patterned sapphire substrate)或是奈米級之圖案化藍寶石基板(nano-patterned sapphire substrate)具有良好的匹配性,對於發光二極體元件有較佳的磊晶品質。
接著,同樣參考第1圖。於緩衝層12上方係同樣利用磊晶成長方式依序形成n-型半導體層14、主動層16以及p-型半導體層18,其中n-型半導體層14及p-型半導體層18之材料均為氮化鎵,只是n-型半導體層14的電性與p-型半導體層18的電性相反。另外,主動層16係為多層量子井(multi-quantum well)。
接著請繼續參考第1圖。透明導電層20係形成於p-型半導
體層18上,其透明導電層20之材料可以是石墨烯(Graphene)、氧化鋅(ZnO)或是銦錫氧化物(ITO,indium tin oxide),其中較佳的是銦錫氧化物。於本發明中,透明導電層20可以增加電流的擴散效率,而可以降低正向電壓(forward voltage),使得其發光二極體元件的電流不會產生急促變化,可以避免發光二極體元件因電流驟降或是驟升而造成元件崩潰的問題。緊接著,係將導電基板22以結合(bonding)的方式形成在透明導電層20上,其係作為發光二極體元件之電極,其材料係由鈦(Ti)、鋁(Al)、錫(Sn)、鎳(Ni)、金(Au)、銅(Cu)、鉻(Cr)、銀(Ag)、鉑(Pt)、鎢(W)等金屬元素或其合金(群組中選出)所堆疊而成。
接著,請參考第2圖。第2圖係表示利用剝離技術(lift-off)將基板與緩衝層分離,並於緩衝層上形成凹凸不平之表面之截面示意圖。在第2圖中,係將第1圖之結構上下顛倒,並且根據先前已在基板10上所形成之圖案利用剝離技術,將基板10與緩衝層12分離,其中剝離技術係為雷射剝離技術(laser lift-off)或其他乾式及濕式蝕刻剝離技術,這使得在基板10與緩衝層12分開之後,在原先緩衝層12與基板10結合之表面,由於基板10上的圖案而造成在緩衝層的表面也形成凹凸不平的表面122。
緊接著,係對緩衝層12的凹凸不平的表面122再進行粗糙化步驟,使得緩衝層12的表面除了凹凸不平,如第2圖中參考標號122所示之外,還有粗糙化表面,如第2圖中參考標號124所示。其目的是為了增加光線在此發光二極體元件中的反射率,使得當光線由發光二極體元件射出時,其具有較佳的光萃取率,而得到較佳的發光效率。於本發明的實施例中,其粗糙化步驟係利用蝕刻技術,其特別是乾式蝕刻技術。
接著請參考第3圖。第3圖係表示在緩衝層上形成金屬電極之截面示意圖。在第3圖中,係將金屬電極24形成在緩衝層12之凹凸不平122以及粗糙化124之表面。於此實施例中,金屬電極24做為發光二極體元件之電極,其材料係由鈦(Ti)、鋁(Al)、錫(Sn)、鎳(Ni)、金(Au)、銅(Cu)、鉻(Cr)、銀(Ag)、鉑(Pt)、鎢(W)等金屬元素或其合金(群組中選出)所堆疊而成。
因此根據本發明所揭露之發光二極體元件可以藉由雷射剝離技術使得做為緩衝層12之未摻雜之氮化鎵層的厚度減少,以降低未摻雜之氮化鎵層對於紫外光的吸收程度,並且藉由緩衝層12之凹凸不平122及粗糙化124之表面可以增加光線在發光二極體元件內的反射率,以提高當光線射出發光二極體元件時,其具有高的光萃取率,而增加發光二極體元件之發光效率。
Claims (1)
- 一種具有石墨烯層的發光二極體結構之製作方法,包含:提供一基板,其中該基板具有凹凸不平之一表面,該基板係一奈米級圖案化藍寶石基板;形成一緩衝層在該奈米級圖案化藍寶石基板上,其中該緩衝層為未摻雜之氮化鎵(undoped GaN);形成一n-型半導體層在該緩衝層上,其中該n-型半導體層係一n-型氮化鎵;形成一主動層在該n-型半導體層上,其中該主動層係多層量子井(multi-quantum well);形成一p-型半導體層在該主動層上,其中該p-型半導體層係一p-型氮化鎵;形成一透明導電層在該p-型半導體層上,其中該透明導電層係石墨烯(Graphene);結合一導電基板在該透明導電層上;執行一雷射剝離步驟,係根據該導電基板上之凹凸不平之該表面以使該導電基板與該緩衝層分離,並使得在該緩衝層上形成凹凸不平之一表面;對該緩衝層之凹凸不平之該表面執行一乾式蝕刻步驟,使得該緩衝層之凹凸不平之該表面上同時具有粗糙表面;以及形成一金屬電極在該緩衝層上,該金屬電極係由錫(Sn)、銅(Cu)、以及鎢(W)金屬元素或其合金群組中所選出。
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JP2002016285A (ja) * | 2000-06-27 | 2002-01-18 | National Institute Of Advanced Industrial & Technology | 半導体発光素子 |
GB0902569D0 (en) * | 2009-02-16 | 2009-04-01 | Univ Southampton | An optical device |
US20120180868A1 (en) * | 2010-10-21 | 2012-07-19 | The Regents Of The University Of California | Iii-nitride flip-chip solar cells |
-
2014
- 2014-04-02 TW TW103112245A patent/TWI642204B/zh active
- 2014-07-08 US US14/325,906 patent/US20150287881A1/en not_active Abandoned
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TW201214750A (en) * | 2010-03-05 | 2012-04-01 | Lg Innotek Co Ltd | Light emitting device, method of manufacturing the same, light emitting device package |
US20110220933A1 (en) * | 2010-03-09 | 2011-09-15 | Kabushiki Kaisha Toshiba | Semiconductor light emitting device and method of fabricating semiconductor light emitting device |
US20110220937A1 (en) * | 2010-03-10 | 2011-09-15 | Hwan Hee Jeong | Light emitting device and ligth emitting device pakage |
TW201216503A (en) * | 2010-10-12 | 2012-04-16 | Tekcore Co Ltd | Method for fabricating a vertical light-emitting diode with high brightness |
US20130069032A1 (en) * | 2011-09-15 | 2013-03-21 | Kabushiki Kaisha Toshiba | Semiconductor light emitting device, wafer, method for manufacturing semiconductor light emitting device, and method for manufacturing wafer |
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US20150287881A1 (en) | 2015-10-08 |
TW201539783A (zh) | 2015-10-16 |
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