TWI641989B - Neuromorphic computing device - Google Patents

Abstract

A neurological computing device includes a plurality of column lines, a plurality of row lines, and a plurality of synapse units. The synaptic units are located at the intersection of the column line and the row line, respectively. The synaptic units include a first synapse unit and a second synapse unit. The first synapse unit includes a first resistance adjustable element and a first transistor coupled in series with the first resistance adjustable element. The first transistor has a first aspect ratio and is configured to receive a first turn-on voltage. The second synaptic unit includes a second resistance adjustable element and a second transistor serially coupled to the second resistance adjustable element. The second transistor has a second aspect ratio and is configured to receive a second turn-on voltage. The first aspect ratio is different from the second aspect ratio, and/or the first turn-on voltage is different from the second turn-on voltage.

Description

Neurological computing device

The present invention generally relates to a neural-like computing device, and more particularly to a neural computing device implemented based on a memory array hardware architecture.

Recently, a neural-like computing device implemented using a memory array has been proposed. This type of neural computing device has the advantage of low power consumption compared to using a processor to perform a neural-like calculus.

A neurological computing device typically includes a plurality of synapse units. Each synapse unit corresponds to a weight value. When an input vector is applied to the neural-like computing device, the input vector is multiplied by a weight vector formed by the weight values associated with the associated one or more synaptic units to obtain a sum of product result. Product terms and operations are widely used in neurological devices.

Traditionally, the synaptic unit includes a series of resistive memory (ReRAM) and a transistor to form a "1S1R" circuit structure in which resistive memory is used to present different weight values, while a transistor is used as a Switching element. However, the resistance value of the resistive memory tends to be unfavorable due to resistance distribution, instability, data retention, resistance drift, etc., so that the resistive memory cannot be accurately controlled at the desired resistance value, resulting in Synaptic units are unable to provide the required weight values, which in turn affects the correctness and stability of the neural-like computing device.

The present invention generally relates to a neural computing device implemented based on a memory array hardware architecture. According to an embodiment of the invention, the synapse unit in the neural-like computing device comprises a resistance adjustable element and a transistor, wherein the weight value to be presented by the synaptic unit is determined by the conductivity of the transistor, and the resistance value can be The tuning element is only used as a switching element. Since the conductivity of the transistor can be precisely controlled by the magnitude of the applied on-voltage and/or the aspect ratio (W/L) of the transistor, the accuracy and stability of the product term and the operation can be effectively improved. In addition, since the resistance value of the resistance-adjustable element is simply set to a low resistance state or a high resistance state as a switching element, it is advantageous to integrate the above-mentioned transistor with adjustable conductivity. The multi-bit multi-level weight value is realized in the sum operation.

According to one aspect of the invention, a neurological computing device is presented. The neurological computing device includes a plurality of column lines, a plurality of row lines, and a plurality of synaptic units. The synaptic units are located at the intersection of the column line and the row line, respectively. The synaptic units include a first synapse unit and a second synapse unit. The first synapse unit includes a first resistance adjustable element and a first transistor coupled in series with the first resistance adjustable element. The first transistor has a first aspect ratio and is configured to receive a first turn-on voltage. The second synaptic unit includes a second resistance adjustable element and a second transistor serially coupled to the second resistance adjustable element. The second transistor has a second aspect ratio and is configured to receive a second turn-on voltage. The first aspect ratio is different from the second aspect ratio, and/or the first turn-on voltage is different from the second turn-on voltage.

According to another aspect of the invention, a neural-like computing device is provided that is adapted to perform a product term sum operation on an input vector. The neurological computing device includes a plurality of column lines, a plurality of row lines, and a plurality of synaptic units. The column lines are used to receive input vectors. The line line is used to output the product term and result of the input vector and the weight vector. The synaptic cells are located at the intersection of the column lines and the row lines and are used to form the weight vector. The synaptic units include a first synapse unit and a second synapse unit. The first synapse unit includes a first resistance adjustable element and a first transistor coupled in series with the first resistance adjustable element. The first resistance adjustable component is configured to be set to a low resistance state or a high resistance state. When the first resistance adjustable element is set to a low resistance state, the first conductivity of the first transistor represents a first weight value of the first synapse unit, and the first weight value is included in the weight vector. The second synaptic unit includes a second resistance adjustable element and a second transistor serially coupled to the second resistance adjustable element. The second resistance adjustable component is configured to be set to a low resistance state or a high resistance state. When the second resistance adjustable element is set to a low resistance state, the second conductivity of the second transistor represents a second weight value of the second synaptic unit, and the second weight value is included in the weight vector.

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

FIG. 1 schematically depicts the circuit structure of a nerve-like computing device 100. The neural-like computing device 100 includes column lines BL ₁ to BL ₂ , row lines SL ₁ to SL ₆ , word lines WL ₁ to WL ₆ , and a plurality of synapse units SP _1,1 to SP _1,6 and SP _{2, 1} ~ SP _2,6 . The synapse cells SP _1,1 to SP _1,6 and SP _2,1 to SP _{2,6 are} located at intersections of the column lines BL ₁ to BL ₂ and the row lines SL ₁ to SL ₆ . Although the neural-like computing device 100 illustrated in FIG. 1 is illustrated by an array of 2 ́6 synaptic units, the present invention is not limited thereto, and the neural-like computing device 100 may include M column lines and N lines. a row line, and M ́ N synaptic units located at the intersection of the column lines and the row lines, where M, N are positive integers greater than one.

The neural-like computing device 100 can perform a product term sum operation on the input vector. An input vector as used herein refers to a vector of one or more input elements (eg, voltage values, current values). As shown, column lines BL ₁ , BL ₂ receive input voltages x1 and x2, respectively. Therefore, the input vector can be expressed as a one-dimensional matrix of [x1, x2].

The synaptic units SP _1,1 ~SP _1,6 , SP _2,1 ~SP _{2,6 are} used to form a weight vector consisting of one or more weight values. For example, the weight values of the synaptic units SP _1,1 ~SP _1,6 in the first column are w11~w16, and the weight values of the synaptic units SP _2,1 ~SP _2,6 in the second column are respectively W21~w26, wherein the weight values w11~w16, w21~w26 can be described by the conductivity of the transistor or other suitable physical quantity. For example, if the electro-crystalline system is a MOS, the conductivity refers to the ability to conduct current between the drain and source terminals of the transistor.

Each of the synapse units includes a series of resistance adjustable elements and a transistor. As shown, the synapse unit SP _1,1 includes a resistance adjustable element R _1,1 and a transistor T _1,1 . The adjustable value component can be a resistive memory (ReRAM), a phase change memory (PCRAM), a magnetoresistive memory (MRAM), a fuse/anti-fuse device, or other high resistance state and low resistance. The device of the value state.

According to an embodiment of the present invention, the resistance adjustable element is used as a switching element that is binaryly set to a low resistance state or a high resistance state to implement an ON/OFF function. The transistor is used as a weighting element to present a specific conductivity to determine the weight value of the synaptic unit.

The resistance adjustable component is set to a low resistance state to enable the synapse unit or to be set to a high resistance state to disable the synapse unit. When the synapse unit is enabled, the weight value corresponding to the enabled synaptic unit will be included in the weight vector during the product term and operation. Conversely, when the synaptic unit is disabled, the weight value corresponding to the disabled synaptic unit will not be included in the weight vector during the product term and operation. This is because when the resistance-adjustable component is set to a high-resistance state (that is, the synapse unit is disabled), the synapse cell hardly conducts current, that is, does not contribute to the output current on the row line.

The line lines SL ₁ ~SL ₆ provide output terms and results by conducting an output current. For example, assume that all synaptic units SP ₁₁ ~SP ₁₆ , SP ₂₁ ~SP ₂₆ are enabled (that is, the resistance adjustable elements in the synapse units are set to a low resistance state), through Adding the output current on the line lines SL ₁ to SL ₃ , the product direction and the result SUM1 can be obtained as follows:

(Formula 1)

Where the input vector is [x1, x2] and the weight vector is .

Similarly, by collecting the currents of the line lines SL ₄ to SL ₆ , the product direction and the result SUM2 can be obtained as follows:

(Formula 2)

Where the input vector is [x1, x2] and the weight vector is .

Unlike typical neurological computing devices, the weight values in the weight vectors described above (eg, w11~w16, w21~w26) are dominated by the conductivity of the transistor in the synaptic unit, rather than being adjustable by the resistance. The resistance value of the component dominates. Instead, according to the neural computing device of the present invention, the resistance adjustable element in the synapse unit acts as a switching element. In this way, not only can each weight value be accurately set, but also the magnitude of the weight value can be adversely affected by resistance distribution, instability, data maintenance, and resistance drift.

On the other hand, you can observe Equation 1 and rewrite it as follows:

The equivalent weight value W1 = w11 + w12 + w13, and the equivalent weight value W2 = w21 + w22 + w23.

For the same reason, you can observe Equation 2 and rewrite it as follows:

The equivalent weight value W3 = w14 + w15 + w16, the equivalent weight value W4 = w24 + w25 + w26.

It can be seen that in a product and result (such as SUM1), a combination of synaptic units (such as SP _1,1 , SP _1,2 , SP _1,3 ) that receive the same input voltage (such as x1) can be obtained. A multi-bit/multi-order equivalent weight value (such as W1 ) is implemented for the input voltage. For example, if w11:w12:w13 is 1:2:4, then W1 can be represented as a binary 3-bit (8th-order) value.

According to an embodiment of the invention, the conductivity can be determined by adjusting at least one of (1) the on-voltage and (2) the aspect ratio (W/L) of the transistor in the synapse unit, thereby determining the weight of the synapse unit. The size of the value. As used herein, "on voltage" means applied to a control terminal of a transistor (eg, a gate of a MOS or a base of a BJT) via a word line (eg, WL ₁ ) sufficient to turn the transistor on and operate. The voltage in the triode region. To assist in understanding, the first embodiment to the third embodiment are explained. However, it should be noted that the present invention is not limited by the contents of the exemplary embodiments.

Embodiment 1

According to the first embodiment, the transistors in the different synaptic units may have different aspect ratios. Therefore, the transistors in the synaptic cells will exhibit different electrical conductivities in response to the same turn-on voltage, thereby determining the weight value of the synaptic unit.

FIG. 2 is a top plan view of a partial circuit layout of a nerve-like computing device 200 according to the first embodiment. The neural-like computing device 200 includes column lines BL _i , BL _i+1 , BL _i+2 , row lines SL _j , word lines WL, and synaptic units SP _i,j , SP _i+1,j , SP _{i+2 , j} . Although FIG. 2 depicts only 3 ́1 synaptic units, it should be noted that the neurological computing device 200 can include any number of synaptic units and combinations.

In this embodiment, the column lines BL _i to BL _{i+2 are} formed in the second metal layer (M2). The row line SL _j forms a first metal layer (M1) under the second metal layer. The synaptic units SP _i,j , SP _i+1,j , SP _i+2,j receive the turn-on voltage Vg via the word line WL.

The synaptic unit SP _i,j comprises a series of resistance adjustable elements R _i,j and a transistor T _i,j . The synaptic unit SP _i+1,j includes a series of resistance adjustable elements R _i+1,j and a transistor T _i+1,j . The synaptic unit SP _i+2,j comprises a series of resistance adjustable elements R _i+2,j and a transistor T _i+2,j . As shown, the transistors T _i,j , T _i+1,j , T _i+2,j have different sizes, that is, the transistors T _i,j , T _i+1,j ,T _{i +2, j} have a first aspect ratio, a second aspect ratio, and a third aspect ratio, respectively.

Each of the transistors T _i,j , T _i+1,j , T _i+2,j formed on the substrate is electrically connected to the row line SL _j located at the first metal layer. In response to the input voltage x applied to the column lines BL _i ~ BL _i+2 , the transistors T _i,j , T _i+1,j , T _i+2,j can generate an output current on the row line SL _j . The total output current on the row line SL _j i.e. corresponding to a product term for the SUM result and the input voltage x.

The resistance adjustable element R _{i,j is} electrically connected between the transistor T _i,j and the column line BL _i . The resistance adjustable element R _{i+1,j is} electrically connected between the transistor T _i+1,j and the column line BL _i+1 . The resistance adjustable element R _{i+2,j is} electrically connected between the transistor T _i+2,j and the column line BL _i+2 .

The word line WL is electrically connected to the control terminals of the transistors T _i,j , T _i+1,j , T _i+2,j for transmitting the on-voltage Vg to the respective transistors T _i,j ,T _{i+1 , j} , T _{i+2, j} .

Combining the synaptic units SP _i,j , SP _i+1,j , SP _i+2,j , an equivalent weight value w for the input voltage x can be achieved. For example, the aspect ratio of each of the transistors T _i,j , T _i+1,j , T _i+2,j can be appropriately designed such that the transistors T _i,j , T _i+1,j , T _i+2,j may respectively present the respective electrical conductivities s ₁ , s ₂ , s _{3 in} response to the on-voltage Vg, wherein the electrical conductivity s ₁ , s ₂ , s ₃ respectively correspond to (or represent) the synaptic unit SP _{i , The} weight value of _j , SP _{i+1, j} , SP _{i+2, j} .

In one example, the ratio between two different degrees of electrical conductivity is the nth power of 2, where n is an integer. For example, s ₁ :s ₂ :s ₃ can be 1:2:4 to achieve an equivalent weight value w of a binary 3-bit. Specifically, if the low resistance state of the resistance adjustable component is represented by bit "1" and the high resistance state is represented by bit "0", then the resistance adjustable component R _i,j , R _{i+ When 1,j} , R _i+2,j are all in the low resistance state (1, 1, 1), the transistors T _i,j , T _i+1,j , T _{i+2,j are} all generated for the output current. The contribution is such that the total output current on the line line SL _j is maximum, so the equivalent weight value w is equivalent to 7 (=1+2+4). Similarly, when the resistance states of the resistance-adjustable elements R _i,j , R _i+1,j , R _i+2,j are (1, 0, 1), respectively, the total output current on the line line SL1 is only Contributed by the transistors T _i,j and T _i+2,j , where the equivalent weight value w is equivalent to 5 (=1+0+4).

In other examples, the ratio between the electrical conductivities of the different transistors may be arbitrary.

In order to obtain more precision, the conductivity (s _on ) of the resistance variable element in the low resistance state can be taken into consideration when designing the weight value of the synaptic unit. For example, in order to achieve a 3-bit equivalent weight value w through the synaptic units SP _i,j , SP _i+1,j , SP _i+2,j , s ₁ //s _on :s ₂ / can be designed /s _on :s ₃ //s _on is about 1:2:4.

Embodiment 2

According to the second embodiment, the transistors in the different synaptic units have the same aspect ratio, but receive different levels of on-voltage to exhibit different degrees of conductivity to determine the weight values of the synaptic units.

FIG. 3 is a top plan view of a portion of the circuit layout of the nerve-like computing device 300 according to the second embodiment. The neural-like computing device 300 includes a column line BL _i ', a row line SL _j ', SL _j+1 ', SL _j+2 ', a word line WL _j ', WL _j+1 ', WL _j+2 ' and a burst Touch unit SP _i,j ', SP _i,j+1 ', SP _i,j+2 '. Although FIG. 3 depicts only 1 ́3 synaptic units, it should be noted that the neurological computing device 300 can include any number of synaptic units and combinations.

The column line BL _i ' is formed on the second metal layer. The row lines SL _j ', SL _j+1 ', SL _j+2 ' form a first metal layer under the second metal layer. In this embodiment, the synaptic units SP _i,j ', SP _i,j+1 ', SP _i,j+2 ' are respectively via the word line WL _j ', WL _j+1 ', WL _j+2 ' Different on-voltages Vg1, Vg2, and Vg3 are received.

The synaptic unit SP _i,j ' comprises a series of resistance adjustable elements R _i,j 'and a transistor T _i,j '; the synapse unit SP _i,j+1 ' comprises a series of adjustable value elements R _{i , j+1} 'and the transistor T _i,j+1 '; the synaptic unit SP _i,j+2 ' comprises a series of resistance adjustable elements R _i,j+2 'and a transistor T _i,j+2 '. The transistors T _i,j ', T _i,j+1 ', T _i,j+2 ' have the same size. Each of the transistors T _i,j ', T _i,j+1 ', T _i,j+2 ' is electrically connected to the row lines SL _j ', SL _j+1 ', SL _{j of the} first metal layer, respectively ₊₂ '.

The resistance adjustable element R _i,j ' is electrically connected between the transistor T _i,j ' and the column line BL _i '. The resistance adjustable element R _i,j+1 ' is electrically connected between the transistor T _i,j+1 ' and the column line line BL _i '. The resistance adjustable element R _i,j+2 ' is electrically connected between the transistor T _i,j+2 ' and the column line line BL _i '.

Via the word lines WL _j ', WL _j+1 ', WL _j+2 ', the control terminals of the transistors T _i,j ', T _i,j+1 ', T _i,j+2 ' are respectively turned on. Voltages Vg1, Vg2, Vg3. The input voltage x' is applied to the column line BL _i '. In response to the input voltage x', the synaptic units SP _i,j ', SP _i,j+1 ', SP _i,j+2 ' may be in the line lines SL _j ', SL _j+1 ', SL _{j+2, respectively} 'The corresponding output current is generated on the '. The sum of the output currents can be used to represent an integral term and the result SUM' which is almost equal to the product of the input voltage x' and an equivalent weight value w', which is the synaptic unit SP _{i , j} ', SP _{i, j+1} ', SP _{i, j+2} 'decide.

By appropriately designing the sizes of the turn-on voltages Vg1, Vg2, and Vg3, the transistors T _i,j ', T _i,j+1 ', T _i,j+2 ' can exhibit electrical conductivity s ₁ ', s ₂ ', respectively. s ₃ ', wherein the electrical conductivity s ₁ ', s ₂ ', s ₃ ' respectively represent the weight values of the synaptic units SP _i,j ', SP _i,j+1 ', SP _i,j+2 '. The ratio of conductivity s ₁ ':s ₂ ':s ₃ ' can be arbitrary, for example 1:2:4 or 1:1:1.

In order to obtain more precision, the conductivity (s _on ) of the resistance variable element in the low resistance state can be taken into consideration when designing the weight value of the synaptic unit. For example, in order to achieve a 3-bit equivalent weight value w' through the synaptic unit SP _i,j ', SP _i,j+1 ', SP _i,j+2 ', the turn-on voltages Vg1, Vg2 can be adjusted. The size of Vg3 is planned to be s ₁ '//s _on :s ₂ '//s _on :s ₃ '//s _on is approximately 1:2:4.

Embodiment 3

According to the third embodiment, the transistors in the different synaptic units have different aspect ratios and receive different levels of on-voltage to exhibit different degrees of conductivity to determine the weight values of the synaptic units.

4 is a top plan view of a portion of a circuit layout of a nerve-like computing device 400 in accordance with a third embodiment. The neural-like computing device 400 includes a plurality of column lines BL _i ''~BL _i+3 '', a plurality of row lines SL _j ''~SL _j+3 '', and a plurality of word lines WL _j ''~WL _{j j +3} '' and 4 ́4 synaptic units. Although FIG. 4 depicts only 4 ́4 synaptic units, it should be noted that the neurological computing device 400 can include any number of synaptic units and combinations.

The word line WL _j '' and WL _j+2 '' are applied with the turn-on voltage Vg1, and the word lines WL _j+1 '' and WL _j+3 '' are applied with the turn-on voltage Vg2.

The synapse unit coupled to the column lines BL _i '' and BL _i+1 '' receives the input voltage x1. The synapse unit coupled to the column lines BL _i+2 '', BL _i+3 '' receives the input voltage x2. Collecting row line SL _j '' and SL _{j + 1} 'on the output current', and results can be obtained product term SUM1 ''. Collect the output current on the line line SL _j+2 '' and SL _j+3 '' to obtain the product term and the result SUM2''

According to the example of Fig. 3, the transistors in the synaptic unit SP _i,j '' and the crystals in the synaptic unit SP _i,j+1 '' have the same aspect ratio (= WD1/LH). The transistor in the synaptic unit SP _i+1,j '' and the transistor in the synaptic unit SP _i+1,j+1 '' have a width to length ratio (= WD2/LH).

By appropriately designing the aspect ratio of the transistor and the value of the on-voltage, the synaptic units SP _i,j '', SP _i,j+1 '', SP _i+1,j '', SP _{i+1 The} weight values of _j+1 '' are planned to be w11'', w12'', w21'', w22'', respectively. The values of the weight values w11'', w12'', w21'', w22'' may be arbitrary depending on the synaptic units SP _i,j '', SP _i,j+1 '', SP _{i+ 1,j} '', SP _{i+1, j+1} '' conductivity of the transistor. In an example, the turn-on voltage Vg1 is less than Vg2, and the aspect ratio (WD1/LH) is less than (WD2/LH), such that the ratio between the weight values is w11'': w12'': w21'': w22'' 1:2:4:8, to achieve binary 4 through synaptic units SP _i,j '', SP _i,j+1 '', SP _i+1,j '', SP _i+1,j '' The equivalent weight value w'' of the bit (16th order).

In summary, the present invention generally relates to a neural computing device implemented based on a memory array hardware architecture. According to an embodiment of the invention, the synapse unit in the neural-like computing device comprises a resistance adjustable element and a transistor, wherein the weight value to be presented by the synaptic unit is determined by the conductivity of the transistor, and the resistance value can be The tuning element is only used as a switching element. Since the conductivity of the transistor can be precisely controlled by the magnitude of the applied on-voltage and/or the aspect ratio (W/L) of the transistor, the correctness of the product and operation performed by the neural-like computing device can be effectively improved. And stability. In addition, since the resistance value of the resistance-adjustable element is simply set to a low resistance state or a high resistance state as a switching element, it is advantageous to integrate the above-mentioned transistor with adjustable conductivity. The multi-bit multi-level weight value is realized in the sum operation.

Although the present invention has been disclosed above by way of example, it is not intended to limit the invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100, 200, 300, 400‧‧‧ class neural computing devices

BL ₁ ~BL ₂ , BL _i , BL _i+1 , BL _i+2 , BL _i ', BL _i ''~BL _i+3 ''‧‧‧ Column line

SL ₁ ~SL ₆ , SL _j , SL _j ', SL _j+1 ', SL _j+2 ', SL _j ''~SL _j+3 ''‧‧‧

SP _1,1 ~SP _1,6 , SP _2,1 ~SP _2,6 , SP _i,j , SP _i+1,j ,SP _i+2,j ,SP _i,j ',SP _{i,j+ 1} ', SP _{i, j+2} ', SP _{i, j} '', SP _{i, j+1} '', SP _{i+1, j} '', SP _{i+1, j+1} ''‧‧‧ Touch unit

X1, x2, x‧‧‧ input voltage

R _1,1 , R _i,j , R _i+1,j , R _i+2,j , R _i,j ',R _i,j+1 ',R _i,j+2 '‧‧‧ resistance Adjustable component

T _1,1 , T _i,j , T _i+1,j , T _i+2,j ,T _i,j ',T _i,j+1 ',T _i,j+2 '‧‧‧ transistor

WL ₁ ~ WL ₆ , WL, WL _j ', WL _j+1 ', WL _j+2 ', WL _j ''~ WL _j+3 ''‧‧‧ character line

Vg, Vg1, Vg2, Vg3‧‧‧ turn-on voltage

SUM1, SUM2, SUM, SUM', SUM1'', SUM2''‧‧‧ product terms and results

WD1, WD2‧‧‧ transistor width

LH‧‧‧Optical length

Fig. 1 schematically shows the circuit structure of a neurological computing device. 2 is a top plan view of a portion of a circuit layout of a nerve-like computing device in accordance with an embodiment. 3 is a top plan view of a partial circuit layout of a neural-like computing device according to Embodiment 2. 4 is a top plan view of a partial circuit layout of a neural-like computing device according to Embodiment 3.

Claims (10)

A neurological computing device includes: a plurality of column lines; a plurality of line lines; and a plurality of synapse units respectively located at intersections of the column lines and the line lines, the synapse units comprising: a first a synaptic unit, comprising: a first resistance adjustable component; and a first transistor coupled in series with the first resistance adjustable component, the first transistor having a first aspect ratio and receiving a first on-voltage; and a second synapse unit, comprising: a second resistance adjustable component; and a second transistor coupled in series with the second resistance adjustable component, the second transistor having a second aspect ratio is used to receive a second turn-on voltage; wherein the first aspect ratio is different from the second width-to-length ratio, and/or the first turn-on voltage is different from the second turn-on voltage. The neural computing device of claim 1, wherein the neural computing device is configured to perform an integral term operation on an input vector, the column lines for receiving the input vector, the row lines for outputting An integral term of the input vector and a weight vector, the synapse units are configured to form the weight vector; the first resistance adjustable component is configured to be binaryally set to a low resistance state or In a high resistance state, the second resistance adjustable component is configured to be binaryly set to the low resistance state or the high resistance state. The neural computing device of claim 2, wherein a first conductivity represented by the first transistor receiving the first turn-on voltage determines a first weight value, the first weight value being included in the weight And a second conductivity represented by the second transistor receiving the second turn-on voltage determines a second weight value, where the second weight value is included in the weight vector. The neural computing device of claim 3, wherein the first on-voltage is the same as the second on-voltage, and the first aspect ratio of the first transistor and the second transistor The second synapse unit and the second synapse unit are coupled to the two of the column lines, and receive the first on voltage and the second on voltage via a word line; The ratio between the first conductivity and the second conductivity is about 2 n-th power, where n is an integer. The neural computing device of claim 3, wherein the first aspect ratio of the first transistor is the same as the second width to length ratio of the second transistor, and the first conduction voltage and the first The two on-voltages are different in magnitude; the first synapse unit and the second synapse unit are coupled to one of the column lines, and receive the first on-voltage and the second on-voltage via different word lines The ratio between the first conductivity and the second conductivity is about n times the power of 2, where n is an integer. The neural computing device of claim 3, wherein the first aspect ratio of the first transistor is different from the second width to length ratio of the second transistor, and the first conduction voltage is The second on-voltage is different in magnitude; the first synapse unit and the second synapse unit are coupled to two different column lines of the column lines and two different row lines of the row lines, and different The word line receives the first turn-on voltage and the second turn-on voltage respectively; a ratio between the first conductivity and the second conductivity is about 2 n-th power, wherein n is an integer. A neural-like computing device is adapted to perform an integral term operation on an input vector, the neural computing device comprising: a plurality of column lines for receiving the input vector; and a plurality of row lines for outputting the input vector and An integral term and a result of a weight vector; and a plurality of synaptic units respectively located at intersections of the column lines and the row lines, wherein the synapse units are used to form the weight vector, and include: a synapse unit, comprising: a first resistance adjustable component for being set to a low resistance state or a high resistance state; and a first transistor coupled in series with the first resistance adjustable component When the first resistance adjustable component is set in the low resistance state, a first conductivity of the first transistor represents a first weight value of the first synapse unit, and the first weight value Included in the weight vector; and a second synapse unit, comprising: a second resistance adjustable component configured to be set to the low resistance state or the high resistance state; and a second transistor, The second resistance adjustable component is connected in series, The second resistance adjustable component is set in the low resistance state, and a second conductivity of the second transistor represents a second weight value of the second synaptic unit, and the second weight value is included in The weight vector. The neural computing device of claim 7, wherein the first on-voltage is the same as the second on-voltage, and the first aspect ratio of the first transistor and the second transistor The second synapse unit and the second synapse unit are coupled to both of the column lines, and receive the first turn-on voltage and the second turn-on voltage via a word line. The neural computing device of claim 7, wherein the first aspect ratio of the first transistor is the same as the second width to length ratio of the second transistor, and the first conduction voltage and the first The two on-voltages are different in magnitude; the first synapse unit and the second synapse unit are coupled to one of the column lines, and receive the first on-voltage and the second on-voltage via different word lines . The neural computing device of claim 7, wherein the first aspect ratio of the first transistor is different from the second width to length ratio of the second transistor, and the first conduction voltage is The second on-voltages are different in magnitude; the first synapse unit and the second synapse unit are coupled to two different column lines of the column lines and two different row lines of the row lines, and are different The word line receives the first turn-on voltage and the second turn-on voltage, respectively.