CN109829539A - Class nerve computing device - Google Patents
Class nerve computing device Download PDFInfo
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- CN109829539A CN109829539A CN201711184889.3A CN201711184889A CN109829539A CN 109829539 A CN109829539 A CN 109829539A CN 201711184889 A CN201711184889 A CN 201711184889A CN 109829539 A CN109829539 A CN 109829539A
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Abstract
The invention discloses a type nerve computing devices, including a plurality of alignment, a plurality of line and multiple cynapse units.These cynapse units are located at the infall of alignment and line.These cynapse units include the first cynapse unit and the second cynapse unit.First cynapse unit includes the first resistance value adjustable element and the first transistor that concatenates with the first resistance value adjustable element.The first transistor has the first breadth length ratio and to receive the first conducting voltage.Second cynapse unit includes the second resistance value adjustable element and the second transistor that concatenates with the second resistance value adjustable element.Second transistor has the second breadth length ratio and to receive the second conducting voltage.First breadth length ratio is different with the second breadth length ratio and/or the first conducting voltage is different with second conducting voltage.
Description
Technical field
The present invention relates generally to a type nerve computing device, and is based on memory array hardware frame more particularly to one kind
Structure realizes etc neural computing device.
Background technique
Recently, the class nerve computing device realized using memory array is suggested.Compared to utilizing a processor to hold
The calculation of row class nerve, this type nerve computing device have the advantages that low-power consumption.
Class nerve computing device generally includes multiple cynapse units (synapse).Each cynapse unit corresponds to a weight
Value.When an input vector is applied to class nerve computing device, input vector will with corresponding to one or more associated cynapse units
The weight vectors that are constituted of weighted value be multiplied, to obtain a product item and (sum of product) result.Product item and operation are wide
It is used in class nervous device generally.
Traditionally, cynapse unit includes the resistance-type memory (ReRAM) and transistor of series winding, with formation " 1S1R "
Circuit structure, wherein resistance-type memory is for different weighted values is presented, and transistor is then as switch element.So
And the resistance value of resistance-type memory often maintains (retention), resistance value to float because of resistance value distribution, unstability, data
The unfavorable factors such as shifting cause cynapse unit that can not mention so that resistance-type memory can not be accurately controlled in desired resistance value
For required weighted value, and then affect the correct and stability of class nerve computing device.
Summary of the invention
The present invention relates generally to a kind of class nerve computing device realized based on memory array hardware structure.According to this
Inventive embodiments, the cynapse unit in class nerve computing device include resistance value adjustable element and transistor, wherein cynapse unit
Weighted value to be presented is to be determined by the conducting degree size of transistor, and resistance value adjustable element is only as a switch member
Part.It is smart since the conducting degree of transistor can pass through the size of conducting voltage being applied and/or the breadth length ratio (W/L) of transistor
Regulate and control quasi-ly, therefore the correctness and stability of long-pending item and operation can be effectively improved.Further, since the resistance value of resistance value adjustable element
Low-resistance state of value or high resistant state of value only need to be merely set to using as switch element, therefore cooperate conducting degree above-mentioned adjustable
Transistor, be the weighted value for being conducive to realize the more level of multidigit member in product item and operation.
According to an aspect of the invention, it is proposed that a type nerve computing device.Class nerve computing device include a plurality of alignment,
A plurality of line and multiple cynapse units.These cynapse units are located at the infall of alignment and line.These cynapse units
Including the first cynapse unit and the second cynapse unit.First cynapse unit includes the first resistance value adjustable element and hinders with first
It is worth the first transistor of adjustable element concatenation.The first transistor has the first breadth length ratio and to receive the first conducting voltage.The
Two cynapse units include the second resistance value adjustable element and the second transistor that concatenates with the second resistance value adjustable element.Second crystal
Pipe has the second breadth length ratio and to receive the second conducting voltage.First breadth length ratio is different with the second breadth length ratio and/or first leads
The pressure that is powered is different with second conducting voltage.
According to another aspect of the invention, it is proposed that a type nerve computing device, it is suitable for executing product to input vector
Item and operation.Class nerve computing device includes a plurality of alignment, a plurality of line and multiple cynapse units.Alignment is to receive input
Vector.Product item and result of the line to export input vector and weight vectors.These cynapse units are located at alignment and line
Infall, and to form the weight vectors.These cynapse units include the first cynapse unit and the second cynapse unit.First
Cynapse unit includes the first resistance value adjustable element and the first transistor that concatenates with the first resistance value adjustable element.First resistance value can
Adjust element to be configured to low-resistance state of value or high resistant state of value.When the first resistance value adjustable element is set at low resistance shape
State, the first electrical conductivity system of the first transistor represent the first weighted value of the first cynapse unit, and the first weighted value is contained in weight
Vector.Second cynapse unit includes the second resistance value adjustable element and the second transistor that concatenates with the second resistance value adjustable element.
Second resistance value adjustable element is to be configured to low-resistance state of value or high resistant state of value.When the second resistance value adjustable element is set at
Low-resistance state of value, the second electrical conductivity system of second transistor represent the second weighted value of the second cynapse unit, the second weighted value packet
Contained in weight vectors.
More preferably understand to have to above-mentioned and other aspect of the invention, special embodiment below, and cooperates institute's attached drawing
Detailed description are as follows for formula:
Detailed description of the invention
Fig. 1 is schematically painted the circuit structure of class nerve computing device.
Fig. 2 is the top view of the partial circuit layout of the class nerve computing device according to depicted in embodiment one.
Fig. 3 is the top view of the partial circuit layout of the class nerve computing device according to depicted in embodiment two.
Fig. 4 is the top view of the partial circuit layout of the class nerve computing device according to depicted in embodiment three.
[symbol description]
100,200,300,400: class nerve computing device
BL1~BL2、BLi、BLi+1、BLi+2、BLi’、BLi"~BLi+3": alignment
SL1~SL6、SLj、SLj’、SLj+1’、SLj+2’、SLj"~SLj+3": line
SP1,1~SP1,6、SP2,1~SP2,6、SPi,j、SPi+1,j、SPi+2,j、SPi,j’、SPi,j+1’、SPi,j+2’、SPi,j”、
SPi,j+1”、SPi+1,j”、SPi+1,j+1": cynapse unit
X1, x2, x: input voltage
R1,1、Ri,j、Ri+1,j、Ri+2,j、Ri,j’、Ri,j+1’、Ri,j+2': resistance value adjustable element
T1,1、Ti,j、Ti+1,j、Ti+2,j、Ti,j’、Ti,j+1’、Ti,j+2': transistor
WL1~WL6、WL、WLj’、WLj+1’、WLj+2’、WLj"~WLj+3": wordline
Vg, Vg1, Vg2, Vg3: conducting voltage
SUM1, SUM2, SUM, SUM ', SUM1 ", SUM2 ": product item and result
WD1, WD2: transistor width
LH: transistor length
Specific embodiment
Fig. 1 is schematically painted the circuit structure of class nerve computing device 100.Class nerve computing device 100 includes alignment
BL1~BL2, line SL1~SL6, wordline WL1~WL6And multiple cynapse cell S P1,1~SP1,6And SP2,1~SP2,6.Cynapse
Cell S P1,1~SP1,6And SP2,1~SP2,6Positioned at alignment BL1~BL2With line SL1~SL6Infall.Although depicted in Fig. 1
Class nerve computing device 100 be to be explained with 2 × 6 cynapse cellular arrays, but the present invention is not limited thereto, class nerve
Computing device 100 may include M alignment, N line and positioned at the M of these alignments and the infall of line × N number of cynapse list
Member, wherein M, N are the positive integer greater than 1.
Class nerve computing device 100 can execute product item and operation to input vector.Input vector described herein refers to
The vector constituted with one or more input elements (such as voltage value, current value).As shown, alignment BL1、BL2It receives respectively
Input voltage x1 and x2.Therefore, input vector is represented by the one-dimensional matrix of [x1, x2].
Cynapse cell S P1,1~SP1,6、SP2,1~SP2,6To form weight vectors, by one or more weighted value institute structures
At.For example, the cynapse cell S P of the 1st column1,1~SP1,6Weighted value be respectively w11~w16, the cynapse unit of the 2nd column
SP2,1~SP2,6Weighted value be respectively w21~w26, wherein weighted value w11~w16, w21~w26 can use transistor conduction
(conductivity) or other suitable physical quantitys are spent to describe.For example, if one MOS of transistor-based, electrical conductivity are meant
The ability of conducting electric current between the drain end of transistor and source terminal.
Each cynapse unit respectively includes the resistance value adjustable element and transistor of concatenation.As shown, cynapse unit
SP1,1Including resistance value adjustable element R1,1And transistor T1,1.Resistance value adjustable element can be resistance-type memory (ReRAM), phase
Variation memory (PCRAM), reluctance type memory (MRAM), fuse/anti-fuse device or other can provide high resistant state of value and
The device of low-resistance state of value.
According to an embodiment of the present invention, resistance value adjustable element is by dualization to be configured to low-resistance as switch element
State of value or high resistant state of value are to realize ON/OFF function.Transistor is then as weight elements, specific conduction is presented
Spend the weighted value to determine cynapse unit.
Resistance value adjustable element, which is configured to low-resistance state of value, to be carried out enable (enable) cynapse unit or is configured to high resistant
State of value carrys out forbidden energy (disable) cynapse unit.When cynapse unit is enabled, weight corresponding to the cynapse unit being enabled
Value is in product item and calculating process, it will is included into weight vectors and does operation.Conversely, this is banned when cynapse unit is disabled
Weighted value corresponding to the cynapse unit of energy will not be included into weight vectors during product item and operation and do operation.
This is because cynapse unit is hardly when resistance value adjustable element is configured to high resistant state of value (namely cynapse unit is disabled)
Meeting conducting electric current, that is, output electric current that will not be online to row generate contribution.
Line SL1~SL6By conduct output currents to provide long-pending item and result.As an example it is assumed that all cynapse units
SP11~SP16、SP21~SP26All being enabled, (the resistance value adjustable element namely in these cynapse units is all configured to low resistance
State), through aggregation line SL1~SL3On output electric current, product can be obtained to as follows with result SUM1:
Wherein input vector is [x1, x2], and weight vectors are
Similarly, through collection line SL4~SL6Electric current, product can be obtained to as follows with result SUM2:
Wherein input vector is [x1, x2], and weight vectors are
Different from typical class nerve computing device, each weighted value in weight vectors described in top (such as w11~
W16, w21~w26) it is to be dominated by the electrical conductivity of transistor in cynapse unit, rather than dominated by the resistance value of resistance value adjustable element.
Instead, class nerve computing device according to the present invention, the resistance value adjustable element in cynapse unit is as switch element.
Through this mode, each weighted value not only can be accurately set, the size that also can avoid weighted value is distributed by resistance value, is unstable
Property, data maintain, the adverse effect of resistance value drift.
On the other hand, observable formula 1 and rewrite it is as follows:
SUM1=x1 × W1+x2 × W2
Wherein equivalent weighted value W1=w11+w12+w13, equivalent weighted value W2=w21+w22+w23.
Similarly, observable formula 2 and rewrite it is as follows:
SUM2=x1 × W3+x2 × W4
Wherein equivalent weighted value W3=w14+w15+w16, equivalent weighted value W4=w24+w25+w26.
It can be seen that, in a product item and result (such as SUM1), can pass through the cynapse list for receiving identical input voltage (such as x1)
Member (such as SP1,1、SP1,2、SP1,3) combination, realize be directed to the input voltage multidigit/multistage equivalent weighted value (such as W1).Citing
For, if w11:w12:w13 is 1:2:4, W1 can be expressed as the value of binary system 3 (8 rank).
It according to embodiments of the present invention, can be by adjusting (1) conducting voltage and (2) breadth length ratio of transistor in cynapse unit
(W/L) at least one determines electrical conductivity, and then determines the size of the weighted value of cynapse unit." conducting described herein
Voltage " is referred to via wordline (such as WL1) be applied to transistor control terminal (such as MOS grid or BJT base stage), and
It is enough the voltage for making transistor turns and operating in triode region (triode region).To help to understand, hereby it is aided with embodiment
One explains to embodiment three.However, it should be appreciated that the present invention is not limited with these illustrative embodiment contents.
Embodiment one
According to embodiment one, the transistor in not homo-synapse unit can have different breadth length ratios.Therefore, these cynapse lists
Transistor in member will be responsive to identical conducting voltage and different electrical conductivities be presented, and then determine the weight of cynapse unit
Value.
Fig. 2 is the top view of the partial circuit layout of the class nerve computing device 200 according to depicted in embodiment one.Class mind
Being computed device 200 includes alignment BLi、BLi+1、BLi+2, line SLj, wordline WL and cynapse cell S Pi,j、SPi+1,j、
SPi+2,j.Although Fig. 2 is only painted 3 × 1 cynapse units, it should be noted that class nerve computing device 200 may include any number of prominent
Touch unit and combination.
In this embodiment, alignment BLi~BLi+2It is formed in second metal layer (M2).Line SLjIt is formed in second metal layer
The first metal layer (M1) of lower section.Cynapse cell S Pi,j、SPi+1,j、SPi+2,jConducting voltage Vg is received via wordline WL.
Cynapse cell S Pi,jIncluding concatenated resistance value adjustable element Ri,jAnd transistor Ti,j.Cynapse cell S Pi+1,jIncluding
Concatenated resistance value adjustable element Ri+1,jAnd transistor Ti+1,j.Cynapse cell S Pi+2,jIncluding concatenated resistance value adjustable element Ri+2,j
And transistor Ti+2,j.As shown, transistor Ti,j、Ti+1,j、Ti+2,jIt has different sizes, that is to say, that transistor
Ti,j、Ti+1,j、Ti+2,jIt is respectively provided with the first length-width ratio, the second length-width ratio and third length-width ratio.
Each transistor T being formed on substratei,j、Ti+1,j、Ti+2,jIt is electrically connected to the line SL positioned at the first metal layerj。
In response to being applied to alignment BLi~BLi+2On input voltage x, transistor Ti,j、Ti+1,j、Ti+2,jIt can be in line SLjUpper generation is defeated
Electric current out.Line SLjOn total output electric current be correspond to one be directed to input voltage x product item and result SUM.
Resistance value adjustable element Ri,jIt is electrically connected at transistor Ti,jWith alignment BLiBetween.Resistance value adjustable element Ri+1,jElectrically
It is connected to transistor Ti+1,jWith alignment BLi+1Between.Resistance value adjustable element Ri+2,jIt is electrically connected at transistor Ti+2,jAnd alignment
BLi+2Between.
Wordline WL is electrically connected transistor Ti,j、Ti+1,j、Ti+2,jControl terminal, to transmit conducting voltage Vg to each crystal
Pipe Ti,j、Ti+1,j、Ti+2,j。
In conjunction with cynapse cell S Pi,j、SPi+1,j、SPi+2,j, it can be achieved that being directed to the equivalent weighted value w of input voltage x.Citing comes
It says, can pass through and be suitably designed each transistor Ti,j、Ti+1,j、Ti+2,jLength-width ratio so that transistor Ti,j、Ti+1,j、Ti+2,jIt can divide
It holds your noise and answers conducting voltage Vg and respective electrical conductivity σ 1, σ 2, σ 3 is presented, wherein electrical conductivity σ 1, σ 2, σ 3 respectively correspond (or representative)
Cynapse cell S Pi,j、SPi+1,j、SPi+2,jWeighted value.
In an example, the n times side that the ratio between two different electrical conductivities is 2, wherein n is integer.For example, σ
1: σ 2: σ 3 can be 1:2:4, to realize binary system 3 equivalent weighted value w.Specifically, if the low-resistance of resistance value adjustable element
State of value indicates that high resistant state of value is indicated with position " 0 " with position " 1 ", then as resistance value adjustable element Ri,j、Ri+1,j、Ri+2,jIt is all low
When resistance value state (1,1,1), transistor Ti,j、Ti+1,j、Ti+2,jContribution all is generated to output electric current, so that line SLjOn it is total defeated
Electric current is maximum out, so when equivalent weighted value w be equivalent to 7 (=1+2+4).Similarly, as resistance value adjustable element Ri,j、Ri+1,j、
Ri+2,jResistance states when being respectively (1,0,1), total output electric current on line SL1 is only by transistor Ti,jAnd Ti+2,jTribute
It offers, equivalent weighted value w is equivalent to 5 (=1+0+4) at this time.
In other examples, the ratio between the electrical conductivity of different crystal pipe can be arbitrary.
More precision in order to obtain, can be by resistance value variable element in low resistance when designing the weighted value of cynapse unit
Electrical conductivity (σ on) when state accounts for.For example, in order to through cynapse cell S Pi,j、SPi+1,j、SPi+2,jRealize 3
Equivalent weighted value w, can design on: σ 3//σ on of on: σ 2//σ of 1//σ of σ is about 1:2:4.
Embodiment two
According to embodiment two, transistor breadth length ratio having the same in not homo-synapse unit, but receive different size of
Conducting voltage and different electrical conductivities is presented, to determine the weighted value of each cynapse unit.
Fig. 3 is the top view of the partial circuit layout of the class nerve computing device 300 according to depicted in embodiment two.Class mind
Being computed device 300 includes alignment BLi', line SLj’、SLj+1’、SLj+2', wordline WLj’、WLj+1’、WLj+2' and cynapse list
First SPi,j’、SPi,j+1’、SPi,j+2'.Although Fig. 3 is only painted 1 × 3 cynapse unit, class nerve computing device 300 should be noted that
It may include any number of cynapse unit and combination.
Alignment BLi' it is formed in second metal layer.Line SLj’、SLj+1’、SLj+2' it is formed in below second metal layer
One metal layer.In this embodiment, cynapse cell S Pi,j’、SPi,j+1’、SPi,j+2' respectively via wordline WLj’、WLj+1’、WLj+2’
Receive different size of conducting voltage Vg1, Vg2, Vg3.
Cynapse cell S Pi,j' it include concatenated resistance value adjustable element Ri,j' and transistor Ti,j'；Cynapse cell S Pi,j+1’
Including concatenated resistance value adjustable element Ri,j+1' and transistor Ti,j+1'；Cynapse cell S Pi,j+2' it include that concatenated resistance value is adjustable
Element Ri,j+2' and transistor Ti,j+2'.Transistor Ti,j’、Ti,j+1’、Ti,j+2' be of the same size.Each transistor Ti,j’、
Ti,j+1’、Ti,j+2' be respectively and electrically connected to be located at the line SL of the first metal layerj’、SLj+1’、SLj+2’。
Resistance value adjustable element Ri,j' it is electrically connected at transistor Ti,j' and alignment BLi' between.Resistance value adjustable element Ri,j+1’
It is electrically connected at transistor Ti,j+1' and alignment alignment BLi' between.Resistance value adjustable element Ri,j+2' it is electrically connected at transistor
Ti,j+2' and alignment alignment BLi' between.
Via wordline WLj’、WLj+1’、WLj+2', transistor Ti,j’、Ti,j+1’、Ti,j+2' control terminal be applied conducting respectively
Voltage Vg1, Vg2, Vg3.Input voltage x ' is applied in alignment BLi'.In response to input voltage x ', cynapse cell S Pi,j’、
SPi,j+1’、SPi,j+2' can be respectively in line SLj’、SLj+1’、SLj+2' on generate corresponding output electric current.These output electric currents
Aggregation can be used to indicate a product item and result SUM ', be no better than the product of input voltage x ' and an equivalent weighted value w ', this
A little effect weighted value w ' systems are by cynapse cell S Pi,j’、SPi,j+1’、SPi,j+2' determine.
Through the size for being suitably designed conducting voltage Vg1, Vg2, Vg3, transistor T may makei,j’、Ti,j+1’、Ti,j+2’
Electrical conductivity σ 1 ', σ 2 ', σ 3 ' are presented respectively, wherein electrical conductivity σ 1 ', σ 2 ', σ 3 ' have respectively represented cynapse cell S Pi,j’、
SPi,j+1’、SPi,j+2' weighted value.The ratio σ 1 ': σ 2 ': σ 3 ' of electrical conductivity can be arbitrary, such as 1:2:4 or 1:1:1.
More precision in order to obtain, can be by resistance value variable element in low resistance when designing the weighted value of cynapse unit
Electrical conductivity (σ on) when state accounts for.For example, in order to through cynapse cell S Pi,j’、SPi,j+1’、SPi,j+2' realize
3 equivalent weighted value w ' can adjust the size of conducting voltage Vg1, Vg2, Vg3 to plan on: σ 2 ' // σ on: σ of σ 1 ' // σ
3 ' // σ on is about 1:2:4.
Embodiment three
According to embodiment three, the transistor in not homo-synapse unit has different breadth length ratios, and receives different size
Conducting voltage and different electrical conductivities is presented, to determine the weighted value of each cynapse unit.
Fig. 4 is the top view of the partial circuit layout of the class nerve computing device 400 according to depicted in embodiment three.Class mind
Being computed device 400 includes a plurality of alignment BLi"~BLi+3", a plurality of line SLj"~SLj+3", a plurality of wordline WLj"~WLj+3" with
And 4 × 4 cynapse units.Although Fig. 4 is only painted 4 × 4 cynapse units, it should be noted that class nerve computing device 400 may include
Any number of cynapse unit and combination.
Wordline WLj" and WLj+2" it is applied conducting voltage Vg1, wordline WLj+1" and WLj+3" it is applied conducting voltage
Vg2。
Couple alignment BLi" and BLi+1" cynapse unit receive input voltage x1.Couple alignment BLi+2”、BLi+3" cynapse
Unit receives input voltage x2.Collect line SLj" and SLj+1" on output electric current, long-pending item and result SUM1 " can be obtained.It receives
Collect line SLj+2" and SLj+3" on output electric current, long-pending item and result SUM2 " can be obtained
According to the example of Fig. 3, cynapse cell S Pi,j" in transistor and cynapse cell S Pi,j+1" in transistor have phase
Same breadth length ratio (=WD1/LH).Cynapse cell S Pi+1,j" in transistor and cynapse cell S Pi+1,j+1" in transistor have
Breadth length ratio (=WD2/LH).
Through the value for the breadth length ratio and conducting voltage for being suitably designed transistor, by cynapse cell S Pi,j”、
SPi,j+1”、SPi+1,j”、SPi+1,j+1" weighted value be formulated for w11 ", w12 ", w21 ", w22 " respectively.These weighted values w11 ",
W12 ", w21 ", w22 " value can be arbitrary, depend on cynapse cell S Pi,j”、SPi,j+1”、SPi+1,j”、SPi+1,j+1" in it is brilliant
The electrical conductivity of body pipe.In an example, conducting voltage Vg1 is less than Vg2, and breadth length ratio (WD1/LH) is less than (WD2/LH), so that
Ratio w11 ": w12 ": w21 ": w22 " between weighted value is about 1:2:4:8, to penetrate cynapse cell S Pi,j”、SPi,j+1”、
SPi+1,j”、SPi+1,j" realize binary system 4 (16 rank) equivalent weighted value w ".
In conclusion the present invention relates generally to a kind of class nerve calculating dress realized based on memory array hardware structure
It sets.According to embodiments of the present invention, the cynapse unit in class nerve computing device includes resistance value adjustable element and transistor, wherein
Cynapse unit weighted value to be presented is to be determined by the conducting degree size of transistor, and resistance value adjustable element is only as one
Switch element.Since the conducting degree of transistor can pass through the size for the conducting voltage being applied and/or the breadth length ratio (W/ of transistor
L) accurately regulate and control, therefore correctness and stability that class nerve computing device executes product item and operation can be effectively improved.In addition,
Due to the resistance value of resistance value adjustable element only need to merely be set to low-resistance state of value or high resistant state of value using as switch member
Part, therefore cooperate the adjustable transistor of conducting degree above-mentioned, it is the weight for being conducive to realize the more level of multidigit in product item and operation
Value.
Although the present invention has been disclosed by way of example above, it is not intended to limit the present invention..The neck of technology belonging to the present invention
Has usually intellectual in domain, without departing from the spirit and scope of the present invention, when can be used for a variety of modifications and variations.Therefore,
Subject to protection scope of the present invention ought be defined depending on appended claims range.
Claims (10)
1. a type nerve computing device, comprising:
A plurality of alignment；
A plurality of line；And
Multiple cynapse units, are located at the infall of these alignments Yu these lines, these cynapse units include:
One first cynapse unit, comprising:
One first resistance value adjustable element；And
One the first transistor is concatenated with the first resistance value adjustable element, the first transistor have one first breadth length ratio and to
Receive one first conducting voltage；And
One second cynapse unit, comprising:
One second resistance value adjustable element；And
One second transistor is concatenated with the second resistance value adjustable element, the second transistor have one second breadth length ratio and to
Receive one second conducting voltage；
Wherein first breadth length ratio is different with second breadth length ratio and/or the first conducting voltage is different with second conducting voltage.
2. class nerve computing device according to claim 1, wherein such neural computing device is to an input vector
A product item and operation are executed, these alignments are to receive the input vector, these lines are to export the input vector and a power
Weight vector one product item and as a result, these cynapse units to form the weight vectors；
The first resistance value adjustable element is by dualization to be configured to a low-resistance state of value or a high resistant state of value, this
Two resistance value adjustable elements are by dualization to be set to the low-resistance state of value or the high resistant state of value.
3. class nerve computing device according to claim 2, wherein the first transistor receive first conducting voltage and
The one first electrical conductivity system presented determines one first weighted value, which is contained in the weight vectors, second crystal
The one second electrical conductivity system that pipe receives second conducting voltage and presents determines one second weighted value, which is contained in
The weight vectors.
4. class nerve computing device according to claim 3, wherein first conducting voltage and second conducting voltage are big
It is small identical, and first breadth length ratio of the first transistor is different with second breadth length ratio of the second transistor；
The first cynapse unit and the second cynapse unit couple these alignments both wherein, and via a wordline receive this
One conducting voltage and second conducting voltage；
The n times side times that ratio between first electrical conductivity and second electrical conductivity is 2, wherein n is integer.
5. class nerve computing device according to claim 3, wherein first breadth length ratio of the first transistor and this
Second breadth length ratio of two-transistor is identical, and first conducting voltage is different with the size of second conducting voltage；
One of the first cynapse unit and the second cynapse unit coupling rank these alignments, and receiving via different wordline should
First conducting voltage and second conducting voltage；
The n times side times that ratio between first electrical conductivity and second electrical conductivity is 2, wherein n is integer.
6. class nerve computing device according to claim 3, wherein first breadth length ratio of the first transistor and this
Second breadth length ratio of two-transistor is different, and first conducting voltage is different with the size of second conducting voltage；
The first cynapse unit and the second cynapse unit are coupled in the two different lines lines and these lines of these alignments
Neither same line, and first conducting voltage and second conducting voltage are received respectively via different wordline；
The n times side times that ratio between first electrical conductivity and second electrical conductivity is 2, wherein n is integer.
7. a type nerve computing device is suitable for executing an input vector one product item and operation, such neural computing device
Include:
A plurality of alignment, to receive the input vector；
A plurality of line, to export a product item and result of the input vector and a weight vectors；And
Multiple cynapse units, are located at the infall of these alignments Yu these lines, these cynapse units are to form the power
Weight vector, and include:
One first cynapse unit, comprising:
One first resistance value adjustable element, to be configured to a low-resistance state of value or a high resistant state of value；And
One the first transistor is concatenated with the first resistance value adjustable element, when the first resistance value adjustable element is set at the low-resistance
State of value, one first weighted value of the one first electrical conductivity system representative of the first transistor the first cynapse unit, first power
Weight values are contained in the weight vectors；And
One second cynapse unit, comprising:
One second resistance value adjustable element, to be configured to the low-resistance state of value or the high resistant state of value；And
One second transistor is concatenated with the second resistance value adjustable element, when the second resistance value adjustable element is set at the low-resistance
State of value, one second weighted value of the one second electrical conductivity system representative of the second transistor the second cynapse unit, second power
Weight values are contained in the weight vectors.
8. class nerve computing device according to claim 7, wherein first conducting voltage and second conducting voltage are big
It is small identical, and first breadth length ratio of the first transistor is different with second breadth length ratio of the second transistor；
The first cynapse unit and the second cynapse unit couple these alignments both wherein, and via a wordline receive this
One conducting voltage and second conducting voltage.
9. class nerve computing device according to claim 7, wherein first breadth length ratio of the first transistor and this
Second breadth length ratio of two-transistor is identical, and first conducting voltage is different with the size of second conducting voltage；
One of the first cynapse unit and the second cynapse unit coupling rank these alignments, and receiving via different wordline should
First conducting voltage and second conducting voltage.
10. class nerve computing device according to claim 7, wherein first breadth length ratio of the first transistor and this
Second breadth length ratio of two-transistor is different, and first conducting voltage is different with the size of second conducting voltage；
The first cynapse unit and the second cynapse unit are coupled in two different lines lines and these lines in these alignments
Neither same line, and receive first conducting voltage and second conducting voltage respectively via different wordline.
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