TWI698810B - Neuromorphic computing device - Google Patents
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Description
本發明是有關於一種類神經計算裝置。 The present invention relates to a kind of neural computing device.
近來,利用記憶體陣列所實現的類神經計算裝置被提出。相較於利用處理器來執行類神經演算,此種類神經計算裝置具有低功耗的優點,並可應用至人工智慧晶片。 Recently, a neuro-like computing device implemented with a memory array has been proposed. Compared with the use of a processor to perform similar neural calculations, this type of neural calculation device has the advantage of low power consumption and can be applied to artificial intelligence chips.
類神經計算裝置通常包括多個突觸單元(synapse)。各個突觸單元對應於一權重值。當一輸入向量施加至類神經計算裝置,輸入向量將與關聯的一或多個突觸單元所對應的權重值所構成的權重向量相乘,以得到一積項和(sum of product)結果。積項和運算廣泛地使用於類神經裝置當中。 Neural computing devices usually include multiple synapse units (synapse). Each synaptic unit corresponds to a weight value. When an input vector is applied to the neuron-like computing device, the input vector is multiplied by a weight vector formed by the weight values corresponding to one or more associated synaptic units to obtain a sum of product result. Product term sum operations are widely used in neuro-like devices.
本發明係有關於一種類神經計算裝置。 The invention relates to a kind of neural computing device.
根據本發明之一方面,提出一種類神經計算裝置。類神經計算裝置包括數個第一神經元電路、數個第二神經元電路及數個突觸權重。第一神經元電路配置在第一神經元區域中。第二神經元電路配置在第二神經元區域中。突觸權重電性連接在第 一神經元電路與第二神經元電路之間,並配置在突觸區域中。第一神經元區域與第二神經元區域分別在突觸區域的相反側。 According to one aspect of the present invention, a neuro-like computing device is provided. The neuron-like computing device includes several first neuron circuits, several second neuron circuits and several synaptic weights. The first neuron circuit is configured in the first neuron area. The second neuron circuit is arranged in the second neuron area. The synaptic weight is electrically connected in the first A neuron circuit and a second neuron circuit are arranged in the synapse area. The first neuron area and the second neuron area are on opposite sides of the synapse area.
根據本發明之另一方面,提出一種類神經計算裝置。類神經計算裝置包括基底、數個突觸權重及數個神經元電路。突觸權重位在基底上。神經元電路電性連接至突觸權重,並配置在突觸權重朝向基底的一側。 According to another aspect of the present invention, a neuro-like computing device is provided. The neuronal computing device includes a base, several synaptic weights, and several neuron circuits. The synaptic weight is located on the base. The neuron circuit is electrically connected to the synapse weight and is arranged on the side of the synapse weight facing the base.
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉實施例,並配合所附圖式詳細說明如下: In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given in conjunction with the accompanying drawings to describe in detail as follows:
102:突觸區域 102: Synaptic area
102L、102M、102N、102T:突觸區域的側 102L, 102M, 102N, 102T: side of the synaptic area
104:第一神經元區域 104: The first neuron area
106:第二神經元區域 106: second neuron area
308:基底 308: Base
308S:上表面 308S: upper surface
620:堆疊結構 620: Stacked structure
622:絕緣層 622: insulating layer
624:絕緣膜 624: insulating film
626:接觸窗 626: contact window
R1、R2、R3、R4、R5、R6、R7、R8:單元電阻 R1, R2, R3, R4, R5, R6, R7, R8: unit resistance
RM1、RM2、RM3、RM4、RM5、RM6、RM7、RM8:電阻材料層 RM1, RM2, RM3, RM4, RM5, RM6, RM7, RM8: resistive material layer
D1、D2、D3:方向 D1, D2, D3: direction
KA1、KA2、KA3、KA4、KA5、KA6、KA7、KA9、KB1、KB2、KB3、KB4、KB5、KB6、KB7、KB9:導體元件 KA1, KA2, KA3, KA4, KA5, KA6, KA7, KA9, KB1, KB2, KB3, KB4, KB5, KB6, KB7, KB9: conductor components
NA1、NA2、NA3、NA4:第一神經元電路 NA1, NA2, NA3, NA4: the first neuron circuit
NB1、NB2、NB3、NB4、NB5、NB6、NB7、NB8:第二神經元電路 NB1, NB2, NB3, NB4, NB5, NB6, NB7, NB8: second neuron circuit
Sin:訊號輸入端 Sin: signal input terminal
Sout:訊號輸出端 Sout: signal output terminal
W1,1、W1,2、W1,3、W1,4、W1,5、W1,6、W1,7、W1,8、W2,1、W2,2、W2,3、W2,4、W2,5、W2,6、W2,7、W2,8、W3,1、W3,2、W3,3、W3,4、W4,1、W4,2:突觸權重 W 1,1 , W 1,2 , W 1,3 , W 1,4 , W 1,5 , W 1,6 , W 1,7 , W 1,8 , W 2,1 , W 2,2 , W 2,3 , W 2,4 , W 2,5 , W 2,6 , W 2,7 , W 2,8 , W 3,1 , W 3,2 , W 3,3 , W 3,4 , W 4,1 , W 4,2 : Synaptic weight
第1圖繪示根據一實施例的類神經計算裝置。 Figure 1 shows a neuro-like computing device according to an embodiment.
第2圖繪示根據一實施例的類神經計算裝置。 Figure 2 shows a neuron-like computing device according to an embodiment.
第3圖繪示根據一實施例的類神經計算裝置。 Figure 3 shows a neuro-like computing device according to an embodiment.
第4圖繪示根據一實施例的類神經計算裝置。 Figure 4 shows a neuro-like computing device according to an embodiment.
第5圖繪示根據一實施例的類神經計算裝置。 Fig. 5 shows a neural-like computing device according to an embodiment.
第6圖繪示根據一實施例的類神經計算裝置。 Fig. 6 shows a neural-like computing device according to an embodiment.
第7圖繪示根據一實施例的類神經計算裝置。 Figure 7 shows a neuro-like computing device according to an embodiment.
第8圖繪示一實施例之具有電阻結構之突觸權重的剖面示意圖。 FIG. 8 is a schematic cross-sectional view of a synaptic weight with a resistance structure according to an embodiment.
第9圖繪示一實施例之類神經計算裝置的上視圖。 Fig. 9 shows a top view of a neural computing device of an embodiment.
以下係以一些實施例做說明。須注意的是,本揭露 並非顯示出所有可能的實施例,未於本揭露提出的其他實施態樣也可能可以應用。再者,圖式上的尺寸比例並非按照實際產品等比例繪製。因此,說明書和圖示內容僅作敘述實施例之用,而非作為限縮本揭露保護範圍之用。另外,實施例中之敘述,例如細部結構、製程步驟和材料應用等等,僅為舉例說明之用,並非對本揭露欲保護之範圍做限縮。實施例之步驟和結構各之細節可在不脫離本揭露之精神和範圍內根據實際應用製程之需要而加以變化與修飾。以下是以相同/類似的符號表示相同/類似的元件做說明。 Some examples are described below. It should be noted that this disclosure Not all possible embodiments are shown, and other implementation aspects not mentioned in this disclosure may also be applicable. Furthermore, the size ratios in the drawings are not drawn in proportion to the actual products. Therefore, the contents of the description and illustrations are only used to describe the embodiments, not to limit the protection scope of the disclosure. In addition, the descriptions in the embodiments, such as detailed structure, process steps, material applications, etc., are for illustrative purposes only, and are not intended to limit the scope of the disclosure. The details of the steps and structures of the embodiments can be changed and modified according to the needs of the actual application process without departing from the spirit and scope of the present disclosure. In the following description, the same/similar symbols represent the same/similar elements.
請參照第1圖,其繪示根據一實施例的類神經計算裝置。類神經計算裝置可應用至人工智慧晶片,其例如可應用於電子設備,例如汽車、行動裝置例如手機等。類神經計算裝置包括突觸單元與神經元電路。神經元電路包括分別在不同神經元區域的第一神經元電路NAi與第二神經元電路NBj。突觸單元可透過導體電路電性連接在第一神經元電路與第二神經元電路之間。 Please refer to Figure 1, which illustrates a neuro-like computing device according to an embodiment. Neural computing devices can be applied to artificial intelligence chips, such as electronic devices such as automobiles, mobile devices such as mobile phones, and so on. Neural computing devices include synaptic units and neuron circuits. The neuron circuit includes a first neuron circuit NAi and a second neuron circuit NBj in different neuron regions. The synapse unit can be electrically connected between the first neuron circuit and the second neuron circuit through a conductor circuit.
實施例中,突觸單元係各包括突觸權重Wi,j。突觸權重Wi,j各包括訊號輸入端Sin及訊號輸出端Sout。來自第一神經元電路NAi的神經元訊號(例如電壓訊號Vi)可經過導體電路傳送至訊號輸入端Sin進入突觸權重Wi,j(例如電阻)轉換成權重訊號(例如根據歐姆定律轉換成的電流訊號Ij),然後權重訊號從訊號輸出端Sout輸出突觸權重Wi,j經過導體電路傳送至第二神經元 電路NBj進行感測及/或計算(例如以電流感測器感測電流訊號Ij,且/或利用計算裝置計算所有進入第二神經元電路NBj的電流訊號Ij的總和)中。此實施例中,訊號輸入端Sin與訊號輸出端Sout係分別位突觸權重Wi,j的相反側。舉例來說,一實施例中,突觸權重Wi,j包括電阻。一實施例中,訊號輸入端Sin為電阻的一端點,且訊號輸出端Sout為電阻的另一端點。一實施例中,電阻包括可變電阻。一實施例中,電阻包括具有3D陣列堆疊結構的電阻電路。但本揭露不限於此。第一神經元電路NAi的神經元訊號、突觸權重Wi,j與權重訊號可符合歐姆定律。突觸權重Wi,j可包括其它合適的權重元件。例如,另一實施例中,突觸權重Wi,j可包括電導,例如具有3D陣列堆疊結構的電導電路。神經元訊號可包括電流訊號。權重訊號可包括電壓訊號。 In an embodiment, the synaptic unit systems each include synaptic weights Wi ,j . The synapse weights W i and j each include a signal input terminal Sin and a signal output terminal Sout. The neuron signal from the first neuron circuit NAi (for example, the voltage signal Vi) can be sent to the signal input terminal Sin through the conductor circuit and enters the synapse weight Wi ,j (for example, resistance) to be converted into a weight signal (for example, into a weight signal according to Ohm's law)的current signal Ij), and then the weight signal is output from the signal output terminal Sout to the synapse weight Wi ,j through the conductor circuit and transmitted to the second neuron circuit NBj for sensing and/or calculation (for example, the current sensor is used to sense the current Signal Ij, and/or calculate the sum of all current signals Ij entering the second neuron circuit NBj) using a computing device. In this embodiment, the signal input terminal Sin and the signal output terminal Sout are respectively located on opposite sides of the synapse weights Wi ,j . For example, in one embodiment, the synaptic weights W i,j include resistance. In one embodiment, the signal input terminal Sin is one terminal of the resistor, and the signal output terminal Sout is the other terminal of the resistor. In one embodiment, the resistor includes a variable resistor. In an embodiment, the resistor includes a resistor circuit having a 3D array stack structure. But this disclosure is not limited to this. The neuron signal, synapse weight Wi ,j, and weight signal of the first neuron circuit NAi can conform to Ohm's law. The synapse weights Wi ,j may include other suitable weight elements. For example, in another embodiment, the synaptic weights W i,j may include conductance, such as a conductance circuit having a 3D array stack structure. The neuron signal may include a current signal. The weight signal may include a voltage signal.
此實施例中,第一神經元電路NAi包括第一神經元電路NA1(即i=1)、第一神經元電路NA2(即i=2)與第一神經元電路NA3(即i=3)。第二神經元電路NBj包括第二神經元電路NB1(即j=1)、第二神經元電路NB2(即j=2)、第二神經元電路NB3(即j=3)與第二神經元電路NB4(即j=4)。突觸權重Wi,j包括突觸權重W1,1至突觸權重W1,4、突觸權重W2,1至突觸權重W2,4、與突觸權重W3,1至突觸權重W3,4。其它實施例中,可視需求變換其它數目的第一神經元電路、及/或第二神經元電路、及/或突觸權重。 In this embodiment, the first neuron circuit NAi includes a first neuron circuit NA1 (ie i=1), a first neuron circuit NA2 (ie i=2), and a first neuron circuit NA3 (ie i=3) . The second neuron circuit NBj includes a second neuron circuit NB1 (ie j=1), a second neuron circuit NB2 (ie j=2), a second neuron circuit NB3 (ie j=3), and a second neuron circuit Circuit NB4 (ie j=4). The synapse weight W i,j includes synapse weight W 1,1 to synapse weight W 1,4 , synapse weight W 2,1 to synapse weight W 2,4 , and synapse weight W 3,1 to synapse weight Touch the weight W 3,4 . In other embodiments, other numbers of first neuron circuits, and/or second neuron circuits, and/or synapse weights can be changed as needed.
突觸權重Wi,j配置在突觸區域102中。第一神經元電路NAi配置在第一神經元區域104中。第二神經元電路NBj
配置在第二神經元區域106中。第一神經元電路NA1、第一神經元電路NA2與第一神經元電路NA3可沿著方向D1依序排列。第二神經元電路NB1、第二神經元電路NB2、第二神經元電路NB3與第二神經元電路NB4可沿著方向D1依序排列。突觸權重Wi,j可延伸在方向D3上。舉例來說,一實施例中,突觸權重Wi,j的電阻可延伸在方向D3上。一實施例中,第一神經元區域104與第二神經元區域106可分別配置在突觸區域102的不同側。例如,此實施例中,第一神經元區域104與第二神經元區域106可分別在突觸區域102的相反側。詳細而言,第一神經元區域104可配置在突觸區域102具有訊號輸入端Sin的側102M上。第二神經元區域106可配置在突觸區域102具有訊號輸出端Sout的側102N上。訊號輸入端Sin位在第一神經元電路NAi與訊號輸出端Sout之間。訊號輸出端Sout位在第二神經元電路NBj與訊號輸入端Sin之間。一實施例中,第一神經元區域104、第二神經元區域106與突觸區域102可配置在一基底(例如第5圖中所示的基底308)上,且彼此可不重疊。
The synapse weights W i,j are arranged in the
實施例中,突觸權重Wi,j可分成不同的突觸權重群組分別電性連接至第一神經元電路NAi的其中之一與第二神經元電路NBj的其中之一。 In an embodiment, the synaptic weights Wi ,j can be divided into different synaptic weight groups and are respectively electrically connected to one of the first neuron circuit NAi and one of the second neuron circuit NBj.
請參照第1圖,一實施例中,第一神經元電路NA1、第一神經元電路NA2與第一神經元電路NA3其中之一可電性連接至在方向D2上呈行(column)排列的第一群組突觸權重。在方向 D1上呈列(row)排列的第二群組突觸權重可電性連接至第二神經元電路NB1、第二神經元電路NB2、第二神經元電路NB3與第二神經元電路NB4其中之一。舉例來說,此實施例中,第一神經元電路NA1係電性連接至之突觸權重W1,1、突觸權重W1,2、突觸權重W1,3與突觸權重W1,4之第一行群組。第一神經元電路NA2係電性連接至突觸權重W2,1、突觸權重W2,2、突觸權重W2,3與突觸權重W2,4之第二行群組。第一神經元電路NA3係電性連接至突觸權重W3,1、突觸權重W3,2、突觸權重W3,3與突觸權重W3,4之第三行群組。在相同面(plane)之突觸權重W1,1、突觸權重W2,1、與突觸權重W3,1的第一列群組係電性連接至第二神經元電路NB1。在相同面之突觸權重W1,2、突觸權重W2,2、與突觸權重W3,2之第二列群組係電性連接至第二神經元電路NB2。在相同面之突觸權重W1,3、突觸權重W2,3、與突觸權重W3,3之第三列群組係電性連接至第二神經元電路NB3。在相同面之突觸權重W1,4、突觸權重W2,4、與突觸權重W3,4之第四列群組係電性連接至第二神經元電路NB4。一實施例中,舉例來說,突觸權重的間距可相同於第一神經元電路的間距。第二神經元電路的數量可相同於突觸權重的堆疊層數。但本揭露不限於此。 Please refer to Figure 1. In one embodiment, one of the first neuron circuit NA1, the first neuron circuit NA2, and the first neuron circuit NA3 can be electrically connected to columns arranged in the direction D2 The first group of synaptic weights. The second group of synaptic weights arranged in a row in the direction D1 can be electrically connected to the second neuron circuit NB1, the second neuron circuit NB2, the second neuron circuit NB3, and the second neuron circuit NB4 one of them. For example, in this embodiment, the first neuron circuit NA1 is electrically connected to the synapse weight W 1,1 , the synapse weight W 1,2 , the synapse weight W 1,3 and the synapse weight W 1 , The first line group of 4 . The first neuron circuit NA2 is electrically connected to the second row group of the synapse weight W 2,1 , the synapse weight W 2,2 , the synapse weight W 2,3 and the synapse weight W 2,4 . The first neuron circuit NA3 is electrically connected to the third row group of synapse weight W 3,1 , synapse weight W 3,2 , synapse weight W 3,3 and synapse weight W 3,4 . The first row group of synaptic weights W 1,1 , synaptic weights W 2,1 , and synaptic weights W 3,1 on the same plane is electrically connected to the second neuron circuit NB1. The second row group of synaptic weights W 1,2 , synaptic weights W 2,2 , and synaptic weights W 3,2 on the same plane is electrically connected to the second neuron circuit NB2. The third row group of synaptic weights W 1,3 , synaptic weights W 2,3 , and synaptic weights W 3,3 on the same plane is electrically connected to the second neuron circuit NB3. The fourth row group of synaptic weights W 1,4 , synaptic weights W 2,4 , and synaptic weights W 3,4 on the same plane is electrically connected to the second neuron circuit NB4. In an embodiment, for example, the interval of the synapse weights may be the same as the interval of the first neuron circuit. The number of second neuron circuits can be the same as the number of stacked layers of synapse weights. But this disclosure is not limited to this.
方向D1、方向D2與方向D3可彼此不同,例如為實質上互相垂直。一實施例中,舉例來說,方向D1可為Y方向,方向D2可為Z方向,方向D3可為X方向。 The directions D1, D2, and D3 may be different from each other, for example, are substantially perpendicular to each other. In an embodiment, for example, the direction D1 may be the Y direction, the direction D2 may be the Z direction, and the direction D3 may be the X direction.
其它實施例中,第一神經元區域104及/或第二神經
元區域106可配置在突觸區域102的下方,例如配置在突觸區域102朝向基底(例如第5圖中所示的基底308)的一側。舉例來說,一實施例中,如第2圖所示,第一神經元區域104的第一神經元電路NA1、第一神經元電路NA2與第一神經元電路NA3可配置在突觸區域102的下方,例如配置在突觸區域102朝向基底(例如第5圖中所示的基底308)的一側。第一神經元區域104可位在突觸區域102與基底(例如第5圖中所示的基底308)之間。另一實施例中,如第3圖所示,第二神經元區域106的第二神經元電路NB1、第二神經元電路NB2、第二神經元電路NB3與第二神經元電路NB4可配置在突觸區域102的下方,例如配置在突觸區域102朝向基底的一側。第二神經元區域106可位在突觸區域102與基底(例如第5圖中所示的基底308)之間。
In other embodiments, the
請參照第4圖繪示之類神經計算裝置,其與第1圖之類神經計算裝置的差異說明如下。第一神經元電路NAi包括第一神經元電路NA1與第一神經元電路NA2。第二神經元電路NBj可更包括依序排列在方向D1上的第二神經元電路NB5、第二神經元電路NB6、第二神經元電路NB7與第二神經元電路NB8。第二神經元電路NB1~NB4可配置在突觸區域102與第二神經元電路NB5~NB8之間。第二神經元電路NB1~NB4可配置交錯第二神經元電路NB5~NB8。突觸單元的突觸權重Wi,j包括第一行之突觸權重W1,1、突觸權重W1,2、突觸權重W1,3與突觸權重W1,4,第二行之突觸權重突觸權重W1,5、突觸權重W1,6、突觸權重W1,7
與突觸權重W1,8,第三行之突觸權重W2,1、突觸權重W2,2、突觸權重W2,3與突觸權重W2,4,及第四行之突觸權重W2,5、突觸權重W2,6、突觸權重W2,7與突觸權重W2,8。
Please refer to the neural computing device like that shown in Figure 4, and the difference between it and the neural computing device like that in Figure 1 is explained as follows. The first neuron circuit NAi includes a first neuron circuit NA1 and a first neuron circuit NA2. The second neuron circuit NBj may further include a second neuron circuit NB5, a second neuron circuit NB6, a second neuron circuit NB7, and a second neuron circuit NB8 that are sequentially arranged in the direction D1. The second neuron circuit NB1~NB4 can be arranged between the
一實施例中,第一神經元電路其中之一可電性連接至數行陣列排列的第一群組突觸權重。在方向D1上交替(alternate)排列的第二群組突觸權重可電性連接至第二神經元電路其中之一。舉例來說,此實施例中,第一神經元電路NA1係電性連接至第一行與第二行的突觸權重W1,1~W1,8之群組。第一神經元電路NA2係電性連接至第三行與第四行的突觸權重W2,1~W2,8之群組。交替排列的突觸權重W1,1與突觸權重W2,1之群組係電性連接至第二神經元電路NB1。突觸權重W1,2與突觸權重W2,2之群組係電性連接至第二神經元電路NB2。可依此類推其它突觸權重與第二神經元電路的連接關係。 In one embodiment, one of the first neuron circuits may be electrically connected to the first group of synaptic weights arranged in rows of arrays. The second group of synaptic weights alternately arranged in the direction D1 can be electrically connected to one of the second neuron circuits. For example, in this embodiment, the first neuron circuit NA1 is electrically connected to the group of synaptic weights W 1,1 to W 1,8 in the first row and the second row. The first neuron circuit NA2 is electrically connected to the synaptic weights W 2,1 to W 2,8 in the third and fourth rows. The group of alternately arranged synaptic weights W 1,1 and W 2,1 is electrically connected to the second neuron circuit NB1. The group of synapse weights W 1,2 and synapse weights W 2,2 is electrically connected to the second neuron circuit NB2. The connection relationship between other synaptic weights and the second neuron circuit can be deduced by analogy.
請參照第5圖繪示之類神經計算裝置,其與第1圖之類神經計算裝置的差異說明如下。第一神經元電路更包括第一神經元電路NA3與第一神經元電路NA4。第一神經元電路NA1至第一神經元電路NA4依序排列在方向D1上。第二神經元電路包括第二神經元電路NB1與第二神經元電路NB2。突觸單元的突觸權重包括排列在方向D2上的第一行突觸權重W1,1、突觸權重W1,2、突觸權重W2,1與突觸權重W2,2,及第二行之突觸權重W3,1、突觸權重W3,2、突觸權重W4,1與突觸權重W4,2。 Please refer to the neural computing device like that shown in Figure 5, and the difference between it and the neural computing device like that in Figure 1 is explained as follows. The first neuron circuit further includes a first neuron circuit NA3 and a first neuron circuit NA4. The first neuron circuit NA1 to the first neuron circuit NA4 are sequentially arranged in the direction D1. The second neuron circuit includes a second neuron circuit NB1 and a second neuron circuit NB2. The synaptic weight of the synaptic unit includes the first row of synaptic weights W 1,1 , synaptic weights W 1,2 , synaptic weights W 2,1 and synaptic weights W 2,2 arranged in the direction D2, and In the second row, the synapse weight W 3,1 , the synapse weight W 3,2 , the synapse weight W 4,1 and the synapse weight W 4,2 .
一實施例中,第一神經元電路其中之一可電性連接
至一行之突觸權重的一部份的第一群組突觸權重。數行在方向D2上交替排列的第二群組突觸權重可電性連接至第二神經元電路其中之一。舉例來說,此實施例中,第一神經元電路NA1係電性連接至第一行下部份的突觸權重W1,1與突觸權重W1,2之群組。第一神經元電路NA2係電性連接至第一行上部份的突觸權重W2,1與突觸權重W2,2之群組。可依此類推其它突觸權重與第一神經元電路的連接關係。在第一行與第二行交替排列的突觸權重W1,1、突觸權重W2,1、突觸權重W3,1與突觸權重W4,1之群組係電性連接至第二神經元電路NB1,突觸權重W1,2、突觸權重W2,2、突觸權重W3,2與突觸權重W4,2之群組係電性連接至第二神經元電路NB2。此實施例中,第一神經元區域104、第二神經元區域106與突觸區域102配置在基底308的上表面308S上,且彼此不重疊。
In one embodiment, one of the first neuron circuits may be electrically connected to the first group of synaptic weights as part of a row of synaptic weights. The rows of the second group of synaptic weights alternately arranged in the direction D2 can be electrically connected to one of the second neuron circuits. For example, in this embodiment, the first neuron circuit NA1 is electrically connected to the group of synaptic weights W 1,1 and W 1,2 in the lower part of the first row. The first neuron circuit NA2 is electrically connected to the group of synaptic weights W 2,1 and W 2,2 on the upper part of the first row. The connection relationship between other synaptic weights and the first neuron circuit can be deduced by analogy. The group of synapse weight W 1,1 , synapse weight W 2,1 , synapse weight W 3,1 and synapse weight W 4,1 alternately arranged in the first row and second row is electrically connected to The second neuron circuit NB1, the group of synapse weight W 1,2 , synapse weight W 2,2 , synapse weight W 3,2 and synapse weight W 4,2 is electrically connected to the second neuron Circuit NB2. In this embodiment, the
請參照第6圖繪示之類神經計算裝置,其與第1圖之類神經計算裝置的差異說明如下。突觸權重Wi,j(i=1、2、3;j=1、2、3、4)可延伸在方向D2上。舉例來說,一實施例中,突觸權重Wi,j包括電阻。突觸權重Wi,j的電阻可延伸在方向D2上。一實施例中,突觸權重Wi,j的訊號輸出端Sout及/或訊號輸入端Sin可位在突觸區域102非面向第一神經元區域104及/或第二神經元區域106的一側。例如,訊號輸出端Sout在突觸區域102的側102T處,訊號輸入端Sin位在相反於側102T的側102L處。舉例來說,突觸區域102的側102T可背向基底(例如第5圖所示的基底308)。突觸區域102的側102L可面向基底。
Please refer to the neural computing device like that shown in FIG. 6, and the difference between it and the neural computing device like that in FIG. 1 is explained as follows. The synapse weights W i , j (i=1, 2, 3; j=1, 2, 3, 4) may extend in the direction D2. For example, in one embodiment, the synaptic weights W i,j include resistance. The resistance of the synapse weights Wi ,j can extend in the direction D2. In one embodiment , the signal output terminal Sout and/or the signal input terminal Sin of the synapse weights W i,j may be located at one of the
一實施例中,第一神經元電路其中之一可電性連接至在方向D3上排列的第一群組突觸權重。在方向D1上排列的第二群組突觸權重可電性連接至第二神經元電路其中之一。舉例來說,此實施例中,第一神經元電路NA1係電性連接至之突觸權重W1,1、突觸權重W1,2、突觸權重W1,3與突觸權重W1,4之群組。第一神經元電路NA2係電性連接至突觸權重W2,1、突觸權重W2,2、突觸權重W2,3與突觸權重W2,4之群組。第一神經元電路NA3係電性連接至突觸權重W3,1、突觸權重W3,2、突觸權重W3,3與突觸權重W3,4之群組。突觸權重W1,1、突觸權重W2,1、與突觸權重W3,1之群組係電性連接至第二神經元電路NB1。突觸權重W1,2、突觸權重W2,2、與突觸權重W3,2之群組係電性連接至第二神經元電路NB2。可依此類推其它突觸權重與第二神經元電路之間的連接關係。 In an embodiment, one of the first neuron circuits may be electrically connected to the first group of synaptic weights arranged in the direction D3. The second group of synaptic weights arranged in the direction D1 can be electrically connected to one of the second neuron circuits. For example, in this embodiment, the first neuron circuit NA1 is electrically connected to the synapse weight W 1,1 , the synapse weight W 1,2 , the synapse weight W 1,3 and the synapse weight W 1 , Group of 4 . The first neuron circuit NA2 is electrically connected to the group of the synapse weight W 2,1 , the synapse weight W 2,2 , the synapse weight W 2,3 and the synapse weight W 2,4 . The first neuron circuit NA3 is electrically connected to the group of the synapse weight W 3,1 , the synapse weight W 3,2 , the synapse weight W 3,3 and the synapse weight W 3,4 . The group of synapse weight W 1,1 , synapse weight W 2,1 , and synapse weight W 3,1 is electrically connected to the second neuron circuit NB1. The group of synaptic weights W 1,2 , synaptic weights W 2,2 , and synaptic weights W 3,2 is electrically connected to the second neuron circuit NB2. The connection relationship between other synaptic weights and the second neuron circuit can be deduced by analogy.
但本揭露不限於此,另一實施例中,突觸權重的訊號輸入端Sin位在突觸區域102的側102T處,訊號輸出端Sout位在相反於側102T的側102L處。
However, the present disclosure is not limited to this. In another embodiment, the signal input terminal Sin of the synapse weight is located at the
其它實施例中,第一神經元區域104(第一神經元電路NAi)及第二神經元區域106(第二神經元電路NBj)其中一者可配置在突觸區域102(突觸權重Wi,j)朝向基底的一側102L,例如配置在突觸區域102(突觸權重Wi,j)與基底的上表面(例如第5圖所示之基底308的上表面308S)之間,或者配置在基底中,亦即配置在基底之上表面下方的基底部分中。
In other embodiments, the
請參照第7圖繪示之類神經計算裝置,其與第6圖之類神經計算裝置的差異說明如下。此實施例中,第一神經元區域104(第一神經元電路NAi)及第二神經元區域106(第二神經元電路NBj)可配置在突觸區域102(突觸權重Wi,j)朝向基底(例如第5圖所示的基底308)的側102L上,例如配置在突觸區域102(突觸權重Wi,j)與基底的上表面(例如第5圖所示之基底308的上表面308S)之間,或者配置在基底中,亦即配置在基底之上表面下方的基底部分中。
Please refer to the neural computing device like that shown in Figure 7. The difference between it and the neural computing device of Figure 6 is explained as follows. In this embodiment, the first neuron area 104 (first neuron circuit NAi) and the second neuron area 106 (second neuron circuit NBj) can be arranged in the synapse area 102 (synaptic weights Wi ,j ) On the
另一實施例中,第一神經元區域104(第一神經元電路NAi)配置在突觸區域102(突觸權重Wi,j)朝向基底的側102L上,例如配置在突觸區域102(突觸權重Wi,j)與基底的上表面之間,或者配置在基底中,而第二神經元區域106(第二神經元電路NBj)類似第6圖所示地配置在突觸區域102的側102N上。
In another embodiment, the first neuron area 104 (first neuron circuit NAi) is arranged on the
又一實施例中,第二神經元區域106(第二神經元電路NBj)配置在突觸區域102(突觸權重Wi,j)朝向基底的側102L上,例如配置在突觸區域102(突觸權重Wi,j)與基底的上表面之間,或者配置在基底中,而第一神經元區域104(第一神經元電路NAi配置在突觸區域102之相反於側102N的側102M上。
In another embodiment, the second neuron area 106 (second neuron circuit NBj) is arranged on the
請參照第8圖,其繪示一實施例之具有3D水平電阻結構之突觸權重的剖面示意圖。堆疊結構620可配置在基底308上。堆疊結構620可包括在實質垂直於基底308之上表面308S的方向D2上交替堆疊的絕緣層622與從基底308依序堆疊的第一層之
電阻材料層RM1、第二層之電阻材料層RM2...至第八層之電阻材料層RM8。
Please refer to FIG. 8, which illustrates a cross-sectional schematic diagram of synaptic weights with a 3D horizontal resistance structure according to an embodiment. The stack structure 620 may be disposed on the
絕緣膜624可形成在堆疊結構620中。導體元件KA1~KA8與導體元件KB1~KB8可形成在絕緣膜624的側表面上,並在方向D2上從堆疊結構620的上表面延伸穿過堆疊結構620並電性連接在電阻材料層RM1至電阻材料層RM8其中之一上。
The insulating
導體元件KA1與導體元件KB1可成對地接觸電阻材料層RM1在方向D3上的不同部分,以在電阻材料層RM1中定義出電性連接在導體元件KA1與導體元件KB1之間並延伸在方向D3上的單元電阻R1。電阻材料層RM1(或單元電阻R1)與導體元件KA1接觸的部分可視為突觸權重之電阻的訊號輸入端Sin,電阻材料層RM1(或單元電阻R1)與導體元件KB1接觸的部分可視為突觸權重之電阻的訊號輸出端Sout。導體元件KA8與導體元件KB8成對地接觸電阻材料層RM8在方向D3上的不同部分,以在電阻材料層RM8中定義出電性連接在導體元件KA8與導體元件KB8之間並延伸在方向D3上的單元電阻R8。電阻材料層RM8(或單元電阻R8)與導體元件KA8接觸的部分可視為突觸權重之電阻的訊號輸入端Sin,電阻材料層RM8(或單元電阻R8)與導體元件KB8接觸的部分可視為突觸權重之電阻的訊號輸出端Sout。可依此類推其它對導體元件分別在電阻材料層RM2~RM7中定義出的單元電阻R2~R7及其訊號輸入端Sin與訊號輸出端Sout。 The conductor element KA1 and the conductor element KB1 can be paired to contact different parts of the resistive material layer RM1 in the direction D3, so as to define an electrical connection in the resistive material layer RM1 between the conductor element KA1 and the conductor element KB1 and extend in the direction Cell resistance R1 on D3. The part of the resistive material layer RM1 (or unit resistance R1) in contact with the conductor element KA1 can be regarded as the signal input terminal Sin of the resistance of the synapse weight, and the part of the resistive material layer RM1 (or unit resistance R1) in contact with the conductor element KB1 can be regarded as a sudden The signal output terminal Sout of the resistance that touches the weight. The conductor element KA8 and the conductor element KB8 contact different parts of the resistive material layer RM8 in the direction D3 in pairs, so as to define an electrical connection in the resistive material layer RM8 between the conductor element KA8 and the conductor element KB8 and extend in the direction D3 On the cell resistance R8. The part of the resistive material layer RM8 (or unit resistance R8) in contact with the conductor element KA8 can be regarded as the signal input terminal Sin of the resistance of the synapse weight, and the part of the resistive material layer RM8 (or unit resistance R8) in contact with the conductor element KB8 can be regarded as a sudden The signal output terminal Sout of the resistance that touches the weight. It can be deduced by analogy for the unit resistors R2 to R7 and the signal input terminal Sin and the signal output terminal Sout defined in the resistive material layers RM2 to RM7 for other pairs of conductor elements.
接觸窗(contact via)626可配置在導體元件上。此實
施例中,接觸窗626配置在KA1~KA8與導體元件KB1~KB2、KB4及KB7~KB8上。導體層包括互相分開的輸入導體部EA1、輸出導體部EB1、輸出導體部EB2、輸出導體部EB3與輸出導體部EB4。輸入導體部EA1、輸出導體部EB1、輸出導體部EB2與輸出導體部EB4並可配置在接觸窗626上。輸入導體部EA1可透過接觸窗626電性連接至導體元件KA1~KA8。輸出導體部EB1可透過接觸窗626電性連接至導體元件KB1與導體元件KB2。輸出導體部EB2可透過接觸窗626電性連接至導體元件KB3與導體元件KB4。輸出導體部EB3並未電性連接接觸窗626,並可藉由形成在導體元件上的絕緣層(未顯示)電性隔離導體元件KB5與導體元件KB6。輸出導體部EB4可透過接觸窗626電性連接至導體元件KB7與導體元件KB8。
A contact via 626 may be arranged on the conductor element. This reality
In the embodiment, the
實施例中,電阻材料層的電阻值可大於導體元件、導體層與接觸窗的電阻值,從而,電阻電路的整體有效電阻可實質上由電阻材料層中的單元電阻造成。例如,導體元件、導體層與接觸窗可用作具有高導電性質的接觸件。電阻材料層的材料可包括但不限於半導體材料,例如N型半導體材料或P型半導體材料,例如以P、B、In、C、N雜質摻雜的多晶矽,或碳基材料(carbon based material),或金屬氮化物(metal nitride)例如TiN、TaN等,或其它合適的電阻材料。導體元件、導體層與接觸窗可包括但不限於鎢、鋁、銅、或其它具有高導電性質的合適金屬或金屬矽化物等導體材料。 In an embodiment, the resistance value of the resistive material layer may be greater than the resistance values of the conductor element, the conductor layer, and the contact window, so that the overall effective resistance of the resistive circuit may be substantially caused by the unit resistance in the resistive material layer. For example, conductor elements, conductor layers and contact windows can be used as contacts with high conductivity. The material of the resistive material layer may include, but is not limited to, semiconductor materials, such as N-type semiconductor materials or P-type semiconductor materials, such as polysilicon doped with P, B, In, C, and N impurities, or carbon-based materials. , Or metal nitride such as TiN, TaN, etc., or other suitable resistance materials. The conductor elements, conductor layers and contact windows may include but are not limited to conductive materials such as tungsten, aluminum, copper, or other suitable metals or metal silicides with high conductivity.
請參照第8圖,舉例來說,來自第一神經元電路NA1的神經元訊號可經過一導體電路(可包括輸入導體部EA1、與輸入導體部EA1電性連接的接觸窗626、或其它可能的導體電路元件)傳送至單元電阻R1與R2的訊號輸入端Sin進入由單元電阻R1與R2形成的並聯電阻轉換成權重訊號。然後,權重訊號從電阻的訊號輸出端Sout輸出經過另一導體電路(可包括輸出導體部EB1、與輸出導體部EB1電性連接的接觸窗626、或其它可能的導體電路元件)傳送至第二神經元電路NB1中。舉例來說,由單元電阻R1與R2造成的並聯電阻可用作如第1圖所示的突觸權重W1,1。可依此類推如第8圖所示之包括單元電阻R4的突觸權重W1,2(例如第1圖)、與包括由單元電阻R7與R8造成之並聯電阻的突觸權重W1,4(例如第1圖)。單元電阻R3並未為電性連接至輸出導體部EB2而為浮接,因此並未對突觸權重W1,2(例如第1圖)造成權重訊號。單元電阻R5與R6並未為電性連接至輸出導體部EB3而為浮接,因此並未對突觸權重W1,3(例如第1圖)造成權重訊號。來自第一神經元電路NA1的神經元訊號經過分別經過突觸權重W1,2、突觸權重W1,3與突觸權重W1,4轉換成權重訊號後再傳送至第二神經元電路NB2、第二神經元電路NB3與第二神經元電路NB4。
Referring to Figure 8, for example, the neuron signal from the first neuron circuit NA1 may pass through a conductor circuit (which may include an input conductor portion EA1, a
實施例中,可根據實際需求適當調變電阻材料層、導體元件、接觸窗與導體層的配置,從而獲得具有預期權重值的突觸權重。舉例來說,單元電阻的電阻值可依據對應的一對導體元件的形狀、相對距離、與電阻材料層接觸的面積、位置及/或電 阻材料層的尺寸、材料、形狀等可能影響有效電阻因子而定,使得不同層之單元電阻的電阻值可任意控制為相同或不同。舉例來說,電阻材料層可具有相同或不同的厚度。電阻材料層可具有相同或不同的材料性質。電阻材料層的材料可包括半導體材料,如矽材料例如多晶矽,或碳基材料(carbon based material),或金屬氮化物(metal nitride)例如TiN、TaN等,或其它合適的電阻材料。電阻材料層的材料可包括N型半導體材料或P型半導體材料。舉例來說,電阻材料層可具有相同或不同的摻雜情況,例如可具有相同或不同的摻雜雜質的種類,且/或具有相同或不同的摻雜濃度。摻雜雜質包括但不限於P、B、In、C、N等元素。 In the embodiment, the configuration of the resistive material layer, the conductor element, the contact window and the conductor layer can be appropriately adjusted according to actual needs, so as to obtain the synapse weight with the expected weight value. For example, the resistance value of the unit resistance can be based on the shape, relative distance, area, position and/or electrical contact of the corresponding pair of conductor elements. The size, material, shape, etc. of the resistive material layer may affect the effective resistance factor, so that the resistance value of the unit resistance of different layers can be arbitrarily controlled to be the same or different. For example, the resistive material layer may have the same or different thickness. The resistive material layer may have the same or different material properties. The material of the resistance material layer may include semiconductor materials, such as silicon materials such as polysilicon, or carbon based materials, or metal nitrides such as TiN, TaN, etc., or other suitable resistance materials. The material of the resistance material layer may include an N-type semiconductor material or a P-type semiconductor material. For example, the resistive material layer may have the same or different doping conditions, for example, may have the same or different doping impurity types, and/or have the same or different doping concentrations. Doping impurities include but are not limited to elements such as P, B, In, C, and N.
但本揭露不限於此。舉例來說,一實施例中,突觸權重W1,1~W1,4及/或其它突觸權重Wi,j可分成不同群組分別定義在不同的堆疊結構中。突觸權重可為平面陣列或3D陣列。其它實施例中,突觸權重可包括2D電阻或其它合適的突觸權重結構。舉例來說,突觸權重可包括電晶體。 But this disclosure is not limited to this. For example, in one embodiment, the synaptic weights W 1,1 to W 1,4 and/or other synaptic weights Wi ,j can be divided into different groups and defined in different stacked structures. The synapse weight can be a planar array or a 3D array. In other embodiments, the synaptic weight may include 2D resistance or other suitable synaptic weight structure. For example, the synaptic weights may include transistors.
第9圖繪示一實施例之類神經計算裝置的上視圖。在同一平面的電晶體各包括基底、源極、汲極、及閘極。例如電晶體T各包括基底308、源/汲極732S、源/汲極732D、及閘極734。電晶體T的源/汲極732S與源/汲極732D分別在閘極734相反側的基底308中。電晶體T'各包括基底308、源/汲極732S、源/汲極732D'、及閘極734'。電晶體T'的源/汲極732S與源/汲極732D'分別在閘極734'相反側的基底308中。電晶體T與電晶體T'可共
用源/汲極732S。一實施例中,源/汲極732S為源極,且源/汲極732D與源/汲極732D'為汲極。閘極734(或閘極734')可沿著方向D3延伸,從而在方向D3上排列的電晶體T(或電晶體T')係具有一共用的閘極。第一導電元件C1S可形成在源/汲極732S上。第一導電元件C1D可形成在源/汲極732D上。第一導電元件C1D'可形成在源/汲極732D'上。一實施例中,第一導電元件C1S第一導電元件C1D、與第一導電元件C1D'為接觸件(contact)。
Fig. 9 shows a top view of a neural computing device of an embodiment. The transistors on the same plane each include a substrate, a source, a drain, and a gate. For example, the transistors T each include a
實施例中,突觸權重具有由不同電晶體配置造成的不同權重值。一實施例中,突觸權重的權重值可由主動電晶體的數量決定。例如第9圖所示之突觸權重W1,1包括電晶體T1。電晶體T1的源/汲極104D'上配置有第一導電元件C1D',因此,電晶體T1可視為主動電晶體,且來自第一神經元電路NAi的神經元訊號可經由第一導電元件C1S進入電晶體T1轉換成權重訊號,然後權重訊號能在經過第一導電元件C1D'後傳送至第二神經元電路NBj。也就是說,突觸權重W1,1的權重值為一個電晶體T'(亦即用作主動電晶體的電晶體T1)造成。突觸權重W1,1的其餘電晶體的源/汲極732D與源/汲極732D'係為浮接(floating),因此並不會有訊號從這些電晶體傳送至第二神經元電路NBj,而視為虛置電晶體。可依此類推其它突觸權重的權重值。第一導電層M1D(第一導電層M1D')可沿著第方向D3延伸,並配置在第一導電元件C1D(第一導電元件C1D')及層間介電層(未顯示)上。一實施例中,第一導電元件C1D(第一導電元件C1D')與第一導電層M1D(第一
導電層M1D')可電性連接在主動電晶體的源/汲極732D(源/汲極732D')與第二神經元電路NBj之間。虛置電晶體的源/汲極732D(源/汲極732D')可藉由層間介電層(未顯示)隔離第一導電層M1D(第一導電層M1D'),從而電性絕緣於第二神經元電路NBj。此實施例中,如第9圖所具體顯示的在同一平面的54個電晶體定義出9個突觸權重。突觸權重各具有6個電晶體,即三個電晶體T與三個電晶體T'。一實施例中,如第9圖所示之突觸權重的權重值關係可為W1,1:W1,2:W1,j:W2,1:W2,2:W2,j:Wi,1:Wi,2:Wi,j=1:5:6:2:4:3:1:2:5。一實施例中,第一導電層M1S、第一導電層M1D與第一導電層M1D'可為第一層金屬層。
In an embodiment, the synapse weights have different weight values caused by different transistor configurations. In one embodiment, the weight value of the synapse weight may be determined by the number of active transistors. For example, the synaptic weight W 1,1 shown in Figure 9 includes a transistor T1. The source/drain 104D' of the transistor T1 is provided with a first conductive element C1D'. Therefore, the transistor T1 can be regarded as an active transistor, and the neuron signal from the first neuron circuit NAi can pass through the first conductive element C1S The input transistor T1 is converted into a weight signal, and then the weight signal can be transmitted to the second neuron circuit NBj after passing through the first conductive element C1D'. In other words, the weight value of the synapse weight W 1,1 is caused by a transistor T'(that is, the transistor T1 used as an active transistor). The source/
綜上所述,雖然本發明已以實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。 In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to those defined by the attached patent scope.
102:突觸區域 102: Synaptic area
102M、102N:突觸區域的側 102M, 102N: side of the synaptic area
104:第一神經元區域 104: The first neuron area
106:第二神經元區域 106: second neuron area
D1、D2、D3:方向 D1, D2, D3: direction
NA1、NA2、NA3:第一神經元電路 NA1, NA2, NA3: the first neuron circuit
NB1、NB2、NB3、NB4:第二神經元電路 NB1, NB2, NB3, NB4: second neuron circuit
Sin:訊號輸入端 Sin: signal input terminal
Sout:訊號輸出端 Sout: signal output terminal
W1,1、W1,2、W1,3、W1,4、W2,1、W2,2、W2,3、W2,4、W3,1、W3,2、W3,3、W3,4:突觸權重 W 1,1 , W 1,2 , W 1,3 , W 1,4 , W 2,1 , W 2,2 , W 2,3 , W 2,4 , W 3,1 , W 3,2 , W 3,3 , W 3,4 : synaptic weight
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