TWI698810B - Neuromorphic computing device - Google Patents

Abstract

A neuromorphic computing device includes first neural circuits, second neural circuits and synapse weights. The first neural circuits are disposed in a first neural region. The second neural circuits are disposed in a second neural region. The synapse weights are electrically connected between the first neural circuits and the second neural circuits, and disposed in a synapse region. The first neural region and the second neural region are on opposing sides of the synapse region respectively.

Description

Neural Computing Device

The present invention relates to a kind of neural computing device.

Recently, a neuro-like computing device implemented with a memory array has been proposed. Compared with the use of a processor to perform similar neural calculations, this type of neural calculation device has the advantage of low power consumption and can be applied to artificial intelligence chips.

Neural computing devices usually include multiple synapse units (synapse). Each synaptic unit corresponds to a weight value. When an input vector is applied to the neuron-like computing device, the input vector is multiplied by a weight vector formed by the weight values corresponding to one or more associated synaptic units to obtain a sum of product result. Product term sum operations are widely used in neuro-like devices.

The invention relates to a kind of neural computing device.

According to one aspect of the present invention, a neuro-like computing device is provided. The neuron-like computing device includes several first neuron circuits, several second neuron circuits and several synaptic weights. The first neuron circuit is configured in the first neuron area. The second neuron circuit is arranged in the second neuron area. The synaptic weight is electrically connected in the first A neuron circuit and a second neuron circuit are arranged in the synapse area. The first neuron area and the second neuron area are on opposite sides of the synapse area.

According to another aspect of the present invention, a neuro-like computing device is provided. The neuronal computing device includes a base, several synaptic weights, and several neuron circuits. The synaptic weight is located on the base. The neuron circuit is electrically connected to the synapse weight and is arranged on the side of the synapse weight facing the base.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given in conjunction with the accompanying drawings to describe in detail as follows:

102: Synaptic area

102L, 102M, 102N, 102T: side of the synaptic area

104: The first neuron area

106: second neuron area

308: Base

308S: upper surface

620: Stacked structure

622: insulating layer

624: insulating film

626: contact window

R1, R2, R3, R4, R5, R6, R7, R8: unit resistance

RM1, RM2, RM3, RM4, RM5, RM6, RM7, RM8: resistive material layer

D1, D2, D3: direction

KA1, KA2, KA3, KA4, KA5, KA6, KA7, KA9, KB1, KB2, KB3, KB4, KB5, KB6, KB7, KB9: conductor components

NA1, NA2, NA3, NA4: the first neuron circuit

NB1, NB2, NB3, NB4, NB5, NB6, NB7, NB8: second neuron circuit

Sin: signal input terminal

Sout: signal output terminal

W _1,1 , W _1,2 , W _1,3 , W _1,4 , W _1,5 , W _1,6 , W _1,7 , W _1,8 , W _2,1 , W _2,2 , W _2,3 , W _2,4 , W _2,5 , W _2,6 , W _2,7 , W _2,8 , W _3,1 , W _3,2 , W _3,3 , W _3,4 , W _4,1 , W _4,2 : Synaptic weight

Figure 1 shows a neuro-like computing device according to an embodiment.

Figure 2 shows a neuron-like computing device according to an embodiment.

Figure 3 shows a neuro-like computing device according to an embodiment.

Figure 4 shows a neuro-like computing device according to an embodiment.

Fig. 5 shows a neural-like computing device according to an embodiment.

Fig. 6 shows a neural-like computing device according to an embodiment.

Figure 7 shows a neuro-like computing device according to an embodiment.

FIG. 8 is a schematic cross-sectional view of a synaptic weight with a resistance structure according to an embodiment.

Fig. 9 shows a top view of a neural computing device of an embodiment.

Some examples are described below. It should be noted that this disclosure Not all possible embodiments are shown, and other implementation aspects not mentioned in this disclosure may also be applicable. Furthermore, the size ratios in the drawings are not drawn in proportion to the actual products. Therefore, the contents of the description and illustrations are only used to describe the embodiments, not to limit the protection scope of the disclosure. In addition, the descriptions in the embodiments, such as detailed structure, process steps, material applications, etc., are for illustrative purposes only, and are not intended to limit the scope of the disclosure. The details of the steps and structures of the embodiments can be changed and modified according to the needs of the actual application process without departing from the spirit and scope of the present disclosure. In the following description, the same/similar symbols represent the same/similar elements.

Please refer to Figure 1, which illustrates a neuro-like computing device according to an embodiment. Neural computing devices can be applied to artificial intelligence chips, such as electronic devices such as automobiles, mobile devices such as mobile phones, and so on. Neural computing devices include synaptic units and neuron circuits. The neuron circuit includes a first neuron circuit NAi and a second neuron circuit NBj in different neuron regions. The synapse unit can be electrically connected between the first neuron circuit and the second neuron circuit through a conductor circuit.

In an embodiment, the synaptic unit systems each include synaptic weights Wi _,j . The synapse weights W _{i and j} each include a signal input terminal Sin and a signal output terminal Sout. The neuron signal from the first neuron circuit NAi (for example, the voltage signal Vi) can be sent to the signal input terminal Sin through the conductor circuit and enters the synapse weight Wi _,j (for example, resistance) to be converted into a weight signal (for example, into a weight signal according to Ohm's law)的current signal Ij), and then the weight signal is output from the signal output terminal Sout to the synapse weight Wi _,j through the conductor circuit and transmitted to the second neuron circuit NBj for sensing and/or calculation (for example, the current sensor is used to sense the current Signal Ij, and/or calculate the sum of all current signals Ij entering the second neuron circuit NBj) using a computing device. In this embodiment, the signal input terminal Sin and the signal output terminal Sout are respectively located on opposite sides of the synapse weights Wi _,j . For example, in one embodiment, the synaptic weights W _i,j include resistance. In one embodiment, the signal input terminal Sin is one terminal of the resistor, and the signal output terminal Sout is the other terminal of the resistor. In one embodiment, the resistor includes a variable resistor. In an embodiment, the resistor includes a resistor circuit having a 3D array stack structure. But this disclosure is not limited to this. The neuron signal, synapse weight Wi _,j, and weight signal of the first neuron circuit NAi can conform to Ohm's law. The synapse weights Wi _,j may include other suitable weight elements. For example, in another embodiment, the synaptic weights W _i,j may include conductance, such as a conductance circuit having a 3D array stack structure. The neuron signal may include a current signal. The weight signal may include a voltage signal.

In this embodiment, the first neuron circuit NAi includes a first neuron circuit NA1 (ie i=1), a first neuron circuit NA2 (ie i=2), and a first neuron circuit NA3 (ie i=3) . The second neuron circuit NBj includes a second neuron circuit NB1 (ie j=1), a second neuron circuit NB2 (ie j=2), a second neuron circuit NB3 (ie j=3), and a second neuron circuit Circuit NB4 (ie j=4). The synapse weight W _i,j includes synapse weight W _1,1 to synapse weight W _1,4 , synapse weight W _2,1 to synapse weight W _2,4 , and synapse weight W _3,1 to synapse weight Touch the weight W _3,4 . In other embodiments, other numbers of first neuron circuits, and/or second neuron circuits, and/or synapse weights can be changed as needed.

The synapse weights W _{i,j are} arranged in the synapse area 102. The first neuron circuit NAi is arranged in the first neuron area 104. The second neuron circuit NBj is arranged in the second neuron area 106. The first neuron circuit NA1, the first neuron circuit NA2, and the first neuron circuit NA3 may be arranged in order along the direction D1. The second neuron circuit NB1, the second neuron circuit NB2, the second neuron circuit NB3, and the second neuron circuit NB4 may be sequentially arranged along the direction D1. The synapse weights W _i,j may extend in the direction D3. For example, in one embodiment _, the resistance of the synapse weights W _i,j may extend in the direction D3. In an embodiment, the first neuron area 104 and the second neuron area 106 may be arranged on different sides of the synapse area 102, respectively. For example, in this embodiment, the first neuron area 104 and the second neuron area 106 may be on opposite sides of the synapse area 102, respectively. In detail, the first neuron region 104 can be disposed on the side 102M of the synapse region 102 having the signal input terminal Sin. The second neuron region 106 can be arranged on the side 102N of the synapse region 102 having the signal output terminal Sout. The signal input terminal Sin is located between the first neuron circuit NAi and the signal output terminal Sout. The signal output terminal Sout is located between the second neuron circuit NBj and the signal input terminal Sin. In an embodiment, the first neuron area 104, the second neuron area 106, and the synapse area 102 may be disposed on a substrate (for example, the substrate 308 shown in FIG. 5), and may not overlap each other.

In an embodiment, the synaptic weights Wi _,j can be divided into different synaptic weight groups and are respectively electrically connected to one of the first neuron circuit NAi and one of the second neuron circuit NBj.

Please refer to Figure 1. In one embodiment, one of the first neuron circuit NA1, the first neuron circuit NA2, and the first neuron circuit NA3 can be electrically connected to columns arranged in the direction D2 The first group of synaptic weights. The second group of synaptic weights arranged in a row in the direction D1 can be electrically connected to the second neuron circuit NB1, the second neuron circuit NB2, the second neuron circuit NB3, and the second neuron circuit NB4 one of them. For example, in this embodiment, the first neuron circuit NA1 is electrically connected to the synapse weight W _1,1 , the synapse weight W _1,2 , the synapse weight W _1,3 and the synapse weight W _{1 ,} The first line group of ₄ . The first neuron circuit NA2 is electrically connected to the second row group of the synapse weight W _2,1 , the synapse weight W _2,2 , the synapse weight W _2,3 and the synapse weight W _2,4 . The first neuron circuit NA3 is electrically connected to the third row group of synapse weight W _3,1 , synapse weight W _3,2 , synapse weight W _3,3 and synapse weight W _3,4 . The first row group of synaptic weights W _1,1 , synaptic weights W _2,1 , and synaptic weights W _3,1 on the same plane is electrically connected to the second neuron circuit NB1. The second row group of synaptic weights W _1,2 , synaptic weights W _2,2 , and synaptic weights W _3,2 on the same plane is electrically connected to the second neuron circuit NB2. The third row group of synaptic weights W _1,3 , synaptic weights W _2,3 , and synaptic weights W _3,3 on the same plane is electrically connected to the second neuron circuit NB3. The fourth row group of synaptic weights W _1,4 , synaptic weights W _2,4 , and synaptic weights W _3,4 on the same plane is electrically connected to the second neuron circuit NB4. In an embodiment, for example, the interval of the synapse weights may be the same as the interval of the first neuron circuit. The number of second neuron circuits can be the same as the number of stacked layers of synapse weights. But this disclosure is not limited to this.

The directions D1, D2, and D3 may be different from each other, for example, are substantially perpendicular to each other. In an embodiment, for example, the direction D1 may be the Y direction, the direction D2 may be the Z direction, and the direction D3 may be the X direction.

In other embodiments, the first neuron region 104 and/or the second neuron The meta-region 106 may be arranged below the synaptic region 102, for example, on the side of the synaptic region 102 facing the base (for example, the base 308 shown in FIG. 5). For example, in an embodiment, as shown in FIG. 2, the first neuron circuit NA1, the first neuron circuit NA2, and the first neuron circuit NA3 of the first neuron area 104 may be arranged in the synapse area 102 Below, for example, it is arranged on the side of the synapse region 102 facing the substrate (for example, the substrate 308 shown in FIG. 5). The first neuron area 104 may be located between the synapse area 102 and the base (for example, the base 308 shown in FIG. 5). In another embodiment, as shown in Figure 3, the second neuron circuit NB1, the second neuron circuit NB2, the second neuron circuit NB3, and the second neuron circuit NB4 of the second neuron area 106 can be configured in The underside of the synapse area 102 is, for example, arranged on the side of the synapse area 102 facing the base. The second neuron region 106 may be located between the synapse region 102 and the base (for example, the base 308 shown in FIG. 5).

Please refer to the neural computing device like that shown in Figure 4, and the difference between it and the neural computing device like that in Figure 1 is explained as follows. The first neuron circuit NAi includes a first neuron circuit NA1 and a first neuron circuit NA2. The second neuron circuit NBj may further include a second neuron circuit NB5, a second neuron circuit NB6, a second neuron circuit NB7, and a second neuron circuit NB8 that are sequentially arranged in the direction D1. The second neuron circuit NB1~NB4 can be arranged between the synapse area 102 and the second neuron circuit NB5~NB8. The second neuron circuits NB1~NB4 can be configured with interleaved second neuron circuits NB5~NB8. The synaptic weights Wi _{,j of the} synaptic unit include the first row of synaptic weights W _1,1 , synaptic weights W _1,2 , synaptic weights W _1,3 and synaptic weights W _1,4 , the second row The synapse weights of the row are synaptic weights W _1,5 , synaptic weights W _1,6 , synaptic weights W _1,7 and synaptic weights W _1,8 , synaptic weights W _2,1 , synapses in the third row Synapse weight W _2,2 , synapse weight W _2,3 and synapse weight W _2,4 , and the fourth row of synapse weight W _2,5 , synapse weight W _2,6 , synapse weight W _{2, 7} and the synapse weight W _2,8 .

In one embodiment, one of the first neuron circuits may be electrically connected to the first group of synaptic weights arranged in rows of arrays. The second group of synaptic weights alternately arranged in the direction D1 can be electrically connected to one of the second neuron circuits. For example, in this embodiment, the first neuron circuit NA1 is electrically connected to the group of synaptic weights W _1,1 to W _{1,8 in} the first row and the second row. The first neuron circuit NA2 is electrically connected to the synaptic weights W _2,1 to W _{2,8 in} the third and fourth rows. The group of alternately arranged synaptic weights W _1,1 and W _2,1 is electrically connected to the second neuron circuit NB1. The group of synapse weights W _1,2 and synapse weights W _2,2 is electrically connected to the second neuron circuit NB2. The connection relationship between other synaptic weights and the second neuron circuit can be deduced by analogy.

Please refer to the neural computing device like that shown in Figure 5, and the difference between it and the neural computing device like that in Figure 1 is explained as follows. The first neuron circuit further includes a first neuron circuit NA3 and a first neuron circuit NA4. The first neuron circuit NA1 to the first neuron circuit NA4 are sequentially arranged in the direction D1. The second neuron circuit includes a second neuron circuit NB1 and a second neuron circuit NB2. The synaptic weight of the synaptic unit includes the first row of synaptic weights W _1,1 , synaptic weights W _1,2 , synaptic weights W _2,1 and synaptic weights W _2,2 arranged in the direction D2, and In the second row, the synapse weight W _3,1 , the synapse weight W _3,2 , the synapse weight W _4,1 and the synapse weight W _4,2 .

In one embodiment, one of the first neuron circuits may be electrically connected to the first group of synaptic weights as part of a row of synaptic weights. The rows of the second group of synaptic weights alternately arranged in the direction D2 can be electrically connected to one of the second neuron circuits. For example, in this embodiment, the first neuron circuit NA1 is electrically connected to the group of synaptic weights W _1,1 and W _{1,2 in} the lower part of the first row. The first neuron circuit NA2 is electrically connected to the group of synaptic weights W _2,1 and W _2,2 on the upper part of the first row. The connection relationship between other synaptic weights and the first neuron circuit can be deduced by analogy. The group of synapse weight W _1,1 , synapse weight W _2,1 , synapse weight W _3,1 and synapse weight W _4,1 alternately arranged in the first row and second row is electrically connected to The second neuron circuit NB1, the group of synapse weight W _1,2 , synapse weight W _2,2 , synapse weight W _3,2 and synapse weight W _4,2 is electrically connected to the second neuron Circuit NB2. In this embodiment, the first neuron area 104, the second neuron area 106, and the synapse area 102 are disposed on the upper surface 308S of the base 308 and do not overlap with each other.

Please refer to the neural computing device like that shown in FIG. 6, and the difference between it and the neural computing device like that in FIG. 1 is explained as follows. The synapse weights W _i , _j (i=1, 2, 3; j=1, 2, 3, 4) may extend in the direction D2. For example, in one embodiment, the synaptic weights W _i,j include resistance. The resistance of the synapse weights Wi _,j can extend in the direction D2. In one embodiment _, the signal output terminal Sout and/or the signal input terminal Sin of the synapse weights W _i,j may be located at one of the synaptic region 102 that does not face the first neuron region 104 and/or the second neuron region 106 side. For example, the signal output terminal Sout is located at the side 102T of the synapse region 102, and the signal input terminal Sin is located at the side 102L opposite to the side 102T. For example, the side 102T of the synapse region 102 may face away from the substrate (such as the substrate 308 shown in FIG. 5). The side 102L of the synapse region 102 may face the substrate.

In an embodiment, one of the first neuron circuits may be electrically connected to the first group of synaptic weights arranged in the direction D3. The second group of synaptic weights arranged in the direction D1 can be electrically connected to one of the second neuron circuits. For example, in this embodiment, the first neuron circuit NA1 is electrically connected to the synapse weight W _1,1 , the synapse weight W _1,2 , the synapse weight W _1,3 and the synapse weight W _{1 ,} Group of ₄ . The first neuron circuit NA2 is electrically connected to the group of the synapse weight W _2,1 , the synapse weight W _2,2 , the synapse weight W _2,3 and the synapse weight W _2,4 . The first neuron circuit NA3 is electrically connected to the group of the synapse weight W _3,1 , the synapse weight W _3,2 , the synapse weight W _3,3 and the synapse weight W _3,4 . The group of synapse weight W _1,1 , synapse weight W _2,1 , and synapse weight W _3,1 is electrically connected to the second neuron circuit NB1. The group of synaptic weights W _1,2 , synaptic weights W _2,2 , and synaptic weights W _3,2 is electrically connected to the second neuron circuit NB2. The connection relationship between other synaptic weights and the second neuron circuit can be deduced by analogy.

However, the present disclosure is not limited to this. In another embodiment, the signal input terminal Sin of the synapse weight is located at the side 102T of the synapse region 102, and the signal output terminal Sout is located at the side 102L opposite to the side 102T.

In other embodiments, the first region 104 neurons (NAi first neuron circuit) region 106 and the second neuron (neuron circuit NBJ second) one of which may be disposed in the region of 102 synaptic (synapse weights W _i , _j ) The side 102L facing the substrate, for example, is arranged between the synapse area 102 (synaptic weights Wi _,j ) and the upper surface of the substrate (for example, the upper surface 308S of the substrate 308 shown in Figure 5), or It is arranged in the substrate, that is, in the portion of the substrate below the upper surface of the substrate.

Please refer to the neural computing device like that shown in Figure 7. The difference between it and the neural computing device of Figure 6 is explained as follows. In this embodiment, the first neuron area 104 (first neuron circuit NAi) and the second neuron area 106 (second neuron circuit NBj) can be arranged in the synapse area 102 (synaptic weights Wi _,j ) On the side 102L facing the substrate (such as the substrate 308 shown in Figure 5), for example, the synapse region 102 (synaptic weights Wi _,j ) and the upper surface of the substrate (such as the substrate 308 shown in Figure 5) Between the upper surface 308S), or in the substrate, that is, in the portion of the substrate below the upper surface of the substrate.

In another embodiment, the first neuron area 104 (first neuron circuit NAi) is arranged on the side 102L of the synapse area 102 (synaptic weights Wi _,j ) facing the base, for example, arranged on the synapse area 102 ( Between the synapse weights Wi _,j ) and the upper surface of the base, or is arranged in the base, and the second neuron area 106 (second neuron circuit NBj) is arranged in the synapse area 102 similar to that shown in Figure 6 On the side 102N.

In another embodiment, the second neuron area 106 (second neuron circuit NBj) is arranged on the side 102L of the synapse area 102 (synaptic weights Wi _,j ) facing the base, for example, it is arranged on the synapse area 102 ( Between the synapse weight Wi _,j ) and the upper surface of the base, or arranged in the base, and the first neuron area 104 (the first neuron circuit NAi is arranged at the side 102M of the synapse area 102 opposite to the side 102N) on.

Please refer to FIG. 8, which illustrates a cross-sectional schematic diagram of synaptic weights with a 3D horizontal resistance structure according to an embodiment. The stack structure 620 may be disposed on the substrate 308. The stacked structure 620 may include one of insulating layers 622 alternately stacked in a direction D2 substantially perpendicular to the upper surface 308S of the substrate 308 and a first layer sequentially stacked from the substrate 308 The resistive material layer RM1, the second resistive material layer RM2... to the eighth resistive material layer RM8.

The insulating film 624 may be formed in the stacked structure 620. The conductor elements KA1~KA8 and the conductor elements KB1~KB8 may be formed on the side surface of the insulating film 624, and extend from the upper surface of the stack structure 620 through the stack structure 620 in the direction D2 and are electrically connected to the resistive material layer RM1 to RM1. On one of the resistive material layers RM8.

The conductor element KA1 and the conductor element KB1 can be paired to contact different parts of the resistive material layer RM1 in the direction D3, so as to define an electrical connection in the resistive material layer RM1 between the conductor element KA1 and the conductor element KB1 and extend in the direction Cell resistance R1 on D3. The part of the resistive material layer RM1 (or unit resistance R1) in contact with the conductor element KA1 can be regarded as the signal input terminal Sin of the resistance of the synapse weight, and the part of the resistive material layer RM1 (or unit resistance R1) in contact with the conductor element KB1 can be regarded as a sudden The signal output terminal Sout of the resistance that touches the weight. The conductor element KA8 and the conductor element KB8 contact different parts of the resistive material layer RM8 in the direction D3 in pairs, so as to define an electrical connection in the resistive material layer RM8 between the conductor element KA8 and the conductor element KB8 and extend in the direction D3 On the cell resistance R8. The part of the resistive material layer RM8 (or unit resistance R8) in contact with the conductor element KA8 can be regarded as the signal input terminal Sin of the resistance of the synapse weight, and the part of the resistive material layer RM8 (or unit resistance R8) in contact with the conductor element KB8 can be regarded as a sudden The signal output terminal Sout of the resistance that touches the weight. It can be deduced by analogy for the unit resistors R2 to R7 and the signal input terminal Sin and the signal output terminal Sout defined in the resistive material layers RM2 to RM7 for other pairs of conductor elements.

A contact via 626 may be arranged on the conductor element. This reality In the embodiment, the contact windows 626 are arranged on KA1~KA8 and the conductor elements KB1~KB2, KB4, and KB7~KB8. The conductor layer includes an input conductor portion EA1, an output conductor portion EB1, an output conductor portion EB2, an output conductor portion EB3, and an output conductor portion EB4 that are separated from each other. The input conductor portion EA1, the output conductor portion EB1, the output conductor portion EB2, and the output conductor portion EB4 can be arranged on the contact window 626. The input conductor part EA1 can be electrically connected to the conductor elements KA1 to KA8 through the contact window 626. The output conductor portion EB1 can be electrically connected to the conductor element KB1 and the conductor element KB2 through the contact window 626. The output conductor portion EB2 can be electrically connected to the conductor element KB3 and the conductor element KB4 through the contact window 626. The output conductor portion EB3 is not electrically connected to the contact window 626, and can electrically isolate the conductor element KB5 and the conductor element KB6 by an insulating layer (not shown) formed on the conductor element. The output conductor portion EB4 can be electrically connected to the conductor element KB7 and the conductor element KB8 through the contact window 626.

In an embodiment, the resistance value of the resistive material layer may be greater than the resistance values of the conductor element, the conductor layer, and the contact window, so that the overall effective resistance of the resistive circuit may be substantially caused by the unit resistance in the resistive material layer. For example, conductor elements, conductor layers and contact windows can be used as contacts with high conductivity. The material of the resistive material layer may include, but is not limited to, semiconductor materials, such as N-type semiconductor materials or P-type semiconductor materials, such as polysilicon doped with P, B, In, C, and N impurities, or carbon-based materials. , Or metal nitride such as TiN, TaN, etc., or other suitable resistance materials. The conductor elements, conductor layers and contact windows may include but are not limited to conductive materials such as tungsten, aluminum, copper, or other suitable metals or metal silicides with high conductivity.

Referring to Figure 8, for example, the neuron signal from the first neuron circuit NA1 may pass through a conductor circuit (which may include an input conductor portion EA1, a contact window 626 electrically connected to the input conductor portion EA1, or other possibilities The conductor circuit element) sent to the signal input terminal Sin of the unit resistors R1 and R2 enters the parallel resistance formed by the unit resistors R1 and R2 and is converted into a weight signal. Then, the weight signal is outputted from the signal output terminal Sout of the resistance through another conductor circuit (which may include the output conductor portion EB1, the contact window 626 electrically connected to the output conductor portion EB1, or other possible conductor circuit elements) to be transmitted to the second Neuron circuit NB1. For example, the parallel resistance caused by the unit resistances R1 and R2 can be used as the synapse weight W _1,1 as shown in Figure ₁ . It can be deduced by analogy as shown in Fig. 8 including the synaptic weight W _{1,2 of the} unit resistance R4 (for example, Fig. 1), and the synaptic weight W _1,4 including the parallel resistance caused by the unit resistance R7 and R8 (For example, Figure 1). The unit resistance R3 is not electrically connected to the output conductor portion EB2 but is floating, and therefore does not cause a weight signal to the synapse weight W _1,2 (for example, FIG. 1). The unit resistors R5 and R6 are not electrically connected to the output conductor portion EB3 but are floating, and therefore do not cause a weight signal to the synapse weight W _1,3 (for example, FIG. 1). The neuron signal from the first neuron circuit NA1 is converted into a weight signal after synaptic weights W _1,2 , synaptic weights W _1,3, and synaptic weights W _1,4, and then sent to the second neuron circuit NB2, the second neuron circuit NB3 and the second neuron circuit NB4.

In the embodiment, the configuration of the resistive material layer, the conductor element, the contact window and the conductor layer can be appropriately adjusted according to actual needs, so as to obtain the synapse weight with the expected weight value. For example, the resistance value of the unit resistance can be based on the shape, relative distance, area, position and/or electrical contact of the corresponding pair of conductor elements. The size, material, shape, etc. of the resistive material layer may affect the effective resistance factor, so that the resistance value of the unit resistance of different layers can be arbitrarily controlled to be the same or different. For example, the resistive material layer may have the same or different thickness. The resistive material layer may have the same or different material properties. The material of the resistance material layer may include semiconductor materials, such as silicon materials such as polysilicon, or carbon based materials, or metal nitrides such as TiN, TaN, etc., or other suitable resistance materials. The material of the resistance material layer may include an N-type semiconductor material or a P-type semiconductor material. For example, the resistive material layer may have the same or different doping conditions, for example, may have the same or different doping impurity types, and/or have the same or different doping concentrations. Doping impurities include but are not limited to elements such as P, B, In, C, and N.

But this disclosure is not limited to this. For example, in one embodiment, the synaptic weights W _1,1 to W _1,4 and/or other synaptic weights Wi _,j can be divided into different groups and defined in different stacked structures. The synapse weight can be a planar array or a 3D array. In other embodiments, the synaptic weight may include 2D resistance or other suitable synaptic weight structure. For example, the synaptic weights may include transistors.

Fig. 9 shows a top view of a neural computing device of an embodiment. The transistors on the same plane each include a substrate, a source, a drain, and a gate. For example, the transistors T each include a substrate 308, a source/drain 732S, a source/drain 732D, and a gate 734. The source/drain 732S and the source/drain 732D of the transistor T are respectively in the substrate 308 on the opposite side of the gate 734. The transistors T'each include a substrate 308, a source/drain electrode 732S, a source/drain electrode 732D', and a gate electrode 734'. The source/drain 732S and the source/drain 732D' of the transistor T'are respectively in the substrate 308 on the opposite side of the gate 734'. Transistor T and Transistor T'can be shared Use source/drain 732S. In one embodiment, the source/drain 732S is a source, and the source/drain 732D and the source/drain 732D' are drains. The gate 734 (or the gate 734') can extend along the direction D3, so that the transistors T (or the transistors T') arranged in the direction D3 have a common gate. The first conductive element C1S may be formed on the source/drain electrode 732S. The first conductive element C1D may be formed on the source/drain electrode 732D. The first conductive element C1D' may be formed on the source/drain 732D'. In an embodiment, the first conductive element C1S, the first conductive element C1D, and the first conductive element C1D′ are contacts.

In an embodiment, the synapse weights have different weight values caused by different transistor configurations. In one embodiment, the weight value of the synapse weight may be determined by the number of active transistors. For example, the synaptic weight W _1,1 shown in Figure 9 includes a transistor T1. The source/drain 104D' of the transistor T1 is provided with a first conductive element C1D'. Therefore, the transistor T1 can be regarded as an active transistor, and the neuron signal from the first neuron circuit NAi can pass through the first conductive element C1S The input transistor T1 is converted into a weight signal, and then the weight signal can be transmitted to the second neuron circuit NBj after passing through the first conductive element C1D'. In other words, the weight value of the synapse weight W _1,1 is caused by a transistor T'(that is, the transistor T1 used as an active transistor). The source/drain 732D and source/drain 732D' of the remaining transistors with the synapse weight W _1,1 are floating, so no signal is transmitted from these transistors to the second neuron circuit NBj , And regarded as a dummy transistor. The weight values of other synaptic weights can be deduced by analogy. The first conductive layer M1D (first conductive layer M1D′) may extend along the first direction D3 and is disposed on the first conductive element C1D (first conductive element C1D′) and the interlayer dielectric layer (not shown). In one embodiment, the first conductive element C1D (first conductive element C1D') and the first conductive layer M1D (first conductive layer M1D') can be electrically connected to the source/drain 732D (source/drain) of the active transistor. Between the pole 732D') and the second neuron circuit NBj. The source/drain 732D (source/drain 732D') of the dummy transistor can be isolated from the first conductive layer M1D (first conductive layer M1D') by an interlayer dielectric layer (not shown), thereby being electrically insulated from the first conductive layer M1D Two neuron circuit NBj. In this embodiment, 54 transistors on the same plane as shown in FIG. 9 define 9 synaptic weights. The synapse weights each have 6 transistors, that is, three transistors T and three transistors T'. In an embodiment, the weight value relationship of the synapse weights shown in Figure 9 may be W _1,1 : W _1,2 : W _1,j : W _2,1 : W _2,2 : W _2,j : W _i,1 :W _i,2 :W _i,j =1:5:6:2:4:3:1:2:5. In an embodiment, the first conductive layer M1S, the first conductive layer M1D, and the first conductive layer M1D′ may be a first metal layer.

In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to those defined by the attached patent scope.

102: Synaptic area

102M, 102N: side of the synaptic area

104: The first neuron area

106: second neuron area

D1, D2, D3: direction

NA1, NA2, NA3: the first neuron circuit

NB1, NB2, NB3, NB4: second neuron circuit

Sin: signal input terminal

Sout: signal output terminal

W _1,1 , W _1,2 , W _1,3 , W _1,4 , W _2,1 , W _2,2 , W _2,3 , W _2,4 , W _3,1 , W _3,2 , W _3,3 , W _3,4 : synaptic weight

Claims (11)

A neural computing device includes: a plurality of first neuron circuits arranged in a first neuron area; a plurality of second neuron circuits arranged in a second neuron area; and a plurality of synaptic weights, Are electrically connected between the first neuron circuits and the second neuron circuits, and are arranged in a synapse area; wherein the first neuron area and the second neuron area are respectively in the synapse The opposite side of the area; and a plurality of transistors, wherein one of the synaptic weights includes a plurality of transistors of the plurality of transistors. As for the neural computing device described in item 1 of the scope of patent application, the synaptic weights each include a signal input terminal and a signal output terminal, and the signal input terminals are located between the first neuron circuits and the Between the signal output terminals, the signal output terminals are located between the second neuron circuits and the signal input terminals. Such as the neural computing device described in item 1 of the scope of patent application, wherein the synaptic weights are divided into different synaptic weight groups and are respectively electrically connected to one of the first neuron circuits and the first neuron circuits. One of two neuron circuits. The neural computing device described in item 1 of the scope of the patent application includes a plurality of resistive material layers and a plurality of insulating layers stacked alternately, wherein the The other of the synaptic weights includes at least one resistive material layer of the resistive material layers. In the neural computing device described in item 1 of the scope of patent application, the plurality of transistors are located on the same plane. The neural computing device as described in item 1 of the scope of patent application further includes a substrate under the first neuron circuits, the second neuron circuits, and the synaptic weights. A neural computing device includes: a base; a plurality of synaptic weights located on the base; a plurality of neuron circuits electrically connected to the synaptic weights and arranged on the synaptic weights facing the base One side; and a plurality of transistors, wherein one of the synaptic weights includes a plurality of transistors of the transistors. The neural computing device as described in item 7 of the scope of patent application, wherein the neuron circuits include a plurality of first neuron circuits, and the first neuron circuits are arranged on the side of the synaptic weights facing the substrate . The neural computing device as described in item 8 of the scope of patent application, wherein the neuron circuits further include a plurality of second neuron circuits, and the second neuron circuits are arranged at the synaptic weights toward the base. On the other hand, the synaptic weights are electrically connected between the first neuron circuits and the second neuron circuits. The neural computing device as described in item 7 of the scope of the patent application includes a plurality of resistive material layers and a plurality of insulating layers stacked alternately, wherein the other of the synaptic weights includes at least one of the resistive material layers Resistive material layer. For the neural computing device described in item 7 of the scope of patent application, the plurality of transistors are located on the same plane.

Images