KR100906063B1 - Test device - Google Patents

Abstract

A test device is disclosed. The test device includes a dummy pattern formed on a semiconductor substrate, a conductive region formed on one side of the dummy pattern, a contact electrode contacting the dummy pattern and the conductive region, and a contact electrode contacting only the conductive region. By the test element, the semiconductor element formed in the semiconductor substrate can be tested.

butting, contact, align, test

Description

TEST DEVICE {TEST DEVICE}

An embodiment discloses a test device.

When forming a semiconductor element such as a transistor formed on a semiconductor substrate, process problems were identified by SEM or TEM.

There is a need for a method capable of identifying such a process problem by inputting an electrical signal.

The embodiment provides a test device capable of identifying the structure of a semiconductor device.

The test device according to the embodiment may include a dummy pattern formed on a semiconductor substrate, a conductive region formed on one side of the dummy pattern, a first contact electrode contacting the dummy pattern and the conductive region, and a contacting region only with the conductive region. And two contact electrodes.

The test device according to the embodiment includes a dummy pattern, a first contact electrode contacting the conductive region, and a second contact electrode contacting only the conductive region.

In this case, an electrical signal may be input to the first contact electrode and / or the second contact electrode to calculate a contact area of the first contact electrode to the conductive region, and the position of the dummy pattern may be determined.

Therefore, the position of the semiconductor device formed in a process such as a dummy pattern can be grasped, and the test device according to the embodiment can test the semiconductor device.

1 is a plan view illustrating a first test pattern of a test device according to an exemplary embodiment. FIG. 2 is a cross-sectional view taken along line II ′ in FIG. 1. 3 is a plan view illustrating a second test pattern of the test device according to the embodiment. 4 is a cross-sectional view taken along line II-II ′ of FIG. 3.

1 to 4, the test device includes a semiconductor substrate 10, a first test pattern 20, and a second test pattern 30.

The semiconductor substrate 10 includes a silicon substrate 11 and an isolation layer 12, and includes first active regions AA1, second active regions AA2, and the second isolation region 12 defined by the isolation layer 12. Third active areas AA3 are included.

The first test pattern 2 ㄲ 0 includes a first device 100, a second device 200, a first connection wire 300, and a second connection wire 400. The first device 100 and the second device 200 are alternately arranged on the semiconductor substrate 10 in parallel.

The first device 100 is formed on the first active area AA1. The first device 100 includes a first dummy pattern 110, a first conductive region 120, a first low concentration region 130, a first contact electrode 140, and a second contact electrode 150. .

The first dummy pattern 110 is formed on the semiconductor substrate 10 and is formed on the first active region AA1. The first dummy pattern 110 may include a dummy gate electrode 111, a dummy spacer 112, and a dummy insulating layer 113.

The dummy gate electrode 111 is disposed on the semiconductor substrate 10 and may be formed together, for example, when the gate electrode is formed on the semiconductor substrate 10. Examples of the material used as the dummy gate electrode 111 may include polycrystalline silicon and the like.

The dummy spacer 112 is disposed on the side of the dummy gate electrode 111, and may be formed together, for example, when forming the spacer on the side of the gate electrode. Examples of the material used as the dummy spacer 112 include nitride and the like.

The dummy insulating layer 113 is disposed between the dummy gate electrode 111 and the semiconductor substrate 10. For example, the dummy insulating layer 113 may be formed together when forming a gate insulating layer formed between the gate electrode and the semiconductor substrate 10.

The first conductive region 120 is formed in the first active region AA1. The first conductive region 120 is formed on one side of the first dummy pattern 110 and is formed by implanting a high concentration of conductive impurities. Therefore, the first conductive region 120 is a conductor.

The first conductive region 120 may be formed when, for example, a source / drain region is formed at one side of the gate electrode.

The first low concentration region 130 is disposed under the first dummy pattern 110 and is formed by implanting a low conductivity type conductivity type impurity. For example, the first low concentration region 130 may be formed when an LDD region is formed under the spacer.

The first contact electrode 140 is disposed on the first active region AA1. The first contact electrode 140 is disposed on the first dummy pattern 110 and the first conductive region 120, and contacts the first dummy pattern 110 and the first conductive region 120. do.

That is, a portion of the lower surface of the first contact electrode 140 contacts the first conductive region 120. Examples of the material that may be used as the first contact electrode 140 may include aluminum, copper, or tungsten.

The second contact electrode 150 is disposed on the first active region AA1 and is disposed on the first conductive region 120. The lower surface of the second contact electrode 150 contacts only the first conductive region 120.

The second element 200 is disposed on the second active area AA2. The second device 200 includes a second dummy pattern 210, a second conductive region 220, a second low concentration region 230, a third contact electrode 240, and a fourth contact electrode 250. .

The second dummy pattern 210 is disposed on the second active area AA2.

The second conductive region 220 is formed in the second active region AA2 and is formed on one side of the second dummy pattern 210.

The second low concentration region 230 is formed under the second dummy pattern 210.

The third contact electrode 240 is disposed on the second dummy pattern 210 and the second conductive region 220, and contacts the second dummy pattern 210 and the second conductive region 220. do.

The fourth contact electrode 250 is formed on the second conductive region 220 and contacts only the second conductive region 220.

The interlayer insulating film 500 covers the semiconductor substrate 10. Examples of the material used as the interlayer insulating film 500 include TEOS, USG, BPSG, and the like.

The first to fourth contact electrodes 140, 150, 240, and 250 are formed through the interlayer insulating layer 500. In addition, the first to fourth contact electrodes 140, 150, 240, and 250 have substantially the same size. For example, the first to fourth contact electrodes 140, 150, 240, and 250 may have a cylindrical shape having substantially the same height and diameter.

The first connection wire 300 connects the first contact electrode 140 and the fourth contact electrode 250. The first connection wire 300 is formed on the interlayer insulating film 500. The first connection wire 300 may be formed integrally with the first contact electrode 140 and the fourth contact electrode 250, for example, and may be used as the first connection wire 300. Examples of copper include copper, aluminum or tungsten.

The second connection wiring 400 is formed on the interlayer insulating film 500 and is electrically connected to the second contact electrode 150 and the fourth contact electrode 250. For example, the second connection wire 400 may be integrally formed with the second contact electrode 150 and the third contact electrode 240.

The second test pattern 30 includes a third device 600 and a third connection wiring 700. A plurality of third elements 600 are disposed on the semiconductor substrate 10 side by side.

The third element 600 is formed on the third active region AA3. The third device 600 includes a third conductive region 620 and a fifth contact electrode 640.

The third conductive region 620 is formed in the third active region AA3. The third conductive region 620 includes a high concentration of conductive impurities and is a conductor. The third conductive region 620 is formed together, for example, when the source / drain regions are formed.

Two fifth contact electrodes 640 are formed on the third conductive region 620. In addition, the distance between the two fifth contact electrodes 640 is substantially the same as the distance between the first contact electrode 140 and the second contact electrode 150. In addition, the distance between the two fifth contact electrodes 640 is equal to the distance between the third contact electrode 240 and the fourth contact electrode 250.

In addition, the first to fifth contact electrodes 140, 150, 240, 250, and 640 have substantially the same size and are made of the same material.

In addition, the first to third wires 300, 500, and 700 have substantially the same size and are made of the same material.

In addition, the resistances of the first conductive region 120, the second conductive region 220, and the third conductive region 620 are substantially the same.

When a predetermined voltage is applied to the first connection line 300 and the second connection line 400 at both ends of the first test pattern 20 and the current is measured, the resistance of the first test pattern 20 is measured. It can be seen.

That is, the first connection wire 300, the first contact electrode 140, the first conductive region 120, the second contact electrode 150, the second connection wire 400, and the third Current flows through the contact electrode 240, the second conductive region 220, and the fourth contact electrode 250.

In addition, when a predetermined voltage is applied to the third connection wires 700 at both ends of the second test pattern 30 and the current is measured, the resistance of the second test pattern 30 can be known.

That is, current flows through the fifth contact electrode 640, the third conductive region 620, and the third connection wiring 700.

The first test pattern 20 and the second test pattern 30 are different from each other in the current flow. That is, the area where the first contact electrode 140 contacts the first conductive region 120 and the area where the third contact electrode 240 contacts the second conductive region 220 and the fifth contact. Differences occur between areas where the electrode 640 contacts the third conductive region 620.

Therefore, the difference between the resistance of the first test pattern 20 and the resistance of the second test pattern 30 is determined by the area where the first contact electrode 140 is in contact with the first conductive region 120 and the first resistance. This occurs because the area where the third contact electrode 240 contacts the second conductive region 220 is smaller than the area where the fifth contact electrode 640 contacts the third conductive region 620.

That is, the resistance of the first test pattern 20 is greater than the resistance of the second test pattern 30.

Therefore, by comparing the difference between the resistance and the experimental data using the TEM, SEM, etc., the contact area of the first contact region 140 of the first contact electrode 140 and the second of the third contact electrode 240 are compared. The contact area of the conductive region 220 can be obtained.

In addition, the contact areas are determined by the positions of the first dummy pattern 110 and the second dummy pattern 210. Therefore, the positions of the first dummy pattern 110 and the second dummy pattern 210 may be obtained by the contact areas.

In addition, elements formed in the same process as the first dummy pattern 110 and the second dummy pattern 210 may be formed by the positions of the first dummy pattern 110 and the second dummy pattern 210. The positions of the devices formed in the process can be calculated.

For example, the positions of the gate electrodes disposed on the semiconductor substrate 10 may be determined by the positions of the first dummy pattern 110 and the second dummy pattern 210.

1 is a plan view illustrating a first test pattern of a test device according to an exemplary embodiment.

FIG. 2 is a cross-sectional view taken along line II ′ in FIG. 1.

3 is a plan view illustrating a second test pattern of the test device according to the embodiment.

4 is a cross-sectional view taken along line II-II ′ of FIG. 3.

Claims (7)

A first dummy pattern formed on the semiconductor substrate; A first conductive region formed on one side of the first dummy pattern; A first contact electrode in contact with the first dummy pattern and the first conductive region; And And a second contact electrode contacting only the first conductive region. The method of claim 1, A second dummy pattern formed on the semiconductor substrate; A second conductive region formed on one side of the second dummy pattern; A third contact electrode in contact with the second dummy pattern and the second conductive region; And And a fourth contact electrode contacting only the second conductive region. The test device of claim 2, further comprising a first connection line electrically connecting the first contact electrode and the fourth contact electrode. The test device of claim 2, further comprising a connection wire electrically connecting the second contact electrode and the fourth contact electrode. A plurality of conductive regions are formed on a semiconductor substrate, and an electrical signal is simultaneously applied to the first contact electrodes in which a portion of the lower surface contacts and the second contact electrodes in contact with all of the lower surface. Measuring a first output signal; And Measuring the second output signal by applying an electrical signal only to the second contact electrodes. 6. The method of claim 5, comprising calculating the first output signal and the second output signal and measuring the contact area of the first contact electrodes. The method of claim 6, further comprising: calculating a position of dummy patterns disposed under the first contact electrodes by measuring contact areas of the first contact electrodes.

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