TWI637377B - Apparatus and methods for driving displays - Google Patents

Abstract

An apparatus for driving an electro-optic display includes: a first switch designed to provide a first voltage value to the electro-optical display during a first driving phase; and a second switch designed to switch between Providing a second voltage value to the electro-optic display during the period; and a capacitor connected to the second switch for providing the second voltage value during the second driving phase, wherein during the first driving phase or During the second driving phase, only one of the first switch and the second switch is open.

Description

Device and method for driving display

The present invention relates to a method for driving a bi-stable electro-optic display and a device used in such a method. In particular, the present invention relates to a driving method and a device for adjusting a gate start voltage value after an active update, so as to reduce a transistor degradation related to a voltage stress that may be caused by a residual voltage discharge.

[Reference to related applications]

This patent application is related to U.S. Provisional Application No. 62 / 370,703 filed on August 3, 2016, and is itself related to U.S. Provisional Application No. 62 / 261,104, filed on November 30, 2015, US Provisional Application Serial No. 62 / 111,927 filed on February 4, 2015 (already filed as a non-temporary application on February 4, 2016, with application serial number 15 / 014,236), and September 16, 2015 US Provisional Application No. 62 / 219,606 filed on the same day.

The complete disclosures of the aforementioned patent applications are incorporated herein by reference.

According to one aspect of the subject matter disclosed herein, a device for driving an electro-optic display may include: a first switch designed to provide a first voltage value to the electro-optic display during a first driving phase; a second A switch designed to provide a second voltage value to the electro-optical display during a second driving phase; and a capacitor connected to the second switch to provide the second voltage during the second driving phase Value, wherein during the first driving phase or the second driving phase, only one of the first switch and the second switch is open.

102‧‧‧PMIC

104‧‧‧voltage line

106‧‧‧Gate driver

108‧‧‧ Pull-down resistor

202‧‧‧PMIC

204‧‧‧Gate start line

206‧‧‧Gate driver

208‧‧‧Drop-down resistor

210‧‧‧Switch

220‧‧‧Active driving phase

222‧‧‧Voltage Decay Phase

302‧‧‧PMIC

304‧‧‧Gate starting voltage line

306‧‧‧Gate driver

308‧‧‧ Resistor

310‧‧‧First switch

312‧‧‧Second switch

314‧‧‧pull-down capacitor

320‧‧‧ Active Drive Phase

322‧‧‧Voltage Decay Phase

402‧‧‧PMIC

404‧‧‧Gate start voltage line

406‧‧‧Gate driver

408‧‧‧ Resistor

410‧‧‧First switch

412‧‧‧Second switch

414‧‧‧pull-down capacitor

416‧‧‧Drop-down resistor

420‧‧‧Active driving phase

422‧‧‧Voltage Decay Phase

502‧‧‧PMIC

504‧‧‧Gate start voltage line

506‧‧‧Gate driver

508‧‧‧ pull-down resistor

510‧‧‧The first switch

512‧‧‧Second switch

514‧‧‧capacitor

602‧‧‧PMIC

604‧‧‧Gate start voltage line

606‧‧‧Gate driver

608‧‧‧Drop-down resistor

610‧‧‧First switch

612‧‧‧Second switch

614‧‧‧pull-down capacitor

616‧‧‧pull-down capacitor

618‧‧‧Drop-down resistor

620‧‧‧Active Drive Phase

622‧‧‧Voltage Decay Phase

702‧‧‧PMIC

704‧‧‧Gate start voltage line

706‧‧‧Gate driver

708‧‧‧Drop-down resistor

710‧‧‧The first switch

712‧‧‧Second switch

714‧‧‧Diode

804‧‧‧Gate starting voltage line

806‧‧‧Gate driver

810‧‧‧The first switch

812‧‧‧first voltage source

814‧‧‧Second switch

816‧‧‧Second voltage source

818‧‧‧Capacitor

820‧‧‧ Resistor

840‧‧‧ active phase

842‧‧‧Second Active Phase

844‧‧‧discharge phase

902‧‧‧line

904‧‧‧line

906‧‧‧line

908‧‧‧line

1002‧‧‧ with residual voltage discharge

1004‧‧‧ without residual voltage discharge

1006‧‧‧ with residual voltage discharge

1008‧‧‧ without residual voltage discharge

1102‧‧‧ with residual voltage discharge

1104‧‧‧ without residual voltage discharge

1106‧‧‧ with residual voltage discharge

1108‧‧‧ without residual voltage discharge

1110‧‧‧Standardization with residual voltage discharge and ON: OFF ratio

1112‧‧‧Standardization with residual voltage discharge and ON: OFF ratio

1202‧‧‧Active update cycle

1204‧‧‧Residual voltage discharge cycle

1204‧‧‧ON status

1206‧‧‧OFF state

1212‧‧‧High quasi-gate line voltage

1214‧‧‧Voltage

1216‧‧‧ Front electrode voltage

1218‧‧‧Low quasi-gate line voltage

Various aspects and embodiments of this application will be described with reference to the accompanying drawings. It should be understood that the drawings are not necessarily drawn to scale. In all occurrences of the drawing, objects appearing in multiple drawings are marked with the same component symbol.

FIG. 1A is a schematic diagram of a simple gate start voltage circuit of an electro-optic display according to some embodiments.

FIG. 1B is a graph showing gate activation voltage versus time during an active update and during a voltage decay phase including a back drive discharge phase according to some embodiments, where the gate activation voltage decays exponentially to ground .

FIG. 1C is a graph showing gate activation voltage versus time during an active update period and a voltage decay phase having a better voltage curve according to some embodiments.

FIG. 2A is a schematic diagram of a gate start voltage circuit of an electro-optic display according to some embodiments, the circuit including a resistor.

FIG. 2B is a graph illustrating the gate start voltage of the circuit of FIG. 2A over time according to some embodiments.

FIG. 3A is a schematic diagram of a gate start voltage circuit of an electro-optical display according to some embodiments, which includes a resistor and a capacitor.

FIG. 3B is a graph illustrating the gate start voltage of the circuit of FIG. 3A over time according to some embodiments.

FIG. 4A is a schematic diagram of a gate start voltage circuit of an electro-optic display according to some embodiments, which includes a resistor and a capacitor.

FIG. 4B is a graph illustrating the gate start voltage of the circuit of FIG. 4A over time according to some embodiments.

FIG. 5A is a schematic diagram of a gate start voltage circuit of an electro-optic display according to some embodiments, which includes a resistor and a capacitor.

FIG. 5B is a graph illustrating the gate start voltage of the circuit of FIG. 5A over time according to some embodiments.

FIG. 6A is a schematic diagram of a gate start voltage circuit of an electro-optic display according to some embodiments, which includes a plurality of resistors and capacitors.

FIG. 6B illustrates a graph of gate start-up voltage versus time for the circuit of FIG. 6A according to some embodiments.

FIG. 7 is a schematic diagram of a gate start voltage circuit of an electro-optical display according to some embodiments, the circuit including a Zener diode.

FIG. 8A is a schematic diagram of a gate start voltage circuit of an electro-optic display according to some embodiments, which includes a resistor and a capacitor.

FIG. 8B is a graph illustrating the gate start voltage of the circuit of FIG. 8A over time according to some embodiments.

FIG. 9 is an explanatory diagram comparing the performance of the device described in FIG. 8A with the performance of a conventional device.

FIG. 10A is a graph showing the number of updates of the maximum gray scale displacement relative to the discharge with and without the residual voltage according to some embodiments.

FIG. 10B is a graph showing the maximum ghost displacement relative to the number of updates with and without residual voltage discharge according to some embodiments.

FIG. 11A is a graph showing the maximum gray-scale displacements relative to the number of updates with residual voltage discharge, no residual voltage discharge, and residual voltage discharge and negative bias according to some embodiments.

FIG. 11B is a graph showing the maximum ghost displacement relative to the number of updates of discharges with residual voltage, discharges without residual voltage, and discharges with reduced voltage and reduced charge bias according to some embodiments.

FIG. 12A is a schematic diagram showing the signal timing of the gate voltage versus time according to some embodiments.

FIG. 12B is a schematic diagram showing the signal timing of voltage versus time according to some embodiments.

Word

An electro-optical display includes a layer of electro-optic material. The term used herein is its conventional meaning in imaging technology. It refers to a material that has a first and a second display state that differ in at least one optical property by applying An electric field to the material changes the material from its first display state to a second display state. In the display of the present invention, the electro-optic medium may be Because they are solid (for convenience, such displays may be referred to as solid-state electro-optic displays hereinafter), in a sense, electro-optic media have a solid external surface, although these media can (and usually) have an internal liquid or gas Fill the space. Therefore, the term "solid-state electro-optical display" includes encapsulated electrophoretic displays, encapsulated liquid crystal displays, and other types of displays discussed below.

Although the optical property is typically color perception to the human eye, it can be another optical property, such as optical transmission, reflectance, brightness, or in the case of a display, the significance of the change in reflectance at electromagnetic wavelengths outside the visible range In terms of mechanical reading, pseudo-color. The word "L *" can be used here and can be expressed as "L *". L * has the usual CIE definition, L * = 116 (R / R0) 1 / 3-16, where R = reflectance and R0 is the standard reflectance value.

The term "gray state" is used here in its conventional sense in imaging technology to refer to one of the two extreme optical states of a pixel, and does not necessarily mean the state of the two extreme states. Black-to-white conversion. For example, several patents and published patent applications referred to below describe electrophoretic displays, where the extreme states are white and dark blue, so that the "gray state" in the middle will actually be light blue. In fact, as already mentioned, the transition between the two extreme states may not be a change in color at all.

The words "bistable" and "bistable" are used herein in the conventional sense of the technology to refer to a display that includes first and second display states that differ in at least one optical property. Element display, and such that, in any given element via a After the address pulse of the duration is adopted to adopt its first or second display state, after the address pulse has been terminated, the state will last at least several times (for example, at least four times), which is used to change the state of the display element The minimum duration of the addressing pulse required. It has been shown in published U.S. Patent Application No. 2002/0180687 that certain particle-based electrophoretic displays with grayscale capabilities are not only stable in their extreme black and white states, but also in the middle. The gray state is stable, and is also true for some other types of electro-optic displays. This type of display is correctly called "multistable" rather than bistable, although for convenience, the term "bistable" can be used here to cover both bistable and multistable monitor.

The term "residual voltage" as used herein refers to a continuous or attenuated electric field that may remain in an electro-optical display after the addressing pulse (a voltage pulse used to change the optical state of the electro-optic medium) is terminated. When the residual voltage approaches a critical value, the decay rate of the residual voltage of the electro-optical display may become low. Even low residual voltages (eg, approximately 200 mV or less) can cause artifacts in electro-optic displays, including but not limited to: displacement of optical states related to addressing pulses, and optical states of displays over time Drift, and / or ghosting.

The existence of a residual voltage after a significant period of time applies a "residual pulse" to the electro-optic medium and, strictly speaking, this residual pulse (rather than a residual voltage) may be responsible for the effect of the optical state of the electro-optic display, which is generally considered to be It is caused by the residual voltage. This residual voltage can cause unwanted effects on the image displayed on the electro-optic display, including but not limited to: the so-called "ghost image" phenomenon, where the trace of the previous image is still visible after the display has been rewritten of.

The "shift" of an optical state related to an addressing pulse refers to a state in which a specific addressing pulse is first applied to an electro-optical display resulting in a first optical state (eg, a first gray level), and the same addressing pulse is then Application to the electro-optic display results in a second optical state (eg, a second grayscale). The residual voltage may shift in the optical state because the voltage applied to the pixels of the electro-optic display during the application of the address pulse includes the sum of the residual voltage and the voltage of the address pulse.

The "drift" of the optical state of the display over time refers to a state in which the optical state of the electro-optical display changes when the display is at rest (for example, during a period when an address pulse is not applied to the display). The residual voltage may shift in the optical state because the optical state of the pixel may depend on the residual voltage of the pixel and the residual voltage of the pixel may decay over time.

As mentioned above, "ghosting" refers to a state in which traces of the previous image are still visible after the electro-optical display has been rewritten. Residual voltage may occur "edge ghosting", which is a type of ghosting in which the outline (edge) of a part of the previous image is still visible.

The term "pulse" is used here in the conventional sense of imaging technology to use its voltage integral over time. However, some bistable electro-optic media functions as charge converters, and when using such media, one of the pulses can be used instead of the definition, that is, current integration over time (which is equal to the total charge applied) can be used. The appropriate pulse definition should be used depending on the role of the medium, such as a voltage-time pulse converter or a charge pulse converter.

Several types of electro-optic displays are known. One type of electro-optic display is a rotating two-color component type, such as in the U.S. Patent No. 5,808,783, 5,777,782, 5,760,761, 6,054,071, 6,055,091, 6,097,531, 6,128,124, 6,137,467, and 6,147,791 (Although this type of display is often referred to as a "rotating two-color ball" display, the term "rotating two-color member" is more accurate, (Because in some of the aforementioned patent documents, the rotating member is not spherical). Such displays use a large number of small bodies (which can be, but are not limited to, spherical or cylindrical) with two or more segments with different optical characteristics and an internal dipole. These main systems are suspended in liquid-filled vacuoles located in a matrix. The vacuoles are filled with liquid so that the main body can rotate freely. The appearance of the display is changed by applying an electric field to the display, thereby rotating the main body to various positions, and changing the main body section seen through a viewing surface. This type of electro-optic medium is typically bistable.

Another type of electro-optic display uses an electrochromic medium, for example, an electrochromic medium in the form of a nanochromic film, which includes an electrode that is formed at least partially from a semi-conductive metal oxide; and A plurality of dye molecules capable of reversible color change and attached to the electrode, see, eg, Nature's 1991, 353,737 by O'Regan, B. et al. And Information Display, 18 (3) by Wood, D., 24 (March 2002). See also Bach, U. et al. Adv. Mater., 2002, 14 (11), 845. Nano-colored films of this type are also described in, for example, US Patent No. 6,301,038, International Application Publication No. WO 01/27690, and US Patent Application No. 2003/0214695. This type of medium is also typically bistable.

Another type of electro-optic display is a particle-based electrophoretic display, in which a plurality of charged particles move under the influence of an electric field. Over-suspended liquid. Certain properties of electrophoretic displays are described in US Patent No. 6,531,997, issued March 11, 2003, entitled "Methods for Addressing Electrophoretic Displays", the entire contents of which are incorporated herein by reference.

When compared to liquid crystal displays, electrophoretic displays can have the following attributes: good brightness and contrast, wide viewing angles, state bistableness, and low power consumption. Nevertheless, the long-term image quality problems of some particle-based electrophoretic displays still prevent their widespread use. For example, the particles making up certain electrophoretic displays may tend to settle, resulting in inadequate service life for such displays.

As mentioned above, the electrophoretic medium may include a suspension fluid. This suspension fluid can be a liquid, but the electrophoretic medium can be made using a gaseous fluid; see, for example, "Electrical toner movement for electronic paper-like" for Kitamura T. et al. display) ", IDW Japan, 2001, Paper HCS1-1 and Yamaguchi Y. et al." Toner display using insulative particles charged triboelectrically ", IDW Japan, 2001, Paper AMD4-4. See also European Patent Application Nos. 1,429,178, 1,462,847, and 1,482,354, and International Patent Application Nos. WO 2004/090626, WO 2004/079442, WO 2004/077140, WO 2004/059379, WO 2004/055586, WO 2004/008239, WO 2004 / 006006, WO 2004/001498, WO 03/091799, and WO 03/088495. When the medium is used in an orientation that allows such settling (e.g., in the medium Set in the vertical plane mark), due to particle sedimentation, some gas-based electrophoretic media may appear to be susceptible to the same types of problems as some liquid-based electrophoretic media. In fact, particle sedimentation appears to be a more serious problem in some gas-based electrophoretic media than in some liquid-based media, because the lower viscosity of gas suspension fluids allows for Electrophoretic particles settle faster.

Many patents and patent applications assigned to or under the Massachusetts Institute of Technology (MIT), E Ink Corporation, E Ink California (LLC), and related companies This case describes various techniques used in encapsulated electrophoretic and microcellular electrophoresis, as well as other electro-optic media. The encapsulated electrophoretic medium includes a plurality of small capsules, each of which contains an internal phase containing electrophoretic flowing particles in a fluid medium and a capsule wall surrounding the internal phase. Typically, the capsule itself is contained in a polymer adhesive to form an adhesive layer between the two electrodes. In a microcellular electrophoresis display, charged particles and fluids are not encapsulated within the microcapsules but are retained within a plurality of chambers formed in a carrier medium (which is typically a polymer film). Later, the term "microcavity electrophoretic display" can be used to cover both encapsulated electrophoretic displays and microcellular electrophoretic displays. Techniques described in these patents and patent applications include: (a) electrophoretic particles, fluids, and fluid additives; see, for example, US Patent Nos. 7,002,728, and 7,679,814; (b) capsules, adhesives, and encapsulation processes; see, for example, the United States Patent Nos. 6,922,276 *** and 7,411,719 ***; (c) cell structure, wall material, and method for forming cells; see, for example, U.S. Patent No. 7,072,095, and U.S. Patent Application Publication No. 2014/0065369; (d) methods for filling and sealing cells; participate in, for example, U.S. Patent No. 7,144,942 and U.S. Patent Application Publication No. 2008/0007815; (e) films and subassemblies containing electro-optic materials; see, for example, U.S. Patent Nos. 6,982,178, 7,839,564; (f) substrates, adhesive layers used in displays And other auxiliary layers and methods; see, for example, U.S. Patent Nos. 7,116,318, and 7,535,624; (g) color formation and color adjustment; see, for example, U.S. Patent Nos. 7,075,502, and 7,839,564; (h) methods for driving displays; see, for example, U.S. Patent No. 5,930,026,6,445,489,6,504,524,6,512,354,6,531,997,6,753,999,6,825,970,6,900,851,6,995,550,7,012,600,7,023,420,7,034,783,7,061,166,7,061,662,7,116,466,7,119,772,7,177,066,7,193,625,7,202,847,7,242,514,7,259,744,7,304,787,7,312,794,7,327,511,7,408,699 , 7,453,445, 7,492,339, 7,528,822 7,545,358,7,583,251,7,602,374,7,612,760,7,679,599,7,679,813,7,683,606,7,688,297,7,729,039,7,733,311,7,733,335,7,787,169,7,859,742,7,952,557,7,956,841,7,982,479,7,999,787,8,077,141,8,125,501,8,139,050,8,174,490,8,243,013,8,274,472,8,289,250,8,300,006, 8,305,341, 8,314,784, 8,373,649, 8,384,658, 8,456,414, 8,462,102, 8,537,105, 8,558,783,8,558,785,8,558,786,8,558,855,8,576,164,8,576,259,8,593,396,8,605,032,8,643,595,8,665,206,8,681,191,8,730,153,8,810,525,8,928,562,8,928,641,8,976,444,9,013,394,9,019,197,9,019,198,9,019,318,9,082,352,9,171,508,9,218,773,9,224,338,9,224,342, 9,224,344, 9,230,492, 9,251,736, 9,262,973, 9,269,311, 9,299,294, 9,373,289, 9,390,066, 9,390,661, and 9,412,314; and U.S. Patent Application Publication Nos. 2003/0102858, 2004/0246562, 2005/0253777, 2007/0070032, 2007/0076289, 2007/0076289, 2007/0076289, 2007/0076289, 2007/0076289, 2007/0076289, 2007/0076289, 2007 0091418, 2007/0103427, 2007/0176912, 2007/0296452, 2008/0024429, 2008/0024482, 2008/0136774, 2008/0169821, 2008/0218471, 2008/0291129, 2008/0303780, 2009/0174651, 2009/0195568, 2009/0322721, 2010/0194733, 2010/0194789, 2010/0220121, 2010/0265561, 2010/0283804, 2011/0063314, 2011/0175875, 2011/0193840, 2011/0193841, 2011/0199671, 2011/0221740, 2012 / 0001957, 2012/0098740, 2013/0063333, 2013/0194250, 2013/0249782, 2013/0321278 2014/0009817, 2014/0085355, 2014/0204012, 2014/0218277, 2014/0240210, 2014/0240373, 2014/0253425, 2014/0292830, 2014/0293398, 2014/0333685, 2014/0340734, 2015/0070744, 2015 / 0097877, 2015/0109283, 2015/0213749, 2015/0213765, 2015/0221257, 2015/0262255, 2016/0071465, 2016/0078820, 2016/0093253, 2016/0140910, and 2016/0180777; (i) applications for displays; see, e.g., U.S. Patent Nos. 7,312,784, 8,009,348, and 9,197,704; and ( j) Non-electrophoretic displays, such as those described in U.S. Patent No. 6,241,921, U.S. Patent Application Publication No. 2015/0277160; and U.S. Patent Application Publication Nos. 2015/0005720 and 2016/0012710.

Many of the aforementioned patents and patent applications have realized that the wall surrounding the separated microcapsules in a encapsulated electrophoretic medium can be replaced by a continuous phase, so a so-called polymer dispersed electrophoretic display is made, where the electrophoretic medium includes a plurality of The separated droplets of the electrophoretic fluid and a continuous phase of a polymer material, and the separated droplets of the electrophoretic fluid in such a polymer-dispersed electrophoretic display can be regarded as capsules or microcapsules, even if there is no separate capsule film and each individual small The same goes for the drop association; see, for example, the aforementioned US Patent Application Publication No. 2002/0131147. Therefore, for the purpose of this patent application, such polymer-dispersed electrophoretic media are considered as a subspecies of encapsulated electrophoretic media.

A related type of electrophoretic display is a so-called "microcellular electrophoretic display". In a microelectrophoresis display, charged particles and suspended fluids are not encapsulated within the microcapsules, but instead are stored in a plurality of chambers formed in a carrier medium (eg, a polymer film). See, for example, International Patent Application Publication No. WO 02/01281 and Published US Patent Application Publication No. 2002/0075556, both of which are assigned to Sipix Imaging Corporation.

Many of the aforementioned E Ink companies and MIT patents and patent applications also consider microelectrophoretic displays and polymer dispersed electrophoretic displays. The term "encapsulated electrophoretic display" can also refer to all such display types, which can also be collectively referred to as "microcavity electrophoretic displays" to summarize the shape across the wall.

Another type of electro-optical display is an electronic wet display, which was developed by Philips and developed in "Video-Speed Electronic Paper Based on Electrowetting" by Hayes RA et al., Nature, 425 , Pp. 383-385 (2003). A co-pending application of US Patent Application No. 10 / 711,802 filed on October 6, 2004 shows that such an electronic wet display can be manufactured as a bi-stable state.

Other types of electro-optic materials can also be used. Of particular interest, bistable ferroelectric liquid crystal displays (FLCs) are known in the art and show the behavior of residual voltages.

Although electrophoretic media are often opaque (because, for example, in many electrophoretic media, particles substantially block the transmission of visible light through the display) and operate in reflective mode, some electrophoretic displays can be manufactured with so-called "Mode" operation, where one display is essentially opaque and one is opaque. See, for example, U.S. Patent Nos. 6,130,774 and 6,172,798, and U.S. Patent Nos. 5,872,552, 6,144,361, 6,271,823, 6,225,971, and 6,184,856. Dielectrophoretic displays that are similar to electrophoretic displays but rely on changes in electric field strength can operate in similar modes; see US Patent No. 4,418,346. Other types of electro-optic displays can also be operated in shutter mode.

Encapsulated electrophoretic displays or microelectrophoretic displays may not suffer from the clustering and sinking failure modes of conventional electrophoretic devices, and may provide additional advantages, such as printing on a variety of flexible and rigid substrates or The ability to coat the display. (The use of the word "printing" is intended to include all forms of printing and coating, including but not limited to: pre-metered coating (e.g., patch die coating), Slit or extrusion coating, swash plate or cascade coating, curtain coating; roller coating (e.g., knife over roll coating, forward and reverse roller coating) roll coating); gravure coating; dip coating; spray coating; meniscus coating; spin coating; brush coating; air knife (air-knife) coating; screen printing process; electrostatic printing process; thermal printing process; inkjet printing process; electrophoretic deposition; and other similar technologies.) Therefore, the resulting display may be flexible. Furthermore, because the display medium is printable (using various methods), the display itself can be made at a low cost.

The bistable or multistable behavior of particle-based electrophoretic displays and similar display behavior of other electro-optic displays (for convenience, such displays can be referred to as "pulse-driven displays"), compared to liquid crystal displays ("LCDs"), in stark contrast. Twisted nematic liquid crystals are not bistable or multistable, but are used as voltage transducers so that a given electric field applied to one pixel of this display produces a specific grayscale at that pixel, regardless of the pixel's previous existence Gray scale. Furthermore, the LC display is driven only in one direction (from non-transmissive or "dark" to transmissive or "light"), and reversed from a lighter state to a deeper state This is affected by reducing or eliminating electric fields. In addition, the gray scale of the pixels of the LC display is not sensitive to the polarity of the electric field, and only sensitive to the value of the electric field. In fact, for technical reasons, commercial LC displays usually reverse the polarity of the driving electric field at frequent intervals. In contrast, for the first approximation, the bi-stable electro-optical display acts as a pulse transducer, so that the final state of the pixel is not only determined by the applied electric field and the time during which the electric field is applied, but also by the state of the pixel before the electric field is applied. .

High-resolution displays can include individual pixels that can be addressed without interfering with neighboring pixels. One way to obtain such pixels is to provide an array of non-linear elements, such as an array of transistors or diodes, plus at least one non-linear element associated with each pixel to produce an "active matrix" display. An address electrode or a pixel electrode (addressing a pixel) is connected to an appropriate voltage source via an associated non-linear element. When the non-linear element is a transistor, the pixel electrode can be connected to the drain of the transistor, and this configuration will be adopted in the following description, although it is basically arbitrary, and the pixel electrode can be connected to the source of the transistor . In a high-resolution array, the pixels can be arranged in a two-dimensional array of rows and columns, so that any particular pixel is uniquely defined by the intersection of a particular row and a particular column. The sources of all transistors in each column can be connected to a single column electrode, and the gates of all transistors in each row can be connected to a single row electrode. Again, if necessary, the source is to the column electrode and the gate. The configuration to the row electrodes may be reversed.

The display can be written in a "line-to-line" manner. The row electrode is connected to a row driver, which can apply a voltage to a selected row of power. To ensure that all transistors in selected rows are conductive, and to apply a voltage to all other rows to ensure that all transistors in these non-selected rows are non-conductive. The column electrode is connected to a column driver, and a selected voltage is placed on various column electrodes to drive the pixels in the selected row to a desired optical state. (The aforementioned voltage is relative to a common front electrode, which can be placed on the opposite side of the electro-optic medium from a non-linear array and extends across the entire display). After a preselected interval known as the "line address time", a selected row is deselected, another row is selected, and the voltage on the column driver is changed so that the next line of the display is written.

Residual voltage discharge

As described in US Patent Provisional Application No. 62 / 111,927, filed on February 4, 2015, the entire contents of which are incorporated herein by reference. A preferred embodiment for dispersing residual voltage causes all transistors to become conductive for an extended period of time. For example, all pixel transistors can be made conductive by making the voltage of the gate line (referred to herein as the "selection line") relative to the source line voltage a value that changes the pixel electrode to a state, where In a non-conductive state, they are relatively conductive and are used to isolate pixels from source lines as part of a normal active matrix driver.

In some embodiments, a specially designed circuit may be provided to address all pixels at the same time. In a standard active matrix operation, the selection line control circuit typically does not set all the gate lines to values that achieve the above-mentioned conductive state for all the pixel electrodes. A convenient way to achieve this is by selecting a line driver The chip is provided with an input control line allowing an external signal to impose a condition in which all selection line outputs receive a voltage provided from a selection driver selected to make the pixel transistor conductive. By applying an appropriate voltage value to this special input control line, all transistors can be made conductive. By way of example, for displays with n-type pixel transistors, some select drivers have an "Xon" control line input. By selecting a voltage value for the input of the Xon pin (which is input to the selection drivers), the gate start voltage is sent to all selection lines. For simplicity, the detailed description of the present invention is written for a backplane using an n-type pixel transistor. In this example, the gate start voltage is positive. However, for backplanes made using p-type pixel transistors, all methods described herein can be used by reversing all voltages described and shown in the present invention. In this example, the gate start voltage will be negative.

For the purpose of dispersing the residual voltage of the electro-optic active matrix display, the gate start voltage is an important voltage. Applying the gate start voltage across the entire display is integrated into the "back drive discharge", which is typically applied at the end of the "active drive phase" (also referred to herein as the "image update" or "active update cycle"). The "back drive discharge phase" (also referred to herein as "residual voltage discharge phase" or "residual voltage discharge phase") is part of the "voltage decay phase", and if the back drive discharge phase is equal to the voltage decay phase, then these The terms are used interchangeably (and are used interchangeably herein).

However, as described in US Patent Provisional Application No. 62 / 219,606 filed on September 16, 2015, the entire contents are incorporated herein by reference for maintaining the pixel transistor in a conductive state An extended duration (for residual voltage discharge) may cause degradation of the pixel transistor and / or displacement of the optical performance of the display. It is advantageous to be able to adjust the gate start voltage value during the back drive discharge phase to reduce and / or prevent the effect of maintaining the pixel transistor for an extended duration. Back drive discharge can be performed after each active update, after a specified number of active updates, after a specified time period, or when required by the user. Moreover, the back drive discharge can be interrupted by the active update, so that the gate start voltage value can not reach 0.

The invention describes a device and method for adjusting a gate start voltage value after actively updating a phase.

E / O electronics

As mentioned above, extended periods of high gate voltage, such as those experienced during the discharge of the residual voltage, may cause the pixel transistor to degrade. Reducing the high gate voltage value and / or accelerating the attenuation rate in order to disperse the residual voltage during the residual voltage discharge can reduce or avoid degradation of the pixel transistor. The optimal attenuation rate for dispersing residual voltage in a display can be determined empirically by balancing the acceptable level of discharge performance and the effect on the transconductance of the pixel transistor. One of the advantages of the present invention is that back drive discharge can be achieved with a lower voltage, which will reduce pixel transistor degradation and avoid optical displacement.

The various aspects described above and other aspects will be described in detail below. It should be understood that these aspects can be used individually or collectively, or any combination of two or more, or they are not mutually exclusive.

Electro-optic displays can receive power from external electronics, such as display controllers, and provide voltage from "power management" circuits. The power management circuit may provide multiple voltages, including a "gate start voltage" provided to a gate line (also referred to herein as a "selection line"), so that the transistor on the selection line becomes conductive. The power management circuit may be a separate component or an integrated circuit (eg, a power management integrated circuit "PMIC"). Additional circuitry may include pull-down resistors and / or pull-down capacitors.

FIG. 1A is a schematic diagram of a simple gate start voltage circuit of an electro-optical display using PMIC 102, which shows a gate start voltage line 104 from PMIC 102 to a gate driver 106 of an active matrix display. The circuit of FIG. 1 allows the gate start voltage 104 to be controlled at the end of active driving by changing the value of the pull-down resistor R 108. A high value of R 108 indicates the rate of decay of the gate start voltage, while a low value of R 108 accelerates the rate of decay of the gate start voltage. Using some level from the PMIC to the capacitive element C (not shown) on the gate driver line 104, the pull-down resistor ("R") 108 will cause the gate activation line 104 to decay exponentially to 0 volts, and The resistor value ("R") multiplied by the line capacitance ("C") is a fixed time given. The voltage decay through resistor R 108 can be calculated by: V ( t ) = V _o e ^{- t / RC}

Among them, V ₀ is the initial voltage, and the line capacitance C includes the parasitic capacitance of the voltage line and any capacitance designed as a part of the PMIC to stabilize the voltage.

The back-driving discharge method described in the aforementioned U.S. Patent Provisional Case No. 62 / 111,927 utilizes the slow start voltage at the gate attenuation. During the back drive discharge phase, which typically occurs after the active update phase, the gate start voltage is typically allowed to decay via a resistor connected to ground. At the time of back drive discharge, all active matrix selection lines are made gate start voltages, and decay from the values during the active display drive to ground.

Figure 1B is a graph showing the gate start voltage versus time during the active update period and during the voltage decay phase including the back drive discharge phase, where the gate start voltage decays exponentially to ground. Time t = 0 is when the active update ends. In FIG. 1B, the "discharge driving back" period is defined as beginning at time _{t. 1} ends at time t _2. In the example where the back drive discharge is started immediately after the update, the time t ₁ may be as small as 0, or may be delayed until the gate start-up voltage value decays, or is reduced to a better value. Then the selected time t ₂ is sufficiently large, such that the discharge is driven back sufficiently reduced bias on the display of the polarization charge is valid, or, if time permits, until the gate voltage starts to decay to zero volts.

As described above, it is advantageous to apply a "gate start" voltage of a sufficiently large value so that the drainage of the pixel residual voltage is not high, so as to reduce the degradation of the transistor. A voltage value higher than required increases the TFT bias stress and does not improve residual voltage drainage. As shown in Figure 1B, the simplest implementation of back drive discharge is to allow the "gate start" voltage to decay exponentially during the back drive discharge. A higher initial voltage value is sufficient for timely drainage of the residual voltage, and even, even lower backward voltage values may be too small to timely drain the residual voltage. Furthermore, it is advantageous to minimize the time for which all the select lines are activated so that sufficient residual voltage is discharged, but Not longer than that time. The present invention achieves these advantages by shaping the time curve of the "gate start" voltage during the back drive discharge phase, and controlling the "gate start" voltage. The present invention uses the metric K, which is useful for evaluating the advantageous characteristics of the "gate start" voltage curve during the back drive discharge phase.

Where T _m is the “gate” between the low voltage magnitude (V _L ) and the high voltage magnitude (V _H ) within the time domain starting at the end of the display update and up to the time t ₂ after the end of the update. The total time of the "start-up" voltage, and T _h is the total time of the "gate-start" voltage greater than V _H. t ₂ is the time when the back-drive discharge ends when it is interrupted by other display processing (such as the next image update). The values V _L and V _H may be defined or defined later based on display performance and use. The specified values of V _L and V _H will be described in more detail below. These voltages are defined relative to other voltages, and are defined relative to "zero voltage" or "ground" used to drive electronic products (source and / or select driver and display controller).

Natural K (K _natural ) can be defined as:

Among them, V ₀ is the gate starting voltage applied during the image update period or the active update period (as mentioned above, all voltages are defined relative to the gate closed-circuit voltage of the display under consideration). For convenience, the normalized K is defined as follows:

Among them, K, K _natural and α are all functions of time t ₂ and voltage parameters V _L and V _H. The preferred voltage curve has an alpha greater than 2 or an alpha greater than 5, or preferably an alpha greater than 20, and the values of V _L and V _H meet at least two of the following restrictions: (1) V _L is at least 5% of V ₀ , (2) V _{H is} less than 80% of V ₀ , (3) V _{H is} greater than V _L , and (4) (V _H -V _L ) / ((V _H + V _L ) /2]>0.1. A fourth limitation may be a match, to ensure that as compared to the average of the V _H and V _L, V _H between the partition and the V _L is significant.

Figure 1C is a graph showing the gate start-up voltage versus time during the active update period and during the voltage decay phase with a better voltage curve. The dashed line previously depicted and described in Figure 1B shows a typical exponential decay after active update. The solid line shows an example of a more favorable voltage curve for the back drive discharge phase, in which the gate start-up voltage rapidly decays or decreases to a smaller value, and then decays from this reduced value with the time of the back drive discharge. As shown in FIG. 1C, the initial rapid reduction of the gate starting voltage value after the active update is completed before the activation of all the selection lines. Alternatively, all selection lines can be activated at t = 0. In another alternative example, all the selection lines may be activated after the gate start voltage is initially reduced and has been attenuated to a desired value, or may be activated after a preset time. After the back-drive discharge is effective to sufficiently reduce the charge polarization in the display, or after the gate start voltage has decayed to 0 volts, all select lines can be closed (t ₂ ).

Figure 2A is the simple circuit layout of Figure 1A. In addition, it includes a "single-pole, single-throw" switch ("SW1") 210 (shown as "open circuit") between PMIC 202 and gate driver 206. ). When the SW1 switch 210 is closed, the circuit actively drives the gate driver 206. When the SW1 switch 210 is open (at the end of active driving), the PMIC 202 will stop driving the high gate voltage 206, and the gate start voltage decay rate will be reduced by the pull-down resistor R 208 and the gate start line 204. Capacitance to decide.

FIG. 2B is a schematic diagram illustrating the gate start voltage of the circuit in FIG. 2A with time when the SW1 switch is closed during the active driving phase 220 and when the SW1 switch is open during the voltage decay phase 222.

FIG. 3A is a schematic diagram of a gate start voltage circuit according to an embodiment of the present invention. FIG. 3A shows a gate driver voltage line 304 having a “single-pole, single-throw” switch (“SW1”) 310 from the gate driver 306 of the PMIC 302 to the active matrix display. The circuit further comprises a resistor R308, a second "single-pole, double-throw" 312 (as shown, based on the position "a") switch ( "SW2"), and the pull-down capacitor C ₁ 314.

Switches SW1 and SW2 are programmed to open and close in approximately synchronous fashion so that only one switch is engaged at a time. When operating, during active display driving, SW1 is closed and SW2 is open, and during the voltage decay phase and back drive discharge, SW1 is open and SW2 is closed. SW1 is an example of a "single-pole, single-throw" switch, where it is connected only when in the closed position. SW2 is an example of a "single-pole, double-throw" switch, which is switched between two points so that it is connected to either position "a" or position "b".

By combining the pull-down capacitor C ₁ 314 and the second switch SW2 312, the gate start voltage value can be reduced to a lower value, and then, the reduced voltage value can be attenuated from this. At the end of active driving, SW1 is open and SW2 is at position "b". The drive voltage ("V") attenuation can be calculated according to the following equation:

Among them, C is the line capacitance of the gate start line 304 and V ₀ is the initial voltage.

FIG. 3B illustrates when the SW1 switch is closed and the SW2 open relationship is in position "a" during the active driving phase 320, and during the voltage decay phase 322, when the SW1 switch is open and SW2 is connected to the position "B" is a schematic diagram of the gate starting voltage of the circuit in FIG. 3A over time. As shown in FIG. 3B, during the active driving phase 320 (when SW1 is closed and SW2 is at the position "a"), the PMIC drives the gate driver 306. During the voltage decay phase [when SW1 is open and SW2 is at position "b"], the voltage value is quickly pulled down to a smaller voltage value (ie, V _o C / (C + C ₁ )], And from this smaller value 322 decays at a rate determined by the pull-down resistor R 308 and the capacitance of capacitors C and C ₁ .

FIG. 4A is a schematic diagram of a gate start voltage circuit according to another embodiment of the present invention. FIG. 4A shows a gate driver voltage line 404 having a first switch (“SW1”) 410 from the gate driver 406 of the PMIC 402 to the active matrix display. The circuit further comprises a resistor R 408, a second switch SW2 412 (as shown, based on the position "a"), the pull-down capacitor ( "C _1") 414, and a second pull-down resistor ( "R _1") 416. Pull-down capacitor C ₁ 414 and pull-down resistors R ₁ 416 and SW2 412 lines are in series, however, they can be relative to the position of the exchange SW2.

As shown in FIG. 4B, during the active driving phase 420 (when SW1 is closed and SW2 is in the position "a"), the PMIC drives the gate driver 406 with the active driving gate start voltage value, and the capacitor C ₁ charges. During voltage decay phase 422 (when SW1 is open and SW2 is at position "b"), the gate start voltage value is reduced to the value of capacitor C ₁ 414, and resistors R 408 and R ₁ 416 At a determined rate. The increase of the capacitor C ₁ and the resistors R and R ₁ allows for a better level of control during the initial reduction and a better level of control for the decay rate of the gate start voltage value.

FIG. 5A is a schematic diagram of a gate start voltage circuit according to another embodiment of the present invention, which is equal to FIG. 3A. FIG. 5A shows the gate driver voltage line 504 having the first switch (“SW1”) 510 from the gate driver 506 of the PMIC 502 to the active matrix display. The circuit further includes a second "single-pole, double-throw" switch ("SW2") 512 (as shown in the figure, tied to position a), which is located on the gate start voltage line 504. SW2 512 engages the pull down resistor R 508 and pull-down capacitor C ₁ 514. During the active driving phase (as in 320 of FIG. 3B) of, when the switch SW1 is closed and SW2 is in the position "a", capacitor C ₁ 514 to be charged. During the phase of voltage decay (as described by 322 in Figure 3B), when SW1 is open and SW2 is at position "b", the voltage value will be initially reduced to the value of capacitor C ₁ 514, followed by a resistance At a rate determined by R 508.

Using FIG. 5A as an example electrophoretic display, the PMIC can drive the gate start-up voltage at +22 volts during the active phase update period. During the back drive discharge phase (residual voltage discharge), a gate start voltage value of +22 volts is exceeded, and a reduced gate high voltage value is preferred. In some displays, residual voltage discharge can be achieved by using a voltage value of approximately +8 volts. The preferred circuit of FIG. 5A includes a capacitor C ₁ that is sufficient to cause the gate start voltage to be quickly reduced to approximately 10-12 volts after the active drive phase. Preferred capacitors C ₁ is approximately equal to the value when it is attached to the display (SW2 based on the position b) when it is not connected PMIC (SW1 based on a position "b"), the gate line of the start capacitor. Because different displays and driving electronics have various gate start capacitors, a single capacitance value C ₁ will not be used for all displays, however, it can be selected based on the desired initial voltage drop. Similarly, regarding resistor R 508, a single resistor value will not be applied to all displays, however, it can be selected based on the desired voltage decay rate.

FIG. 5B is a schematic diagram of a gate start voltage circuit according to another embodiment of the present invention, which is equal to FIG. 4A. FIG. 5B is a schematic diagram of the circuit of FIG. 5A additionally including a pull-down resistor R ₁ 516. In FIG. 5B, SW2 512 is connected to a pull-down resistor R 508, a pull-down capacitor C ₁ 514, and a pull-down resistor R ₁ 516. During the active driving phase (as in 420 of FIG. 4B), the closed circuit when SW1 and SW2 based on the position "a", the discharge capacitor C ₁ 514 to 0V. During the voltage decay phase (as described by 422 in Figure 4B), when SW1 is open and SW2 is in position "b", the voltage value will initially drop to the value of capacitor C ₁ 514, and then a resistor Decreases at the rate determined by R 508 and R ₁ 516.

FIG. 6A is a schematic diagram of a gate start voltage circuit according to another embodiment of the present invention. FIG. 6A shows a gate driver voltage line 604 having a first switch (“SW1”) 610 from the gate driver 606 of the PMIC 602 to the active matrix display. The circuit further comprises a pull-down resistor R 608, pull-down capacitor ( "C _1") 614, a second pull-down resistor ( "R _1") 618, a second pull-down capacitor ( "C _2") 616, and a second switch ( “SW2”) 612 (shown as “open”), which is located between the pull-down resistor R ₁ 618 and the pull-down capacitor C ₂ 616. The pull-down capacitor C ₁ 614, the pull-down resistor R ₁ 618, and the pull-down capacitor C ₂ 616 are connected in series.

When SW1 is closed and SW2 is open, PMIC causes the gate start line to become V ₀ volts, the voltage across C ₁ is increased to V _o * C ₂ / (C ₁ + C ₂ ). The capacitors C ₁ and C _{2 are} selected to set this voltage to a desired low level during the period of the back drive discharge. Resistor R ₁₆₁₈ is selected to avoid violent impulse current, which may not be supported by the PMIC made, and the value of R ₁ may be a 0 ohm, in this _embodiment, R ₁ is not necessary. It should be noted here that the positions of R ₁ 618 and C ₁ 614 are interchangeable. Then, during the back drive discharge cycle, SW1 is open and SW2 is closed, so that the gate line is now maintained at a lower voltage, which decays slowly through discharge through the combined resistance value of resistors R 608 and R ₁ 618. Compared with the previous embodiment, this alternative embodiment has the advantages that (1) the switch SW2 is "single-pole, single-throw", which can be easily implemented with a transistor, and (2) the desired low The voltage can be set more easily and approximately, regardless of the gate line capacitance by selecting the values of C ₁ and C _{2, the} values of C ₁ and C _{2 are} larger than other capacitance values experienced by the gate line 604.

As shown in FIG. 6B, during the active driving phase 620 (when SW1 is closed and SW2 is open), the PMIC drives the gate driver 606 with the gate start voltage value for active driving, and the capacitors C ₁ and C _{2 is} charged to a voltage value added up to the gate start voltage value. In phase 622 the voltage decay (when SW1 is open and SW2 is closed) during the period, the gate voltage starts to drop across the voltage level of ₁ C during the driving of the active, from a lower value and then decay. The addition of capacitors C ₁ and C ₂ and resistors R and R ₁ allows a better level of control over the initial reduction of the gate start voltage value, including time and reduction, and the attenuation rate after the initial decrease in value Better level of control. These values can be set to optimize the reduction of the voltage value during the voltage decay phase, or one or both of these resistors can be removed from the circuit.

FIG. 7 is a schematic diagram of a gate start voltage circuit according to another embodiment of the present invention. FIG. 7 shows the gate driver voltage line 704 having the first switch (“SW1”) 710 from the gate driver 706 of the PMIC 702 to the active matrix display. The circuit further includes a second switch ("SW2") 712 (shown as "open circuit"), which is located on the gate start voltage line 704. SW2 712 is a combination of pull-down resistor R 708 and Zener diode 714. During the phase of the discharge, when SW1 is open and SW2 is closed, the audit diode quickly drops the gate start voltage value to a preset value ("collapse voltage value", as described below), and uses the The voltage is attenuated by the rate at which the resistor R 708 is selected to drop to this value.

Auditor diodes are commercially available diodes that allow current to flow in the forward direction in the same pattern as an ideal diode, but when the voltage is below a fixed value (the "crash voltage") It is also allowed to flow in the opposite direction. The acquisition of the audit diode can have different breakdown voltages and can be selected based on the desired breakdown voltage value of a particular display. Auditor diodes are non-linear between voltage and current, but how it reacts to voltage and current is predictable. When the current is high, the zener diode will drop the voltage quickly, however, once the breakdown voltage is reached, the current is turned off. This is another way to quickly reduce the gate start-up voltage during the voltage decay phase. It is also desirable to use more than one zener diode in place of the zener diode shown in Figure 7. It is common practice to use two or more zener diodes in series to achieve the desired voltage, and the zener diodes in series conduct current to them. An zener diode in series can be used to increase the flexibility in the choice of voltage, and the voltage can be reduced through the zener diode through conduction. In this example, the effective breakdown voltage of such a series of audit diodes is the sum of the "crash voltages" of each of the composed audit diodes.

This circuit has the advantage over previous versions. In previous versions, SW2 was a "single-pole, dual-throw" switch and relied on the capacitor value to achieve the desired voltage at the beginning of the back-drive discharge task. In this version, SW2 is a "single-pole, single-throw" switch, which is simpler. Rather than using a capacitor to control the voltage during the discharge phase, using an audit diode to control the desired voltage gives the voltage to be controlled more confidently during the discharge phase. The resistor in the diagram is optional. I This example should probably be displayed, but it is also possible to show examples without resistors, or to explain examples where the resistor value can be zero.

According to another embodiment of the present invention, a power management circuit (such as a power management integrated circuit PMIC) may be configured to actively control the gate start voltage. During the active update period, the gate start voltage can be set to allow the pixel to be charged to a desired voltage for successful display operation. After the active update, during the timing of the back drive discharge, the gate start voltage can be set to a reduced value, where a lower value is sufficient to achieve the back drive discharge. PMIC uses a switch to output the gate start voltage of the display, switch between the voltage value for actively driving the display and different voltage values for the back drive discharge, and manage the control of the gate start voltage. In some embodiments, the switch may be internal to the PMIC. In other embodiments, the switches and circuits may be external to the PMIC.

FIG. 8A illustrates yet another embodiment according to the inventive subject matter presented here. FIG. 8A illustrates the gate driver 806 from the PMIC to the active matrix display, coupled to the gate start voltage line 804 of the first switch (“SW1”) 810, and SW1 is coupled to the first voltage source 812. To provide a first voltage to the display. Furthermore, the second voltage source 816 (usually a low voltage source) can also be coupled to the gate start voltage line 804 via a second switch (“SW2”) 814, and configured to provide a second voltage to the active matrix type. monitor. In addition, in connection with the voltage line 804 and the gate driver 806, a capacitor C 818 and a resistor R 820 can be connected in parallel to provide better control when the gate start voltage is attenuated.

Fig. 8B illustrates the attenuation of the gate start voltage of the circuit configured as described in Fig. 8A. As shown in the figure, during the active phase 840 (when SW1 is closed and SW2 is in the position "a"), the PMIC drives the display with the active gate start voltage value and charges the capacitor C 818. During the second active phase 842 (when SW1 is in position “b” and SW2 is closed), the PMIC drives the display with a voltage dominated by the second voltage source 816. In this second active phase 842, the display is driven at a voltage level close to the voltage value provided by the second voltage source 816, and therefore the capacitor C 818 is charged and discharged with reference to the voltage value of the second voltage source 816 . Finally, during the discharge phase 844 (when SW1 is in position b and SW2 is in position "a"), the gate start voltage is designed to decay at a rate determined by the combination of capacitor C 818 and resistor R 820 . This configuration allows for a faster initial reduction in the gate start-up voltage and therefore facilitates the overall decay process and improves the reliability of the device.

When used, as shown in Figure 9, after a long service life (such as 100,000 updates), compared to some conventional configurations (lines 906 and 908), described in Figure 8A The configuration provides better reliability (lines 902 and 904).

Transistor and typical charge ratio / transistor degradation

Therefore, in some aspects, the subject matter described herein also provides a method for driving a bi-stable electro-optic display having a plurality of pixels in an active matrix array. Various types of active matrix transistors are commercially available, including: amorphous silicon, microcrystalline, polycrystalline silicon, and organic. Transistors in active matrix displays are typically It is designed to support an ON: OFF ratio of 1: 1000 because most active matrix displays have approximately 1000 lines. For n-channel ("n-type") amorphous silicon thin-film transistors ("a-Si" TFTs) in active matrix displays, the transistor system is in its ON state when there is a positive voltage from the gate to the source ( The row is selected), and the transistor system is in its OFF state when there is a negative voltage across the gate to the source. Therefore, n-type thin film pixel transistors typically experience a positive to negative charge ratio of 1: 1000. For p-channel ("p") amorphous silicon thin film transistors a-Si TFTs in active matrix displays, the voltage polarity is reversed. When there is a negative voltage from the gate to the source, the p-type transistor system is in its ON state, and when there is a positive voltage from the gate to the source, the p-type transistor system is in its OFF state. Therefore, p-type thin-film pixel transistors typically experience a positive to negative charge ratio of 1: 1000. When the ON: OFF ratio is changed so that the transistor is ON more often than the normal ratio, the transistor may be degraded and adversely affect the optical performance of the display. Due to atypical charge bias, amorphous silicon transistors are highly susceptible to degradation. One method for reducing the degradation of this type of transistor is to normalize the ON: OFF ratio by adjusting the transistor to its OFF position so that the ON: OFF ratio will be close to its typical value of 1: 1000. More fully described here.

It should be understood that the typical ON: OFF ratio of the active matrix display can be different from the 1: 1000 ratio, and the aspects of the invention described herein can still be applied.

Charge bias for reducing residual voltage based on electro-optic display

The charge bias may occur when the residual voltage is discharged from an electro-optic display according to the technology disclosed herein, and is more completely revealed. It is shown in US Patent Provisional Application No. 62 / 111,927 filed on February 4, 2015, the entire contents of which are incorporated herein by reference. The residual voltage of one pixel of the electro-optical display can be discharged by activating the transistors of the pixel (ie, turning on all the transistors to ON), and setting the voltages of the front and rear electrodes of the pixel to Approximately the same value over a period of time. The amount of residual voltage discharged by a pixel during the residual voltage discharge pulse can be determined at least in part by the rate at which the pixel discharges the residual voltage, and by the duration of the residual voltage discharge pulse. In some embodiments, the period duration during which the residual voltage discharge pulse is applied (located in the ON position) may be at least 50 ms, at least 100 ms, at least 300 ms, at least 500 ms, at least 1 second, or any other suitable duration.

For example, all pixel transistors can be made conductive by making the gate line voltage relative to the source line voltage a value that causes the pixel transistor to be in a state where it is compared to being used for isolation When the pixels from the source line (as part of a normal active matrix driver) are non-conductive, they are relatively conductive. For n-type thin film pixel transistors, this can be achieved by making the gate line a value substantially higher than the source line voltage value. For p-type thin film pixel transistors, this can be achieved by making the gate line a value substantially lower than the source line voltage value. In an alternative embodiment, all pixel transistors can be made conductive by making the gate line voltage 0 and the source line voltage negative (or, for p-type transistors, becoming Positive voltage).

Alternatively, a specially designed circuit can be provided to address all pixels at the same time. Operation in a standard active matrix However, the selection line control circuit typically does not set all the gate lines to a value that achieves the above-mentioned conductive state for all the pixel transistors. A convenient method to achieve this is to be given by a selection line driver chip, which has an input control line that allows an external signal to impose a condition where all selection line output receptions are selected from the selected pixels. The crystal becomes the voltage provided by the conductive selective driver. By applying an appropriate voltage value to this special input control line, all transistors can be made conductive. By way of example, for displays with n-type pixel transistors, some select drivers have an "Xon" control line input. By selecting a voltage value for the input of the Xon pin (which is input to the selection drivers), the "gate high voltage" is sent to all selection lines and all transistors are opened to the ON state.

When the residual voltage is dispersed using these techniques, the positive to negative charge ratio (such as experienced by n-type transistors) can vary from about 1: 1000 to about 1:10 or even 1: 1. This atypical charge bias can cause transistor degradation and reduced display performance. Due to the atypical charge bias and transistor degradation over time, the current and voltage ("IV") curve of the display shifts in value. If the IV curve is shifted to a higher value, more voltage is needed to actuate the transistor switch. By selectively measuring the gray scale displacement and ghost displacement (measured at the L * value) of the combination of the reflectance of the display, the effect of the displacement on the IV curve can be displayed.

Gray scale shift / ghost shift

There are usually 256 transitions, which are defined to change the display from the 16 possible grayscale states (including polar Black and extremely white) to switch to the same grayscale state of the next image to be displayed. The gray scale displacement system measures 16 of these transformations. Ghost displacement measures the characteristics of the remaining 240 transitions.

Gray-scale placement ("GTP") is a measurement of the optical state resulting from applying 16 transitions to all possible gray-scales (including black and white) when starting from a white image. As shown in Figure 1A, the grayscale placement displacement is the absolute value of the maximum L * displacement above 16 grayscales at time k (which can be defined by the number of sequences), minus the grayscale at time 0 Displacement. GTP shift can also be referred to as grayscale shift here, which can be calculated using the following equation: GTP shift (k) = max | (GTP (k) -GTP (0)) |, where GTP (0) is the initial GTP, and GTP (k) is the GTP measurement value at time k. The GTP displacement is an absolute measurement of 16 conversions.

Ghost measurement measures the conversion from all possible 16 gray levels except white to the remaining 240 gray levels, and subtracts the GTP value of the last gray level displayed. In other words, the ghost measurement system compares the optical state of a gray scale when it is switched from non-white and the optical state of the same gray scale when it is switched from white. As shown in FIG. 1B, the ghost shift is the absolute value of the maximum ghost at time k (which can be defined by the number of sequences), minus the ghost at time 0. Ghost shift can be calculated using the following equation: GHOST shift (k) = max | (GHOST (k) -GHOST (0)) |, where GHOST (0) is the initial ghost measurement and GHOST (k ) Is the ghost measurement at time k. Ghost displacement is a relative measurement based on GTP values.

Before taking measurements for GTP displacement and ghost displacement as shown in Figures 10A, 10B, 11A, and 11B, the display is cleaned by switching the display from its current state to black, white, white, and white. However, any display cleaning technique can be used as long as it is compatible so that the measurements will be comparable.

The various aspects described above and other aspects will now be described in more detail below. It should be understood that these aspects may be used singly or in combination, or any combination of two or more, or they are not mutually exclusive.

Figure 10A shows the acceleration reliability of optical response displacement measured at 45 degrees Celsius with the maximum absolute grayscale displacement relative to the number of updates with a residual voltage discharge of 1002 and the number of updates without a residual voltage discharge of 1004 according to some embodiments. Schematic representation of test results. Each use year is assumed to have 50,000 updates. As shown in Figure 10A, the additional ON time experienced by the transistor with residual voltage discharge (atypical charge bias) results in a significant grayscale of approximately 2L * after approximately 100,000 updates (or more than approximately two years) Displacement.

Figure 10B shows the reliability of acceleration of optical response displacement measured at 45 degrees Celsius with the maximum absolute ghost displacement relative to the number of updates with a residual voltage discharge of 1006 and the number of updates without a residual voltage discharge of 1008 according to some embodiments. Schematic representation of test results. Each use year is assumed to have 50,000 updates. As shown in Figure 10B, due to the additional ON time experienced by the transistor with a residual voltage discharge (atypical charge bias), a significant ghost of approximately 3L * after approximately 100,000 updates (or more than approximately two years) Displacement.

FIG. 11A shows the number of updates with residual voltage discharge 1102, the number of updates without residual voltage discharge 1104, and the standardization of 1110 with residual voltage discharge and ON: OFF ratio by the maximum absolute gray scale displacement according to some embodiments. The number of updates is a graph of the results of the accelerated reliability test of optical response displacement measured at 45 degrees Celsius. Each use year is assumed to have 50,000 updates. As shown in Figure 11A, the extra ON time experienced by the transistor due to residual voltage discharge 1102 (atypical charge bias) results in approximately 100,000 updates (or more than After about two years), a significant grayscale shift of about 2L *. When the update with residual voltage discharge is normalized or shifted by 1110 by trimming the transistor to the OFF position for an additional time period, it is generated after approximately 100,000 updates compared to the update without discharge 1104 The grayscale displacement is only about 0.25L *.

Figure 11B shows the number of updates with residual voltage discharge 1106, the number of updates without residual voltage discharge 1108, and the standardization of 1112 with residual voltage discharge and ON: OFF ratio by the maximum absolute ghost displacement according to some embodiments. The number of updates is a graph of the results of the accelerated reliability test of optical response displacement measured at 45 degrees Celsius. Each use year is assumed to have 50,000 updates. As shown in Figure 11B, the extra ON time experienced by the transistor with a residual voltage discharge of 1106 (atypical charge bias) results in approximately 100,000 updates (or more than After about two years), a significant ghost shift of about 3L *. When the transistor is discharged by trimming the transistor to the OFF position for an additional time period, At the time of the new normalization or offset 1112, compared to the update without the discharge 1108, the ghost shift after only about 100,000 updates is only about 0.75L *.

FIG. 12A is a schematic diagram showing the signal timing of the gate voltage versus time according to some embodiments. FIG. 12A depicts a graph of gate voltage applied to an optical update over time, which includes an active update period 1202, during which a positive and negative transition reflects a sequence of multiple A single time frame in the time frame; a residual voltage discharge (ON state) period 1204; and an OFF state period 1206 in an active matrix display with an n-type transistor. In the n-type transistor, a positive gate voltage is applied to reach the ON state 1204, and a negative voltage is applied to reach the OFF state 1206. In one embodiment, the active update period may be 500 ms, the ON period may be 1 second, and the OFF period may be 2 seconds. These time periods may vary depending on the display usage and / or the number of optical updates required within a defined time period (eg, every minute, or every hour, etc.). As described, the residual voltage discharge pulse (ON state) 1204 is performed after the active update (ie, the optical update) 302 to drain the remaining charge. The OFF state is performed after the ON state to achieve an ON: OFF ratio close to the typical 1: 1000 ratio. Although the 1: 1000 ratio may not be reached, the ON: OFF ratio close to the 1: 1000 ratio, or even only 1:10, will reduce the transistor degradation.

FIG. 12B is a schematic diagram showing signal timings of multiple voltages versus time according to some embodiments using a Xon connection to enable all transistors to be turned on synchronously. Figure 12B depicts a diagram of the gate voltage applied to an optical update over time. Including: (1) an active update period 1202, (2) a residual voltage discharge (ON state) period 1204, and (3) an OFF state period 1206, in an active matrix type display having an n-type transistor. The four voltages shown are high-level gate line voltage ("VDDH") 1212, low-level gate line voltage ("VEE") 1218, front electrode voltage ("VCOM") 1216, and Xon voltage 1214. . Each voltage has a separate zero voltage axis, as described by the solid grey line. The voltage above the solid grey line indicates a positive voltage, while the voltage below the solid grey line indicates a negative voltage. In FIG. 12B, the overall gate voltage described in FIG. 12A is a combination of VDDH and VEE voltages. The gate driver outputs an enable voltage ("VGDOE") (not shown in the figure), which controls which gate voltage (ie, VEE or VDDH) is applied. When grounded, the Xon voltage synchronously activates all transistors, turning on all transistors during the discharge cycle 1204. During the OFF state period 1206, VDDH becomes grounded and the transistors undergo an applied VEE (negative voltage), which is controlled to approach zero toward the end of the period. For an additional time period, by trimming the transistor to its OFF position, the ON: OFF ratio more closely reflects its typical value of 1: 1000. Although it is better to keep the ON: OFF ratio of 1: 1000, any ON: OFF cycle that moves the ratio toward its typical value, even only 1:10, 1:50, or 1: 100, can avoid electricity Crystal degradation.

The OFF cycle adds time to each update. Therefore, the OFF period can be specified in advance for a certain amount of time, which can be determined by the controller based on the update frequency and / or can be interrupted. The OFF cycle preferably occurs after the ON cycle, but can also occur at other times, including before the active update cycle. OFF period can be from 500ms to A range of 4 seconds, preferably a range of 1 second to 2 seconds. Depending on the optical update time and the number of optical updates in a time period, the OFF period can be extended up to 10 seconds.

Further description of certain embodiments

It should be understood that the various embodiments shown in the drawings are illustrative and are not necessarily drawn to scale. References in the entire specification to "one embodiment" or "an embodiment" or "certain embodiments" mean a specific feature, structure, etc. associated with at least one embodiment covered by the embodiment, Materials, or characteristics, but not necessarily in all embodiments. Thus, the appearances of the words "in one embodiment", "in an embodiment", or "in some embodiments" in various places throughout the specification are not necessarily referring to the same embodiment.

Unless the context clearly requires it, in the overall disclosure, the words "including", "including" and others are interpreted in an inclusive sense rather than in an exclusive or exhaustive sense; in other words, "including, but not limited to, For ". Additionally, the words "here," "below," "above," "below," and other similar words mean collectively about this application, not any particular part of this application. When the word "or" is used to refer to a series of two or more items, the word covers all of the following descriptions of the word: any of the items in the list, the items in the list All, and any combination of items in the list.

Therefore, several aspects of at least one embodiment of the technology have been described. It should be understood that for those skilled in the art, various replacements, modifications and improvements can be easily made. Such replacements, modifications and improvements The system is within the spirit and scope of this technology. Therefore, the foregoing description and drawings provide only non-limiting examples.

Claims (18)

A device for driving an electro-optic display includes: a first switch designed to provide a voltage to the electro-optical display during a first driving phase; and a second switch connected to a display module and designed to Controlling the voltage during the second driving phase; and a first resistor coupled to the first switch and the second switch for controlling the attenuation rate of the voltage during the second driving phase, wherein The first switch or the second switch is closed or opened, and the first resistor is always connected to the display module; wherein during the first driving phase or the second driving phase, the first switch and the first switch Only one of the two switches is closed. The device of claim 1 further includes a capacitor coupled to the first resistor to control the attenuation of the voltage during the second driving phase. The device of claim 2, wherein the first resistor and the capacitor are connected in parallel. The device of claim 3, further comprising a second resistor configured in series with the capacitor to control the attenuation of the voltage during the second driving phase. The device of claim 2, wherein the capacitor is connected to ground. The device of claim 2, further comprising a second resistor coupled to the capacitor in series to control the attenuation of the voltage during the second driving phase. The device of claim 1, wherein the electro-optical display is an electrophoretic display. The device of claim 7, wherein the electrophoretic display comprises an electro-optic material or an electrochromic material containing a rotating two-color member. The device of claim 1, wherein the first switch and the second switch are open during the third driving phase. The device of claim 9 further includes a capacitor coupled to the first resistor to control the attenuation of the voltage during the second driving phase and the third driving phase. The device according to claim 10, further comprising a second resistor configured in series with the capacitor to control the attenuation of the voltage during the second driving phase and the third driving phase. A method for driving an electro-optic display includes: making a first on-off circuit of a management circuit to provide a voltage to the electro-optic display during a first driving phase; and making a second on-off circuit of the management circuit to Controlling the voltage during a second driving phase, wherein the second open relationship is connected to a display module; and opening the first switch during the second driving phase to allow a coupling of the management circuit The first resistor controls the attenuation of the voltage, wherein during the first driving phase or the second driving phase, only one of the first switch and the second switch is closed; and wherein whether the first switch or the second switch is closed, The second switch is closed or open, and the first resistor is always connected to the display module. The method of claim 12, further comprising controlling the attenuation of the voltage via a capacitor coupled to the management circuit. The method of claim 13, wherein the capacitor and the first resistor are connected in parallel. The method of claim 13, further comprising coupling a second resistor to the capacitor in series to control the attenuation of the second voltage. The method of claim 12, further comprising coupling a diode to the first resistor to control the attenuation of the second voltage. The method of claim 12, further comprising opening the first switch and the second switch to control the attenuation of the voltage during the third driving phase. The method of claim 12, wherein the electro-optical display is an electrophoretic display.