JP2018529126A - Apparatus and method for driving a display - Google Patents

Abstract

The present invention relates to a method for driving a bistable electro-optic display and an apparatus for use in such a method. More specifically, the present invention relates to a driving method and an apparatus for adjusting a gate-on voltage value after active update so as to reduce transistor degradation associated with voltage stress that can be caused by residual voltage discharge. An apparatus for driving an electro-optic display has a first switch designed to supply a voltage to the electro-optic display during a first drive phase, and to control the voltage during a second drive phase. A second switch designed may be provided and a resistor coupled to the first and second switches to control the rate of voltage decay during the second drive phase.

Description

(Refer to related applications)
This application claims the benefit of US Provisional Application No. 62 / 219,606, filed Sep. 16, 2015.

  This application is also related to US Provisional Application No. 62 / 370,703, filed on August 3, 2016, which itself is US Provisional Application No. 62/370, filed November 30, 2015. 261,104, and US Provisional Application No. 62 / 111,927, filed February 4, 2015.

  This application is further related to copending application Ser. No. 15 / 014,236, filed Feb. 4, 2015. The entire disclosure of the above application and all US patents and published and copending applications referenced below are also incorporated herein by reference.

  The present invention relates to a method for driving a bistable electro-optic display and an apparatus for use in such a method. More specifically, the present invention relates to a driving method and an apparatus for adjusting a gate-on voltage value after active update so as to reduce transistor degradation associated with voltage stress that can be caused by residual voltage discharge.

  According to one aspect of the subject matter disclosed herein, an apparatus for driving an electro-optic display includes a first switch designed to supply a voltage to the electro-optic display during a first drive phase. A second switch designed to control the voltage during the second drive phase and coupled to the first and second switches to control the rate of decay of the voltage during the second drive phase And a resistor. In some embodiments, only one of the first and second switches is engaged during the first or second drive phase. In still some other embodiments, both the first and second switches are engaged during the third drive phase.

  Various aspects and embodiments of the present application are described with reference to the following figures. It should be understood that the figures are not necessarily drawn to scale. Articles appearing in more than one figure are indicated by the same reference number in all the figures in which they appear.

FIG. 1A is a schematic diagram of a simple gate-on voltage electrical circuit of an electro-optic display, according to some embodiments. FIG. 1B is a graph illustrating gate-on voltage versus time during the voltage decay phase, including the active update and post-drive discharge phases, where the gate-on voltage decays exponentially to ground, according to some embodiments. FIG. 1C is a graph illustrating gate-on voltage versus time during a voltage decay phase with active update and a preferred voltage profile, according to some embodiments. FIG. 2A is a schematic diagram of a gate-on voltage electrical circuit of an electro-optic display including resistors, according to some embodiments. FIG. 2B is a schematic diagram depicting gate-on voltage over time for the circuit of FIG. 2A, according to some embodiments. FIG. 3A is a schematic diagram of a gate-on voltage electrical circuit of an electro-optic display, including resistors and capacitors, according to some embodiments. FIG. 3B is a schematic diagram depicting gate-on voltage over time for the circuit of FIG. 3A, according to some embodiments. FIG. 4A is a schematic diagram of a gate-on voltage electrical circuit of an electro-optic display, including resistors and capacitors, according to some embodiments. FIG. 4B is a schematic diagram depicting gate-on voltage over time for the circuit of FIG. 4A, according to some embodiments. FIG. 5A is a schematic diagram of a gate-on voltage electrical circuit of an electro-optic display, including resistors and capacitors, according to some embodiments. FIG. 5B is a schematic diagram of a gate-on voltage electrical circuit of an electro-optic display, including resistors and capacitors, according to some embodiments. FIG. 6A is a schematic diagram of a gate-on voltage electrical circuit of an electro-optic display including a plurality of capacitors and resistors, according to some embodiments. 6B is a schematic diagram depicting gate-on voltage over time for the circuit of FIG. 6A, according to some embodiments. FIG. 7 is a schematic diagram of a gate-on voltage electrical circuit of an electro-optic display including a zener diode, according to some embodiments. FIG. 8A is a schematic diagram of a gate-on voltage electrical circuit of an electro-optic display, including resistors and capacitors, according to some embodiments. FIG. 8B is a schematic diagram depicting gate-on voltage over time for the circuit of FIG. 8A, according to some embodiments. FIG. 9 is a schematic illustration of a comparison of the performance of the device illustrated in FIG. 8A with a conventional device. FIG. 10A is a graph illustrating maximum graytone shifts for several updates with and without residual voltage discharge, according to some embodiments. FIG. 10B is a graph illustrating the maximum afterglow shift for several updates with and without residual discharge, according to some embodiments. FIG. 11A is a graph illustrating maximum graytone shift for several updates with residual discharge, without residual discharge, and with residual discharge and negative bias, according to some embodiments. FIG. 11B is a graph showing the maximum afterglow shift for several updates with residual discharge, without residual discharge, and with residual voltage discharge and reduced negative bias, according to some embodiments. is there. FIG. 12A is a schematic diagram of a signal timing diagram illustrating gate voltage over time, according to some embodiments. FIG. 12B is a schematic diagram of a signal timing diagram illustrating voltage versus time according to some embodiments.

The term electro-optic display includes a layer of electro-optic material, which in its conventional sense in imaging technology, is a material having first and second display states that differ in at least one optical property, Is used herein to refer to a material that changes from its first display state to its second display state upon application of an electric field to. In the display of the present disclosure, the electro-optic medium may be solid in the sense that the electro-optic medium has a solid outer surface (such a display may hereinafter be referred to as a “solid electro-optic display” for convenience). The medium can have an internal liquid or gas-filled space, often with it. Thus, the term “solid-state electro-optic display” includes encapsulated electrophoretic displays, encapsulated liquid crystal displays, and other types of displays discussed below.

The optical property may be a color that can be perceived by the human eye, but this is for light transmission, reflectance, luminescence, or for electromagnetic lengths outside the visible range for displays intended for machine reading. Another optical property such as pseudo color may be used in the sense of a change in reflectance. The term “L star” may be used herein and may be represented by “L ^* ”. L ^* has the usual CIE definition, L ^* = 116 (R / R0) l / 3-16, where R is the reflectivity and R0 is the standard reflectivity value.

  The term “gray state” is used herein to refer to an intermediate state between two extreme optical states of a pixel, in its conventional sense in imaging technology, and is not necessarily black-white between these two extreme states. It does not imply a transition. For example, some of the patents and published applications referenced below describe electrophoretic displays in which the extreme states are white and dark blue, as the intermediate “gray state” would actually be light blue. explain. In fact, as already mentioned, the transition between two extreme states may not be discolored at all.

  The terms “bistable” and “bistable”, in their conventional sense in the art, comprise a display element having first and second display states that differ in at least one optical property, the first or second Using any finite duration addressing pulse to exhibit any of the two display states, after any given element is driven, the display element changes state after the addressing pulse has ended. As used herein to refer to a display whose state will last at least several times, eg, at least four times the minimum duration of the addressing pulse used for. Some particle-based electrophoretic displays for gray scale are stable not only in their extreme black and white states, but also in their intermediate gray states, and the same is true for several other types of electro-optic displays This is shown in published US patent application 2002/0180687. Although this type of display is not bistable and is appropriately referred to as “multistable”, for convenience, the term “bistable” is used herein to cover both bistable and multistable displays. Can be used.

  The term “residual voltage” refers to a sustained or decaying electric field that can remain in the electro-optic display after the addressing pulse (the voltage pulse used to change the optical state of the electro-optic medium) is terminated. As used herein. The rate of decay of the residual voltage of the electro-optic display can be reduced as the residual voltage approaches the threshold. Even low residual voltages (eg, residual voltages of about 200 mV or less) include, but are not limited to, optical state shifts associated with addressing pulses, display optical state drift over time, and / or residuals. Artifacts in electro-optic displays, including shadows, can occur.

  The persistence of the residual voltage over a significant period of time applies a “residual impulse” to the electro-optic medium, strictly speaking, this residual impulse, rather than the residual voltage, is usually considered to be caused by the residual voltage. It may be involved in the effect on the optical state of the optical display. Such residual voltages include, but are not limited to, images displayed on electro-optic displays, including the so-called “afterimage” phenomenon, where the traces of the previous image are still visible after the display is rewritten. Can lead to undesirable effects.

  The “shift” of the optical state associated with the addressing pulse is such that the first application of a particular addressing pulse to the electro-optic display results in a first optical state (eg, a first gray tone) Refers to the situation where subsequent application of the same addressing pulse to the optical display results in a second optical state (eg, a second gray tone). Since the voltage applied to the electro-optic display pixels during application of the addressing pulse includes the sum of the residual voltage and the voltage of the addressing pulse, the residual voltage can cause a shift in the optical state.

  “Drift” of the optical state of the display over time refers to a situation in which the optical state of the electro-optic display changes while the display is stationary (eg, while no addressing pulses are applied to the display). . Since the optical state of the pixel can depend on the residual voltage of the pixel, and the residual voltage of the pixel can decay over time, the residual voltage can cause optical state drift.

  As discussed above, “afterglow” refers to the situation where the traces of the previous image are still visible after the electro-optic display is rewritten. Residual voltage can result in an “edge afterglow”, a type of afterglow in which some contours (edges) of the previous image remain visible.

  The term “impulse” is used herein in its conventional sense in the imaging technique of voltage integration over time. However, some bistable electro-optic media act as charge transducers, in which an alternative definition of impulse is used, ie the integration of current over time (equal to the total charge applied) Can be done. Depending on whether the medium acts as a voltage-time impulse transducer or a charge impulse transducer, an appropriate definition of impulse should be used.

  Several types of electro-optic displays are known. One type of electro-optic display is described, for example, in U.S. Pat. Nos. 5,808,783, 5,777,782, 5,760,761, 6,054,071, 6,055. Rotating two-color member type as described in 091, 6,097,531, 6,128,124, 6,137,467, and 6,147,791 (this book This type of display is often referred to as a “rotating two-color sphere” display, but in some of the patents referred to above, the term “rotating two-color member” is used because the rotating member is not spherical. Are preferred as more accurate). Such displays use multiple small bodies (which can be, but are not limited to, spherical or cylindrical) having two or more sections with different optical properties and internal dipoles. These bodies are suspended in a liquid-filled vacuole in the matrix, and the vacuoles are filled with liquid so that the body is rotatable. The appearance of the display is changed by applying an electric field thereto, thus rotating the body to various positions and changing which of the body sections are seen through the viewing surface. This type of electro-optic medium may be bistable.

  Another type of electro-optic display comprises an electrochromic medium, e.g., an electrode formed at least partially from a semiconductive metal oxide and a plurality of dye molecules attached to the electrode capable of reversible color change. An electrochromic medium in the form of a nanochromic film is used. For example, O'Regan, B.M. , Et al. "Nature" (1991, 353, 737) and Wood, D. et al. "Information Display" (18 (3), 24 (March 2002)). Also, Bach, U.S. , Et al. See also “Adv. Mater” (2002, 14 (11), 845). This type of nanochromic film is also described in, for example, US Pat. No. 6,301,038, WO 01/27690, and US 2003/0214695. This type of medium may be bistable.

  Another type of electro-optic display is a particle-based electrophoretic display in which a plurality of charged particles move through a suspending fluid under the influence of an electric field. Several attributes of an electrophoretic display are entitled “Methods for Addressing Electrophoretic Displays”, which is incorporated herein in its entirety, and issued on March 11, 2003, US Pat. No. 6,531,997. Explained in the issue.

  Electrophoretic displays can have attributes of good brightness and contrast, wide viewing angle, state bistability, and low power consumption when compared to liquid crystal displays. Nevertheless, problems with the long-term image quality of some particle-based electrophoretic displays can exist. For example, the particles that make up some electrophoretic displays can settle, resulting in poor service life for such displays.

  As described above, the electrophoretic medium can include a suspending fluid. The suspending fluid can be a liquid, but the electrophoretic medium can be produced using a gaseous suspending fluid. For example, Kitamura, T .; "Electrical toner movement for electrical paper-like display" (IDW Japan, 2001, Paper HCS1-1) and Yamaguchi, Y. et al. , Et al. See "Toner display using insulating particles charged trielectrically" (IDW Japan, 2001, Paper AMD4-4). Also, European Patent Applications Nos. 1,429,178, 1,462,847, and 1,482,354, and International Applications Nos. WO 2004/090626, WO 2004/079442, WO 2004 No. 077140, WO 2004/059379, WO 2004/055586, WO 2004/008239, WO 2004/006006, WO 2004/001498, WO 03/091799, and WO 03 See also / 088495. Some gas-based electrophoretic media, for example, in labels where the media are placed in a vertical plane, can cause some of them due to particle sedimentation when the media is used in an orientation that allows such sedimentation. It can be prone to the same types of problems as some liquid-based electrophoretic media. In fact, particle settling is some more than some liquid-based ones because the lower viscosity of the gaseous suspension fluid compared to liquid ones allows for more rapid settling of electrophoretic particles. This is considered to be a more serious problem in gas-based electrophoretic media.

  Massachusetts Institute of Technology (MIT), E Ink Corporation, E Ink California, LLC. And numerous patents and applications assigned to or in the name of related companies describe various techniques used in encapsulation and microcell electrophoresis and other electro-optic media. The encapsulated electrophoretic medium comprises a number of small capsules each comprising an inner phase containing electrophoretic movable particles in a fluid medium and a capsule wall surrounding the inner phase. Typically, the capsules are held in a polymer binder so that they themselves form a coherent layer positioned between the two electrodes. In microcell electrophoretic displays, charged particles and fluids are not encapsulated within microcapsules, but instead are retained within a plurality of cavities formed in a propagation medium, typically a polymer film. [[Hereafter, the term “microcavity electrophoretic display” can be used to cover both encapsulation and microcell electrophoretic displays. ] The techniques described in these patents and applications include:

  (A) Electrophoretic particles, fluids, and fluid additives (see, eg, US Pat. Nos. 7,002,728 and 7,679,814)

(B) Capsule, binder, and encapsulation process (see, eg, US Pat. Nos. 6,922,276 ^*** , 7,411,719 ^*** )

  (C) Microcell structures, wall materials, and methods of forming microcells (see, eg, US Pat. No. 7,072,095 and US Patent Application Publication No. 2014/0065369)

  (D) Methods for filling and sealing microcells (see, eg, US Pat. No. 7,144,942 and US Patent Application Publication No. 2008/0007815)

  (E) Films and subassemblies containing electro-optic materials (see, eg, US Pat. Nos. 6,982,178 and 7,839,564)

  (F) Backplanes, adhesive layers, and other auxiliary layers, and methods used in displays (see, eg, US Pat. Nos. 7,116,318 and 7,535,624).

  (G) Color formation and color adjustment (see, eg, US Pat. Nos. 7,075,502 and 7,839,564)

(H) Method for driving a display

  (I) Display applications (see, eg, US Pat. Nos. 7,312,784, and 8,009,348, and 9,197,704)

  (J) Non-electrophoretic displays (see, eg, US Pat. No. 6,241,921 and US Patent Application Publication No. 2015/0277160, and US Patent Application Publication Nos. 2015/0005720 and 2016/0012710)

  In many of the aforementioned patents and applications, the walls surrounding discrete microcapsules in an encapsulated electrophoretic medium are replaced by a continuous phase, so that the electrophoretic medium comprises a plurality of discrete droplets of electrophoretic fluid and a polymer. A so-called polymer-dispersed electrophoretic display comprising a continuous phase of material, wherein the discrete droplets of electrophoretic fluid in such a polymer-dispersed electrophoretic display can be any discrete capsule film Recognize that it can be considered as a capsule or microcapsule even though it is not associated with. For example, see the aforementioned 2002/0131147. Thus, for purposes of this application, such polymer dispersed electrophoretic media are considered subspecies of encapsulated electrophoretic media.

  A related type of electrophoretic display is the so-called “microcell electrophoretic display”. In microcell electrophoretic displays, charged particles and suspending fluid are not encapsulated in microcapsules, but are instead held in a plurality of cavities formed in a propagation medium, such as a polymer film. For example, both are described in Sipix Imaging, Inc. See International Application Publication No. WO 02/01281 and Published US Application No. 2002/0075556, assigned to.

  Many of the aforementioned E Ink and MIT patents and applications also consider microcell and polymer dispersed electrophoretic displays. The term “encapsulated electrophoretic display” can refer to all such display types that can also be collectively described as “microcavity electrophoretic displays” as generalized over the form of walls.

  Another type of electro-optic display was developed by Philips and is described by Hayes, R .; A. , Et al., “Video-Speed Electronic Paper Based on Electronics” (Nature, 425, 383-385 (2003)). In pending application Ser. No. 10 / 711,802, filed Oct. 6, 2004, it is shown that such electrowetting displays can be made bistable.

  Other types of electro-optic materials may also be used. Of particular note, bistable ferroelectric liquid crystal displays (FLC) are known in the art and exhibit residual voltage behavior.

  Electrophoretic media are opaque (eg, in many electrophoretic media, because the particles substantially block the transmission of visible light through the display) and may operate in reflective mode, but some electrophoresis The display can be made to operate in a so-called “shutter mode” where one display state is substantially opaque and one is light transmissive. For example, U.S. Pat. Nos. 6,130,774 and 6,172,798 and U.S. Pat. Nos. 5,872,552, 6,144,361, 6,271,823, , 225,971, and 6,184,856. An electrophoretic display that is similar to an electrophoretic display but relies on variations in electric field strength can operate in a similar mode. See U.S. Pat. No. 4,418,346. Other types of electro-optic displays may also be able to operate in shutter mode.

  Encapsulated or microcell electrophoretic displays may not suffer from the agglomeration and sedimentation failure modes of traditional electrophoretic devices, such as the ability to print or coat the display on a wide variety of flexible and rigid substrates, etc. Further advantages may be provided. (The use of the word “printing” includes, but is not limited to, roll coating such as patch die coating, slot or extrusion coating, slide or cascade coating, pre-weighing coating such as curtain coating, knife over roll coating, forward reverse roll coating, etc. , Gravure coating, dip coating, spray coating, meniscus coating, spin coating, brush coating, air knife coating, silk screen printing process, electrostatic printing process, thermal printing process, inkjet printing process, electrophoretic deposition, and other similar techniques Intended to include all forms of printing as well as coatings.) Thus the resulting display It may be flexible. Furthermore, since the display media can be printed (using various methods), the display itself can be made inexpensively.

  The bistable or multi-stable behavior of particle-based electrophoretic displays and other electro-optic displays that display similar behavior (such displays may be referred to hereinafter as “impulse driven displays” for convenience) are: In contrast to that of a liquid crystal display (“LCD”). Twisted nematic liquid crystals are not bistable or multi-stable, but applying a given electric field to a pixel in such a display is not practical in the pixel, regardless of the gray level previously present in the pixel. Acts as a voltage transducer to produce a static gray level. In addition, LC displays can only be driven in one direction (non-transparent or “dark” to transmissive or “bright”), reducing or eliminating the electric field to reverse the brighter state to the darker state. A transition is brought about. Also, the gray level of LC display pixels is sensitive not only to the polarity of the electric field, but only to its magnitude, and for technical reasons, commercial LC displays usually have a driving field polarity at frequent intervals. Reverse. In contrast, a bistable electro-optic display is such that the final state of the pixel depends not only on the applied electric field and the time that the electric field is applied, but also on the state of the pixel prior to the application of the electric field. For an approximation of 1, it acts as an impulse transducer.

  A high resolution display may include individual pixels that are addressable without interference from adjacent pixels. One way to obtain such pixels is to provide an array of non-linear elements, such as transistors or diodes, with at least one non-linear element associated with each pixel to produce an “active matrix” display. An addressing or pixel electrode that addresses one pixel is connected to an appropriate voltage source through an associated non-linear element. When the non-linear element is a transistor, the pixel electrode may be connected to the drain of the transistor and this arrangement will be assumed in the following description, but is arbitrary and the pixel electrode is Can be connected to the source of a transistor. In a high resolution array, pixels are arranged in a two-dimensional array of rows and columns so that any particular pixel is uniquely defined by the intersection of one defined row and one defined column. Also good. While the sources of all transistors in each column may be connected to a single column electrode, the gates of all transistors in each row may be connected to a single row electrode and again The assignment of sources to rows and gates to columns may be reversed if desired.

The display may be written in a line-by-line manner. The row electrode applies a voltage to the selected row electrode, such as to ensure that all transistors in the selected row are conductive, while Connected to a row driver, which can apply a voltage to all other rows, such as to ensure that all transistors in it remain non-conductive. The column electrodes are connected to column drivers that apply voltages selected to drive the pixels in the selected row to their desired optical state to the various column electrodes. (The foregoing voltage is for a common front electrode that can be provided from the non-linear array to the opposite side of the electro-optic medium and extends across the entire display.) Known as "line address time" After the preselected interval, the selected row is deselected, another row is selected, and the voltage on the column driver is changed so that the next line of the display is written.
(Residual voltage discharge)

  Preferred implementation for dissipating residual voltage, as described in US Provisional Application No. 62 / 111,927, filed Feb. 4, 2015, which is incorporated herein by reference in its entirety. The configuration allows all pixel transistors to conduct for an extended period of time. For example, all pixel transistors use a gate line (referred to herein as a “select line”) voltage to the source line voltage to isolate the pixel from the source line as part of normal active matrix drive. Compared to the non-conductive state, the pixel transistor can be made conductive by a value that makes it relatively conductive.

  In some embodiments, specially designed circuits may be provided to address all pixels simultaneously. In standard active matrix operation, the select line control circuit typically does not set all gate lines to values that achieve the above-described conduction state for all pixel transistors. A convenient way to achieve this condition allows an external signal to provide a condition to receive a voltage supplied to a selection driver that is selected so that all selected line outputs conduct the pixel transistors. Provided by a select line driver chip having an input control line. All transistors may be turned on by applying an appropriate voltage value to the special input control line. As an example, for a display with n-type pixel transistors, some select drivers have an “Xon” control line input. By selecting the voltage value to be input to the Xon pin input to the selection driver, the gate-on voltage is routed to all the selection lines. For simplicity, the description of the present invention has been written for a backplane employing n-type pixel transistors. In this case, the gate-on voltage is positive. However, for backplanes made using p-type pixel transistors, all methods described herein can be employed by reversing all voltages described and shown in the present invention. In this case, the gate-on voltage will be negative.

  The gate-on voltage is an important voltage for the purpose of dissipating the residual voltage of the electro-optic active matrix display. Application of a gate-on voltage across the entire display is typically applied at the end of an “active drive phase” (also referred to herein as “image update” or “active update period”) Indispensable for “post-discharge”. The “post-drive discharge phase” (also referred to herein as “residual voltage discharge phase” or “residual voltage discharge”) is a part of the “voltage decay phase”, and the post-drive discharge phase becomes the voltage decay phase. If equal, these terms may be used interchangeably (used interchangeably herein).

  However, it is necessary for residual voltage discharge as described in US Provisional Application No. 62 / 219,606, filed September 16, 2015, which is incorporated herein by reference in its entirety. Holding the pixel transistor in a conducting state for a long duration assumed may cause pixel transistor degradation and / or a shift in the optical performance of the display. Advantageously, the gate-on voltage value can be adjusted during the post-drive discharge phase so as to reduce and / or prevent the effect of holding the pixel transistor over a long duration. Post-drive discharge may occur after a full active update, after a specified number of active updates, after a specified time period, or when requested by the user. Further, the post-drive discharge may be interrupted by active update so that the gate-on voltage value cannot reach zero.

The present invention describes an apparatus and method for adjusting a gate-on voltage value after an active update phase.
(E / O electronic equipment)

  As explained above, long periods of high gate voltage values, such as those received during residual voltage discharge, can cause pixel transistor degradation. Reducing the high gate voltage value during the residual voltage discharge and / or accelerating the decay rate to dissipate the residual voltage may reduce or prevent pixel transistor degradation. The optimal decay rate for dissipating the residual voltage in the display can be determined empirically by balancing the acceptable level of discharge effectiveness and the effect on the transconductance of the pixel transistors. One advantage of the present invention is that post-drive discharge can be achieved at lower voltages, reducing pixel transistor degradation and preventing optical shifts.

  Various aspects described above as well as further aspects will now be described in detail below. It should be understood that these aspects can be used alone, all together, or any combination of two or more to the extent that they are not mutually exclusive.

  The electro-optic display may receive power from an external electronic device such as a display controller and supply voltage from a “power management” circuit. The power management circuit provides a plurality of voltages “including gate-on voltage” supplied to the gate line (also referred to herein as a “selection line”) to conduct the transistors on the selected line May be. The power management circuit may be a discrete component or an integrated circuit (eg, a power management integrated circuit (“PMIC”)). The additional circuitry may include a pull-down resistor and / or a pull-down capacitor.

  FIG. 1A is a schematic diagram of a simple gate-on voltage electrical circuit of an electro-optic display using the PMIC 102, showing a gate-on voltage line 104 from the PMIC 102 to the gate driver 106 of the active matrix display. The circuit of FIG. 1 makes it possible to control the gate-on voltage 104 at the end of active driving by changing the value of the pull-down resistor R108. A high value of R108 will slow down the gate-on voltage decay rate, while a low value of R108 will accelerate the gate-on voltage decay rate. Assuming some level of capacitive element (“C”) (not shown) on line 104 from the PMIC to the gate driver, pull-down resistor (“R”) 108 has a line capacitance (“C”) Will decay gate exponentially exponentially to zero volts with a time constant determined by the resistor value multiplied by ("R"). The voltage decay through the R resistor 108 can be calculated as follows.

Where V _O is the initial voltage and line capacitance C includes the parasitic capacitance of the voltage line and any capacitance that is designed as part of the PMIC to stabilize the voltage. .

  The post-drive discharge method described in US Provisional Application No. 62 / 111,927, cited above, utilizes slow decay of the gate-on voltage. During the post-drive discharge phase, which usually occurs after the active update phase, the gate-on voltage is typically allowed to decay through a resistor connected to ground. In post-drive discharge, all active matrix select lines are brought to a gate-on voltage that decays from that value to ground during active display drive.

FIG. 1B is a graph showing the gate-on voltage versus time during the voltage decay phase, including the active update and post-drive discharge phases, where the gate-on voltage decays exponentially to ground. Time t = 0 is the end of the active update. In FIG. 1B, the “post-drive discharge” period is defined as starting at time t _{1 and} ending at time t ₂ . Time t ₁ can be as small as zero, in which case the post-drive discharge may begin immediately after the update or be delayed until the gate-on voltage value decays or decreases to a preferred value. Time t ₂ in order driving after the discharge is effective to sufficiently reduce the dielectric polarization in the display, or if the time is permitted until the gate-on voltage to decay to zero volts, chosen to be sufficiently large Is done.

  As explained above, it is advantageous to apply a “gate on” voltage that is large enough, but not higher, to allow draining of the pixel residual voltage to reduce transistor degradation. . A voltage scale higher than necessary increases the TFT bias stress and is unlikely to improve the residual voltage drain. As shown in FIG. 1B, the simplest implementation of a post-drive discharge is one that allows the “gate on” voltage to decay exponentially during the post-drive discharge. A higher initial voltage value is sufficient for a timely drain of residual voltage, even if the lower subsequent voltage value may be too small to allow a timely drain of residual voltage. In addition, it is advantageous to minimize time so that all select lines are turned on to allow sufficient residual voltage discharge, but not longer. The present invention controls the “gate on” voltage to achieve these advantages by shaping the time profile of the “gate on” voltage during the post-drive discharge phase. The present invention utilizes metric K, which is useful for assessing the advantageous nature of the “gate on” voltage profile during the post-drive discharge phase.

Where T _m is the low voltage magnitude (V _L ) and high voltage magnitude (V _H ) in the time domain where the “gate on” voltage begins at the end of the display update and ends at time t ₂ after the end of the update. located between a total time, T _h is "gate-on" voltage is above V _H, the total time. t ₂ is the end of the time of driving after the discharge when not interrupted by other display processes such as the next image update. The values V _L and V _H may be defined or bound below based on display performance and usage. Assigning values for V _L and V _H is described in further detail below. The voltage is defined relative to another voltage, all with respect to “zero voltage” or “ground” for the drive electronics (source and / or select driver and display controller).

Nature K (“K _natural ”) may be defined as follows:

Where V ₀ is the “gate on” voltage applied during image update or active update (as explained above, all voltages are relative to the “gate off” voltage for the display under consideration. Defined). For convenience, the normalized K referred to here is defined as follows.

_Where K, K _natural , and alpha (“α”) are all functions of time t ₂ and voltage parameters V _L and V _H. Preferred voltage profiles have alphas greater than 2, alphas greater than 5, or preferably alphas greater than 20, and the values of V _L and V _H have the following constraints: 1) V _L is V ₀ At least 5%, 2) V _H is less than 80% of V ₀ , 3) V _H is above _VL , and 4) (V _H −V _L ) / [(V _H + V _L ) / 2. ] Satisfies at least two of the constraints of> 0.1. The fourth constraint can be met to ensure that the separation between the V _H and V _L is significant compared to the average of the V _H and V _L.

FIG. 1C is a graph showing gate-on voltage versus time during a voltage decay phase with active update and a preferred voltage profile. The dashed line depicted and described above in FIG. 1B shows typical exponential decay after active update. The solid line shows an example of a more advantageous voltage profile for the post-drive discharge phase where the gate-on voltage value decays rapidly or is reduced to a lower value and then decays from this reduced value over the time of the post-drive discharge. . As shown in FIG. 1C, the initial rapid reduction of the gate-on value after active update is completed prior to “turning on” all select lines. Alternatively, all select lines may be turned on at t = 0. As another alternative, all select lines may be turned on after the gate-on voltage value is first reduced and attenuated to the desired value, or after a predetermined time. All select lines may be turned off after the post-drive discharge has been effective in sufficiently reducing the dielectric polarization in the display, or alternatively after the gate on voltage has decayed to zero voltage (t ₂ ).

  2A further includes a “single pole single throw” switch (“SW1”) 210 (“open” as shown) between the PMIC 202 and the gate driver 206. It is the schematic of a layout. When the SW1 switch 210 is closed, the circuit actively drives the gate driver 206. When the SW1 switch 210 is opened (at the end of active drive), the PMIC 202 stops driving the gate high voltage 206 and the gate-on voltage decay rate varies with the various static voltages received by the pull-down resistor R208 and the gate online 204. It will be determined by the capacitance.

  FIG. 2B is a schematic diagram depicting the gate-on voltage over time of the circuit of FIG. 2A during the active drive phase 220 when the SW1 switch is closed and the voltage decay phase 222 when the SW1 switch is open. is there.

FIG. 3A is a schematic diagram of a gate-on voltage electrical circuit according to an embodiment of the present invention. FIG. 3A shows a gate-on voltage line 304 with a first “single pole single throw” switch (“SW1”) 310 from the PMIC 302 to the gate driver 306 of the active matrix display. The circuit further includes a resistor R308, a second “single pole double throw” switch (“SW2”) 312 (in position “a” as shown), a pull-down capacitor (“C ₁ ”) 314, Is provided.

  Switches SW1 and SW2 are programmed to open and close almost simultaneously so that only one switch is engaged at a time. In operation, SW1 closes and SW2 opens during active display drive, while SW1 opens and SW2 closes during the voltage decay phase and post-drive discharge. SW1 is an example of a single pole single throw switch that is connected only when it is in the closed position. SW2 is an example of a single pole double throw switch that is switched between two points so that it is always connected to either position "a" or position "b".

By incorporating pull-down capacitor C ₁ 314 and second switch SW 2 312, the gate-on voltage value may be reduced to a lower value and then attenuated from this reduced voltage value. At the end of active drive, SW1 is open, SW2 is in position “b”, and drive voltage (“V”) attenuation may be calculated according to the following equation:

Where C is the line capacitance of the gate online 304 and V ₀ is the initial voltage.

FIG. 3B shows the active drive phase 320 when the SW1 switch is closed and the SW2 switch is in position “a”, and the voltage decay phase 322 when the SW1 switch is open and the SW2 switch is connected to position “b”. 3B is a schematic diagram depicting the gate-on voltage over time for the circuit of FIG. 3A in FIG. As shown in FIG. 3B, the PMIC drives the gate driver 306 during the active drive phase 320 (when SW1 is closed and SW2 is in position “a”). During the voltage decay phase (when the SW1 switch is open and the SW2 switch is connected to position “b”), the voltage value is quickly pulled down to a smaller voltage value (ie, V _O C / (C + C ₁ )), at a rate that is determined by the capacitance of the pull-down resistor R308 and C and _{C 1,} it decays from this value less than 322.

FIG. 4A is a schematic diagram of a gate-on voltage electrical circuit according to another embodiment of the present invention. FIG. 4A shows a gate-on voltage line 404 with a first switch (“SW1”) 410 from the PMIC 402 to the gate driver 406 of the active matrix display. The circuit further includes a resistor R408, a second switch (“SW2”) 412 (in position “a” as shown), a pull-down capacitor (“C ₁ ”) 414, and a second pull-down resistor Device (“R ₁ ”) 416. Pull-down capacitor C ₁ 414 and pull-down resistor R ₁ 416 are in series with SW 2 412. However, their position with respect to SW2 may be exchanged.

As shown in FIG. 4B, during the active drive phase 420 (when SW1 is closed and SW2 is in position “a”), the PMIC drives the gate driver 406 at the active drive gate-on voltage value and the capacitor C ₁ Charge the 414. During the voltage decay phase 422 (when the SW1 switch is open and the SW2 switch is in position “b”), the gate-on voltage value is reduced to the value of capacitor C ₁ 414 and determined by resistors R 408 and R ₁ 416. Decay at the speed The addition of capacitor C ₁ and resistors R and R ₁ allows an initial reduction in gate-on voltage value and a further degree of control over the decay rate.

FIG. 5A is a schematic diagram of a gate-on voltage electrical circuit according to another embodiment of the present invention, equivalent to FIG. 3A. FIG. 5A shows a gate-on voltage line 504 with a first switch (“SW1”) 510 from the PMIC 502 to the gate driver 506 of the active matrix display. The circuit further comprises a second single pole double throw switch (“SW2”) 512 (in position “a” as shown) positioned on the gate on voltage line 504. SW2 512 engages pull-down resistor R508 and pull-down capacitor C ₁ 514. During the active drive phase (as depicted at 320 in FIG. 3B), when SW1 is closed and SW2 is in position “a”, capacitor C ₁ 514 will be charged. During the voltage decay phase (as depicted at 322 in FIG. 3B), when SW1 is open and SW2 is in position “b”, the voltage value first drops to the value of capacitor C ₁ 514 and then , Will decay at a rate determined by resistor R508.

Using FIG. 5A as an exemplary electrophoretic display, during the active update phase, the PMIC may drive a gate-on voltage at +22 volts. During the post-drive discharge phase (“residual voltage discharge”), the gate-on voltage value of +22 volts is excessive, and a reduced gate high voltage value is preferred. In some displays, the residual voltage discharge may be achieved by using a voltage value of about +8 volts. Preferred circuit of Figure 5A contains sufficient capacitor C ₁ in order to lower up quickly to about 10 to 12 volts on voltage after active driving phase. The preferred capacitor C ₁ value is attached to the display (SW2 is at position “b”) but is approximately equal to the gate-on-line capacitance when the PMIC is disconnected (SW1 is at position “b”). . Since different displays and driving electronics have various gate-capacitance single capacitance value C ₁ is, but would not be applied to all of the display, based on the desired initial voltage drop May be selected. Similar to resistor R508, a single resistor value may not apply to all displays, but may be selected based on the desired voltage decay rate.

FIG. 5B is a schematic diagram of a gate-on voltage electrical circuit according to another embodiment of the present invention, equivalent to FIG. 4A. FIG. 5B is a schematic diagram of the electrical circuit of FIG. 5A further comprising a pull-down resistor R ₁ 516. In FIG. 5B, SW2 512 engages pull-down resistor R508, pull-down capacitor C ₁ 514, and pull-down resistor R ₁ 516. During the active drive phase (as depicted at 420 in FIG. 4B), when SW1 is closed and SW2 is in position “a”, capacitor C ₁ 514 will discharge to 0V. During the voltage decay phase (as depicted at 422 in FIG. 4B), when SW1 is open and SW2 is in position “b”, the voltage value first drops to the value of capacitor C ₁ 514 and then , Will decay at a rate determined by resistors R508 and R ₁ 516.

FIG. 6A is a schematic diagram of a gate-on voltage electrical circuit according to another embodiment of the present invention. FIG. 6A shows a gate-on voltage line 604 with a first switch (“SW1”) 610 from the PMIC 602 to the gate driver 606 of the active matrix display. The circuit further includes a pull-down resistor R608, a pull-down capacitor (“C ₁ ”) 614, a second pull-down resistor (“R ₁ ”) 618, a second pull-down capacitor (“C ₂ ”) 616, A second switch (“SW2”) 612 (“open” as shown) positioned between resistor R ₁ 618 and pull-down capacitor C ₂ 616. Pull-down capacitor C ₁ 614, pull-down resistor R ₁ 618, and pull-down capacitor C ₂ 616 are in series.

PMIC is closed SW1, by opening the SW2, when the gate line to _{V o} volts, the voltage across the _{C 1 is} raised to ^{_{V o * C 2 / (C}} 1 + C 2). Capacitor C ₁ and C ₂ is selected to set the lower level is desired this voltage during driving after the discharge period. Resistor R ₁ 618 is selected to avoid current spikes that cannot be supported by the PMIC, and the value of R ₁ may be 0 ohms, in which case R ₁ is not required. It should also be noted here that the positions of R ₁ 618 and C ₁ 614 can be interchanged. Then, during the driving after the discharge period, the gate line is held at a lower voltage, voltage, so slowly attenuated through through composite resistance of resistor R608 and R ₁ 618 discharge, SW1 is opened, SW2 is closed. The advantages of this alternative embodiment compared to the previous embodiment are: 1) the switch SW2 is “single pole single throw”, which can be easily implemented with transistors, and 2) desired The lower voltage is more easily set almost independently of the gate line capacitance by choosing C ₁ and C ₂ values that are much larger than other capacitances received by the gate line 604 Can do.

As shown in FIG. 6B, during the active drive phase 620 (when SW1 is closed and SW2 is open), the PMIC drives the gate driver 606 at the gate-on voltage value for active drive, Capacitors C ₁ and C ₂ are charged to a voltage value summed with the “gate on” voltage value. During the voltage decay phase 622 (when the SW1 switch is open and the SW2 switch is closed), the gate-on voltage value drops to the level of voltage across C ₁ during active drive and then this lower value. Attenuates from. The addition of capacitors C ₁ and C ₂ and resistors R and R ₁ gives a better degree of control over the initial reduction of the gate-on voltage value in both time and the amount of reduction, as well as the decay rate after the initial drop in value. to enable. These values may be set to optimize the voltage value reduction during the voltage decay phase, or one or both of these resistors may be removed from the electrical circuit.

  FIG. 7 is a schematic diagram of a gate-on voltage electrical circuit according to another embodiment of the present invention. FIG. 7 shows a gate-on voltage line 704 with a first switch (“SW1”) 710 from the PMIC 702 to the gate driver 706 of the active matrix display. The circuit further comprises a second switch (“SW2”) 712 (“open” as shown) positioned on the gate-on voltage line 704. SW2 712 engages pull-down resistor R708 and zener diode 714. During the discharge phase, when SW1 is opened and SW2 is closed, the Zener diode quickly drops the gate-on voltage value to a predetermined value (the “breakdown voltage” value described below) and the voltage is at this value. The speed to descend to is affected by an optional resistor R708.

  Zener diodes, like ideal diodes, allow current to flow in the forward direction, but can also flow in the reverse direction when the voltage exceeds a certain value ("breakdown voltage") It is a commercially available diode. Zener diodes are available with different breakdown voltages and may be selected based on the desired breakdown voltage value for a particular display. A Zener diode is non-linear between voltage and current, but it can be predicted how it reacts to voltage and current. Zener diodes quickly drop the voltage when the current is high, but once the breakdown voltage is reached, the current cuts off. This is another way to quickly drop the gate-on voltage value during the voltage decay phase. It may be desirable to use more than one zener diode instead of that shown in FIG. It is common practice to use a series of two or more zener diodes to achieve the desired voltage above which a series of zener diodes will conduct current. A series of Zener diodes may be employed to gain the flexibility of selecting a voltage above which the voltage is dropped through conduction through the Zener diode. In this case, the effective “breakdown voltage” of such a series of Zener diodes is the sum of the “breakdown voltages” of each of the constituent Zener diodes.

  This circuit has advantages over previous versions. In previous versions, SW2 is a “single pole double throw” switch and relies on the capacitor value to achieve the desired voltage at the start of a post drive discharge session. In this version, SW2 is a "single pole single throw" switch that is much simpler. This provides more reliable control of the voltage during the discharge phase than a circuit that uses a Zener diode to control the desired voltage and employs a capacitor to control the voltage during the discharge phase. The resistors in the figure are optional. Perhaps not only this example, but also the one without a resistor should be shown, or it should be explained that the resistor value can be zero.

  According to another embodiment of the present invention, the power management circuit (power management integrated circuit, PMIC, etc.) may be configured to actively control the gate-on voltage. During active update, the gate on value may be set to allow the pixel to be fully charged to the desired voltage for successful display operation. After active update, during the post-drive discharge time, the gate-on voltage may be set to a reduced value, where a lower scale is sufficient to achieve the post-drive discharge. The PMIC manages gate-on voltage control using a switch that switches a gate-on voltage output to the display between a voltage value for actively driving the display and a different voltage value for post-drive discharge. In some embodiments, the switch is internal to the PMIC. In other embodiments, the switches and electrical circuits are external to the PMIC.

  FIG. 8A illustrates yet another embodiment according to the present subject matter presented herein. FIG. 8A illustrates a gate-on voltage line 804 that is coupled to a first switch (“SW1”) 810 from the PMIC to the gate driver 806 of the active matrix display, where SW1 provides the first voltage to the display. Is coupled to a first voltage source 812. In addition, a second voltage source 816, typically a low voltage source, is also coupled to the gate-on voltage line 804 through a second switch (“SW2”) 814 to provide a second voltage to the active matrix display. It may be configured. Further, capacitor C818 and resistor R820 may be connected in parallel with respect to voltage line 804 and gate driver 806 to provide better control over gate-on voltage decay.

  FIG. 8B illustrates the attenuation of the gate-on voltage as configured by the circuit illustrated in FIG. 8A. As shown, during the active phase 840 (when SW1 is closed and SW2 is in position “a”), the PMIC drives the display at the active drive gate on voltage value and charges the capacitor C818. During the second active phase 842 (when SW1 is in position “b” and SW2 is closed), the PMIC drives the display at a voltage determined by the second voltage source 816. In this second active phase 842, the display is driven at a voltage level close to the voltage value supplied by the second voltage source 816, and the capacitor C818 refers to the voltage value of the second voltage source 816, Charge or discharge accordingly. Finally, during the discharge phase 844 (when SW1 is in position “b” and SW2 is in position “a”), the gate-on voltage decays at a rate determined by the combination of capacitor C818 and resistor R820. Designed to do. This configuration allows for a faster initial reduction of the gate-on voltage, thus facilitating the overall attenuation process and improving device reliability.

During use, as illustrated in FIG. 9, after a long period of use (eg, 100,000 updates), the configuration illustrated in FIG. 8A is a number of conventional configurations (lines 906 and 908). Better reliability (lines 902 and 904).
(Transistor and typical charge ratio / transistor degradation)

  Thus, in some aspects, the subject matter described herein also provides a method of driving a bistable electro-optic display having a plurality of pixels in an active matrix array. Various types of active matrix transistors are commercially available, including amorphous silicon, microcrystals, polysilicon, and organic, among others. The transistors in an active matrix display are typically designed to support an on: off ratio of 1: 1000 since most active matrix displays have about 1000 rows. For an n-channel (“n-type”) amorphous silicon thin film transistor (“a-Si TFT”) in an active matrix display, the transistor is in its on state when there is a positive voltage on the gate-source ( A row is selected) and is in its off state when there is a negative voltage on the gate source. Thus, n-type thin film pixel transistors typically experience a positive to negative charge ratio of 1: 1000. For p-channel (“p-type”) a-Si TFTs in active matrix displays, the voltage polarity is reversed. A p-type transistor is in its on state when there is a negative voltage on its gate and source, and it is in its off state when there is a positive voltage on its gate and source. Thus, p-type thin film pixel transistors typically experience a negative to positive charge ratio of 1: 1000. When the on: off ratio is changed so that the transistor is on more frequently than the normal ratio, the transistor can degrade and adversely affect the optical performance of the display. Amorphous silicon transistors are highly susceptible to degradation due to atypical charge bias. One method for reducing this type of transistor degradation is to reduce the transistor so that the on: off ratio is closer to its typical value of 1: 1000, as described more fully herein. By setting the off position, the on: off ratio is standardized.

It should be understood that the typical on: off ratio of an active matrix display can differ from the 1: 1000 ratio, and the aspects of the invention described herein still apply.
(Charge bias based on reduction of residual voltage of electro-optic display)

  Charge bias is disclosed more fully in US Provisional Application No. 62 / 111,927, filed Feb. 4, 2015, disclosed herein and incorporated herein by reference in its entirety. Can occur when residual voltage is discharged from the electro-optic display. The residual voltage of the pixel of the electro-optic display is activated by activating the pixel transistors (i.e. turning on all transistors) and setting the voltage on the front and back electrodes of the pixel to approximately the same value over a period of time, It may be discharged. The amount of residual voltage discharged by the pixel during the residual voltage discharge pulse may depend, at least in part, on the rate at which the pixel discharges the residual voltage and the duration of the residual voltage discharge pulse. In some embodiments, the duration of the period during which the residual voltage discharge pulse is applied (in the on position) is at least 50 milliseconds, at least 100 milliseconds, at least 300 milliseconds, at least 500 milliseconds, at least It may be 1 second, or any other suitable duration.

  For example, all pixel transistors compare the pixel transistor to the non-conductive state used to isolate the pixel from the source line as part of normal active matrix drive. It can be made conductive by setting it to a value that renders it relatively conductive. For n-type thin film pixel transistors, this can be achieved by bringing the gate line to a value substantially higher than the source line voltage value. For p-type thin film pixel transistors, this can be achieved by bringing the gate line to a value substantially lower than the source line voltage value. In an alternative embodiment, all pixel transistors can be made conductive by setting the gate line voltage to zero and the source line voltage to a negative (or positive for p-type transistors) voltage.

  Alternatively, a specially designed circuit may be provided to address all the pixels simultaneously. In standard active matrix operation, the select line control circuit typically does not set all gate lines to values that achieve the above-described conduction state for all pixel transistors. A convenient way to achieve this condition allows an external signal to provide a condition to receive a voltage supplied to a selection driver that is selected so that all selected line outputs conduct the pixel transistors. Provided by a select line driver chip having an input control line. All transistors may be turned on by applying an appropriate voltage value to the special input control line. As an example, for a display with n-type pixel transistors, some select drivers have an “Xon” control line input. By selecting a voltage value to input to the Xon pin input to the select driver, a “gate high” voltage is routed to all select lines, turning on all transistors.

When the residual voltage is dissipated using these techniques, for example, the positive to negative charge ratio received by the n-type transistor can vary from about 1: 1000 to about 1:10 or even 1: 1. . This atypical charge bias can cause transistor degradation and reduced display performance. As atypical charge bias and transistor degradation increase over time, the display's current and voltage-voltage ("IV") curves shift values. If the IV curve shifts to a higher value, more voltage is needed to activate the transistor switch. The impact of IV curve shifts can be shown by optically measuring the graytone shift and afterglow shifts that occur as a result of display reflectivity (measured in L Star (L ^* )). .
(Gray tone shift / Afterglow shift)

  Typically, 256 transitions are defined that switch the display from the 16 possible gray states currently on the display (including extreme black and extreme white) to the same gray state in the next image to be displayed. Has been. The gray tone shift measures 16 of these transitions. The afterglow shift measures the nature of the remaining 240 transitions.

A graytone arrangement ("GTP") is an optical state resulting from applying 16 transitions to all possible graytones (including black and white) when starting from a white image. taking measurement. As shown in FIG. 1A, the graytone placement deviation can be defined by the number of sequences minus the graytone deviation at time zero, the absolute value of the maximum L ^* deviation over 16 graytones at time k. It is. The GTP shift, also referred to herein as the graytone shift, may be calculated using the equation: GTP shift (k) = max | (GTP (k) −GTP (0)) | , Where GTP (0) is the initial GTP and GTP (k) is the GTP measurement at time k. The GTP shift is an absolute measurement of 16 transitions.

  The afterglow measures the remaining 240 transitions from all 16 possible graytones, except white, to all possible 16 graytones, and is finally displayed. The gray tone GTP value is divided. That is, the afterglow measurement compares the optical state of the gray tone when transitioning from a non-white gray tone with the optical state of the same gray tone when transitioning from white. As shown in FIG. 1B, the afterglow shift is the absolute value of the maximum afterglow at time k, which can be defined by the number of sequences minus the afterglow at time zero. The afterglow shift may be calculated using the equation: GHOST shift (k) = max | (GHOST (k) −GHOST (0)) |, where GHOST (0) is the initial It is an afterglow measurement, and GHOST (k) is an afterglow measurement at time k. The afterglow shift is a relative measurement based on the GTP value.

  Prior to making GTP shift and afterglow shift measurements, the display is switched from its current state to black, white, white, white, as shown in FIGS. 10A, 10B, 11A, and 11B. Cleared by switching. However, any display clearing technique may be used as long as the measured values are consistent so that they are equivalent.

  Various aspects described above, as well as further aspects, will now be described in detail below. It should be understood that these aspects can be used alone, all together, or any combination of two or more to the extent that they are not mutually exclusive.

FIG. 10A illustrates an optical response shift at 45 degrees Celsius, measuring 1002 with residual voltage discharge and 1004 without residual voltage discharge, maximum absolute graytone shift versus number of updates, according to some embodiments. It is a graph which shows the result of an accelerated reliability test. Each year of use is assumed to have 50,000 updates. As shown in FIG. 10A, the additional on-time that the transistor experiences as a result of residual voltage discharge (atypical charge bias) is about 2 L ^* significant after about 100,000 updates (or over about 2 years). Causes a graytone shift.

FIG. 10B illustrates an optical response shift at 45 degrees Celsius, measuring 1006 with residual voltage discharge and 1008 without residual voltage discharge, the maximum absolute afterglow shift for the number of updates, according to some embodiments. It is a graph which shows the result of an accelerated reliability test. Each year of use is assumed to have 50,000 updates. As shown in FIG. 10B, the additional on-time that the transistor experiences as a result of residual voltage discharge (atypical charge bias) is about 3 L ^* significant after about 100,000 updates (or over about 2 years). Causes an afterglow shift.

FIG. 11A shows 1102 with residual voltage discharge, 1104 without residual voltage discharge, and 1110 with normalization of residual voltage discharge and on: off ratio, maximum absolute graytone bias versus number of updates, according to some embodiments. It is a graph which shows the result of the acceleration reliability test in 45 degree Celsius which measures the optical response shift by transfer. Each year of use is assumed to have 50,000 updates. As shown in FIG. 11A, the additional on-time that the transistor experiences as a result of residual voltage discharge 1102 (atypical charge bias) is approximately 100,000 updates after the update 1104 compared to update 1104 without discharge ( (Or over about 2 years) resulting in a significant gray tone shift of about 2L ^* . When update with residual voltage discharge is normalized or offset by putting the transistor in the off position for an additional period of time, the result of 1110, approximately 100,000 updated graytone shifts is accompanied by discharge. Compared to no update 1104, it is only about 0.25L ^* .

FIG. 11B illustrates 1106 with residual voltage discharge, 1108 without residual voltage discharge, and 1112 with normalization of the on-off ratio and the maximum absolute afterglow for the number of updates, according to some embodiments. It is a graph which shows the result of the acceleration reliability test in 45 degree Celsius which measures the optical response shift by transfer. Each year of use is assumed to have 50,000 updates. As shown in FIG. 11B, the additional on-time that the transistor undergoes as a result of the residual voltage discharge 1106 (atypical charge bias) is approximately 100,000 updates after the update 1108 compared to the update 1108 without discharge ( Or over about 2 years) resulting in a significant afterglow shift of about 3L ^* . When updates with residual voltage discharge are normalized or offset by putting the transistor in the off position for an additional time period, the result of 1112 after approximately 100,000 update after-shifts is accompanied by discharge. Compared to no update 1108, it is only about 0.75L ^* .

  FIG. 12A is a schematic signal timing diagram illustrating gate voltage over time, according to some embodiments. FIG. 12A depicts a diagram of applied gate voltage over time for one optical update, including an active update period 1202, where each positive and negative transition is active in an active matrix display with n-type transistors. A single frame in a series of frames is reflected during the update period, the residual voltage discharge (on state) period 1204, and the off state period. In an n-type transistor, a positive gate voltage is applied to achieve the on state 1204 while a negative voltage is applied to achieve the off state 1206. In one embodiment, the active update period may be 500 milliseconds, the on period may be 1 second, and the off period may be 2 seconds. These time periods may vary depending on the number of optical updates required for display usage and / or defined time periods, for example, every minute, every hour, etc. As depicted, the residual voltage discharge pulse (ON state) 1204 is triggered after active update (ie, optical update) 302 to drain residual charge. The off state is triggered after the on state to achieve an on: off ratio that is closer to the typical 1: 1000 ratio. Although the 1: 1000 ratio may not be achieved, transistor degradation will be reduced even if the on: off ratio approaching the 1: 1000 ratio is only 1:10.

  FIG. 12B is a schematic signal timing diagram illustrating multiple voltages over time using a display that utilizes a Xon connection to turn on all transistors simultaneously, according to some embodiments. FIG. 12B shows an active matrix display with n-type transistors applied over time for one optical update, including an active update period 1202, a residual voltage discharge (on state) period 1204, and an off state period. Draw a diagram of the voltage. The four voltages shown are a high level gate line voltage (“VDDH”) 1212, a low level gate line voltage (“VEE”) 1218, a front electrode voltage (“VCOM”) 1216, and a Xon voltage 1214. Each voltage has a separate zero voltage axis depicted as a gray solid line. A voltage above the gray solid line indicates a positive voltage, while a voltage below the gray solid line indicates a negative voltage. In FIG. 12B, the overall gate voltage depicted in FIG. 12A is a combination of VDDH and VEE voltages. The gate driver output enabled a voltage (“VGDOE”) (not shown) that controls which gate voltage (ie, VEE or VDDH) is applied. The Xon voltage activates all transistors simultaneously when grounded, thus turning on all transistors during the discharge period 1204. During the off state period 1206, VDDH is grounded and the transistor receives an applied VEE (negative voltage) that is controlled to approach zero towards the end of the period. By putting the transistor in its off position for an additional time period, the on: off ratio more closely reflects its typical value of 1: 1000. It is preferred to keep the on: off ratio at 1: 1000, but any on that will shift the ratio towards its typical value, even if it is only 1:10, 1:50, or 1: 100 : The off period can prevent transistor deterioration.

The off period adds time to each update. Thus, the off period may be reassigned a defined amount of time, may be determined by the controller based on the frequency of updates, and / or may be interrupted. The off period preferably occurs after the on period, but may occur at other times, including before the active update period. The off period may range from 500 milliseconds to 4 seconds, preferably from 1 second to 2 seconds. Depending on the optical update time and the number of optical updates over a period of time, the off period may be extended up to 10 seconds.
(Further description of some embodiments)

  It should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. Reference throughout this specification to “one embodiment” or “an embodiment” or “some embodiments” refers to a particular feature, structure, material, or characteristic described in connection with the embodiment. Is not necessarily included in all embodiments, but is included in at least one embodiment. As a result, the appearances of the phrases “in one embodiment”, “in one embodiment”, or “in some embodiments” in various places throughout this specification are not necessarily referring to the same embodiment. I don't mean.

  Throughout this disclosure, the words “comprising”, “comprising”, and the like are intended to be exclusive or exhaustive unless the context clearly requires otherwise. In contrast, it is to be interpreted in a comprehensive sense, that is, in the sense of “including but not limited to”. In addition, the words “herein”, “below” herein, “above”, “below”, and words of similar meaning refer to the present application as a whole, not any particular part of this application. Point to. When the word “or” is used with reference to a list of two or more items, the word is a list of all of the following interpretations of the word, ie any of the items in the list: All of the items in the list, and any combination of items in the list.

  Although several aspects of at least one embodiment of the present technology have thus been described, it should be understood that various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the technology. Thus, the foregoing description and drawings provide only non-limiting examples.

According to one aspect of the subject matter disclosed herein, an apparatus for driving an electro-optic display includes a first switch designed to supply a voltage to the electro-optic display during a first drive phase. A second switch designed to control the voltage during the second drive phase and coupled to the first and second switches to control the rate of decay of the voltage during the second drive phase And a resistor. In some embodiments, only one of the first and second switches is engaged during the first or second drive phase. In still some other embodiments, both the first and second switches are engaged during the third drive phase.
This specification provides the following, for example.
(Item 1)
An apparatus for driving an electro-optic display,
A first switch designed to supply voltage to the electro-optic display during a first drive phase;
A second switch designed to control the voltage during a second drive phase;
A resistor coupled to the first and second switches to control the rate of decay of the voltage during the second drive phase;
An apparatus comprising:
(Item 2)
The apparatus of claim 1, wherein only one of the first and second switches is engaged during the first or second drive phase.
(Item 3)
The apparatus of claim 1, further comprising a capacitor coupled to the resistor to control the attenuation of the voltage during the second drive phase.
(Item 4)
Item 5. The apparatus of item 4, further comprising a resistor placed in series with the capacitor to control the attenuation of the voltage during the second drive phase.
(Item 5)
The apparatus of claim 2, further comprising a resistor coupled to the capacitor in series to control the attenuation of the voltage during the second drive phase.
(Item 6)
The apparatus of item 1, wherein the first and second switches are engaged and disengaged during a third drive phase.
(Item 7)
11. The apparatus of item 10, further comprising a capacitor coupled to the resistor to control the attenuation of the voltage during the second and third drive phases.
(Item 8)
Item 11. The apparatus of item 10, further comprising a resistor placed in series with the capacitor to control the attenuation of the voltage during the second and third drive phases.
(Item 9)
A method for driving an electro-optic display comprising:
Engaging a first switch of a management circuit and supplying a voltage to the electro-optic display during a first drive phase;
Engaging a second switch of the management circuit to control the voltage during a second drive phase;
Disengaging the first switch during the second drive phase, allowing a resistor coupled to the management circuit to control the decay of the voltage;
Including a method.
(Item 10)
14. The method of item 13, further comprising controlling the attenuation of the voltage through a capacitor coupled to the management circuit.
(Item 11)
14. The method of item 13, wherein the capacitor is in parallel with the resistor.
(Item 12)
14. The method of item 13, further comprising coupling a resistor in series with the capacitor to control the attenuation of the second voltage.
(Item 13)
14. The method of item 13, further comprising coupling a diode to the resistor to control the attenuation of the second voltage.
(Item 14)
14. The method of item 13, further comprising disengaging the first and second switches during a third drive phase to control the decay of the voltage.
(Item 15)
Item 14. The method according to Item 13, wherein the electro-optic display is an electrophoretic display.

Claims (15)

An apparatus for driving an electro-optic display,
A first switch designed to supply a voltage to the electro-optic display during a first drive phase;
A second switch designed to control the voltage during a second drive phase;
A resistor coupled to the first and second switches to control the rate of decay of the voltage during the second drive phase;
An apparatus comprising:   The apparatus of claim 1, wherein only one of the first and second switches is engaged during the first or second drive phase.   The apparatus of claim 1, further comprising a capacitor coupled to the resistor to control the attenuation of the voltage during the second drive phase.   The apparatus of claim 4, further comprising a resistor placed in series with the capacitor to control the attenuation of the voltage during the second drive phase.   The apparatus of claim 2, further comprising a resistor coupled to the capacitor in series to control the attenuation of the voltage during the second drive phase.   The apparatus of claim 1, wherein the first and second switches are engaged and disengaged during a third drive phase.   The apparatus of claim 10, further comprising a capacitor coupled to the resistor to control the attenuation of the voltage during the second and third drive phases.   The apparatus of claim 10, further comprising a resistor disposed in series with the capacitor to control the attenuation of the voltage during the second and third drive phases. A method for driving an electro-optic display comprising:
Engaging a first switch of a management circuit and supplying a voltage to the electro-optic display during a first drive phase;
Engaging a second switch of the management circuit to control the voltage during a second drive phase;
Disengaging the first switch during the second drive phase, allowing a resistor coupled to the management circuit to control the decay of the voltage;
Including a method.   The method of claim 13, further comprising controlling the attenuation of the voltage through a capacitor coupled to the management circuit.   The method of claim 13, wherein the capacitor is in parallel with the resistor.   The method of claim 13, further comprising coupling a resistor in series with the capacitor to control the attenuation of the second voltage.   The method of claim 13, further comprising coupling a diode to the resistor to control the attenuation of the second voltage.   14. The method of claim 13, further comprising disengaging the first and second switches during a third drive phase to control the decay of the voltage.   The method of claim 13, wherein the electro-optic display is an electrophoretic display.