TWI634635B - Semiconductor package structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor package structure includes a wafer, a plurality of first conductive bumps, and a first encapsulant. The wafer has opposing first and second surfaces. The wafer includes two layers of semiconductor elements. The two semiconductor element layers extend from the first surface and the second surface into the wafer, respectively. Two patterned circuit layers including a plurality of pads are respectively disposed on the first surface and the second surface. The two semiconductor element layers are electrically connected to the two patterned circuit layers, respectively. The first conductive bumps are respectively disposed on the pads of the first surface. The first encapsulant is disposed on the first surface and exposes the plurality of top surfaces of the first conductive bumps. In addition, a method of fabricating a semiconductor package structure has also been proposed.

Description

Semiconductor package structure and manufacturing method thereof

The present invention relates to a package structure and a method of fabricating the same, and more particularly to a semiconductor package structure and a method of fabricating the same.

Wafer Level Chip Scale Package (WLCSP) technology refers to the wafer after the production is completed, after all or most of the package and test procedures are performed on the entire wafer, and then the cutting process is performed. To form a single component. Because wafer-level chip-scale packaging technology has the advantages of smaller package size, better electrical performance, easier assembly process, and lower production cost, it attracts wafer manufacturers and manufacturers in the test industry to invest heavily in this technology. in.

In the existing wafer level wafer size packaging technology, a single side of the wafer is usually implanted to transfer the electrical signal of the wafer to an external printed circuit board (PCB). However, in such a manner However, it cannot meet the demand for high pin count (I/O).

The present invention provides a semiconductor package structure having a higher number of pins.

The present invention provides a method of fabricating a semiconductor package structure for fabricating the above-described semiconductor package structure.

An embodiment of the invention provides a semiconductor package structure including a wafer, a plurality of first conductive bumps, and a first encapsulant. The wafer has opposing first and second surfaces. The wafer includes a first semiconductor element layer and a second semiconductor element layer. The first semiconductor device layer and the second semiconductor device layer extend from the first surface and the second surface, respectively, into the wafer. A first patterned circuit layer and a second patterned circuit layer are respectively disposed on the first surface and the second surface. The first patterned circuit layer and the second patterned circuit layer respectively include a plurality of first pads and a plurality of second pads. The first semiconductor element layer and the second semiconductor element layer are electrically connected to the first patterned circuit layer and the second patterned circuit layer, respectively. The first conductive bumps are respectively disposed on the first pads. The first encapsulant is disposed on the first surface and exposes the plurality of top surfaces of the first conductive bumps.

In an embodiment of the invention, the wafer further includes a plurality of second conductive bumps disposed on the second pads.

In an embodiment of the invention, the wafer further includes a second encapsulant. The second encapsulant is disposed on the second surface and exposes the plurality of top surfaces of the second conductive bumps.

In an embodiment of the invention, the top surfaces of the second conductive bumps are provided with solder balls.

In an embodiment of the invention, the top surfaces of the first conductive bumps are provided with solder balls.

An embodiment of the invention provides a method of fabricating a semiconductor package structure comprising the following steps. Provide wafers. The wafer has opposing first and back sides. The wafer includes a first semiconductor element layer that extends from the first surface into the wafer. The first surface is provided with a first patterned circuit layer. The first patterned circuit layer includes a plurality of first pads. The first semiconductor element layer is electrically connected to the first patterned circuit layer. A plurality of first conductive bumps are formed on the first pads. Forming a first encapsulant on the first surface, and the first encapsulant covers the first conductive bumps. A thinning process is performed on the back side of the wafer to expose the wafer to the second surface. A second semiconductor device layer is formed on the second surface, and the second semiconductor device layer is extended from the second surface into the wafer. Forming a second patterned wiring layer on the second surface, the second patterned wiring layer including a plurality of second pads. The second semiconductor device layer is electrically connected to the second patterned circuit layer. At least a portion of the first encapsulant is removed to expose a plurality of top surfaces of the first conductive bumps.

In an embodiment of the invention, the manufacturing method further includes forming a plurality of second conductive bumps on the second pads.

In an embodiment of the invention, the manufacturing method further includes forming a second encapsulant on the second surface. The second encapsulant covers the second conductive bumps. At least a portion of the second encapsulant is removed to expose the plurality of top surfaces of the second electrically conductive bumps.

In an embodiment of the invention, the manufacturing method further includes forming solder balls on the top surfaces of the second conductive bumps.

In an embodiment of the invention, the manufacturing method further includes forming solder balls on the top surfaces of the first conductive bumps.

In the semiconductor package structure of the embodiment of the present invention, the first semiconductor device layer and the second semiconductor device layer of the wafer are electrically connected to the first patterned circuit layer on the first surface and the second surface, respectively. The second patterned circuit layer, the first patterned circuit layer and the second patterned circuit layer respectively comprise a plurality of first pads and a plurality of second pads to connect the first semiconductor device layer and the second semiconductor device The electrical signals of the layers are transferred to an external substrate or wafer. Through the above configuration, the semiconductor package structure of the embodiment of the present invention has a higher number of pins (ie, a high I/O number). Furthermore, the present invention further provides a method of fabricating a semiconductor package structure for fabricating the above-described semiconductor package structure, and the semiconductor package structure manufactured by the method of fabricating the semiconductor package structure of the present invention has a high number of pins.

The above described features and advantages of the invention will be apparent from the following description.

1A to 1K' illustrate a method of fabricating a semiconductor package structure in accordance with various embodiments of the present invention.

A method of fabricating a semiconductor package structure according to an embodiment of the present invention is described in the following paragraphs, for example, a semiconductor package structure suitable for fabricating a wafer level. Referring first to FIG. 1A, a wafer 110 is provided. The wafer 110 has opposing first and second surfaces S1 and S1. Wafer 110 includes a first semiconductor device layer 112 that extends from first surface S1 into wafer 110. The first surface S1 can be regarded as an active surface. The first surface S1 is provided with a first patterned wiring layer 112a. The first semiconductor element layer 112 is electrically connected to the first patterned wiring layer 112a. The first patterned wiring layer 112a includes a plurality of first pads P1. The first semiconductor element layer 112 is electrically connected to the first patterned wiring layer 112a.

In the present embodiment, the material of the wafer 110 is, for example, Silicon (Si), but the invention is not limited thereto. The material of the first patterned circuit layer 112a is, for example, a metal material, but the invention is not limited thereto. The thickness T of the wafer 110 is, for example, 150 micrometers (micrometer, μm), but the invention is not limited thereto. The first semiconductor device layer 112 includes, for example, a thin film transistor (TFT), a metal oxide semiconductor field effect transistor (MOSFET), or a complementary metal oxide semiconductor (Complementary). Metal-Oxide-Semiconductor, CMOS), but the invention is not limited thereto.

Referring to FIG. 1B, a plurality of first conductive bumps 120 are formed on the first pads P1 of the first surface S1. The conductive bumps 120 are electrically connected to the first pads P1. In this embodiment, the material of the first conductive bumps 120 is, for example, copper (Cu), aluminum (Al), or an alloy thereof (Cu/Al). The manner of forming the conductive bumps 120 is, for example, electroplating, but the invention is not limited thereto.

Next, referring to FIG. 1C , a first encapsulant 130 is formed on the first surface S1 , and the first encapsulant 130 covers the first conductive bumps 120 . In the present embodiment, the material of the first encapsulant 130 is, for example, an Epoxy Molding Compound (EMC), but the invention is not limited thereto. More specifically, in the present embodiment, the thickness of the first encapsulant 130 is, for example, 300 micrometers, but the invention is not limited thereto.

Referring to FIG. 1D, a thinning process is performed on the back surface BS of the wafer 110 to expose the wafer 110 to the second surface S2. In the present embodiment, the thickness T' of the wafer 110 after the thinning process is, for example, 50 micrometers, but the invention is not limited thereto. The thinning process is, for example, a Grinding process, an Etching process, or a Polishing process, but the invention is not limited thereto.

Referring to FIG. 1E, a second semiconductor device layer 114 is formed on the second surface S2. The second semiconductor device layer 114 extends from the second surface S2 into the wafer 110. At this time, the second surface S2 can be regarded as an active surface. In the wafer 110, the first semiconductor element layer 112 and the second semiconductor element layer 114 are separated from each other. In detail, the method of forming the second semiconductor device layer 114 is, for example, a semiconductor process. The semiconductor process includes, for example, an Epidaxy Process, a Thermal Process, a Photolithography Process, a Doping Process, an Ion Implantation Process, and an Etching Process (Etching). Process or a multi-process combination such as a deposition process, the invention is not limited thereto. The second semiconductor device layer 114 includes, for example, a Thin Film Transistor (TFT), a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), or a Complementary Metal Oxide Semiconductor (Complementary). Metal-Oxide-Semiconductor, CMOS), the invention is not limited thereto.

Referring to FIG. 1F, a second patterned wiring layer 114a is formed on the second active surface S2, and the second patterned wiring layer 114a includes a plurality of second pads P2. The second semiconductor device layer 114 is electrically connected to the second patterned wiring layer 114a. In detail, the second patterned circuit layer 114a is formed by, for example, a photolithography process and a deposition process to form the second patterned circuit layer 114a, but the invention is not limited thereto. . The material of the second patterned circuit layer 114a is, for example, a metal material, but the invention is not limited thereto.

Referring to FIG. 1G, at least a portion of the first encapsulant 130 is removed to expose the plurality of top surfaces 122 of the first conductive bumps 120. The method of removal is, for example, grinding or laser ablation. So far, the semiconductor package structure 100 in the embodiment of the present invention has been substantially completed. In the embodiment, the semiconductor package structure 100 includes a wafer 110 , a plurality of first conductive bumps 120 , and a first encapsulant 130 . The wafer 110 has opposing first and second surfaces S1 and S2. The wafer 110 includes a first semiconductor element layer 112 and a second semiconductor element layer 114. The first semiconductor element layer 112 and the second semiconductor element layer 114 extend from the first surface S1 and the second surface S2 into the wafer 110, respectively. The first patterned circuit layer 112a and the second patterned circuit layer 114a are respectively disposed on the first surface S1 and the second surface S2. The first patterned wiring layer 112a includes a plurality of first pads P1. The second patterned wiring layer 114a includes a plurality of second pads P2.

As described above, in the semiconductor package structure 100 of the embodiment of the present invention, the first semiconductor device layer 112 and the second semiconductor device layer 114 of the wafer 110 are electrically connected to the first pattern on the first surface S1, respectively. The wiring layer 112a and the second patterned wiring layer 114a on the second surface S2 (i.e., the wafer 110 has a first surface S1 and a second surface S2 that can be regarded as active surfaces). The first patterned wiring layer 112a and the second patterned wiring layer 114a respectively include a plurality of first pads P1 and a plurality of second pads P2 to electrically charge the first semiconductor element layer 112 and the second semiconductor element layer 114. The signal is transmitted to an external substrate or wafer. Therefore, the semiconductor package structure 100 in the embodiment of the present invention has a higher number of pins (ie, a high I/O number).

The method of making various embodiments of the present invention will continue to be described in the following paragraphs. 1A to FIG. 1G, referring to FIG. 1H, solder balls B are formed on the top surfaces 122 of the first conductive bumps 120. In the present embodiment, the solder ball B is, for example, a solder ball, a solder paste or a tin layer, but the invention is not limited thereto. Thus far, the semiconductor package structure 100a of the embodiment of the present invention has been substantially completed. Therefore, the main difference between the semiconductor package structure 100a of FIG. 1H and the semiconductor package structure 100 of FIG. 1G is that in the semiconductor package structure 100a of FIG. 1H, the top surfaces 122 of the first conductive bumps 120 are provided with solder balls B. .

1A to 1G, referring to FIG. 1H', a plurality of second conductive bumps 140 are formed on the second pads P2 of the second surface S2. In this embodiment, the material of the second conductive bumps 140 is, for example, copper (Cu), aluminum (Al) or an alloy thereof, but the invention is not limited thereto. Referring to FIG. 1I', a second encapsulant 150 is formed on the second surface S2, and a second encapsulant 150 covers the second conductive bumps 140. Referring to FIG. 1J', at least a portion of the second encapsulant 150 is removed to expose the plurality of top surfaces 142 of the second conductive bumps 140. Thus far, the semiconductor package structure 100b of the embodiment of the present invention has been substantially completed. Therefore, the main difference between the semiconductor package structure 100b of FIG. 1J' and the semiconductor package structure 100 of FIG. 1G is that, in the semiconductor package structure 100b of FIG. 1J', a plurality of second conductive bumps 140 and a second encapsulant 150 are further included. . The second conductive bumps 140 are respectively disposed on the second pads P2. The second encapsulant 150 is disposed on the second surface S2 and exposes the plurality of top surfaces 142 of the second conductive bumps 140.

Referring to FIG. 1K', a method of manufacturing the semiconductor package structure of FIGS. 1A to 1J' is performed to form solder balls B on the top surfaces 142 of the second conductive bumps 140. Thus far, the semiconductor package structure 100c of still another embodiment of the present invention has been substantially completed. Therefore, the main difference between the semiconductor package structure 100c of FIG. 1K' and the semiconductor package structure 100b of FIG. 1J' is that in the semiconductor package structure 100c of FIG. 1K', the top surfaces 142 of the second conductive bumps 140 are provided with solder. Ball B.

FIG. 2 is a schematic diagram of the diced monolithic package structure of the semiconductor package structure 100 of FIG. 1H circumscribed to the substrate.

Referring to FIG. 2, the semiconductor package structure 100 is diced to form a plurality of single chip package structures 10. FIG. 2 exemplarily shows a single chip package structure 10 through the solder balls B and the metal wires 160 to be external to a substrate. 200 electrical connection. That is, the single chip package structure 10 can pass through the solder ball B, the metal wire 160, the conductive pillar (not shown) or other forms of conductive members (not shown) to make the single chip package structure and The external substrate (the substrate is, for example, a printed circuit board or a circuit board manufactured by other kinds of processes, but the invention is not limited thereto) is electrically connected to respectively replace the first one of the single chip package structures 10 The electrical signals of the semiconductor device layer 112 and the second semiconductor device layer 114 are transferred to the external substrate. Alternatively, in other embodiments not shown, the wafer may be additionally stacked on the single chip package structure 10, and the wafer and the single chip package structure 10 are electrically connected through the conductive member to electrically connect the two to each other. The electrical signals of the first semiconductor device layer 112 and the second semiconductor device layer 114 in the single chip package structure 10 are respectively transferred to the external wafer. Therefore, the semiconductor package structure 100 of the embodiment of the present invention has high flexibility in circuit design.

In the semiconductor package structure of the embodiment of the present invention, the first semiconductor device layer and the second semiconductor device layer of the wafer are electrically connected to the first patterned circuit layer on the first surface and the first a second patterned circuit layer on the two surfaces, the first patterned circuit layer and the second patterned circuit layer respectively include a plurality of first pads and second pads to connect the first semiconductor device layer and the second semiconductor device The electrical signals of the layers are transferred to an external substrate or wafer. Through the above configuration, the semiconductor package structure of the embodiment of the present invention has a higher number of pins (ie, a high I/O number).

Further, the semiconductor package structure of the embodiment of the present invention forms a plurality of single chip package structures through a subsequent dicing process, and the single chip package structure can transmit different types of conductive members (for example, solder balls, metal wires, conductive posts, or Other forms of conductive members) are used to electrically connect a single wafer package structure to an external substrate or wafer. Therefore, the semiconductor package structure of the embodiment of the present invention has high flexibility in circuit design.

In addition, the present invention further provides a method of fabricating a semiconductor package structure to fabricate the above-described semiconductor package structure, and the semiconductor package structure manufactured by the method for fabricating the semiconductor package structure of the present invention has a high number of pins, and the circuit design It has a high elasticity.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10: Single chip package structure 100, 100a, 100b, 100c: semiconductor package structure 110: wafer 112: first semiconductor element layer 112a: first patterned circuit layer 114: second semiconductor element layer 114a: second patterning Circuit layer 120: first conductive bumps 122, 142: top surface 130: first encapsulant 140: second conductive bump 150: second encapsulant 160: metal wire 200: substrate B: solder ball BS: back S1: First surface S2: second surface T, T': thickness P1: first pad P2: second pad

1A to 1K' illustrate a method of fabricating a semiconductor package structure in accordance with various embodiments of the present invention. 2 is a schematic diagram of the diced monolithic package structure of the semiconductor package structure of FIG. 1G circumscribed to the substrate.

Claims (10)

A semiconductor package structure comprising: a wafer having an opposite first surface and a second surface, the wafer including a first semiconductor device layer and a second semiconductor device layer, the first semiconductor device layer and the The second semiconductor device layer extends from the first surface and the second surface into the wafer, and the first surface and the second surface are respectively provided with a first patterned circuit layer and a second patterned circuit layer. The first patterned circuit layer and the second patterned circuit layer respectively include a plurality of first pads and a plurality of second pads, wherein the first semiconductor device layer and the second semiconductor device layer respectively a patterned circuit layer and the second patterned circuit layer are electrically connected, wherein the first semiconductor device layer and the second semiconductor device layer are not electrically connected; a plurality of first conductive bumps are respectively disposed on the first The first pads of the surface; and a first encapsulant disposed on the first surface and exposing the plurality of top surfaces of the first conductive bumps. The semiconductor package structure of claim 1, wherein the wafer further comprises a plurality of second conductive bumps respectively disposed on the second pads of the second surface. The semiconductor package structure of claim 2, wherein the wafer further comprises a second encapsulant disposed on the second surface, the second encapsulant exposing the plurality of tops of the second conductive bumps surface. The semiconductor package structure of claim 3, wherein the top surfaces of the second conductive bumps are provided with solder balls. The semiconductor package structure of claim 1, wherein the top surfaces of the first conductive bumps are provided with solder balls. A method of fabricating a semiconductor package structure includes: providing a wafer having a first surface and a back surface, the wafer including a first semiconductor component extending from the first surface into the wafer The first surface of the layer is provided with a first patterned circuit layer, the first patterned circuit layer includes a plurality of first pads, wherein the first semiconductor device layer is electrically connected to the first patterned circuit layer; The first conductive bumps are respectively disposed on the first pads; a first encapsulant is formed on the first surface, and the first encapsulant covers the first conductive bumps; the back surface of the wafer Performing a thinning process to expose the wafer to a second surface; forming a second semiconductor device layer on the second surface, wherein the second semiconductor device layer extends from the second surface into the wafer; Forming a second patterned circuit layer on the second surface, the second patterned circuit layer includes a plurality of second pads, wherein the second semiconductor device layer is electrically connected to the second patterned circuit layer; Remove at least The first encapsulant to expose the top surface of a first plurality of the plurality of conductive bumps. The method for fabricating a semiconductor package structure according to claim 6, further comprising forming a plurality of second conductive bumps on the second pads of the second surface. The method for fabricating a semiconductor package structure according to claim 7, further comprising forming a second encapsulant on the second surface, the second encapsulant covering the second conductive bumps, and removing at least Part of the second encapsulant to expose a plurality of top surfaces of the second conductive bumps. The method for fabricating a semiconductor package structure according to claim 8 further includes forming solder balls on the top surfaces of the second conductive bumps. The method for fabricating a semiconductor package structure according to claim 6, further comprising forming solder balls on the top surfaces of the first conductive bumps.