TW202129860A - Semiconductor package - Google Patents

Abstract

A semiconductor package includes a first interposer, a second interposer, a first die, a second die and at least one bridge structure. The first interposer and the second interposer are embedded by a first dielectric encapsulation. The first die is disposed over and electrically connected to the first interposer. The second die is disposed over and electrically connected to the second interposer. The at least one bridge structure is disposed between the first die and the second die.

Description

Semiconductor package

The embodiment of the present invention relates to a semiconductor package and a method of forming the same.

In recent years, the semiconductor industry has experienced rapid development due to continuous improvement in the integration density of various electronic devices (such as transistors, diodes, resistors, capacitors, etc.). Mainly speaking, the continuous reduction in minimum feature size has brought about improvements in integration density, which allows more devices to be integrated into a given area.

These smaller electronic devices also require smaller packages that take up less area than previous packages. One of the promising semiconductor packages is the "chip on wafer on substrate (CoWoS)" structure used in advanced products for cloud computing, data center, and supercomputer applications. Although existing semiconductor packages are generally sufficient for their intended purpose, they are not completely satisfactory in all aspects.

According to an alternative embodiment of the present disclosure, a method of forming a semiconductor package includes the following operations. A first intermediary piece and a second intermediary piece are provided. A first redistribution layer structure is formed on the first side of the first interposer and the second interposer above the first interposer and the second interposer, wherein the first redistribution layer structure is electrically connected to the first interposer and the second interposer. Two intermediary pieces. The first die, the second die, and at least one bridge structure are placed above the first rewiring layer structure, wherein the first interposer is electrically connected to the at least one bridge structure between the first die and the second die The second intermediary. A second redistribution layer structure is formed above the first interposer and the second interposer at a second side of the first interposer and the second interposer opposite to the first side. The board base is bonded to the second redistribution layer structure.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. The following specific examples of elements and arrangements are set forth in order to convey the present disclosure in a simplified manner. Of course, these are only examples and not intended to be limiting. For example, in the following description, forming the second feature on or on the first feature may include an embodiment in which the second feature and the first feature are formed in direct contact, and may also include an embodiment in which the second feature is directly in contact with the first feature. An embodiment in which an additional feature can be formed between the feature and the first feature so that the second feature and the first feature may not directly contact. In addition, the same reference numbers and/or letters may be used in various examples of the present disclosure to refer to the same or similar components. This repeated use of reference numbers is for the sake of conciseness and clarity, and does not itself represent the relationship between the various embodiments and/or configurations discussed.

In addition, for example, "below", "below", "lower", "on", "above", "overly", "above", "below The spatial relative terms of "upper" and similar terms are used to facilitate the description of the relationship of one element or feature relative to another element or feature as shown in the figure. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated by 90 degrees or in other orientations), and the spatial relative descriptors used in this article can also be interpreted accordingly.

1A to 1R are schematic cross-sectional views of a method of forming a semiconductor package according to some embodiments. It should be understood that the present disclosure is not limited by the methods described below. Additional operations may be provided before, during, and/or after the method, and some of the operations described below may be replaced or removed for additional embodiments of the method.

Although FIGS. 1A to 1S are described with respect to the method, it should be understood that the structure disclosed in FIGS. 1A to 1S is not limited to this method, but can be used as a structure independent of the method alone.

Referring to FIG. 1A, the first intermediary piece I1 and the second intermediary piece I2 are attached to the carrier CC1. In some embodiments, the carrier CC1 comprises a glass carrier or a suitable carrier. In some embodiments, the first intermediary member I1 is attached to the carrier CC1 through the adhesive layer AL1, and the second intermediary member I2 is attached to the carrier CC1 through the adhesive layer AL2. Each of the adhesion layer AL1 and the adhesion layer AL2 may include an oxide layer, die attach tape (DAF), or a suitable adhesive.

In some embodiments, the first interposer I1 includes a first substrate S1, a first substrate through hole TSV1, and a first conductive structure CS1. The first substrate S1 may include elemental semiconductors such as silicon and germanium, and/or compound semiconductors, such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, gallium nitride, or indium phosphide. The first substrate S1 can be doped as needed. The first substrate via TSV1 (also referred to as “first silicon via” in some examples) extends from the front side of the first substrate S1 toward the back side of the first substrate S1. The first substrate through hole TSV1 may not penetrate the first substrate S1 at this stage.

In some embodiments, the first conductive structure CS1 is disposed above the front side of the first substrate S1. The first conductive structure CS1 is simply shown in FIG. 1A, and a partial enlarged view is shown on the left side of FIG. 1A. In some embodiments, the first conductive structure CS1 includes a dielectric layer and conductive features embedded in the dielectric layer. The conductive features include metal lines, metal vias, metal pads, and/or metal contacts. In some embodiments, each conductive feature includes Cu, Al, Ti, Ta, W, Ru, Co, Ni, the like, or a combination thereof. In some embodiments, a seed layer and/or barrier layer may be disposed between each conductive feature and the adjacent polymer layer. The seed layer may include Ti/Cu. The barrier layer may include Ta, TaN, Ti, TiN, CoW, or a combination thereof. In some embodiments, each dielectric layer includes silicon oxide, silicon nitride, silicon oxynitride, SiOC, the like, or a combination thereof. The etch stop layer may be inserted between two adjacent dielectric layers. The dielectric layer of the first conductive structure CS1 can be replaced with a polymer layer or an insulating layer as needed. In some embodiments, each polymer layer includes a photosensitive material, such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), the like, or a combination thereof. In some embodiments, the critical dimension of the first conductive structure CS1 close to the first substrate S1 is different (for example, smaller) than the critical dimension of the first conductive structure CS1 away from the first substrate S1. Specifically, the width of the metal line ML11 (or metal via MV11) of the first conductive structure CS1 close to the first substrate S1 is different (for example, smaller) than the metal line ML12 of the first conductive structure CS1 away from the first substrate S1 (Or metal via MV12) width. In some examples, the metal via MV11 and the metal via MV12 are referred to as the zeroth copper via. In some embodiments, the metal via MV11 and the metal via MV12 are the topmost vias, and the dielectric layer may cover the metal via MV11 and the metal via MV12.

In some embodiments, the first interposer I1 is an active interposer containing at least one functional device or integrated circuit device included in the first conductive structure CS1. In some instances, this active interposer is called a "device-containing interposer". In some embodiments, the functional device includes an active device, a passive device, or a combination thereof. Functional devices include, for example, but not limited to, transistors, capacitors, resistors, diodes, photodiodes, fuse devices, and/or other similar elements. In some embodiments, the functional device includes gate dielectric layers, gate electrodes, source/drain regions, spacers, and the like.

In other embodiments, the first intermediary I1 is a passive intermediary, which is used to indicate a lack of functional devices or integrated circuit devices. In some instances, this passive interposer is called a "device-free interposer".

In some embodiments, the second interposer I2 includes a second substrate S2, a second substrate through hole TSV2, and a second conductive structure CS2. The second substrate S2, the second substrate through hole TSV2, and the second conductive structure CS2 of the second interposer I2 can be similar to the first substrate S1, the first substrate through hole TSV1, and the first conductive structure CS1. Therefore, the materials and configurations of these elements can be Refers to the material and configuration of the first intermediate member I1, and the details are not repeated in this article.

The second substrate via TSV2 (also referred to as “second silicon via” in some examples) extends from the front side of the second substrate S2 toward the back side of the second substrate S2. The second substrate through hole TSV2 may not penetrate the second substrate S2 at this stage. In some embodiments, the second conductive structure CS2 is disposed above the front side of the second substrate S2. The second conductive structure CS2 is simply shown in FIG. 1A, and a partially enlarged view is shown on the right side of FIG. 1A. In some embodiments, the critical dimension of the second conductive structure CS2 close to the second substrate S2 is different (for example, smaller) than the critical dimension of the second conductive structure CS2 away from the second substrate S2. Specifically, the width of the metal line ML21 (or metal via MV21) of the second conductive structure CS2 close to the second substrate S2 is different from (for example, smaller than) the width of the metal line ML22 of the second conductive structure CS2 away from the second substrate S2 (Or metal via MV22) width.

In some embodiments, the second interposer I2 is an active interposer containing at least one functional device or integrated circuit device included in the second conductive structure CS2. In other embodiments, the second intermediary I2 is a passive intermediary, which is used to indicate lack of functional devices or integrated circuit devices.

In some embodiments, the first intermediary element I1 and the second intermediary element I2 are both active intermediary elements. In other embodiments, the first intermediary piece I1 and the second intermediary piece I2 are both passive intermediary pieces. In other embodiments, one of the first intermediate element I1 and the second intermediate element I2 is an active intermediate element, and the other of the first intermediate element I1 and the second intermediate element I2 is a passive intermediate element. In addition, the critical dimension of the first intermediary I1 can be similar to or different from the critical dimension of the second intermediary I2 according to design requirements.

In some embodiments, the gap width G between the first interposer I1 and the second interposer I2 does not exceed about 150 microns. For example, the gap width G between the first interposer I1 and the second interposer I2 is in the range of about 50 micrometers to 150 micrometers. Other values or ranges of the gap width G can be adopted according to process requirements.

Referring to FIG. 1B, a first dielectric sealing body E1 is formed around the first intermediary member I1 and the second intermediary member I2. Specifically, the first dielectric sealing body E1 fills the gap between the first intermediate piece I1 and the second intermediate piece I2, and covers the sidewalls and top of the first intermediate piece I1 and the second intermediate piece I2. As shown in the enlarged view of FIG. 1B, the first dielectric sealing body E1 covers the top of the first conductive structure CS1 and the top of the second conductive structure CS2. In some embodiments, the first dielectric sealing body E1 includes a molding compound, a molding underfill, a resin, or the like. In some embodiments, the first dielectric sealing body E1 includes a polymer material, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), the like, or a combination thereof. The first dielectric sealing body E1 can be formed through a molding process followed by a curing process.

1C, a grinding process is performed on the first dielectric sealing body E1. In some embodiments, according to the grinding process, the top surface of the first dielectric sealing body E1 is substantially coplanar with the top surfaces of the first interposer I1 and the second interposer I2. As shown in the enlarged view of FIG. 1C, according to the grinding process, the top surfaces of the metal via MV12 and the metal via MV22 are exposed. In some embodiments, the grinding process can remove the dielectric layer above the metal via MV12 and the metal via MV22 until the metal via MV12 and the metal via MV22 are exposed.

1D, the first redistribution layer structure RDL1 is formed above the first dielectric sealing body E1, the first interposer I1, and the second interposer I2. In some examples, the first redistribution layer structure RDL1 is referred to as a “front-side redistribution layer structure”. In some embodiments, the first redistribution layer structure RDL1 is electrically connected to the first conductive structure CS1 of the first interposer I1 and the second conductive structure CS2 of the second interposer I2. In some embodiments, the first redistribution layer structure RDL1 includes a redistribution layer embedded in a polymer layer. The rewiring layer includes metal lines, metal vias, metal pads and/or metal contacts. In some embodiments, each rewiring layer includes Cu, Al, Ti, Ta, W, Ru, Co, Ni, the like, or a combination thereof. In some embodiments, a seed layer and/or barrier layer may be disposed between each redistribution layer and an adjacent polymer layer. The seed layer may include Ti/Cu. The barrier layer may include Ta, TaN, Ti, TiN, CoW, or a combination thereof. In some embodiments, each polymer layer includes a photosensitive material, such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), the like, or a combination thereof. The polymer layer of the first redistribution layer structure RDL1 can be replaced with a dielectric layer or an insulating layer as needed.

Subsequently, the bump B1 is formed over the first redistribution layer structure RDL1 and is electrically connected to the first redistribution layer structure RDL1. In some embodiments, the bump B1 includes a solder bump, and/or may include a metal pillar (for example, a copper pillar), a solder cap formed on the metal pillar, and/or the like. In some examples, the bump B1 is referred to as a "micro bump". The bump B1 can be formed by a suitable process such as evaporation, electroplating, ball drop, or screen printing.

1E, at least one first die C1, at least one second die C2, at least one third die C3, at least one fourth die C4, and at least one bridge structure 100 are formed in the first The wiring layer structure RDL1 is electrically connected to the first rewiring layer structure RDL1 through bumps B1.

The first die C1 may include logic die, memory die, CPU, GPU, xPU, MEMS die, SoC die, or similar die. The first die C1 may include various passive microelectronic devices and active microelectronic devices, such as resistors, capacitors, inductors, fuses, diodes, and P-channel field effect transistors (PFETs) , N-channel field effect transistor (NFET), metal-oxide-semiconductor FET (MOSFET), complementary MOS (complementary MOS, CMOS) transistor, high-voltage transistor, High-frequency transistors, other suitable components or combinations thereof. Adjacent first dies C1 may have the same or different functions.

The second die C2 may include logic die, memory die, CPU, GPU, xPU, MEMS die, SoC die or similar die. The second die C2 can include various passive microelectronic devices and active microelectronic devices, such as resistors, capacitors, inductors, fuses, diodes, P-channel field effect transistors (PFET), and N-channel field effect transistors. (NFET), Metal Oxide Semiconductor FET (MOSFET), Complementary MOS (CMOS) Transistor, High Voltage Transistor, High Frequency Transistor, other suitable components or combinations thereof. The adjacent second dies C2 may have the same or different functions.

In some embodiments, the first die C1 and the second die C2 have similar functions. In other embodiments, the first die C1 and the second die C2 have different functions. In addition, according to process requirements, the size of the first die C1 may be similar to or different from the size of the second die C2. The size can be height, width, size, top view area, or a combination thereof.

The third die C3 may include a memory die or a memory stack, such as a high bandwidth memory (HBM) cube. The memory chips in the memory stack can have the same or different heights.

The fourth die C4 may include a memory die or a memory stack, such as a high-bandwidth memory (HBM) cube. The memory chips in the memory stack can have the same or different heights.

In addition, according to process requirements, the size of the third die C3 may be similar to or different from the size of the fourth die C4. The size can be height, width, size, top view area, or a combination thereof.

The bridge structure 100 is formed above the first rewiring layer structure RDL1 and between the first die C1 and the second die C2. In some embodiments, the bridge structure 100 is formed across the first dielectric sealing body E1 between the first interposer I1 and the second interposer I2. In some embodiments, the bridge structure 100 may be placed such that the first die C1, the second die C2, the third die C3, and the fourth die C4 surround the bridge structure 100. In other words, the bridge structure 100, the first die C1, the second die C2, the third die C3, and the fourth die C4 are located at the same level. In some embodiments, according to a top view, the bridge structure 100 partially overlaps at least one of the first interposer I1 and the second interposer I2.

The bridge structure 100 provides electrical wiring between different interposers, dies, or die stacks. The bridge structure 100 may include wiring patterns disposed on/in a semiconductor substrate (such as a silicon substrate). The wiring pattern includes substrate perforations, lines, vias, pads, and/or contacts. In some examples, the bridge structure 100 is referred to as a "connected structure", a "bridge die", or a "silicon bridge."

In some embodiments, the bridge structure 100 does not contain active devices (such as transistors or the like) and/or passive devices (such as resistors, capacitors, inductors, or the like). For example, the bridge structure 100 may only include wiring patterns for signal transmission and not for other functions. In some instances, this bridge structure 100 is referred to as a "device-less die". However, the present disclosure is not limited to this. In alternative embodiments, the bridge structure 100 may include active devices and/or passive devices for performing functions other than signal transmission.

Still referring to FIG. 1E, the first underfill layer UF1 is formed to fill the first redistribution layer structure RDL1 and the first die C1, the second die C2, the third die C3, the fourth die C4, and the bridge structure 100 The space between each of them, and surrounds the bump B1. In some embodiments, the first underfill layer UF1 includes a molding compound (for example, epoxy resin), and is formed using a dispensing process, an injection process, and/or an injection process.

After that, the second dielectric sealing body E2 is formed around the first die C1, the second die C2, the third die C3, the fourth die C4 and the bridge structure 100. Specifically, the second dielectric sealing body E2 fills the gaps between the adjacent dies and between the bridge structure 100 and the adjacent dies, and covers the first dies C1, the second dies C2, and the third dies. C3, the fourth die C4, and the sidewall and top of the bridge structure 100. In some embodiments, the second dielectric sealing body E2 includes a molding compound, a molding underfill, a resin, or the like. In some embodiments, the second dielectric sealing body E2 includes a polymer material, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), the like, or a combination thereof. The second dielectric sealing body E2 can be formed through a molding process followed by a curing process.

1F, the carrier CC2 is attached to the second dielectric sealing body E2. In some embodiments, the carrier CC2 includes a glass carrier or a suitable carrier. In some embodiments, the carrier CC2 is attached to the second dielectric sealing body E2 through an adhesive layer AL3. The adhesion layer AL3 may include an oxide layer, die attach tape (DAF), or a suitable adhesive.

Referring to FIG. 1G, the structure of FIG. 1F is turned over, and the carrier CC1 is peeled from the structure of FIG. 1F. In one embodiment, the lift-off process is a laser lift-off process or a suitable process.

1H, the adhesive layer AL1 and the adhesive layer AL2 are removed from the first intermediary member I1 and the second intermediary member I2, respectively. In some embodiments, the removal process is an etching process and/or a cleaning process. In some embodiments, according to the removal process of FIG. 1H, the surface of the first dielectric sealing body E1 is higher than the back sides of the first intermediary member I1 and the second intermediary member I2.

Referring to FIG. 1I, a polishing process is performed on the first dielectric sealing body E1, the first intermediary member I1, and the second intermediary member I2. In some embodiments, the first dielectric sealing body E1, the first substrate S1 of the first interposer I1, and the second substrate S2 of the second interposer I2 are thinned by a grinding process. In some embodiments, according to the polishing process of FIG. 1I, the surface of the first dielectric sealing body E1 is substantially as high as the back sides of the first intermediary member I1 and the second intermediary member I2.

1J, a polishing process is performed on the first interposer I1 and the second interposer I2 until the first substrate through hole TSV1 and the second substrate through hole TSV2 are exposed. In some embodiments, chemical mechanical polishing is performed on the first substrate S1 of the first interposer I1 and the second substrate S2 of the second interposer I2 by using the first substrate through hole TSV1 and the second substrate through hole TSV2 as a polishing stop layer (Chemical mechanical polishing, CMP) process. In some embodiments, according to the polishing process of FIG. 1J, the surface of the first dielectric sealing body E1 is higher than the back sides of the first interposer I1 and the second interposer I2.

1K, a recessing process is performed on the first substrate S1 of the first interposer I1 and the second substrate S2 of the second interposer I2 until the surfaces of the first substrate S1 and the second substrate S2 are perforated with respect to the first substrate TSV1 and The surface of the second substrate through hole TSV2 is recessed. Specifically, the bottom portions of the first substrate through hole TSV1 and the second substrate through hole TSV2 are exposed by the first substrate S1 and the second substrate S2, respectively. In some embodiments, the recessing process includes an etch-back process or a suitable process.

After that, the insulating layer IL is conformally formed over the first interposer I1, the second interposer I2, and the first dielectric sealing body E1. In some embodiments, the insulating layer IL includes a polymer material, such as polybenzoxazole (PBO), polyimide (PI), or the like. In other embodiments, the insulating layer IL includes an inorganic material, such as silicon oxide, silicon nitride, silicon oxynitride, or any suitable dielectric material.

1L, a grinding process and a polishing process are performed on the insulating layer IL and the first dielectric sealing body E1 until the first substrate through hole TSV1 and the second substrate through hole TSV2 are exposed. In some embodiments, a wheel milling process is performed on the insulating layer IL and the first dielectric sealing body E1, and then the insulating layer IL and the second substrate through hole TSV1 and TSV2 are used as a polishing stop layer. The first dielectric sealing body E1 performs a chemical mechanical polishing (CMP) process. In some embodiments, according to the grinding process and polishing process of FIG. 1L, the surface of the first dielectric sealing body E1 and the surface of the first substrate through hole TSV1, the surface of the second substrate through hole TSV2, the surface of the first insulating layer IL1, and The surfaces of the second insulating layer IL2 are substantially coplanar. Specifically, the bottom portion of the first base through hole TSV1 is surrounded by the first insulating layer IL1, and the bottom portion of the second base through hole TSV2 is surrounded by the second insulating layer IL2. In some embodiments, the first insulating layer IL2 is regarded as a part of the first interposer I1, and the second insulating layer IL2 is regarded as a part of the second interposer IL2.

1M, the second rewiring layer structure RDL2 is formed above the first dielectric sealing body E1, the first interposer I1, and the second interposer I2. In some examples, the second redistribution layer structure RDL2 is referred to as a "backside redistribution layer structure". The second redistribution layer structure RDL2 is electrically connected to the first base through hole TSV1 of the first interposer I1 and the second base through hole TSV2 of the second interposer I2. In some embodiments, the second redistribution layer structure RDL2 includes a redistribution layer embedded in a polymer layer. The rewiring layer includes metal lines, metal vias, metal pads and/or metal contacts. In some embodiments, each rewiring layer includes Cu, Al, Ti, Ta, W, Ru, Co, Ni, the like, or a combination thereof. In some embodiments, a seed layer and/or barrier layer may be disposed between each redistribution layer and an adjacent polymer layer. The seed layer may include Ti/Cu. The barrier layer may include Ta, TaN, Ti, TiN, CoW, or a combination thereof. In some embodiments, each polymer layer includes a photosensitive material, such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), the like, or a combination thereof. The polymer layer of the second rewiring layer structure RDL2 can be replaced with a dielectric layer or an insulating layer as needed.

In some embodiments, the critical dimension of the second rewiring layer structure RDL2 is different from (for example, greater than) the critical dimension of the first rewiring layer structure RDL1. Specifically, the width of the metal lines, metal vias, metal pads, or metal contacts of the second rewiring layer structure RDL2 is different from (for example, greater than) the metal lines, metal vias, metal contacts of the first rewiring layer structure RDL1. The width of the pad or metal contact.

Referring to FIG. 1N, a polymer pattern PM is formed over the second rewiring layer RDL2. In some embodiments, each polymer pattern includes a photosensitive material, such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), the like, or a combination thereof. In some embodiments, the polymer pattern PM is a plurality of individual ring patterns.

Referring to FIG. 10, bumps B2 are formed over the second rewiring layer structure RDL2 and are electrically connected to the second rewiring layer structure RDL2. In some embodiments, each bump B2 is disposed in the corresponding polymer pattern PM and is in physical contact with the corresponding polymer pattern PM. In some embodiments, the bump B2 includes a solder bump, and/or may include a metal pillar (for example, a copper pillar), a solder cap formed on the metal pillar, and/or the like. In some examples, the bump B2 is referred to as a "controlled collapse chip connection (C4) bump". The bump B2 can be formed by a suitable process such as evaporation, electroplating, ball drop, or screen printing.

1P, a wafer tape T is attached to the second rewiring layer structure RDL2 and bump B2. In some embodiments, the wafer tape T includes PVC, polyolefin, polyethylene, or other suitable materials.

After that, the carrier CC2 is peeled off from the second dielectric sealing body E2. In one embodiment, the lift-off process is a laser lift-off process or a suitable process. Next, the adhesive layer AL3 is removed from the second dielectric sealing body E2. In some embodiments, the removal process is an etching process and/or a cleaning process.

Referring to FIG. 1Q, the structure of FIG. 1P is turned over, and a polishing process is performed on the second dielectric sealing body E2. In some embodiments, according to the polishing process of FIG. 1Q, the top surface of the second dielectric sealing body E2 is in contact with the first die C1, the second die C2, the third die C3, the fourth die C4, and the bridge die. The top surface of the pellet 100 is substantially coplanar.

1R, a wafer dicing process is performed on the structure of FIG. 1Q along the cutting line CL to cut through the second dielectric sealing body E2, the first redistribution layer structure RDL1, the first dielectric sealing body E1, and the second heavy Wiring layer structure RDL2. After the wafer dicing process or the singulation process, adjacent semiconductor packages PK are separated from each other.

1S, a board substrate 200 is formed under the second rewiring layer structure RDL2 and electrically connected to the second rewiring layer structure RDL2. In some embodiments, the board substrate 200 is bonded to the second rewiring layer structure RDL2 through bumps B2.

In some embodiments, the board substrate 200 includes a core layer and two stacked layers on opposite sides of the core layer. In some embodiments, the core layer includes a prepreg (which contains epoxy, resin, and/or glass fiber), polyimide, photo image dielectric (PID), the like, or a combination thereof . In some embodiments, the build-up layer comprises prepreg (which contains epoxy resin, resin and/or glass fiber), polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), Nitride (such as silicon nitride), oxide (such as silicon oxide), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass ( boron-doped phosphosilicate glass, BPSG), analogs or combinations thereof. The material of the core layer may be different from the material of the build-up layer. In some embodiments, the board substrate 200 includes a wire pattern 202 that penetrates the core layer and the build-up layer to provide electrical wiring between different interposers, dies, or die stacks. The wire pattern 202 includes lines, vias, pads, and/or contacts. In some examples, the board substrate 200 is referred to as a “printed circuit board (PCB)”. In other embodiments, the core layer of the board substrate 200 may be omitted as needed, and this board substrate 200 is referred to as a "core-free board substrate".

After that, the second underfill material layer UF2 is formed to fill the space between the second redistribution layer structure RDL2 and the board substrate 200 and surround the bump B2. In some embodiments, the second underfill layer UF2 includes a molding compound (for example, epoxy resin), and is formed using a dispensing process, an injection process, and/or an injection process.

Subsequently, the bump B3 is formed under the board substrate 200 and is electrically connected to the board substrate 200. In some embodiments, each bump B3 is electrically connected to the wire pattern 202 of the board substrate 200. In some embodiments, the bump B3 includes a solder bump, and/or may include a metal pillar (for example, a copper pillar), a solder cap formed on the metal pillar, and/or the like. In some examples, the bump B3 is referred to as a "ball grid array (BGA) ball". The bump B3 can be formed by a suitable process such as evaporation, electroplating, ball drop, or screen printing. In some embodiments, the semiconductor package 10 of the present disclosure is thus completed.

FIG. 2 is a schematic top view of a semiconductor package according to some embodiments. For simplicity and clarity of description, only a few elements are shown in the top view of FIG. 2. In some embodiments, FIG. 1S is a cross-sectional view of the semiconductor package along the line I-I of FIG. 2.

1S and FIG. 2, the semiconductor package 10 includes a first interposer I1 and a second interposer I2 embedded in a first dielectric sealing body E1. The semiconductor package 10 further includes a first die C1 disposed above the first interposer I1 and electrically connected to the first interposer I1, and a second die C1 disposed above the second interposer I2 and electrically connected to the second interposer I2. Die C2. The semiconductor package 10 further includes a bridge structure 100 disposed above the first interposer I1 and the second interposer I2 and partially overlapping the first interposer I1 and the second interposer I2. The bridge structure is arranged between the first die C1 and the second die C2. In some embodiments, the semiconductor package 10 further includes a plurality of third dies C3 disposed above the first interposer I1 and beside the first die C1, and a plurality of third dies C3 disposed above the second interposer I2 and next to the second interposer I2. A plurality of fourth dies C4 beside the die C2. In some embodiments, the third crystal grain C3 is located on both sides of the first crystal grain C1, and the fourth crystal grain C4 is located on both sides of the second crystal grain C2. In some embodiments, the semiconductor package 10 further includes a board substrate 200 disposed under the first interposer I1 and the second interposer I2.

For a larger reticle size CoWoS process, particles on the reticle will damage the yield. In some embodiments of the present disclosure, the interposer is configured as chiplets with a smaller size, and the semiconductor die is disposed above the interposer and passes through at least one bridge between the semiconductor die and the underlying interposer The structures are electrically connected to each other. In this way, the production yield can be significantly improved. In some embodiments, since the interposer of the present disclosure is a small chip, rather than a conventional monolithic interposer, the semiconductor package of the present disclosure is referred to as a "chip on fan-out on substrate. , CoFoS)” structure.

The top view configuration of Figure 2 can be modified as needed. Several examples are provided below for illustrative purposes, and the examples are not construed as limiting the scope of the present disclosure. The ordinary skilled person should understand that other top view configurations of the semiconductor package are possible.

In some embodiments, as shown in FIG. 3, four first dies C1 are provided on one side of one bridge structure 100, and four second dies C1 are provided on the other side of the same bridge structure 100 C2. In some embodiments, FIG. 1S is a cross-sectional view of the semiconductor package along the line I-I of FIG. 3.

In some embodiments, as shown in FIG. 4, a first die C1 is provided on one side of two bridge structures 100, and a second die C2 is provided on the other side of the same bridge structure 100 . In some embodiments, FIG. 1S is a cross-sectional view of the semiconductor package along the line I-I of FIG. 4.

In some embodiments, as shown in FIG. 5, two first die C1 are provided on one side of two bridge structures 100, and one second die is provided on the other side of the same bridge structure 100 C2. In some embodiments, FIG. 1S is a cross-sectional view of the semiconductor package along the line I-I of FIG. 5.

In view of the foregoing, the number of bridge structures and the number of semiconductor dies on both sides of the bridge structure can be adjusted according to process requirements. In addition, the number of semiconductor dies (for example, the first dies to the fourth dies) at both sides of the bridge structure may be the same or different according to process requirements. In some embodiments, the edge of the bridge structure is substantially aligned with the edge of the adjacent semiconductor die, as shown in FIGS. 2 and 3. In other embodiments, the edge of the bridge structure is not aligned with the edge of the adjacent semiconductor die, as shown in FIGS. 4 and 5. For example, the edge of the bridge structure may be recessed relative to the edge of the adjacent semiconductor die. Alternatively, at least a portion of the bridge structure may extend beyond the edge of the adjacent semiconductor die.

FIG. 6 illustrates a method of forming a semiconductor package according to some embodiments. Although the method is illustrated and/or described as a series of actions or events, it should be understood that the method is not limited to the illustrated order or actions. Therefore, in some embodiments, the actions may be performed in a different order than illustrated, and/or may be performed simultaneously. In addition, in some embodiments, the described actions or events can be subdivided into multiple actions or events, which can be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some illustrated actions or events may be omitted, and other unillustrated actions or events may be included.

At act 302, a first intermediary piece and a second intermediary piece are set. FIG. 1A shows a cross-sectional view of some embodiments corresponding to act 302.

At act 304, a first redistribution layer structure is formed over the first interposer and the second interposer at the first side of the first interposer and the second interposer, wherein the first redistribution layer structure is electrically connected to the first interposer. An intermediary piece and a second intermediary piece. In some embodiments, the first side is the front side of the first intermediary member and the second intermediary member. FIGS. 1B to 1D show cross-sectional views of some embodiments corresponding to act 304.

At act 306, the first die, the second die, and at least one bridge structure are placed above the first redistribution layer structure, wherein the first interposer passes through at least one of the first die and the second die. The bridge structure is electrically connected to the second interposer. FIG. 1E shows a cross-sectional view of some embodiments corresponding to act 306. The order of placing the first die, the second die, and the at least one bridge structure is not limited by the present disclosure. In some embodiments, the first die corresponds to the first interposer and is electrically connected to the first interposer, and the second die corresponds to the second interposer and is electrically connected to the second interposer.

At act 308, the third die and the fourth die are placed above the first rewiring layer structure, where the third die corresponds to the first interposer and is electrically connected to the first interposer, and the fourth die Corresponding to the second intermediate member and electrically connected to the second intermediate member. FIG. 1E shows a cross-sectional view of some embodiments corresponding to act 308. In some embodiments, the third die and the first die provide different functions and are located at the same side, and the fourth die and the second die provide different functions and are located at the same side. The order of placing the third die and the fourth die is not limited by the present disclosure. In addition, the order of action 306 and action 308 can be exchanged as needed. In some embodiments, action 308 is optional and can be omitted as needed.

At 310, a second redistribution layer structure is formed over the first interposer and the second interposer at a second side of the first interposer and the second interposer opposite to the first side. In some embodiments, the second side is the back side of the first intermediary member and the second intermediary member. 1F to 1M show cross-sectional views of some embodiments corresponding to act 310.

At 312, the board base is bonded to the second redistribution layer structure. FIGS. 1N to 1S show cross-sectional views of some embodiments corresponding to act 312.

The semiconductor package of FIG. 1S can be modified according to process requirements. 7 to 10 are cross-sectional views of various semiconductor packages according to alternative embodiments. The semiconductor packages of FIGS. 7 to 10 are beneficial to reduce cost and/or size. The differences between the semiconductor packages are described in detail below, and the similarities are not repeated herein.

The semiconductor package 11 of FIG. 7 is similar to the semiconductor package 10 of FIG. 1S, and the difference therebetween is: the semiconductor package 10 of FIG. The package 11 omits the first rewiring layer structure RDL1. Specifically, in the semiconductor package 11 of FIG. 7, the first die C1 and the third die C3 are in physical contact with the first interposer I1, and the second die C2 and the fourth die C4 are in physical contact with the second interposer. I2 is in physical contact, and the bridge structure 100 is in physical contact with each of the first intermediary I1 and the second intermediary I2. In some embodiments, when the first dielectric sealing body E1 and the second dielectric sealing body E2 are made of the same material, the interface between the first dielectric sealing body E1 and the second dielectric sealing body E2 may be Invisible. In some examples, the first dielectric sealing body E1 and the second dielectric sealing body E2 may be regarded as a single molding layer.

The semiconductor package 12 of FIG. 8 is similar to the semiconductor package 10 of FIG. 1S, and the difference therebetween is: the semiconductor package 10 of FIG. The package 12 omits the second rewiring layer structure. Specifically, in the semiconductor package 12 of FIG. 8, the bump B2 is in physical contact with the first base through hole TSV1 of the first interposer I1 and the second base through hole TSV2 of the second interposer I2.

The semiconductor package 13 of FIG. 9 is similar to the semiconductor package 10 of FIG. 1S, and the difference therebetween is: the semiconductor package 10 of FIG. 1S is provided with a first rewiring layer structure RDL1 and a second rewiring layer RDL2, but optional Ground, the first rewiring layer structure RDL1 and the second rewiring layer RDL2 are omitted from the semiconductor package 13 of FIG. 9. Specifically, in the semiconductor package 13 of FIG. 9, the first die C1 and the third die C3 are in physical contact with the first interposer I1, and the second die C2 and the fourth die C4 are in physical contact with the second interposer. I2 is in physical contact, and the bridge structure 100 is in physical contact with each of the first intermediary I1 and the second intermediary I2. In addition, in the semiconductor package 13 of FIG. 9, the bump B2 is in physical contact with the first base through hole TSV1 of the first interposer I1 and the second base through hole TSV2 of the second interposer I2.

The semiconductor package 14 of FIG. 10 is similar to the semiconductor package 10 of FIG. 1S, and the difference therebetween is: the semiconductor package 10 of FIG. Optionally, the first redistribution layer structure RDL1, bump B2, and the board substrate 200 are omitted from the semiconductor package 14 of FIG. 10. Specifically, the bump B3 is in physical contact with the second redistribution layer structure RDL2.

Hereinafter, the semiconductor package of the present disclosure is described with reference to FIGS. 1S, FIGS. 2 to 5, and FIGS. 7 to 10. It should be understood that the present disclosure is not limited by the structure described below. For additional embodiments of the structure, additional features may be added to the structure, and some of the features described below may be replaced or removed.

In some embodiments, the semiconductor package 10/11/12/13/14 includes a first interposer I1, a second interposer I2, a first die C1, a second die C2, and at least one bridge structure 100. The first intermediate piece I1 and the second intermediate piece I2 are embedded in the first dielectric sealing body E1. The first die C1 is disposed above the first interposer I1 and is electrically connected to the first interposer I1. The second die C2 is disposed above the second interposer I2 and is electrically connected to the second interposer I2. At least one bridge structure 100 is disposed between the first die C1 and the second die C2.

In some embodiments, the semiconductor package 10/11/12/13/14 further includes a second dielectric sealing body E2 surrounding the first die C1 and the second die C2. The material contained in the second dielectric sealing body E2 may be the same as or different from the material contained in the first dielectric sealing body E1.

In some embodiments, the semiconductor package 10/12 further includes a first rewiring layer structure disposed between the first interposer I1 and the first die C1 and between the second interposer I2 and the second die C2 RDL1.

In some embodiments, the first die C1 and the second die C2 are disposed on the first side (for example, the front side) of the first interposer I1 and the second interposer I2, and the semiconductor package 10/11/14 further It includes a second redistribution layer structure RDL2 disposed at a second side (for example, the back side) opposite to the first side (for example, the front side) of the first interposer I1 and the second interposer I2.

In some embodiments, the first die C1 and the second die C2 are disposed at the first side (for example, the front side) of the first interposer I1 and the second interposer I2, and the semiconductor package 10/11/12/ 13 further includes a board base 200 disposed at a second side (for example, the back side) opposite to the first side (for example, the front side) of the first intermediate part I1 and the second intermediate part I2.

In some embodiments, the semiconductor package 10 further includes a first rewiring layer structure RDL1 disposed between the first interposer I1 and the first die C1 and between the second interposer I2 and the second die C2, And a second rewiring layer structure RDL2 disposed between the board substrate 200 and each of the first interposer I1 and the second interposer I2. In some embodiments, the critical dimension of the second rewiring layer structure RDL2 is greater than the critical dimension of the first rewiring layer structure RDL1.

In some embodiments, the semiconductor package further includes bumps B1 disposed between the first redistribution layer structure RDL1 and each of the first die C1, the second die C2, and the bridge structure 100. In some embodiments, the semiconductor package further includes bumps B2 disposed between the second redistribution layer structure RDL2 and the board substrate 200. In some embodiments, the semiconductor package further includes a bump B3 disposed at the side of the board substrate 200 opposite to the bump B2. In some embodiments, the size of the bump B3 is larger than the size of the bump B2, and the size of the bump B2 is larger than the size of the bump B1. The size can be height, width, size, top view area, or a combination thereof.

In some embodiments, as shown in FIG. 1S, according to process requirements, the first dielectric sealing body E1 (between the first interposer and the second interposer) located between the bridge structure 100 and the underlying one can be omitted B1 in the middle area R1. In some embodiments, as shown in FIG. 1S, according to process requirements, the first dielectric sealing body E1 (between the first interposer and the second interposer) located between the board substrate 200 and the overlying B2 in the middle area R2.

In some embodiments (not shown), the semiconductor package further includes a through dielectric via (TDV) at the same level as the first interposer I1 and the second interposer I2. For example, the dielectric through hole penetrates the first dielectric sealing body E1, and is located beside the first interposer I1 and the second interposer I2, and is used to provide between the die or die stack or between the die and the board substrate Electrical wiring between. The dielectric perforation can penetrate the first dielectric sealing body E1 between the first intermediary member I1 and the second intermediary member I2. The dielectric perforation can penetrate the first dielectric sealing body E1 at the outer side of the first intermediary member I1 and the second intermediary member I2.

In some embodiments, each of the first intermediary I1 and the second intermediary I2 is a passive intermediary. In some embodiments, each of the first intermediary I1 and the second intermediary I2 is an active intermediary. In some embodiments, the width of the gap between the first intermediary member I1 and the second intermediary member I2 is substantially equal to or less than about 150 microns.

In some embodiments, the first interposer I1 includes a first substrate through hole TSV1 and a first conductive structure CS1 above the first substrate through hole TSV1, and the first conductive structure CS1 is electrically connected to the first die C1. In some embodiments, the second interposer I2 includes a second substrate through hole TSV2 and a second conductive structure CS2 above the second substrate through hole TSV2, and the second conductive structure CS2 is electrically connected to the second die C2.

In some embodiments, the critical dimension of the first conductive structure CS1 close to the first crystal grain C1 is larger than the critical dimension of the first conductive structure CS1 far away from the first crystal grain C1. In some embodiments, the critical dimension of the second conductive structure CS2 close to the second crystal grain C2 is greater than the critical dimension of the second conductive structure CS2 far away from the second crystal grain C2.

In some embodiments, the semiconductor package 10/11/12/13/14 further includes a third die C3 disposed above the first interposer I1 and beside the first die C1, and a third die C3 disposed on the second interposer The fourth die C4 above I2 and beside the second die C2. In some embodiments, the first die C1 and the second die C2 are SoC die, and the third die C3 and the fourth die C4 are memory die.

In some embodiments, at least one bridge structure 100 is a deviceless die. In some embodiments, at least one bridging structure 100 partially overlaps each of the first interposer I1 and the second interposer I2. However, the present disclosure is not limited to this. In other embodiments (not shown), at least one of the plurality of bridge structures 100 may only partially overlap with one of the first intermediary member I1 and the second intermediary member I2 due to space constraints. In other embodiments, at least one of the plurality of bridging structures 100 may partially overlap the first dielectric sealing body E1 between the first interposer I1 and the second interposer I2.

In the above-described embodiments, at least one bridge structure is configured to provide electrical wiring between individual interposers, and thus between individual semiconductor dies. However, the present disclosure is not limited to this. In other embodiments, the bridge structure may be omitted, and one of the semiconductor dies provides a function similar to the bridge structure. In some instances, such semiconductor dies are referred to as "device-containing bridge dies."

FIG. 11 is a cross-sectional view of a semiconductor package according to other embodiments. The structure of FIG. 11 is similar to the structure of FIG. 1S, so the differences therebetween are described in detail below and the similarities are not repeated herein. The materials and configurations of the elements of FIG. 11 may refer to the materials and configurations of similar elements described in the foregoing embodiments.

FIG. 12 is a schematic top view of a semiconductor package according to other embodiments. For simplicity and clarity of description, only a few elements are shown in the top view of FIG. 12. In some embodiments, FIG. 11 is a cross-sectional view of the semiconductor package along the line I-I of FIG. 12.

11 and 12, the semiconductor package 20 includes a first interposer I1 and a second interposer I2 embedded in a first dielectric sealing body E1. The semiconductor package 20 further includes a first die C1 disposed above the first interposer I1 and electrically connected to the first interposer I1, and a second die C1 disposed above the second interposer I2 and electrically connected to the second interposer I2. Die C2. One of the first die C1 and the second die C2 (for example, the second die C2 in this example) is configured to electrically connect the first interposer I1 to the second interposer I2. Specifically, the second die C2 is formed above the second intermediate member I2, crosses the first dielectric sealing body E1 between the first intermediate member I1 and the second intermediate member I2 laterally, and extends to the first intermediate member I1 superior. In some embodiments, the semiconductor package 20 further includes a plurality of third dies C3 disposed above the first interposer I1 and beside the first die C1, and a plurality of third dies C3 disposed above the second interposer I2 and next to the second interposer I2. A plurality of fourth dies C4 beside the die C2. In some embodiments, the third crystal grain C3 is located on both sides of the first crystal grain C1, and the fourth crystal grain C4 is located on both sides of the second crystal grain C2. In some embodiments, the semiconductor package 20 further includes a board substrate 200 disposed under the first interposer I1 and the second interposer I2.

In some embodiments of the present disclosure, the interposer is configured as a small chip with a smaller size, and the semiconductor die is disposed above the interposer and is electrically connected to each other through at least one of the semiconductor die and the underlying interposer. In this way, the production yield can be significantly improved. In some embodiments, since the interposer of the present disclosure is a small chip, rather than a conventional monolithic interposer, the semiconductor package of the present disclosure is referred to as a "fan-out chip on substrate (CoFoS)" structure.

The top view configuration of Figure 12 can be modified as needed. A modified example is provided below for illustrative purposes, and the modified example is not construed as limiting the scope of the present disclosure. The ordinary skilled person should understand that other top view configurations of the semiconductor package are possible.

In some embodiments, as shown in FIG. 13, four first dies C1 are disposed above the first interposer I1, and two second dies C2 are disposed above the second interposer I2 and extend to the first interposer I2. An intermediary piece I1 is on. In some embodiments, FIG. 11 is a cross-sectional view of the semiconductor package along the line I-I of FIG. 13.

In view of the foregoing, the number of semiconductor dies (for example, the first to fourth dies) at the two opposite sides may be the same or different according to process requirements.

The method of forming the semiconductor package 20 is similar to the method of forming the semiconductor package 10 described in FIGS. 1A to 1S, except that the bridge structure is omitted during the die pick-and-place operation of FIG. 1E. Specifically, the second die C2 of the semiconductor package 20 provides the function of the bridge structure 100 of the semiconductor package 10.

FIG. 14 shows a method of forming a semiconductor package according to other embodiments. Although the method is illustrated and/or described as a series of actions or events, it should be understood that the method is not limited to the illustrated order or actions. Therefore, in some embodiments, the actions may be performed in a different order than illustrated, and/or may be performed simultaneously. In addition, in some embodiments, the described actions or events can be subdivided into multiple actions or events, which can be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some illustrated actions or events may be omitted, and other unillustrated actions or events may be included.

At act 402, a first mediator and a second mediator are set.

At act 404, a first redistribution layer structure is formed over the first interposer and the second interposer at the first side of the first interposer and the second interposer, wherein the first redistribution layer structure is electrically connected to the first interposer. An intermediary piece and a second intermediary piece. In some embodiments, the first side is the front side of the first intermediary member and the second intermediary member.

At act 406, the first die and the second die are placed above the first redistribution layer structure, wherein the first interposer is electrically connected to the second interposer through the second die. The order of placing the first die and the second die is not limited by the present disclosure. In some embodiments, the first die corresponds to the first intermediate member and is electrically connected to the first intermediate member, and the second die corresponds to the second intermediate member and is electrically connected to the first intermediate member and the second intermediate member.

At act 408, the third die and the fourth die are placed above the first rewiring layer structure, where the third die corresponds to the first interposer and is electrically connected to the first interposer, and the fourth die Corresponding to the second intermediate member and electrically connected to the second intermediate member. In some embodiments, the third die and the first die provide different functions and are located at the same side, and the fourth die and the second die provide different functions and are located at the same side. The order of placing the third die and the fourth die is not limited by the present disclosure. In addition, the order of action 406 and action 408 can be exchanged as needed. In some embodiments, action 408 is optional and can be omitted as needed.

At act 410, a second redistribution layer structure is formed over the first interposer and the second interposer at a second side of the first interposer and the second interposer opposite to the first side. In some embodiments, the second side is the back side of the first intermediary member and the second intermediary member.

At act 412, the board substrate is bonded to the second redistribution layer structure.

The semiconductor package of FIG. 11 can be modified according to process requirements. 15 to 18 are cross-sectional views of various semiconductor packages according to alternative embodiments. The semiconductor packages of FIGS. 15 to 18 are advantageous for reducing cost and/or size. The differences between the semiconductor packages are described in detail below, and the similarities are not repeated herein.

The semiconductor package 21 of FIG. 15 is similar to the semiconductor package 20 of FIG. 11, and the difference therebetween is: the semiconductor package 20 of FIG. The package 21 omits the first rewiring layer structure RDL1. Specifically, in the semiconductor package 21 of FIG. 15, the first die C1 and the third die C3 are in physical contact with the first interposer I1, and the second die C2 is in contact with the first interposer I1 and the second interposer. I2 is in physical contact, and the fourth die C4 is in physical contact with the second intermediary I2.

The semiconductor package 22 of FIG. 16 is similar to the semiconductor package 20 of FIG. 11, and the difference therebetween is: the semiconductor package 20 of FIG. The package 22 omits the second rewiring layer structure RDL2. Specifically, in the semiconductor package 22 of FIG. 16, the bump B2 is in physical contact with the first base through hole TSV1 of the first interposer I1 and the second base through hole TSV2 of the second interposer I2.

The semiconductor package 23 of FIG. 17 is similar to the semiconductor package 20 of FIG. 11, and the difference therebetween is that the semiconductor package 20 of FIG. 11 is provided with a first rewiring layer structure RDL1 and a second rewiring layer RDL2, but optional Ground, the first rewiring layer structure RDL1 and the second rewiring layer RDL2 are omitted from the semiconductor package 23 of FIG. 17. Specifically, in the semiconductor 23 of FIG. 17, the first die C1 and the third die C3 are in physical contact with the first interposer I1, and the second die C2 is in physical contact with the first interposer I1 and the second interposer I2. And the fourth die C4 is in physical contact with the second interposer I2. In addition, in the semiconductor package 23 of FIG. 17, the bump B2 is in physical contact with the first base through hole TSV1 of the first interposer I1 and the second base through hole TSV2 of the second interposer I2.

The semiconductor package 24 of FIG. 18 is similar to the semiconductor package 20 of FIG. 11, and the difference therebetween is: the semiconductor package 20 of FIG. Optionally, the first rewiring layer structure RDL1, bump B2, and board substrate 200 are omitted from the semiconductor package 24 of FIG. 18. Specifically, the bump B3 is in physical contact with the second redistribution layer structure RDL2.

Hereinafter, the semiconductor package of the present disclosure will be described with reference to FIGS. 11 to 13 and FIGS. 15 to 18. It should be understood that the present disclosure is not limited by the structure described below. For additional embodiments of the structure, additional features may be added to the structure, and some of the features described below may be replaced or removed.

In some embodiments, the semiconductor package 20/21/22/23 includes a board substrate 200, a first interposer I1, a second interposer I2, a first die C1, and a second die C2. In some embodiments, the board substrate 200 includes a core layer and two stacked layers on opposite sides of the core layer. In other embodiments, the core layer of the board substrate 200 may be omitted as needed, and this board substrate 200 is referred to as a "core-free board substrate". The first intermediate piece I1 and the second intermediate piece I2 are arranged above the board base 200. The first die C1 is arranged above the first interposer I1. The second die C2 is arranged above the second interposer I2 and extends to the first interposer I1. In some embodiments, the second die C2 partially overlaps each of the first interposer I1 and the second interposer I2.

In some embodiments, the semiconductor package 20/21/22/23/24 further includes a first dielectric sealing body E1 surrounding the first interposer I1 and the second interposer I2, and surrounding the first die C1 and the second interposer. A second dielectric sealing body E2 of two crystal grains C2. The material contained in the second dielectric sealing body E2 may be the same as or different from the material contained in the first dielectric sealing body E1.

In some embodiments, the semiconductor package 20/22 further includes a first rewiring layer structure disposed between the first interposer I1 and the first die C1 and between the second interposer I2 and the second die C2 RDL1.

In some embodiments, the semiconductor package 20/21/24 further includes a second redistribution layer structure RDL2 disposed between the board substrate 200 and each of the first interposer I1 and the second interposer I2.

In some embodiments, the critical dimension of the second rewiring layer structure RDL2 is greater than the critical dimension of the first rewiring layer structure RDL1.

In some embodiments, the semiconductor package further includes bumps B1 disposed between the first rewiring layer structure RDL1 and each of the first die C1 and the second die C2. In some embodiments, the semiconductor package further includes bumps B2 disposed between the second redistribution layer structure RDL2 and the board substrate 200. In some embodiments, the semiconductor package further includes a bump B3 disposed at the side of the board substrate 200 opposite to the bump B2. In some embodiments, the size of the bump B3 is larger than the size of the bump B2, and the size of the bump B2 is larger than the size of the bump B1. The size can be height, width, size, top view area, or a combination thereof.

In some embodiments, as shown in FIG. 11, according to process requirements, the second die C2 and the underlying first dielectric sealing body E1 (between the first interposer and the second interposer) can be omitted. ) B1 in the area between R1. In some embodiments, as shown in FIG. 11, according to process requirements, the first dielectric sealing body E1 (between the first interposer and the second interposer) located between the board substrate 200 and the overlying B2 in the middle area R2.

In some embodiments (not shown), the semiconductor package further includes a dielectric via (TDV) at the same level as the first interposer I1 and the second interposer I2. For example, the dielectric through hole penetrates the first dielectric sealing body E1, and is located beside the first interposer I1 and the second interposer I2, and is used to provide between the die or die stack or between the die and the board substrate Electrical wiring between. The dielectric perforation can penetrate the first dielectric sealing body E1 between the first intermediary member I1 and the second intermediary member I2. The dielectric perforation can penetrate the first dielectric sealing body E1 at the outer side of the first intermediary member I1 and the second intermediary member I2.

In some embodiments, each of the first intermediary I1 and the second intermediary I2 is a passive intermediary. In some embodiments, each of the first intermediary I1 and the second intermediary I2 is an active intermediary. In some embodiments, the width of the gap between the first intermediary member I1 and the second intermediary member I2 is substantially equal to or less than about 150 microns.

In some embodiments, the first interposer I1 includes a first substrate through hole TSV1 and a first conductive structure CS1 above the first substrate through hole TSV1, and the first conductive structure CS1 is electrically connected to the first die C1. In some embodiments, the second interposer I2 includes a second substrate through hole TSV2 and a second conductive structure CS2 above the second substrate through hole TSV2, and the second conductive structure CS2 is electrically connected to the second die C2.

In some embodiments, the critical dimension of the first conductive structure CS1 close to the first crystal grain C1 is larger than the critical dimension of the first conductive structure CS1 far away from the first crystal grain C1. In some embodiments, the critical dimension of the second conductive structure CS2 close to the second crystal grain C2 is greater than the critical dimension of the second conductive structure CS2 far away from the second crystal grain C2.

In some embodiments, the semiconductor package 20/21/22/23/24 further includes a third die C3 disposed above the first interposer I1 and beside the first die C1, and a third die C3 disposed on the second interposer The fourth die C4 above I2 and beside the second die C2. In some embodiments, the first die C1 and the second die C2 are SoC die, and the third die C3 and the fourth die C4 are memory die.

In view of the foregoing, in some embodiments of the present disclosure, the interposer is provided as a small chip with a smaller size, and the semiconductor die is disposed above the interposer and is electrically connected to each other through at least one bridge structure or one of the semiconductor die . In some embodiments, the intermediary of the present disclosure undergoes a testing process before the pick-and-place operation of the intermediary, so all the intermediaries of the present disclosure are known good intermediaries. In this way, the production yield can be significantly improved, and the production cost can be greatly reduced.

This disclosure covers many variations of the above examples. It should be understood that different embodiments may have different advantages, and not all embodiments must require specific advantages.

According to some embodiments of the present disclosure, a semiconductor package includes a first interposer, a second interposer, a first die, a second die, and at least one bridge structure. The first intermediate member and the second intermediate member are embedded in the first dielectric sealing body. The first die is arranged above the first intermediate member and is electrically connected to the first intermediate member. The second die is arranged above the second interposer and is electrically connected to the second interposer. At least one bridge structure is disposed between the first die and the second die.

In some embodiments, it further includes a first redistribution layer structure disposed between the first interposer and the first die, and between the second interposer and the Between the second crystal grains. In some embodiments, the first die and the second die are disposed at the first side of the first interposer and the second interposer, and the semiconductor package further includes The second rewiring layer structure at the second side of the first interposer and the second interposer opposite to the first side. In some embodiments, the first die and the second die are disposed at the first side of the first interposer and the second interposer, and the semiconductor package further includes A board base at a second side of the first intermediate member and the second intermediate member opposite to the first side. In some embodiments, it further includes: a first redistribution layer structure disposed between the first interposer and the first die and between the second interposer and the second die; And a second redistribution layer structure is arranged between the board base and each of the first interposer and the second interposer. In some embodiments, the critical dimension of the second rewiring layer structure is greater than the critical dimension of the first rewiring layer structure. In some embodiments, each of the first intermediary and the second intermediary is a passive intermediary. In some embodiments, each of the first mediator and the second mediator is an active mediator. In some embodiments, the first interposer includes a first substrate through hole and a first conductive structure located above the first substrate through hole, and the first conductive structure is electrically connected to the first die, and The second interposer includes a second substrate through hole and a second conductive structure located above the second substrate through hole, and the second conductive structure is electrically connected to the second die. In some embodiments, the critical dimension of the first conductive structure close to the first crystal grain is greater than the critical dimension of the first conductive structure away from the first crystal grain, and wherein the second conductive structure The critical size of the structure close to the second crystal grain is larger than the critical size of the second conductive structure away from the second crystal grain. In some embodiments, it further includes: a third die disposed above the first interposer and beside the first die; and a fourth die disposed above the second interposer and at Next to the second die. In some embodiments, the at least one bridge structure is a deviceless die. In some embodiments, the at least one bridge structure partially overlaps each of the first interposer and the second interposer.

According to an alternative embodiment of the present disclosure, a method of forming a semiconductor package includes the following operations. A first intermediary piece and a second intermediary piece are provided. A first redistribution layer structure is formed on the first side of the first interposer and the second interposer above the first interposer and the second interposer, wherein the first redistribution layer structure is electrically connected to the first interposer and the second interposer. Two intermediary pieces. The first die, the second die, and at least one bridge structure are placed above the first rewiring layer structure, wherein the first interposer is electrically connected to the at least one bridge structure between the first die and the second die The second intermediary. A second redistribution layer structure is formed above the first interposer and the second interposer at a second side of the first interposer and the second interposer opposite to the first side. The board base is bonded to the second redistribution layer structure.

In an alternative embodiment, it further includes: on the first intermediate piece and the second intermediate piece at a second side of the first intermediate piece and the second intermediate piece opposite to the first side Forming a second redistribution layer structure above; and bonding the board base to the second redistribution layer structure.

According to yet another alternative embodiment of the present disclosure, a semiconductor package includes a board substrate, a first interposer, a second interposer, a first die, and a second die. The first intermediate member and the second intermediate member are arranged above the board base. The first die is arranged above the first intermediate member. The second die is arranged above the second intermediate member and extends to the first intermediate member.

In yet another alternative embodiment, it further comprises: a first rewiring layer structure, arranged between the first interposer and the first die and between the second interposer and the second die between. In yet another alternative embodiment, it further includes: a second redistribution layer structure disposed between the board base and each of the first interposer and the second interposer. In yet another alternative embodiment, it further includes: a third die disposed above the first interposing member and beside the first die; and a fourth die disposed above the second interposing member And beside the second crystal grain. In yet another alternative embodiment, it further includes: a first dielectric sealing body that surrounds the first intermediate member and the second intermediate member; and a second dielectric sealing body that surrounds the first die and the The second crystal grain.

It may also include other features and processes. For example, a test structure can be included to assist in the verification test of a 3D package or 3DIC device. The test structure may include, for example, test pads formed in the redistribution layer or on a substrate that allows testing of 3D packages or 3DIC, the use of probes and/or probe cards, and the like. The verification test can be performed on the intermediate structure as well as the final structure. In addition, the structure and method disclosed herein can be used in combination with a test method that incorporates intermediate verification of known good crystal grains to increase yield and reduce cost.

The foregoing outlines the features of several embodiments so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and those skilled in the art can make various changes and Replace and change.

10, 11, 12, 13, 14, 20, 21, 22, 23, 24: semiconductor package 100: bridge structure 200: board base 202: Wire pattern 302, 304, 306, 308, 310, 312, 402, 404, 406, 408, 410, 412: Action AL1, AL2, AL3: Adhesive layer B1, B2, B3: bump C1: The first die C2: second die C3: third grain C4: Fourth die CC1, CC2: Carrier CL: cutting line CS1: The first conductive structure CS2: second conductive structure E1: The first dielectric sealing body E2: Second dielectric sealing body G: gap width I1: The first intermediary I2: The second intermediary IL: insulating layer IL1: first insulating layer IL2: second insulating layer I-I: line ML11, ML12, ML21, ML22: metal wire MV11, MV12, MV21, MV22: metal through holes PK: Semiconductor package PM: polymer pattern R1, R2: District RDL1: The first rewiring layer structure RDL2: The second rewiring layer structure S1: First substrate S2: second substrate T: Wafer tape TSV1: First substrate perforation TSV2: second substrate perforation UF1: The first underfill layer UF2: The second underfill layer

1A to 1S are schematic cross-sectional views of a method of forming a semiconductor package according to some embodiments. 2 to 5 are schematic top views of semiconductor packages according to some embodiments. FIG. 6 illustrates a method of forming a semiconductor package according to some embodiments. 7-10 are cross-sectional views of various semiconductor packages according to some embodiments. FIG. 11 is a cross-sectional view of a semiconductor package according to other embodiments. 12 to 13 are schematic top views of semiconductor packages according to other embodiments. FIG. 14 shows a method of forming a semiconductor package according to other embodiments. 15 to 18 are cross-sectional views of various semiconductor packages according to other embodiments.

10: Semiconductor package

100: bridge structure

200: board base

202: Wire pattern

B1, B2, B3: bump

C1: The first die

C2: second die

C3: third grain

C4: Fourth die

CL: cutting line

CS1: The first conductive structure

CS2: second conductive structure

E1: The first dielectric sealing body

E2: Second dielectric sealing body

G: gap width

I1: The first intermediary

I2: The second intermediary

IL1: first insulating layer

IL2: second insulating layer

ML11, ML12, ML21, ML22: metal wire

MV11, MV12, MV21, MV22: metal through holes

R1: District

RDL1: The first rewiring layer structure

RDL2: The second rewiring layer structure

S1: First substrate

S2: second substrate

T: Wafer tape

TSV1: First substrate perforation

TSV2: second substrate perforation

UF1: The first underfill layer

UF2: The second underfill layer

Claims (1)

A semiconductor package includes: The first intermediate piece and the second intermediate piece are embedded in the first dielectric sealing body; The first die is arranged above the first intermediate member and is electrically connected to the first intermediate member; The second die is arranged above the second interposer and is electrically connected to the second interposer; and At least one bridge structure is arranged between the first crystal grain and the second crystal grain.

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