TWI633635B - Stacked chip packaging structure capable of improving space utilization rate and packaging method thereof - Google Patents

Abstract

A stacked chip package structure and a package method thereof for improving space utilization, comprising a die, a conductive carrier, a support layer, a protective layer and an electrode layer; the upper surface of the die is provided with the conductive load a supporting layer disposed around the die and the lower surface of the conductive carrier, the protective layer covering the die, the supporting layer and the conductive carrier, and the protective layer is exposed on the surface of the conductive carrier, the electrode The layer is disposed on the lower surface of the die, and a stack of package structures is disposed on the surface of the conductive carrier plate, so that the die is electrically connected to the stacked package structure via the conductive carrier to transmit signals; The three-dimensional packaging method can reduce the space occupied by the two-dimensional package of the horizontal plane, thereby reducing the size of the package and achieving the purpose of improving space utilization.

Description

Stacked chip packaging structure capable of improving space utilization rate and packaging method thereof

The present invention relates to a packaging structure, and more particularly to a stacked wafer packaging structure and packaging method capable of improving space usage.

With the development of the industry, many fields need to use processors or communication components manufactured by semiconductor processes. Taking the processor as an example, a wafer-side manufacturer uses a semiconductor process to manufacture a processor chip, and a package-side packager packages the processor chip to complete the processor as seen on the market.

However, with the development of Moore's Law reaching the limit, it is becoming increasingly difficult for manufacturers at each wafer end to reduce the size of the wafer, so they have cooperated with packaging industry to improve the efficiency of the chip through packaging.

Currently, packaging methods include Package On Package (POP), and Wafer Level Chip Scale Package (WLCSP, WLCSP). Among them, the POP method will have Logic and storage chip packages with the same appearance are individually packaged and then stacked and connected, which has the advantages of high yield and low cost.

The WLCSP method is an emerging packaging method that combines two technologies, Chip Scale Package and Wafer Level Package. After packaging and testing on the entire wafer, it is cut into a single finished product without the need for wire bonding and filling process steps. The size of the packaged wafer is almost the same as that of a bare wafer, which can reduce the size of the wafer and greatly improve signal transmission. Speed, and reduce noise interference.

However, when a chip using the POP method and a chip using the WLCSP method need to be combined for further improvement, the two chips can only be connected in a horizontal two-dimensional manner. As a result, the area of the processor will change. Large, making space utilization lower.

In view of the problems existing in the above-mentioned prior art, the present invention provides a stacked chip packaging structure and a packaging method capable of improving space utilization. Through a three-dimensional packaging method, a wafer using a POP method and a wafer using a WLCSP method are stacked. Together, the space occupied by the two-dimensional package in the horizontal plane can be reduced, thereby reducing the size of the package to achieve the purpose of improving space utilization.

The technical means adopted to achieve the above-mentioned purpose is to make the aforementioned stacked chip packaging method capable of improving space utilization, which includes the following steps: providing a first substrate having a first release film on the first substrate; setting A plurality of first crystal grains are on the first release film; a support layer is provided around the first crystal grains; a plurality of first conductive carriers are provided, and each first conductive carrier is disposed on a corresponding first crystal On the grains and on the support layer around the first grain, and form an electrical connection with the corresponding first grain; a first protective layer is provided to cover the first grains, the support layer and the first grains A conductive carrier board, and the upper surfaces of the first conductive carrier boards are exposed to the first protective layer; a plurality of stacked packaging structures are arranged on the first conductive carrier boards, each of which is stacked into a packaging structure and a corresponding first The conductive substrate is electrically connected; the first substrate and the first release film are removed; and an electrode layer is disposed on a lower surface of the first crystal grains.

It can be known from the above method that the first die is electrically connected to the stacked package structure through the first conductive carrier board to transmit signals. The vertical and vertical three-dimensional packaging method can reduce the occupation of two-dimensional packaging in the horizontal plane. Space, thereby reducing the size of the package to achieve the purpose of improving space utilization.

Another technical means adopted to achieve the above purpose is to make the aforementioned stacked chip package structure capable of improving space utilization rate, which includes: a first die; a first conductive carrier board having an upper surface and a lower surface A lower surface of the first conductive carrier board is electrically connected to the first die to transmit a signal; a support layer is provided around the first die to support the first conductive carrier board; a first protective layer, Covering the first die, the first conductive carrier board and the support layer, and the upper surface of the first conductive carrier board is exposed to the first protective layer; an electrode layer is disposed under the first die; Surface; a stack of packaging structures, disposed on an upper surface of the first conductive carrier board and electrically connected to the first conductive carrier board.

It can be known from the above structure that the first die and the stacked package structure are electrically connected by the first conductive carrier board to transmit signals. The vertical and vertical three-dimensional packaging method can reduce the occupation of two-dimensional packaging in the horizontal plane. Space, thereby reducing the size of the package to achieve the purpose of improving space utilization.

Regarding the stacked wafer structure capable of improving the space utilization rate of the present invention, it is mainly completed by a packaging method. In order to clearly explain the flow of the packaging method, it will be described in conjunction with the drawings of this case.

Please refer to FIG. 1 for a manufacturing process of the packaging method. The packaging method includes steps S11 to S18, and FIGS. 2 to 8 are schematic cross-sectional structural diagrams corresponding to the manufacturing processes of steps S11 to S18. In order to explain step S11, please refer to FIGS. 1 and 2. In step S11, a first substrate 31 is provided. The first substrate 31 has an upper surface and a lower surface. The upper surface of the first substrate 31 has a first surface.一 离 膜 32。 A release film 32.

In step S12, a plurality of first crystal grains 11 are provided on the upper surface of the first release film 32. The first crystal grains 11 have an upper surface 111 and a lower surface 112, respectively. The lower surface 112 of 11 is attached to the first release film 32.

In the preferred embodiment, during the manufacturing process of the packaging method, the first substrate 31 is used to carry the first dies 11; in FIG. 2, the number of the first dies 11 is three. , But not limited to this, the number of the first crystal grains 11 may be determined according to the actual process conditions.

Please refer to FIGS. 1 and 3. FIG. 3 is a schematic cross-sectional structure of steps S13 and S14. In step S13, a support layer 12 is provided around each of the first grains 11. Specifically, the support layer 12 includes a plurality of support pillars 121, and each of the first grains 11 has several supports. Column 121. In the preferred embodiment, the supporting pillars 121 may be copper pillars, respectively.

Among them, each support pillar 121 has a first distance L1 between the corresponding first die 11 and the distance length of each first distance L1 is the same; there is a second distance between two adjacent support pillars 121. L2, the second distance L2 is greater than the first distance L1.

In step S14, a plurality of first conductive substrates 13 are provided on the first crystal grains 11 and the support layer 12. Specifically, each of the first conductive substrates 13 has an upper surface and a lower surface. The lower surface of the first conductive carrier plate 13 is disposed on an upper surface 111 of a corresponding first die 11 and a corresponding support pillar 121 around the first die 11. The first conductive carrier 13 and the first A die 11 is electrically connected to transmit signals.

Please refer to FIGS. 1 and 4. In step S15, a first protective layer 14 is provided to cover the first crystal grains 11, the support layer 12 and the first conductive carrier plates 13. An upper surface of a conductive carrier plate 13 is exposed on the first protective layer 14.

In step S16, please refer to FIG. 1 and FIG. 5. A plurality of stacked packaging structures 20 are disposed on the upper surfaces of the first conductive carriers 13, and each of the packaging structures 20 and a corresponding first conductive carrier 13 are stacked. Electrically connected to pass signals.

In this preferred embodiment, please refer to FIGS. 1, 4 and 5. In step S15, before the first protective layer 14 is set, a second release film 32A is further provided. The mold film 32A has an upper surface and a lower surface, and the lower surface is adhered to the upper surfaces of the first conductive carriers 13 to prevent the first protective layer 14 from being covered when the first protective layer 14 is disposed. The upper surfaces of the first conductive carriers 13 shield the circuits on the upper surfaces of the first conductive carriers 13. When the stacked packaging structures 20 are disposed, the second release film 32A is removed first, so that the upper surfaces of the first conductive carriers 13 are exposed, each of the stacked packaging structures 20 and a corresponding first The conductive carrier 13 forms an electrical connection.

In the preferred embodiment, the first protective layer 14 fills a space formed between the first release film 32 and the second release film 32A with a resin through a potting method to cover The first dies 11, the support layer 12 and the first conductive carrier plates 13.

In this preferred embodiment, the stacked packaging structure 20 can be disposed on the first conductive carrier plate 13 by a soldering method.

In the preferred embodiment, the first release film 32 and the second release film 32A are made of the same material, and are adhesive and easy to peel and remove.

In the preferred embodiment, the stacked package structure 20 includes a second die 21, a first electrical connection layer 22, a second protective layer 23, a second conductive carrier board 24, and a second electrical connection. Layer 25. The second electrical connection layer 25 is electrically connected to the first conductive substrate 13. The second conductive substrate 24 is disposed on the second electrical connection layer 25. The first electrical connection layer 22 is disposed on the second conductive substrate. On the board 24, the second die 21 is disposed on the first electrical connection layer 22, the second protective layer 23 is disposed on the second conductive carrier plate 24, and covers the second die 21 and the first一 电 连接 层 22。 An electrical connection layer 22. The first electrical connection layer 22 includes a plurality of solder balls and is spaced apart from each other on the upper surface of the second conductive substrate 24. The second electrical connection layer 25 includes a plurality of solder balls, and is spaced apart from each other on the lower surface of the second conductive substrate 24.

Please refer to FIGS. 1, 5, and 6. In step S17, the first substrate 31 and the first release film 32 are removed to expose the lower surfaces 112 of the first crystal grains 11.

Please refer to FIGS. 1 and 7. In step S18, an electrode layer 15 is disposed on the lower surface 112 of the first crystal grains 11. Specifically, the electrode layer 15 includes a plurality of solder balls, and a plurality of solder balls are provided on the lower surface 112 of each of the first crystal grains 11, which are distributed on the lower surface 112 of the first crystal grains and the supporting pillars 121. Lower surface.

Please refer to FIGS. 1 and 8. In step S19, singulation is performed on the first protective layer 14 through a singulation method (Singulation) to form several independent stacked chip packages of the present invention. Structure; wherein each of the first die 11, the corresponding supporting layer 12, the connected first conductive carrier plate 13, the surrounding first protective layer 14, and the connected electrode layer 15 constitute a wafer-level package structure, each The wafer-level package structure and the connected stacked package structure 20 constitute a stacked chip package structure of the present invention.

In the preferred embodiment, the wafer-level package structure is manufactured by a wafer level chip scale package (WLCSP, hereinafter referred to as WLCSP); the stacked package structure 20 is formed through It is made by a package on package method (Package On Package, POP, hereinafter referred to as POP).

According to the above structure content, it can be known that the first conductive carrier plate 13 carries the first die 11 and the stacked package structure 20 to each other, and can reduce the occupation of the two-dimensional package in the horizontal plane through the vertical and vertical three-dimensional packaging method. To reduce the size of the package to achieve the purpose of improving space utilization.

In addition, since only signals can be transmitted through the first conductive carrier plate 13, the second electrical connection layer 25, the second conductive carrier plate 24, and the first electrical connection layer 22, the distance of signal transmission can be effectively reduced. .

11‧‧‧ first die

111‧‧‧ top surface

112‧‧‧ lower surface

12‧‧‧ support layer

121‧‧‧ support column

13‧‧‧The first conductive carrier board

14‧‧‧first protective layer

15‧‧‧ electrode layer

20‧‧‧ stacked into a package structure

21‧‧‧Second grain

22‧‧‧First electrical connection layer

23‧‧‧Second protective layer

24‧‧‧Second conductive carrier board

25‧‧‧Second electrical connection layer

31‧‧‧first substrate

32‧‧‧The first release film

32A‧‧‧Second Release Film

L1‧‧‧First distance

L2‧‧‧Second Distance

FIG. 1 is a manufacturing flowchart of a preferred embodiment of the present invention. FIG. 2 is a first schematic cross-sectional view of a preferred embodiment of the present invention. FIG. 3 is a second schematic sectional view of a preferred embodiment of the present invention. FIG. 4 is a third schematic cross-sectional view of a preferred embodiment of the present invention. FIG. 5 is a fourth cross-sectional view of a preferred embodiment of the present invention. FIG. 6 is a fifth cross-sectional view of a preferred embodiment of the present invention. FIG. 7 is a sixth cross-sectional view of a preferred embodiment of the present invention. FIG. 8 is a schematic sectional view of a seventh embodiment of the present invention.

Claims (5)

A stacked chip packaging method capable of improving space utilization rate includes the following steps: providing a first substrate having a first release film on the first substrate; and setting a plurality of first crystal grains on the first release film A support layer is provided around the first die; a plurality of first conductive carriers are provided, and each first conductive carrier is provided on a corresponding first die and a support layer around the first die; A first protective layer is provided to cover the first crystal grains, the support layer and the first conductive carrier board, and the upper surface of the first conductive carrier board is exposed to the first protective layer; Most of the stacked packaging structures are on the first conductive carrier boards, and each of the stacked packaging structures is electrically connected to a corresponding first conductive carrier board; the first substrate and the first release film are removed; and an electrode layer is provided On the lower surface of the first grains. The packaging method capable of improving space utilization according to claim 1, wherein in the step of setting a first protective layer, before the first protective layer is further provided, the method further includes the following steps: setting a second release film The second release film is disposed on the first crystal grains, the support layer, and the first conductive carriers. The packaging method capable of improving space utilization as described in claim 2, wherein after the first protective layer is provided, the method further includes the following steps: removing the second release film to expose the first conductive carriers The upper surface of the board is electrically connected to the stacked package structure. The packaging method capable of improving space utilization according to claim 1, wherein after setting the electrode layer, the method further includes the following steps: cutting the first protective layer to form a plurality of independent stacked chip packaging structures . The packaging method capable of improving the space utilization rate according to claim 1, wherein in the step of setting the first protective layer, the first protective layer is formed by a potting method.