TWI625195B - Polishing head and method for polishing semiconductor wafer backside - Google Patents

Abstract

Embodiments of the present invention provide a polishing head including a base, a support layer, and an abrasive layer. The support layer is disposed on the base, and the abrasive layer is disposed on the support layer. The abrasive layer includes a plurality of bumps. The bump has an arcuate outer surface, and adjacent two bumps are spaced apart.

Description

Grinding head and method of grinding the back side of a semiconductor wafer

Embodiments of the present invention relate to a semiconductor device production apparatus and a processing method thereof, and more particularly to a semiconductor wafer production apparatus and a method of polishing a back side of a semiconductor wafer.

Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The semiconductor device is usually fabricated by sequentially depositing an insulating or dielectric layer material, a conductive layer material, and a semiconductor layer material on a semiconductor substrate, and by using a lithography process and a lithography process to form various material layers. Patterning to form circuit components and components on top of the semiconductor substrate. Typically dozens or hundreds of integrated circuits are fabricated on a single semiconductor wafer.

The smallest feature size in a lithography process is called critical dimension (CD). The smaller the critical dimension, the harder it is to focus the image on the wafer surface. In the current technology, after the photoresist is applied to the surface of the wafer, the back side of the wafer may be contaminated by photoresist, which causes the wafer to be in the subsequent exposure process, because the wafer surface has a height difference, and the image cannot be effectively The image is focused on the surface of the wafer, causing the product to be scrapped.

Therefore, there is a need for a method for polishing the backside of a wafer after the photoresist coating process.

Some embodiments of the present invention provide a polishing head. The polishing head includes a base. The polishing head further includes a support layer disposed on the base. The polishing head also includes an abrasive layer disposed over the support layer. The abrasive layer includes a plurality of bumps. The bumps have curved outer surfaces and are spaced apart from one another.

Some embodiments of the present invention provide a method of polishing a back side of a semiconductor wafer. The above method includes providing a polishing head. An abrasive layer on the polishing head for polishing the back side of the semiconductor wafer includes a plurality of bumps having curved outer surfaces spaced apart from one another. The method also includes contacting a central region on the back side of the semiconductor wafer with the abrasive layer of the polishing head to polish the central region. The method further includes contacting a peripheral region surrounding the central region on the back side of the semiconductor wafer with the abrasive layer of the polishing head to polish the peripheral region. The height at which the polishing head grinds the central region is greater than the height at which the polishing head grinds the peripheral region.

1‧‧‧Processing system

3‧‧‧ carrying case

5‧‧‧Semiconductor wafer

7‧‧‧Loading

9‧‧‧Loading

10‧‧‧Photoresist coating module

20‧‧‧Abrasion module

21‧‧‧Exposure module

23‧‧‧Outer support

25‧‧‧ linkage

30‧‧‧Exposure module

40‧‧‧ polishing head

41‧‧‧Base

410‧‧‧ inside part

411‧‧‧ outer edge

42‧‧‧Support layer

420‧‧‧ bottom

421‧‧‧First ring structure

422‧‧‧second ring structure

423‧‧‧ central structure

424‧‧‧Perforation

412‧‧‧Connecting head

43‧‧‧Lower layer

44‧‧‧Upper layer

45‧‧‧Abrasive layer

451‧‧‧Abrased sheet (first abrasive sheet)

452‧‧‧Abrased sheet (second abrasive sheet)

453‧‧‧film

454‧‧‧Bumps

50‧‧‧ Back side

51‧‧‧ edge

52‧‧‧Central area

53‧‧‧ peripheral area

100‧‧‧ method

110, 120, 130‧‧‧ operations

A1, a2, a3, a4‧‧‧ directions

C‧‧‧ Center

R1, r2, r3‧‧‧ rotating shaft

H0, H1, H2, H3‧‧‧ height

Figure 1 shows a schematic diagram of a processing system in accordance with some embodiments of the present invention.

Fig. 2 is a schematic view showing a polishing module according to some embodiments of the present invention.

Figure 3 is a cross-sectional view showing a polishing head according to some embodiments of the present invention.

Figure 4 shows a top view of a polishing head of some embodiments of the invention.

Fig. 5 is a cross-sectional view taken along line A-A' of Fig. 4.

Figure 6 is a flow chart showing a method of polishing the back side of a semiconductor wafer in accordance with some embodiments of the present invention.

Figure 7 is a schematic view showing one of the steps of a method of polishing the back side of a semiconductor wafer in accordance with some embodiments of the present invention, wherein the polishing head grinds the back side of the semiconductor wafer Central area.

Figure 8 is a schematic illustration of one of the steps of a method of polishing the back side of a semiconductor wafer in accordance with some embodiments of the present invention, wherein the polishing head abuts the back side of the semiconductor wafer at a height H1.

Figure 9 is a schematic illustration of one of the steps of a method of polishing the back side of a semiconductor wafer in accordance with some embodiments of the present invention, wherein the polishing head grinds a peripheral region of the back side of the semiconductor wafer.

Figure 10 is a schematic illustration of one of the steps of a method of polishing the backside of a semiconductor wafer in accordance with some embodiments of the present invention, wherein the polishing head abuts the back side of the semiconductor wafer at a height H2.

11 is a schematic diagram showing one of the steps of a method of polishing the back side of a semiconductor wafer in accordance with some embodiments of the present invention, wherein the polishing head abuts the back side of the semiconductor wafer at a height H3.

The following disclosure is provided to illustrate various embodiments of the invention. Of course, these specific examples are not intended to limit the invention. For example, if the disclosure of the present specification describes forming a first feature on or above a second feature, that is, it includes an embodiment in which the formed first feature is in direct contact with the second feature. Also included is an embodiment in which additional features are formed between the first feature and the second feature described above, such that the first feature and the second feature may not be in direct contact. In addition, different examples in the description of the invention may use repeated reference symbols and/or words. These repeating symbols or The use of words for the sake of simplicity and clarity is not intended to limit the relationship between the various embodiments and/or the appearance structures.

Furthermore, for convenience of describing the relationship of one element or feature in the drawings to another (plural) element or (complex) feature, space-related terms such as "below", "below", "lower", "above", "upper" and similar terms. It will be understood that the spatially relative terms encompass different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. The device may also be additionally positioned (eg, rotated 90 degrees or at other orientations) and the description of the spatially relevant terms used may be interpreted accordingly. It will be appreciated that additional operational steps may be provided before, during, and after the method, and in some method embodiments, some of the operational steps may be replaced or omitted.

It should be noted that the embodiments discussed herein may not necessarily describe every component or feature that may be present within the structure. For example, one or more components may be omitted from the drawings, such as may be omitted from the drawings when the description of the components may be sufficient to convey various aspects of the embodiments. Furthermore, the method embodiments discussed herein may be discussed in a particular order, but in other method embodiments, the order may be performed in any reasonable order.

Figure 1 shows a schematic diagram of a processing system 1 of some embodiments of the present invention. According to an embodiment of the invention, the processing system 1 comprises a photoresist coating module 10, a polishing module 20, an exposure module 30 and one or more loading magazines, for example two loading magazines 7, 9. The configuration of the processing system 1 and the number of modules can be increased or decreased according to requirements, and are not limited to this embodiment.

The loading cassettes 7, 9 are configured to house a carrying case 3 that can be used to load a plurality of semiconductor wafers 5, and the processing system 1 has an opening relative to the loading cassettes 7, 9. The port is for the semiconductor wafer 5 to pass. In some embodiments, the carrying case 3 on the loading cassette 7 is for placing the semiconductor wafer 5 to be processed, and the carrying case 3 on the loading cassette 9 is for placement in the processing system 1. Semiconductor wafer 5. It should be understood that the number of load ports of the processing system 1 may be increased or decreased as desired, and is not limited to the embodiment shown in FIG. In addition, the installation position of the loading cassette 7 and the loading cassette 9 of the processing system 1 can also be changed. For example, the loading cassette 7 of the processing system 1 is placed adjacent to the loading cassette 9.

In some embodiments, the semiconductor wafer 5 enters the processing system 1 and is sequentially processed through the photoresist coating module 10, the polishing module 20, and the exposure module 30. The semiconductor wafer 5 supplied to the carrying case 3 on the loading cassette 7 is subjected to a photoresist coating process in the photoresist coating module 10, and sent to the polishing module 20 to planarize the photoresist. Next, the semiconductor wafer 5 is sent from the polishing module 20 to the exposure module 30, and the photoresist on the surface of the semiconductor wafer 5 is exposed to the exposure module 30. Finally, the semiconductor wafer 5 is sent by the exposure module 30 to the carrier box 3 located on the loading cassette 9. The movement of the semiconductor wafer 5 can be performed by one or more robot arms (not shown in FIG. 1) provided in the processing system 1.

In some embodiments, the processing parameters of the photoresist coating module 10, the polishing module 20, and the exposure module 30, and the transport time of the semiconductor wafer 5 through the robot arm can be transmitted through a pre-implanted program in a computer or The microprocessor (not shown in Figure 1) operates.

According to some embodiments of the present invention, the structural features of the polishing module 20 are as follows:

Figure 2 shows a schematic view of a polishing module 20 in accordance with some embodiments of the present invention. According to an embodiment of the invention, the polishing module 20 includes a wafer holder 21, an A plurality of outer support seats (for example, two outer support seats 23), a link 25 and a polishing head 40. It should be understood that the components in the grinding module 20 may be additionally increased or decreased, and are not limited to this embodiment.

The wafer holder 21 is configured to hold the semiconductor wafer 5 when the polishing head 40 polishes the peripheral side 53 of the edge 51 on the back side 50 of the semiconductor wafer 5. The wafer holder 21 can be an electrostatic wafer holder (e-chuck). Alternatively, the wafer holder 21 is coupled to a vacuum source and the semiconductor wafer 5 is fixed over the wafer holder 21 by vacuum generated by a vacuum source. In some embodiments, the wafer holder 21 is rotatable about a rotational axis r1 through its center. Further, the wafer holder 21 can be moved up and down in the direction of the parallel rotation axis r1 as indicated by an arrow a1.

In some embodiments, as shown in FIG. 2, the outer diameter of the semiconductor wafer 5 is sufficiently larger than the width of the wafer holder 21. Thus, when the semiconductor wafer 5 is placed on the wafer holder 21, the peripheral region 53 on the back side 50 of the semiconductor wafer 5 that is close to the edge 51 is not covered by the wafer holder 21.

The outer support base 23 is configured to fix the semiconductor wafer 5 when the polishing head 40 polishes the central region 52 of the semiconductor wafer 5. In some embodiments, the outer support base 23 is coupled to a vacuum source and the semiconductor wafer 5 is secured to the outer support base 23 by vacuum generated by a vacuum source. In some embodiments, the two outer support seats 23 are movable up and down in the direction of the parallel rotation axis r1 as indicated by the arrow a2. In some embodiments, the two outer support seats 23 are movable back and forth in a horizontal direction as indicated by arrow a4.

In some embodiments, the polishing module 20 includes two outer support seats 23. The two outer support seats 23 are respectively located on opposite sides of the wafer holder 21. The spacing between the two outer support seats 23 is smaller than the diameter of the semiconductor wafer 5, larger than the semi-conductive The width of the central region 52 of the bulk wafer 5. As a result, when the semiconductor wafer 5 is fixed on the two outer support seats 23, the central region 52 of the semiconductor wafer 5 is not covered by the two outer support seats 23.

The central region 52 of the semiconductor wafer 5 is defined as a location at a particular pitch from the center of the semiconductor wafer 5 to the edge 51 of the semiconductor wafer 5. The above specific pitch is about 50% of the radius of the semiconductor wafer 5. The peripheral region 53 of the semiconductor wafer 5 is defined as the region of the central region 52 to the edge 51 of the semiconductor wafer 5.

The link 25 is configured to carry the abrading head 40 and control the position of the abrading head 40. In some embodiments, the polishing head 40 is coupled to the end of the link 25 so as to be rotatable about a rotation axis r2, and the link 25 is swingable back and forth about a rotation axis r3 to change the polishing head 40 relative to the semiconductor crystal. The position of the circle 5. For example, the link 25 can move the polishing head 40 below the semiconductor wafer 5, and the link 25 can swing about the axis of rotation r3 such that the polishing head 40 is at the center of the semiconductor wafer 5 to the edge 51 of the semiconductor wafer 5. Move over the area between areas of arbitrary width. In some embodiments, the link 25 can be moved up and down in the direction of the parallel rotation axis r3 as indicated by the arrow a3 to change the spacing of the polishing head 40 from the semiconductor wafer 5 or to change the polishing head 40 to apply to the semiconductor crystal. The pressure of the circle 5.

Fig. 3 is a cross-sectional view showing a polishing head 40 of a portion of the embodiment of the present invention, and Fig. 4 is a top view showing a polishing head 40 of a part of the embodiment of the invention. The structural features of the polishing head 40 according to some embodiments of the present invention are explained below.

In some embodiments, the polishing head 40 includes a base 41, a support layer 42 and an abrasive layer 45. The configuration of the polishing head 40 and the number of modules can be increased or decreased as required, and are not limited to this embodiment.

In some embodiments, the base 41 is a circular plate-like structure. complex A plurality of perforations 424 penetrate the front and rear surfaces of the base 41 to facilitate the removal of the slurry used during the grinding process and the debris generated during the grinding process. In some embodiments, the base 41 has a circular inner portion 410. The inner portion 410 of the base 41 extends from the center of the base 41 toward the outer edge 411 of the base 41 and is spaced apart from the outer edge 411. The width of the inner portion 410 is from about 10% to about 15% of the width of the base 41. In some embodiments, the base 41 further includes a connector 412 for connecting the links 25. The connector 412 can be coupled to the link 25 using any suitable means (e.g., screwing).

The support layer 42 is configured to support the abrasive layer 45 above the susceptor 41 and to act as a buffer during the grinding process. In some embodiments, the support layer 42 includes one or more annular structures, such as a first annular structure 421 and a second annular structure 422, and a central structure 423.

The center structure 423 is disposed on the inner portion 410 of the base 41 and has a circular cross section in the plane of the parallel base 41. The first annular structure 421 and the second annular structure 422 are disposed outside the inner portion 410 of the base 41 (that is, the first annular structure 421 and the second annular structure 422 surround the central structure 423, such as the fourth The figure is shown and located between the inner portion 410 of the base 41 and the outer edge 411. For example, the first annular structure 421 is disposed adjacent to the outer edge 411 of the base 41, and the second annular structure 422 is located between the first annular structure 421 and the central structure 423. The first annular structure 421 and the second annular structure 422 are spaced apart from each other and are not connected to each other. Moreover, the second annular structure 422 and the central structure 423 are spaced apart from each other and are not connected to each other. The through holes 424 formed at least partially on the base 41 are exposed to the outside by the above-described spacing.

In an exemplary embodiment, the central structure 423 of the support layer 42 occupies the base 41 The ratio of the area is about 10%; the ratio of the second annular structure 422 of the support layer 42 to the area of the pedestal 41 is between about 20% and 25%; and the first annular structure 421 of the support layer 42 occupies the pedestal The ratio of 41 areas is between about 65% and 70%.

In some embodiments, the support layer 42 is formed by laminating two materials having different characteristics. For example, the support layer 42 includes a lower layer body 43 and an upper layer body 44. The lower layer body 43 is fixed to the base 41, and the upper layer body 44 is fixed to the lower layer body 43. The lower layer body 43 may be made of a material that is not easily deformed, such as metal or plastic, and the upper layer body 44 may be made of a material that is easily elastically deformable, such as a polyvinyl alcohol (PVA) sponge.

In one embodiment, the thickness of the upper layer body 44 is approximately equal to 13 mm. In this way, during the polishing process of the semiconductor wafer 5, the polishing head 40 can provide the buffering when the polishing layer 45 contacts the semiconductor wafer 5 by the characteristic that the upper layer body 44 is easily elastically deformed, thereby increasing the polishing uniformity.

In some embodiments, the upper layer body 44 is separated from the base 41 by a height difference, and the lower layer body 43 is made of a material that is less likely to absorb water by the upper layer body 44. With the above features, the polishing liquid deposited on the susceptor 41 and not quickly removed will not be absorbed by the upper layer body 44, and will affect the elastic deformation characteristics of the upper layer body 44. Thus, the grinding uniformity can be further improved. However, it should be understood that various changes and variations can be applied to embodiments of the present invention, and the support layer 42 can also be fabricated from a single material.

In some embodiments, the support layer 42 has a height variation relative to the base 41. For example, as shown in FIG. 3, the height of the first annular structure 421 of the support layer 42 gradually increases from the inner portion 410 of the base 41 toward the outer edge 411 of the base 41. In an embodiment, below the first annular structure 421 The layer body 43 has a trapezoidal cross section, and the upper layer body 44 has a cross section of a parallelogram.

However, it should be understood that various changes and modifications can be applied to the embodiments of the invention. The cross section of the lower layer body 43 and the upper layer body 44 of the first annular structure 421 may be any shape, and the structural aspect of the first annular structure 421 is not limited thereto. In another embodiment, the portion of the first annular structure 421 near the central structure 423 has a uniform height, and the height of the portion of the first annular structure 421 near the outer edge 411 gradually increases.

The polishing layer 45 is configured to polish the back side 50 of the semiconductor wafer 5. In some embodiments, the abrasive layer 45 is secured over the bottom surface 420 of the support layer 42 opposite the base 41. In some embodiments, as shown in FIG. 4, the abrasive layer 45 includes one or more different forms of abrasive sheets, such as a trapezoidal first abrasive sheet 451 and a hexagonal second abrasive sheet 452.

The first abrasive sheet 451 covers the second annular structure 422 of the support layer 42 and the bottom surface 420 of the central structure 423. On the second annular structure 422, two adjacent first abrasive sheets 451 are separated by a channel, and Directly connected for the passage of grinding fluid and grinding.

Fig. 5 is a cross-sectional view showing the A-A' line of the first polishing sheet 451 of Fig. 4. In some embodiments, the first abrasive sheet 451 includes a film 453 and a plurality of bumps 454 disposed on the film 453. In some embodiments, the bump 454 has a curved outer surface. The curved outer surface of each of the bumps 454 has a uniform curvature and the bumps 454 are part of a sphere. However, it should be understood that various changes and modifications can be applied to the embodiments of the invention.

In the remaining embodiments, the outer surface of the bump 454 has a continuous curve. Rate changes. In some embodiments, each of the bumps 454 located in the first abrasive sheet 451 is symmetrical about its center C and has an arcuate outer surface. That is, the bump 454 has a smooth outer surface, thereby avoiding scratching the semiconductor wafer 5 during the polishing of the semiconductor wafer 5.

In some embodiments, two adjacent bumps 454 are separated by a channel and are not directly connected for the passage of the grinding during the grinding process. Therefore, the phenomenon that the semiconductor wafer 5 is scratched by the chipping between the polishing head 40 and the semiconductor wafer 5 can be further avoided. In some embodiments, the plurality of bumps 454 are arranged along a plurality of axes, wherein the plurality of bumps 454 on adjacent axes are staggered. The bumps 454 may be made of a material of higher hardness diamond particles and a resin polymer.

The second abrasive sheet 452 covers the bottom surface 420 of the first annular structure 421 of the support layer 42. The two adjacent second abrasive sheets 452 are separated by a channel and are not directly connected for grinding liquid and grinding. by. In some embodiments, the structural features of the second abrasive sheet 452 are similar to those of the first abrasive sheet 451, and are not repeated for simplicity of illustration.

It should be understood that although in the embodiment of Figures 3-4, the support layer 42 has two annular structures 421, 422, the number of annular structures of the support layer 42 is not limited thereto. In some embodiments, the support layer 42 includes only a ring structure and a center structure 423, which are spaced apart from each other and are not connected. In other embodiments, the support layer 42 includes three annular structures and a central structure 423 spaced apart from one another and not connected. In other embodiments, the central structure 423 of the support layer 42 is replaced by another annular structure having a smaller radius. The abrasive layer 45 is formed on all of the above annular structures and the opposite ends of the central structure Above the bottom of the seat 41.

FIG. 6 shows a flow chart of a method 100 of polishing the back side 50 of a semiconductor wafer 5 in accordance with some embodiments of the present invention. For the sake of example, the flow is illustrated by the schematic diagrams of Figures 7-11. In different embodiments, some of the stages can be replaced or eliminated. Additional features can be added to the semiconductor device structure. In various embodiments, some of the above characteristics may be replaced or eliminated.

The method 100 begins at operation 110 by providing a polishing head 40 as described in any of the above embodiments. In some embodiments, the polishing head 40 is disposed at the end of the link 25 and is moved to a position below the central region 52 of the semiconductor wafer 5 as shown in FIG. 7 under the control of the link 25.

In some embodiments, the polishing head 40 is further controlled to move upward by the link 25 such that the polishing layer 45 (Fig. 3) of the polishing head 40 contacts the back side 50 of the semiconductor wafer 5. In some embodiments, the outer support base 23 rises in the direction of the semiconductor wafer 5 and abuts the semiconductor wafer 5 before the polishing head 40 reaches a position below the central region 52 of the semiconductor wafer 5. Further, the wafer holder 21 is lowered in a direction away from the semiconductor wafer 5, and the central region 52 of the semiconductor wafer 5 is not supported by the wafer holder 21.

Next, the method 100 continues to operation 120 by polishing the central region 52 of the back side 50 of the semiconductor wafer 5. In some embodiments, the polishing head 40 grinds the central region 52 of the back side 50 of the semiconductor wafer 5 about a rotational axis r2 at a rotational speed of from about 300 rpm to about 495 rpm. During the process of grinding the central region 52 of the back side 50 of the semiconductor wafer 5, the outer support 23 drives the semiconductor wafer 5 to move in the direction indicated by the arrow a4 of FIG. 7 so that the polishing head 40 refers to the arrow a4. The direction passes through the central region 52 of the back side 50 of the semiconductor wafer 5.

In some embodiments, during the polishing of the central region 52 of the back side 50 of the semiconductor wafer 5, the link 25 is swung over the rotating axis r3 such that the polishing head 40 faces the back side 50 of the semiconductor wafer 5. All surfaces of the central region 52 are ground. The amplitude of the swing of the link 25 described above may be gradually increased from the beginning of the operation 120 to the middle of the operation 120, and gradually decreased until the middle of the operation 120 until the end of the operation 120. As such, the polishing head 40 grinds a substantially circular region on the central region 52 of the back side 50 of the semiconductor wafer 5. However, it should be understood that various changes and modifications can be applied to the embodiments of the invention. In an embodiment of the semiconductor wafer 5 having a 300 mm dimension, the central region has a width of about 75 mm.

In some embodiments, in operation 120, the polishing head 40 is urged by the link 25 to continuously apply pressure to the semiconductor wafer 5 to conform the polishing head 40 to the back side 50 of the semiconductor wafer 5. Thus, the height of the central region 52 of the semiconductor wafer 5 is higher than the peripheral region 53 of the semiconductor wafer 5 by the abutment of the polishing head 40 in the upward direction.

For example, as shown in FIG. 8, the polishing head 40 is in contact with the central region 52 of the back side 50 of the semiconductor wafer 5 at a height H1, and the two outer support pads 23 are in contact with the back side 50 of the semiconductor wafer 5. The position is at height H0. Since the central region 52 of the back side 50 of the semiconductor wafer 5 is abutted upward by the polishing head 40, the height H1 is greater than the height H0. In an exemplary embodiment, the difference between the height H1 and the height H0 described above may be substantially equal to 1 mm. However, it should be understood that various changes and modifications can be applied to the embodiments of the invention. The difference between the height H1 and the height H0 may be based on the nature of the material to be ground on the back side 50 of the semiconductor wafer 5, the rotational speed of the polishing head 40, or applied to the semiconductor wafer. The type of the polishing liquid on the back side 50 of 5 is changed.

Next, the method 100 continues to operation 130 by polishing the peripheral region 53 of the back side 50 of the semiconductor wafer 5. In some embodiments, prior to operation 130, wafer holder 21 rises in the direction of semiconductor wafer 5 and abuts central region 52 of semiconductor wafer 5 and holds semiconductor wafer 5 thereon. Further, the outer support base 23 is separated from the back side 50 of the semiconductor wafer 5 and descends in a direction away from the semiconductor wafer 5. Thus, the peripheral region 53 of the semiconductor wafer 5 is not supported by the outer support base 23.

Next, the polishing head 40 is moved to a position below the peripheral region 53 of the semiconductor wafer 5 as shown in FIG. 9 under the control of the link 25. In some embodiments, the polishing head 40 is further controlled to move upward by the link 25 such that the polishing layer 45 (Fig. 3) of the polishing head 40 contacts the peripheral region 53 of the back side 50 of the semiconductor wafer 5.

In some embodiments, after the polishing head 40 contacts the peripheral region 53 of the back side 50 of the semiconductor wafer 5, the polishing head 40 begins to grind the back side 50 of the semiconductor wafer 5 about the rotational axis r2 at a rotational speed of about 295 rpm to about 500 rpm. Peripheral area 53. During the polishing of the peripheral region 53 of the back side 50 of the semiconductor wafer 5, the wafer holder 21 drives the semiconductor wafer 5 to rotate about the rotation axis r1 at a rotation speed of about 2000 rpm. In some embodiments, the direction of rotation of the polishing head 40 about the axis of rotation r2 is opposite to the direction of rotation of the wafer holder 21 about the axis of rotation r1.

In some embodiments, during the polishing of the peripheral region 53 of the back side 50 of the semiconductor wafer 5, the link 25 begins to gradually approach the semiconductor wafer from the region of the central region 52 where the adjacent central region 52 borders the peripheral region 53. The edge 51 of the 5 advances such that the polishing head 40 grinds all surfaces of the peripheral region 53 of the back side 50 of the semiconductor wafer 5, with a portion of the central region 52 being repeatedly ground.

In some embodiments, when the polishing head 40 grinds the peripheral region 53, the height of the polishing head 40 at a position near the central region 52 of the semiconductor wafer 5 is higher than the position of the polishing head 40 near the edge 51 of the semiconductor wafer 5. The height is low, and the progressively upward pressure is applied to ensure that the polishing head 40 is in constant contact with the back side 50 of the semiconductor wafer 5, and the possibility of occurrence of vibration is reduced.

For example, as shown in FIG. 10, when the polishing head 40 polishes the first region 53 of the back side 50 of the semiconductor wafer 5 close to the first position of the central region 52, the polishing head 40 and the back side of the semiconductor wafer 5 The contact position of 50 is at height H2, and the position of contact of wafer holder 21 with back side 50 of semiconductor wafer 5 is at height H0. Since the peripheral region 53 of the back side 50 of the semiconductor wafer 5 is abutted upward by the polishing head 40, the height H2 is greater than the height H0. In an exemplary embodiment, the difference between the height H2 and the height H0 described above may be substantially equal to 2 mm. In an embodiment of polishing a semiconductor wafer 5 having a diameter of about 300 mm, a region of the back side 50 of the semiconductor wafer 5 from about 50 mm to about 135 mm from the center is ground by a polishing head 40 having a height set at H2. Part of the central region 52 is repeatedly ground.

Further, as shown in FIG. 11, the polishing head 40 is in contact with the back side 50 of the semiconductor wafer 5 when the polishing head 40 polishes the peripheral portion 53 of the back side 50 of the semiconductor wafer 5 to the second position of the edge 51. The position is at height H3, and the wafer holder 21 is in contact with the back side 50 of the semiconductor wafer 5 at a height H0. Since the peripheral region 53 of the back side 50 of the semiconductor wafer 5 is abutted upward by the polishing head 40, the height H3 is greater than the height H0. In an exemplary embodiment, the difference between the height H3 and the height H0 described above may be substantially equal to 3 mm. In an embodiment of polishing a semiconductor wafer 5 having a diameter of about 300 mm, The region of the back side 50 of the semiconductor wafer 5 from about 75 mm to about 150 mm from the center is ground by a polishing head 40 having a height set at H2.

However, it should be understood that various changes and modifications can be applied to the embodiments of the invention. The difference between the height H2 and the height H0 and the difference between the height H3 and the height H0 may be based on the properties of the material to be polished on the back side 50 of the semiconductor wafer 5, the rotational speed of the polishing head 40, or applied to the semiconductor wafer 5. The type of the polishing liquid on the back side 50 is changed, and the purpose of enhancing the grinding effect can be achieved as long as the condition that the height H3 is greater than the height H2 is satisfied.

In some embodiments, during the polishing of the peripheral region 53 of the back side 50 of the semiconductor wafer 5 by the polishing head 40, the grinding link 25 continuously applies pressure to the polishing head 40 toward the back side 50 of the semiconductor wafer 5, and The polishing layer 45 is maintained in continuous contact with the peripheral region 53 of the back side 50 of the semiconductor wafer 5, and the polishing layer 45 is not separated from the peripheral region 53 of the back side 50 of the semiconductor wafer 5. On the other hand, the adjustment of the polishing head 40 from the above height H2 to the height H3 is directly adjusted from the height H2 to the height H3 at a predetermined time. Alternatively, the adjustment of the polishing head 40 from the height H2 to the height H3 is performed gradually over a relatively long period of time (for example, within 1 second).

It is to be noted that since the first annular structure 42 of the support layer 42 of the polishing head 40 is gradually increased in the radial direction, when the polishing head 40 is close to the position of the edge 51 of the semiconductor wafer 5, even the semiconductor wafer 5 The warpage is caused by the abutment of the polishing head 40, and the abrasive sheet 452 (Fig. 4) is still in close contact with the back side 50 of the semiconductor wafer 5. Therefore, the polishing head 40 can efficiently grind the region on the back side 50 of the semiconductor wafer 5 that is close to the edge 51.

On the other hand, since the polishing pad 452 is used for grinding a semiconductor wafer The bump 454 (Fig. 5) of the back side 50 of 5 has a curved outer surface, and the bump 454 is in contact with the back side 50 of the semiconductor wafer 5 with a relatively small dot area. Thus, the polishing head 40 can grind the area on the back side 50 of the semiconductor wafer 5 that is relatively close to the edge 51. At the same time, it is also effective to prevent the polishing head from being exposed to the outside of the edge 51 of the semiconductor wafer 5 after being pressed by the strip-shaped abrasive sheet, thereby causing the front surface of the semiconductor wafer 5 to be contaminated by the abrasive particles. In an exemplary embodiment, the photoresist material on the back side 50 of the semiconductor wafer 5 near the edge 51 is completely ground. In another exemplary embodiment, the photoresist material that extends inwardly from the edge 51 in the range of about 1 mm is not subjected to grinding. In this way, in a part of the process of avoiding polishing the bevel structure on the edge 51 of the semiconductor wafer 5, the polishing head 40 can grind the maximum area of the back side 50 of the semiconductor wafer 5 without causing The above-mentioned conductive structure material is pealed.

The above embodiment employs an abrasive sheet having a plurality of bumps to grind the back side of the semiconductor wafer. Since the bump has a curved outer surface, the contact point of the bump with the back side of the semiconductor wafer is small, so that the polishing area can be precisely controlled. In addition, due to the bumps and being spaced apart from each other, the chipping generated during the grinding process can be eliminated by centrifugal force through the passage between the bumps. Therefore, the procedure for polishing the polishing sheet with the horizontal stripe shape reduces the time required to clean the semiconductor wafer with the inner layer sponge, thereby effectively improving the production efficiency.

Some embodiments of the present invention provide a polishing head. The polishing head includes a base. The polishing head further includes a support layer disposed on the base. The polishing head also includes an abrasive layer disposed over the support layer. The abrasive layer includes a plurality of bumps. The bumps have curved outer surfaces and are spaced apart from one another.

In an embodiment, the base has an inner portion. Inner part It is spaced apart from an outer edge of the base. The support layer includes a first annular structure and a central structure. The first annular structure is located between the inner portion and the outer edge. The center structure is disposed at the inner portion. The first annular structure is spaced apart from the central structure, and the abrasive layer is disposed over the first annular structure and the central structure.

In an embodiment, the support layer further includes a second annular structure, the second annular structure is located between the first annular structure and the central structure, and is spaced apart from the first annular structure and the central structure, wherein the polishing layer It is disposed above the second annular structure.

In an embodiment, the height of the first annular structure gradually increases from the inner portion of the base toward the outer edge of the base.

In one embodiment, the polishing layer includes a plurality of abrasive sheets, and adjacent two abrasive sheets are spaced apart from one another.

In an embodiment, the support layer includes a lower layer body and an upper layer body. The lower layer is connected to the base. The upper layer connects the lower layer to the polishing layer. The upper layer is separated from the base by a height difference.

In an embodiment, the upper layer body comprises a PVA sponge.

Some embodiments of the present invention provide a method of polishing a back side of a semiconductor wafer. The above method includes providing a polishing head. An abrasive layer on the polishing head for polishing the back side of the semiconductor wafer includes a plurality of bumps having curved outer surfaces spaced apart from one another. The method also includes contacting a central region on the back side of the semiconductor wafer with the abrasive layer of the polishing head to polish the central region. The method further includes contacting a peripheral region surrounding the central region on the back side of the semiconductor wafer with the abrasive layer of the polishing head to polish the peripheral region. The height at which the polishing head grinds the central region is greater than the height at which the polishing head grinds the peripheral region.

In one embodiment, in the step of polishing the peripheral region, the polishing head progressively advances toward an edge of the semiconductor wafer from the boundary between the central region and the peripheral region. In a first position in the peripheral region near the central region, the polishing head is at a first height, and in a second position in the peripheral region near the edge of the semiconductor wafer, the polishing head is at a second height, second The height is greater than the first height.

In one embodiment, the method further includes rotating the polishing head to move the fracture to a spacing between adjacent two bumps and discharging between the polishing head and the semiconductor wafer.

The above summary of the features of the various embodiments of the invention are in the It will be appreciated by those of ordinary skill in the art that the present disclosure may be readily utilized as a variation or design basis for other structures or processes to achieve the same objectives and/or advantages of the embodiments of the invention. It is to be understood by those of ordinary skill in the art that the invention may be modified or substituted without departing from the spirit and scope of the invention. With retouching.

Claims (10)

A polishing head comprising: a base; a support layer disposed on the base, wherein the support layer comprises a central structure and a first annular structure surrounding the central structure, and the first annular structure Separating from the central structure; and an abrasive layer disposed on the support layer and including a plurality of bumps having a curved outer surface spaced apart from each other. The polishing head according to claim 1, wherein the base has an inner portion spaced apart from an outer edge of the base, wherein the central structure of the support layer is disposed at the inner portion. The first annular structure of the support layer is located between the inner portion and the outer edge of the base, and the first annular structure and the central structure have the abrasive layer thereon. The polishing head of claim 2, wherein the support layer further comprises a second annular structure, the second annular structure is located between the first annular structure and the central structure, and the first ring The shaped structure is spaced from the central structure by a distance, wherein the second annular structure has the abrasive layer thereon. The polishing head of claim 2, wherein the height of the first annular structure gradually increases from the inner portion of the base toward the outer edge of the base. The polishing head according to claim 1, wherein the polishing layer comprises a plurality of polishing sheets, and two adjacent polishing sheets are spaced apart from each other. The polishing head of claim 1, wherein the support layer comprises: a lower layer body coupled to the base; An upper layer body is connected to the underlying layer body, wherein the upper layer body is separated from the pedestal by a height difference by the lower layer body. The polishing head of claim 6, wherein the upper layer body comprises a polyvinyl alcohol (PVA) sponge. A method of polishing a back side of a semiconductor wafer, comprising: providing a polishing head, wherein the polishing head has an abrasive layer, the polishing layer comprising a plurality of bumps having curved outer surfaces spaced apart from each other; The polishing layer of the polishing head contacts a central region on the back side of the semiconductor wafer to polish the central region; and the polishing layer of the polishing head contacts the central region on the back side of the semiconductor wafer a peripheral region for grinding the peripheral region; wherein the polishing head grinds the peripheral region at a height greater than a height at which the polishing head grinds the central region. The method of claim 8, wherein in the step of grinding the peripheral region, the polishing head gradually advances from an edge of the central region to the peripheral region toward an edge of the semiconductor wafer; wherein the periphery In a first position in the region adjacent to the central region, the polishing head is at a first height, and in the peripheral region is adjacent to a second position of the edge of the semiconductor wafer, the polishing head is located at a second position Height, the second height being greater than the first height. The method of claim 8, wherein the polishing the head polishes the central region and the peripheral region, comprising rotating the polishing head to move the fragmentation generated during the grinding to the adjacent two of the convex portions. Between the blocks, the chips are discharged between the polishing head and the semiconductor wafer.