JP3575944B2 - Polishing method, polishing apparatus, and method of manufacturing semiconductor integrated circuit device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a polishing method, a polishing apparatus, and a manufacturing technique of a semiconductor integrated circuit device, and is particularly effective when applied to a chemical mechanical polishing (CMP) technique in a manufacturing process of a semiconductor integrated circuit device. It is about technology.
[0002]
[Prior art]
The CMP technique used in a manufacturing process of a semiconductor integrated circuit device is a technique used when an excessive portion of a buried conductor film is selectively removed at the time of flattening an interlayer insulating film and forming a plug or the like.
[0003]
The planarization by the CMP can realize a flatness of the order of several nanometers over the entire semiconductor chip, and can form a mirror-like surface without any surface morphology (shape) and defects, thereby forming an excellent surface state.
[0004]
A specific method of CMP is, for example, as follows. First, the back surface of a semiconductor wafer is attached to a wafer holding portion of a CMP polishing apparatus via a pad (back pad). A guide ring is provided on the outer periphery of the semiconductor wafer for the main purpose of preventing the semiconductor wafer from coming off during the polishing process.
[0005]
Subsequently, after the abrasive is dropped on the polishing pad arranged to face the main surface of the semiconductor wafer, the semiconductor wafer is pressed against the polishing pad by moving the wafer holder in the direction of the polishing pad.
[0006]
Then, the main surface of the semiconductor wafer is polished by moving the semiconductor wafer and the polishing pad relative to each other in a direction horizontal to the main surfaces while a predetermined pressure is uniformly applied to the surface of the semiconductor wafer. .
[0007]
The polishing pad includes, for example, a soft polishing pad, a hard polishing pad, and a two-layer pad in which the two types of pads are bonded. The soft polishing pad has good uniformity in the amount of polishing in the main surface of the semiconductor wafer because the polishing pad follows the shape of the main surface of the semiconductor wafer, but it cannot be said that the flatness representing the degree of elimination of the level difference is sufficient. On the other hand, the hard polishing pad does not follow the shape of the main surface of the semiconductor wafer because the polishing pad does not follow the shape of the main surface of the semiconductor wafer. Further, the two-layer pad has properties intermediate to both soft and hard polishing pads.
[0008]
The polishing pad is damaged when polishing a semiconductor wafer or the like. In order to remove the damaged layer, a dressing process for shaving the polishing pad with diamond or the like is performed. The polishing pad is replaced when the polishing pad is worn down to a certain thickness and the polishing uniformity is degraded.
[0009]
By the way, as described above, when a hard polishing pad is used, the flattening of the steps is excellent, but the uniformity of the polishing amount is poor. This is because if the pressure on the semiconductor wafer is a mechanical rigid pressure, the entire surface of the semiconductor wafer is uniformly pressed.
[0010]
That is, when a polishing pad made of a viscoelastic body is pressed against a plate-shaped semiconductor wafer or the like by applying uniform pressure to the polishing pad and the polishing pad and the semiconductor wafer are relatively moved in a direction horizontal to each other's main surfaces, the polishing pad is Is compressed by pressure, but a portion of the polishing pad which is located on the outer periphery of the semiconductor wafer and is not compressed tries to sneak into the back surface of the semiconductor wafer by relative motion, so that stress concentrates on the end face of the semiconductor wafer.
[0011]
Therefore, the vicinity of the end face of the semiconductor wafer is abnormally polished, and a region having a large amount of polishing is generated in a region of about 1 to 2 cm from the outer periphery of the semiconductor wafer. In addition, the present inventors have found that rigid pressurization has many factors such as mechanical processing accuracy and variations in the thickness of semiconductor wafers.
[0012]
Therefore, according to the technology studied by the present inventor as a technology considering such a problem, a space in which a fluid such as air can flow between a wafer holding portion and a back pad of a CMP polishing apparatus is formed as a film. There is a method in which a fluid is caused to flow in the space and the semiconductor wafer is pressurized through the above-mentioned film by the fluid pressure at that time.
[0013]
In the case of this technique, since the pressure on the semiconductor wafer is performed by the pressure of a fluid or the like, there is no mechanical variation, and the pressure can be uniformly applied to the semiconductor wafer.
[0014]
The CMP polishing technique is described, for example, in Press Journal Inc., issued on December 20, 1993, “Monthly Semiconductor World, January 1994”, pp. 58-62.
[0015]
[Problems to be solved by the invention]
However, in the case of the CMP technique using the fluid pressurization method, due to the mechanical properties of the film described above, stress concentration occurs locally on the outer periphery of the semiconductor wafer, and as a result, a region with a large amount of polishing occurs on the outer periphery of the semiconductor wafer. The inventor has found that there is a problem.
[0016]
An object of the present invention is to provide a technique capable of improving in-plane polishing uniformity of an object to be polished during a polishing process using a CMP polishing technique.
[0017]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0018]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0019]
In the polishing method of the present invention, the surface to be polished of the object to be polished held on the low rigid thin plate of the object to be polished via the back pad is polished by the fluid pressure mechanism provided in the holder to be polished. A polishing method for chemically and mechanically polishing while pressed against a pad, wherein the low-rigidity thin plate is so formed that a pressure distribution in a plane of the object to be polished becomes uniform throughout the polishing process. The polishing process is performed by setting the deformed state of the bent portion on the outer periphery of the above.
[0020]
The method of manufacturing a semiconductor integrated circuit device according to the present invention includes, after forming an insulating film on a semiconductor wafer, holding the semiconductor wafer via a back pad on a low-rigidity thin plate side of a wafer holding unit in a polishing apparatus;
When polishing the surface to be polished of the semiconductor wafer held by the wafer holding unit chemically and mechanically in a state pressed against a polishing pad by a fluid pressure mechanism provided in the wafer holding unit,
Polishing is performed by setting the deformed state of the bent portion on the outer periphery of the low-rigidity thin plate so that the pressure distribution in the plane of the semiconductor wafer is entirely uniform, and the upper surface of the insulating film is flattened. And a process.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. (Note that components having the same function are denoted by the same reference numerals throughout the drawings for describing the embodiments, and repetitive description thereof will be omitted.) Do).
[0022]
(Embodiment 1)
FIG. 1 is an explanatory view of a polishing apparatus according to an embodiment of the present invention, FIGS. 2 and 3 are enlarged explanatory views of main parts in the polishing apparatus of FIG. 1, and FIG. 4 is a polishing process using the polishing apparatus of FIG. FIG. 5 is an explanatory view of various pressure distributions in the surface of a semiconductor wafer when the polishing is performed, and FIGS. 5 to 7 are cross-sectional views of main parts in a manufacturing process of a semiconductor integrated circuit device using the polishing apparatus of FIG.
[0023]
The polishing apparatus 1 according to the first embodiment shown in FIGS. 1 and 2 is a polishing apparatus used when polishing a main surface of, for example, a semiconductor wafer (an object to be polished) 2 by CMP (Chemical Mechanical Polishing).
[0024]
A platen 4 is rotatably supported in a housing 3 of the polishing apparatus 1 so as to be rotatable about a rotation shaft 4a installed perpendicularly to a main surface thereof. A polishing pad 5 is attached on the main surface of the surface plate 4. The polishing pad 5 is made of a hard material such as polyurethane.
[0025]
Above the surface plate 4, a dresser section 6, an abrasive supply pipe 7, and a wafer carrier (a workpiece holding section, a wafer holding section) 8 are installed in order from the left of FIG. 1.
[0026]
The dresser 6 is a mechanism for removing a portion of the polishing pad 5 consumed by the polishing process, and is capable of moving linearly in the horizontal and vertical directions with respect to the main surface of the platen 4. And is installed so as to be rotatable about a central axis perpendicular to the main surface of the surface plate 4.
[0027]
The polishing agent supply pipe 7 is a component for supplying the polishing agent 9 used in the polishing process onto the main surface of the polishing pad 5, and is installed substantially above the center of the platen 4.
[0028]
The wafer carrier 8 is a mechanism that holds the semiconductor wafer 2 and presses the main surface of the semiconductor wafer 2 against the polishing pad 5 using a fluid pressure during the polishing process. It is installed so as to be able to move linearly in the horizontal and vertical directions, and is installed so as to be rotatable about a central axis perpendicular to the main surface of the surface plate 4.
[0029]
A fluid inflow chamber (fluid chamber) 8b is provided inside the carrier main body 8a of the wafer carrier 8. A fluid such as air is supplied into the fluid inflow chamber 8b through a fluid supply pipe (fluid inflow portion) 8c.
[0030]
The fluid inflow chamber 8b communicates with a fluid pressurizing chamber (fluid chamber) 8e via a fluid pressure equalizing plate 8d. The fluid pressure equalizing plate 8d is made of, for example, porous ceramic, and supplies the air supplied to the fluid inflow chamber 8b uniformly into the fluid pressurizing chamber 8e so that the pressure applied to the surface of the semiconductor wafer 2 becomes uniform. It is a member to be adjusted.
[0031]
The fluid pressurizing chamber 8e is formed by a film 8f provided on a lower surface of the carrier body 8a, that is, a surface facing the polishing pad 5.
[0032]
The film 8f is made of a flexible material such as polyethylene so as to be deformable by a fluid such as air supplied into the fluid pressurizing chamber 8e, and has a back pad 8g on its main surface. The semiconductor wafer 2 is held with its main surface opposed to the polishing pad 5 side. The back pad 8g is made of, for example, polyurethane or silicone rubber.
[0033]
The film 8f and the back pad 8g have perforations 8h (see FIG. 2) for adsorbing the semiconductor wafer 2 to the back pad 8g when the semiconductor wafer 2 is carried by the wafer carrier 8. The suction hole 8h is formed so as to communicate the fluid pressurizing chamber 8e with the outside world.
[0034]
The outer periphery of the film 8f is sandwiched and fixed by a carrier body 8a and a guide ring 8i provided on the outer periphery of the lower surface so as to surround the semiconductor wafer 2. The guide ring 8i is a member for preventing the semiconductor wafer 2 from coming off the wafer carrier 8 during the polishing process, and is made of a material harder than abrasive particles such as aluminum nitride or silicon carbide.
[0035]
That is, the thickness of the guide ring 8i and the thickness from the lower surface of the film 8f to the main surface of the semiconductor wafer 2 can always be kept constant. Thus, the main surface of the semiconductor wafer 2 can always be polished well.
[0036]
Next, a main part of the wafer carrier 8 according to the first embodiment will be described with reference to FIG.
[0037]
In the first embodiment, the deformation state of the bent portion of the film 8f near the outer periphery of the semiconductor wafer 2 is set so that the distribution of the pressure applied to the surface of the semiconductor wafer 2 during the polishing process becomes uniform as a whole. Have been. Accordingly, it is possible to reduce the occurrence of stress concentration on the outer periphery of the semiconductor wafer 2, so that it is possible to suppress the outer periphery of the semiconductor wafer 2 from being abnormally polished.
[0038]
In the first embodiment, the boundary between the region where the film 8f contacts the back pad 8g and the region where the film 8f does not contact the back pad 8g corresponds to the boundary between the necessary region and the unnecessary region on the semiconductor wafer 2. ing. The necessary area is an area necessary for manufacturing a product.
[0039]
The reason why the peak of the stress concentration is concentrated is that the research by the present inventors has found that the film 8f hits the boundary portion between the region in contact with the back pad 8g and the region not in contact with the back pad 8g and the vicinity thereof.
[0040]
That is, by arranging the boundary between the region where the film 8f contacts the back pad 8g and the region where the film 8f does not contact the unnecessary region on the outer periphery of the semiconductor wafer 2, the outer periphery of the semiconductor wafer 2 is caused by the peak of the stress concentration. Even if the phenomenon of abnormal polishing occurs, the abnormally polished area can be generated in an area unnecessary for the production of the product, so that the polishing can be performed without lowering the reliability and yield of the product. Processing can be performed.
[0041]
In FIG. 3, A is the thickness of the film 8f, B is the thickness of the guide ring 8i, C is the thickness of the back pad 8g, D is the thickness of the semiconductor wafer 2, and E is the inner wall of the guide ring 8i. G is the gap between the film 8f and the back pad 8g, F is the amount of deflection of the film 8f, G is the distance from the edge of the semiconductor wafer 2 to the place where the film 8f is in contact with the back pad 8g, and θ is the film 8f. The deflection angle is shown.
[0042]
In the first embodiment, for example, the following various conditions are set in order to make the state of the film 8f as described above.
[0043]
The film 8f is made of, for example, polyethylene, and has a Young's modulus of, for example, about 400 kg / mm ² , and a thickness A of, for example, about 0.25 mm. The gap E is set to, for example, about 0 to 2 mm depending on the transfer accuracy of the semiconductor wafer 2, and is set to about 1 mm in the first embodiment.
[0044]
The deflection amount F of the film 8f is, for example, about 0 to 1 mm when the semiconductor wafer 2 is transferred (during vacuum suction), and is, for example, about 0.125 mm in the first embodiment. The amount of deflection F of 0 mm in this case is based on the amount of compression of the back pad 8g that holds the semiconductor wafer 2.
[0045]
In addition, the bending amount F of the film 8f can be expressed by F = 0.81 ³ (pl ⁴ / YA) ^1/2 when there is bending rigidity, and F = 12pl ⁴ / (384YA) when there is no bending rigidity. ³ ). p is pressure, l is the radius of the film 8f, and Y is Young's modulus.
[0046]
The distance G from the end of the semiconductor wafer 2 to the point where the film 8f contacts the back pad 8g is, for example, about 10 mm. This is because the concentration of stress on the outer periphery of the semiconductor wafer 2 by the polyurethane polishing pad 5 (Young's modulus; 10 kg / mm ² ) used in the first embodiment was experimentally up to about 10 mm. . At this time, the deflection angle θ of the film 8f was, for example, 0.65 °.
[0047]
As described above, when the gap E between the semiconductor wafer 2 and the guide ring 8i is, for example, 2 mm or less, the difference between the thickness B of the guide ring 8i and the thickness D of the semiconductor wafer 2 and the thickness C of the back pad 8g is obtained. However, the pressure is adjusted so as to be, for example, about 0.5 mm to 1 mm.
[0048]
The relationship between the Young's modulus Y of the film 8f and the thickness A of the film 8f is set as Y · A ^x = constant (X = 1 to 3). At this time, the deflection angle θ is set to 0 to 63 °, and tan θ = (B−C + D) / (E + G) = constant.
[0049]
The range of the bending angle was set to 0 ° as the minimum angle for performing fluid pressure on the semiconductor wafer 2. In addition, the maximum angle was set to 63 ° due to restrictions on the transfer (vacuum suction) of the semiconductor wafer 2.
[0050]
FIG. 4 shows a polishing process result when the main surface of the semiconductor wafer 2 is polished by such a polishing apparatus 1. 4, the horizontal axis indicates the position coordinates of the semiconductor wafer 2, and the vertical axis indicates the amount of pressurization.
[0051]
J indicates a pressure distribution caused by a reaction force of the polishing pad 5 when the surface of the semiconductor wafer 2 is uniformly pressurized and polished, and K indicates an effect on the semiconductor wafer 2 of the film 8f using the present invention. The pressure distribution is shown, and L represents the pressure distribution applied to the semiconductor wafer 2 according to the present invention.
[0052]
According to the first embodiment, the pressure applied to the semiconductor wafer 2 by the reaction force of the polishing pad 5 and the pressing force of the film 8f can be kept constant. Thereby, it is possible to uniformly polish the main surface of the semiconductor wafer 2.
[0053]
The operation of the polishing apparatus 1 will be described with reference to FIGS. First, after rotating the surface plate 4 about the rotation shaft 4a, an abrasive 9 is dropped on the main surface of the surface plate 4 through an abrasive supply pipe 7. At this time, the abrasive 9 is uniformly spread on the main surface of the platen 4 by centrifugal force by rotating the platen 4.
[0054]
Subsequently, the semiconductor wafer 2 is held by the wafer carrier 8 with its main surface facing the polishing pad 5, and then the wafer carrier 8 is lowered to the surface plate 4. At this time, the semiconductor wafer 2 is held by vacuum suction until the wafer carrier 8 descends.
[0055]
The wafer carrier 8 descending on the surface plate 4 makes the same rotational movement as the surface plate 4. In addition, it is oscillating at the same time as rotation. At this time, in the wafer carrier 8, the film 8f is deformed by supplying the air supplied to the fluid inflow chamber 8b through the fluid supply pipe 8c to the fluid pressurization chamber 8e via the fluid pressure equalizing plate 8d. Then, the semiconductor wafer 2 is pressed against the polishing pad 5 at a predetermined pressure. Thus, the main surface of the semiconductor wafer 2 is polished.
[0056]
After the polishing process is completed, the wafer carrier 8 is raised, and the dresser unit 6 is lowered instead. Then, the polishing pad 5 is conditioned by the rotating motion and the swinging motion of the platen 4.
[0057]
Next, a method of manufacturing a semiconductor integrated circuit device using the polishing apparatus 1 of the first embodiment will be described with reference to FIGS.
[0058]
FIG. 5 is a fragmentary cross-sectional view of the semiconductor wafer 2 during a manufacturing step of the semiconductor integrated circuit device according to the first embodiment. The semiconductor substrate 2s constituting the semiconductor wafer 2 is made of, for example, silicon (Si) single crystal, and a field insulating film 10 made of, for example, silicon dioxide (SiO ₂ ) is formed on the upper surface thereof. On the field insulating film 10, a wiring 11 made of, for example, aluminum (Al) or an Al alloy is formed.
[0059]
First, as shown in FIG. 6, an interlayer insulating film 12 made of, for example, SiO ₂ is deposited on such a semiconductor substrate 2s by a CVD method or the like. At this stage, irregularities are formed on the upper surface of the interlayer insulating film 12.
[0060]
Subsequently, after the semiconductor wafer 2 is held by the wafer carrier 8 of the polishing apparatus 1, the upper surface of the interlayer insulating film 12 on the main surface of the semiconductor wafer 2 is flattened by the polishing apparatus 1. Thereby, as shown in FIG. 7, the upper surface of the interlayer insulating film 12 on the semiconductor wafer 2 is flattened.
[0061]
According to the first embodiment, as described above, the inside of the main surface of the semiconductor wafer 2 can be uniformly flattened.
[0062]
According to the first embodiment, the following effects can be obtained.
[0063]
(1). The deformed state of the bent portion of the film 8f near the outer periphery of the semiconductor wafer 2 is changed so that the distribution of the pressure applied to the surface of the semiconductor wafer 2 during the polishing process becomes uniform throughout. Can be reduced, so that the outer periphery of the semiconductor wafer 2 is abnormally polished due to the stress concentration can be suppressed. That is, it is possible to improve the uniformity of the in-plane polishing amount of the semiconductor wafer 2. Therefore, the reliability and yield of the semiconductor integrated circuit device can be improved.
[0064]
(2). By setting the boundary between the region where the film 8f contacts the back pad 8g and the region where the film 8f does not contact the boundary between the necessary region and the unnecessary region on the semiconductor wafer 2, the outer periphery of the semiconductor wafer 2 is Even if the phenomenon of abnormal polishing occurs due to the stress concentration peak, the abnormally polished area can be caused in an area unnecessary for the manufacture of a product. Polishing can be performed without lowering reliability and yield.
[0065]
(Embodiment 2)
FIG. 8 is an enlarged cross-sectional view of a main part of a polishing apparatus according to another embodiment of the present invention.
[0066]
In the second embodiment, as shown in FIG. 8, the back pad 8g of the polishing apparatus 1 is made of a viscoelastic material such as silicone rubber or polyurethane.
[0067]
As a result, the film 8f that is not in contact with the back pad 8g before the polishing process is bent during the polishing process and comes into contact with the back pad 8g, so that pressure is concentrated on the contact area of the back pad 8g (the area of the distance G in FIG. 8). Even so, the pressure can be dispersed, so that the pressure applied to the main surface of the semiconductor wafer 2 can be made uniform as a whole.
[0068]
Therefore, in the second embodiment, the same effect as in the first embodiment can be obtained.
[0069]
(Embodiment 3)
FIG. 9 is an enlarged sectional view of a main part of a polishing apparatus according to another embodiment of the present invention.
[0070]
In the third embodiment, as shown in FIG. 9, the cross-sectional shape of the guide ring 8i of the polishing apparatus 1 is formed, for example, in an L-shape. The thickness of the lower step portion of the guide ring 8 i is equal to the thickness D of the semiconductor wafer 2.
[0071]
The diameter of the back pad 8g is larger than the diameter of the semiconductor wafer 2, and the back pad 8g is formed and held so that the end of the back pad 8g covers the step of the guide ring 8i.
[0072]
Thus, the load applied from the back pad 8g to the outer periphery of the semiconductor wafer 2 can be applied to the guide ring 8i, and the load can be dispersed. Can be reduced, and abnormal removal of the outer periphery of the semiconductor wafer 2 can be suppressed.
[0073]
In the third embodiment, the boundary between the region where the film 8f contacts the back pad 8g and the region where the film 8f does not contact the back pad 8g is set so as to be located further on the outer periphery than the outer periphery of the semiconductor wafer 2.
[0074]
Thereby, even if the outer periphery of the semiconductor wafer 2 is abnormally polished due to the peak of the stress concentration, the abnormally polished region is generated in a region unnecessary for manufacturing a product. It is possible.
[0075]
Therefore, in the third embodiment, the same effect as in the first embodiment can be obtained.
[0076]
As described above, the invention made by the inventor has been specifically described based on the embodiments. However, the present invention is not limited to the first to third embodiments, and can be variously modified without departing from the gist thereof. Needless to say,
[0077]
For example, in the above-described embodiment, the case where the CMP technique is used to planarize the interlayer insulating film has been described. However, the present invention is not limited to this, and various applications are possible. For example, a conductive film embedded in a connection hole. It can also be applied to flattening of the upper surface and the like.
[0078]
In the above description, the case where the invention made by the present inventor is mainly applied to the CMP technique used in the manufacturing process of the semiconductor integrated circuit device, which is the application field as the background, has been described, but the invention is not limited thereto. For example, it can be applied to a CMP technique used in a manufacturing process of a liquid crystal substrate or the like. The present invention is at least applicable to those using the CMP technique.
[0079]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0080]
(1). According to the polishing method of the present invention, during the polishing process, the deformation state of the bent portion on the outer periphery of the low-rigidity thin plate is set such that the pressure distribution in the surface of the workpiece is uniform throughout. Is performed, during the polishing process using the CMP polishing technique, the stress concentration generated on the outer periphery of the object to be polished can be reduced, so that the in-plane polishing uniformity of the object to be polished can be improved. .
[0081]
(2). According to the method of manufacturing a semiconductor integrated circuit device of the present invention, the polishing process is performed by setting the deformed state of the bent portion on the outer periphery of the low-rigidity thin plate so that the pressure distribution in the plane of the semiconductor wafer is entirely uniform. And flattening the upper surface of the insulating film formed on the semiconductor wafer, it is possible to reduce the concentration of stress generated on the outer periphery of the semiconductor wafer during the polishing process using the CMP polishing technique. Polishing uniformity of the in-plane insulating film can be improved. Therefore, the yield and reliability of the semiconductor integrated circuit device can be improved.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a polishing apparatus according to an embodiment of the present invention.
FIG. 2 is an enlarged explanatory view of a main part of the polishing apparatus of FIG. 1;
FIG. 3 is an enlarged explanatory view of a main part of the polishing apparatus of FIG. 1;
FIG. 4 is an explanatory diagram of various pressure distributions in a semiconductor wafer surface when a polishing process is performed by using the polishing apparatus of FIG. 1;
5 is a fragmentary cross-sectional view of the semiconductor integrated circuit device in a manufacturing step using the polishing apparatus of FIG. 1;
6 is a fragmentary cross-sectional view of the semiconductor integrated circuit device in a manufacturing step following that of FIG. 5 when the polishing apparatus of FIG. 1 is used;
7 is a fragmentary cross-sectional view of the semiconductor integrated circuit device in a manufacturing step following that of FIG. 6 when the polishing apparatus of FIG. 1 is used;
FIG. 8 is a cross-sectional view of a main part of a polishing apparatus according to another embodiment of the present invention.
FIG. 9 is a cross-sectional view of a main part of a polishing apparatus according to another embodiment of the present invention.
[Explanation of symbols]
1 polishing apparatus 2 semiconductor wafer (object to be polished)
2s Semiconductor substrate 3 Housing 4 Surface plate 4a Rotating shaft 5 Polishing pad 6 Dresser unit 7 Abrasive supply tube 8 Wafer carrier (substrate to be polished, wafer holder)
8a Carrier body 8b Fluid inflow chamber (fluid chamber)
8c Fluid supply pipe (fluid inflow section)
8d Fluid pressure equalizing plate 8e Fluid pressurizing chamber (fluid chamber)
8f film (low rigidity thin plate)
8g Back pad 8h Suction hole 8i Guide ring 9 Abrasive 10 Field insulating film 11 Wiring 12 Interlayer insulating film (insulating film)

Claims (5)

The outer peripheral portion is fixed to the polished object holding portion , the central portion is pushed downward by the fluid pressurizing mechanism, and the back surface of the polished surface of the polished object held via the back pad on the deformed low rigid thin plate, wherein a polishing treatment method for polishing chemically and mechanically in a state pressed against the polishing pad by the fluid pressure mechanism provided in the polishing target holding unit, when the polishing process, the pre-Symbol low rigidity sheet The product of the object to be polished acquires a boundary portion between a region in contact with the back pad and a region in contact with the back pad of a bent portion of a peripheral portion corresponding to a connection portion between the fixed outer peripheral portion and the deformed central portion, which is connected to the deformed central portion. A polishing method characterized in that the polishing method is arranged in a peripheral region that is not performed. 2. The polishing method according to claim 1, wherein the back pad is made of a viscoelastic body. A polishing apparatus for chemically and mechanically polishing a polished surface of a polished object held by a polished object holding portion against a polishing pad by a fluid pressure mechanism provided in the polished object holding portion. And
The fluid pressurizing mechanism section is provided on the polishing pad side in the fluid chamber provided in the polishing target holding section, a fluid inflow section for flowing fluid into the fluid chamber, and the polishing target holding section. Forming the fluid chamber, having a low-rigidity thin plate fixed to the polished-piece holding portion, the outer peripheral portion deformed by the pressure of the fluid flowing into the fluid chamber,
During polishing, the object to be polished disposed on the lower surface of the low-rigidity thin plate via a back pad is pressed downward at the center by the pressure of the fluid flowing into the fluid chamber, thereby deforming the low-rigidity rigid plate. Therefore a thin plate, having a structure for pressing the polishing pad,
During the polishing process, pre Symbol extruded downward and fixed outer peripheral portion of the low-rigidity thin plate, the boundary between the flexure region not in contact with the area in contact with the back pad near portion corresponding connecting portion between the deformed central portion part of the polishing apparatus characterized by product of the object to be polished is placed so as to be disposed in the region of the periphery which is not acquired. 4. The polishing apparatus according to claim 3, wherein a guide ring surrounding the object to be polished is provided on a surface facing the polishing pad in the object to be polished, and an outer peripheral edge of the back pad is guided by the guide. A polishing apparatus characterized by having a structure relating to a ring. After an insulating film is formed on the semiconductor wafer, the semiconductor wafer is fixed to the wafer holding portion of the polishing apparatus , the outer peripheral portion is fixed, and the central portion is pushed downward by a fluid pressurizing mechanism , and the semiconductor wafer is returned to the deformed low-rigid thin plate side. Holding through a pad;
When polishing the surface to be polished of the semiconductor wafer held by the wafer holding unit chemically and mechanically in a state pressed against a polishing pad by a fluid pressure mechanism provided in the wafer holding unit,
Before Symbol extruded downward and fixed outer peripheral portion of the low-rigidity thin plate, the boundary between the flexure area which is not in contact with the region in contact with the back pad near portion corresponding connecting portion between the deformed central portion, said semiconductor Performing a polishing process by setting the wafer so as to be arranged in a peripheral region where a product of the wafer is not obtained, and flattening the upper surface of the insulating film.

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