TWI624946B - Method for manufacturing semiconductor device and device manufactured by the same - Google Patents

Abstract

A method of manufacturing a semiconductor device and an element obtained by using the same. According to an embodiment, a substrate having at least a first region and a second region is provided, the first region includes a plurality of first gates, the second region includes a plurality of second gates, and the adjacent first gates And the adjacent second gate is separated by an insulating layer, wherein the upper surface of the insulating layer has a plurality of recesses. Thereafter, a capping layer is formed on the first gate, the second gate, and the insulating layer, and is filled in the recess. Next, the cap layer is removed to reach the upper surface of the insulating layer, thereby forming a plurality of insulating deposits to fill the recesses. Wherein the upper surface of the insulating deposit is substantially flush with the upper surface of the insulating layer.

Description

Manufacturing method of semiconductor element and application thereof

The present invention relates to a method of fabricating a semiconductor device and an element using the same, and more particularly to a method of fabricating a semiconductor device including a gate electrode having a sufficient height to improve the electronic characteristics of the fabricated semiconductor device.

In recent years, the size of semiconductor components has been decreasing. For semiconductor technology, increasing the size of semiconductor structures, improving speed, improving performance, increasing density, and reducing costs are all important development goals. As the size of semiconductor components shrinks, the electronic characteristics of the components must be maintained or even improved to meet market product requirements. For example, if the layers of the semiconductor structure and the associated components are defective or damaged, the electronic characteristics of the structure may be neglected, which is one of the important issues to be paid attention to in manufacturing the semiconductor component. In general, a semiconductor element having excellent electrical performance must have good properties such as a complete profile and a sufficient gate height. In general, the existing gate forming process causes a spacer loss which affects the gate height. Insufficient gate height can affect the electrical performance of the fabricated semiconductor components.

Therefore, how to produce a gate with sufficient height in the semiconductor process to solve the problem of gate height loss is one of the topics that the relevant industry pays attention to.

SUMMARY OF THE INVENTION The present invention relates to a method of fabricating a semiconductor device and an element for use thereof, which is obtained by using an insulating deposit to obtain a gate of a sufficient height to improve the electronic characteristics of the fabricated semiconductor device.

According to an embodiment, a method of fabricating a semiconductor device is proposed. Providing a substrate having at least one first region and a second region, the first region comprising a plurality of first gates, the second region comprising a plurality of second gates, and adjacent The first gate and the adjacent second gate are separated by an insulation, wherein the upper surface of the insulating layer has a plurality of recesses. Thereafter, a capping layer is formed on the first gate, the second gate, and the insulating layer, and the recesses are filled. Next, the cover layer is removed to reach the upper surface of the insulating layer.

According to an embodiment, a semiconductor structure is provided, including a substrate having at least a first region and a second region, wherein the first region includes a plurality of first gates, and the second region includes a plurality of second gates, and The adjacent first gate and the adjacent second gate are separated by an insulating layer, wherein the upper surface of the insulating layer has a plurality of recesses. The semiconductor structure further includes a plurality of insulating depositions filling the recesses, wherein the upper surface of the insulating deposit is substantially flush with the upper surface of the insulating layer.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

10‧‧‧Substrate

11, 11' ‧ ‧ first temporary structure

112‧‧‧First pseudo gate structure

112a‧‧‧First temporary layer

112h‧‧‧First hard mask layer

114, 214, 114’, 214’ ‧ ‧ spacers

16, 16'‧‧‧Contact etch stop layer

21, 21’ ‧ ‧ second temporary structure

212‧‧‧Second pseudo gate structure

212a‧‧‧Second temporary layer

212h‧‧‧Second hard mask layer

31, 31'‧‧‧ first bump

32, 32’‧‧‧second bump

41, 41'‧‧‧Mobile dielectric layer

42. 42'‧‧‧ High Density Plasma (HDP) Dielectric Layer

421‧‧‧The upper surface of the HDP dielectric layer

51‧‧‧Insulation

61‧‧‧ dent

70‧‧‧ Coverage

70'‧‧‧Insulating sediments

711‧‧‧ Upper surface of insulating deposits

A1‧‧‧ first area

A2‧‧‧Second area

A3‧‧‧Bump area

H0, H1‧‧‧ gate height

h‧‧‧Thickness of the cover layer

D‧‧‧ Depth of depression

1A to 1F are schematic views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 2A is an enlarged schematic view showing the gate and the insulating layer of the first temporary structure in Fig. 1D.

Fig. 2B is an enlarged schematic view showing the gate and the insulating layer of the first temporary structure in Fig. 1F.

The embodiment proposes a method of manufacturing a semiconductor element. The gate of the semiconductor device fabricated in accordance with the embodiments has sufficient final gate height and a complete surface profile to provide excellent electrical performance. The manufacturing method of the disclosed embodiment solves the problem of the gate height loss that often occurs in the conventional process for fabricating a conventional semiconductor device.

The following embodiments are presented in conjunction with the drawings to explain in detail the related manufacturing methods and the component structures obtained using the same. However, the disclosure is not limited to this. This disclosure does not show all possible embodiments. The structure and process may be modified and modified to meet the needs of the actual application without departing from the spirit and scope of the disclosure. Therefore, other implementations not presented in the present disclosure may also be applicable. Furthermore, The scale ratios on the drawings are not drawn to the scale of the actual product. Therefore, the description and illustration are for illustrative purposes only and are not intended to be limiting.

In an embodiment, the deposition of a cover layer is followed by a planarization step to form insulating depositions to fill the depressions generated by the previous steps, so that the upper surface of the insulating deposit is substantially flush with the upper surface of the gate. level. Thus, the semiconductor component fabricated in accordance with the embodiments has a gate having sufficient gate height and full surface profile. The manufacturing method of the embodiment can be applied to semiconductor components produced by many different manufacturing methods, such as semiconductor devices fabricated by high-k metal gate-metal (GMG) processes, but the disclosure Not limited to a particular aspect. The detailed manufacturing steps are not limited to the description and illustration of the embodiments, and may be modified and modified according to actual application conditions and process requirements. The following is a description of the embodiment of the HKMG process disclosed in the high-k dielectric layer (High K last), but it is not limited thereto.

1A to 1F are schematic views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. In an embodiment, a substrate 10 has at least a first area A1 and a second area A2. The substrate 10 in the illustration may further include a bump area A3. In one embodiment, the first area A1 and the second area A2 are, for example, an NMOS area and a PMOS area, respectively. In one embodiment, the bump region A3 may include at least one first bump 31 such as a logic bump, and a second bump 32 such as a SRAM bump. The manufacturing method proposed in the embodiment can be widely applied to semiconductor elements of different aspects. In one of the application states In the example, the first area A1 includes, for example, a plurality of first fin field effect transistors (first FinFETs), and the second area A2 includes, for example, a plurality of second fin field effect transistors (second FinFETs).

As shown in FIG. 1A, the first area A1 and the second area A2 of the substrate 10 respectively include at least a first dummy structure 11 and a second temporary structure 21. The first temporary structure 11 includes a first dummy gate structure 112 on the substrate 10, and spacers 114 are located on both sides of the first dummy gate structure 112. Similarly, the second temporary structure 21 includes a second dummy gate structure 212 on the substrate 10, and the spacers 214 are located on opposite sides of the second dummy gate structure 212.

In one embodiment, the first pseudo gate structure 112 includes a first temporary layer 112a formed on the substrate 10 and a first hard mask layer 112h formed on the first temporary layer 112a. The first temporary layer 112a includes, for example, a polysilicon layer or an amorphous germanium layer formed on a thin oxide layer. In one embodiment, the first hard mask layer 112h is, for example, but not limited to, a nitride layer, an oxide layer, or both; for example, the first hard mask layer 112h includes an amorphous layer. One layer of tantalum nitride on the tantalum layer and one oxide layer formed on the tantalum nitride layer. The spacers 114 may be a plurality of spacers or a single layer spacer as shown in FIG. 1A. Similarly, the second pseudo gate structure 212 includes a second temporary layer 212a (eg, a polysilicon layer or an amorphous layer formed on a thin oxide layer) formed on the substrate 10, and a second hard mask. A layer 212h (for example, one SIN layer formed on the amorphous germanium layer and one oxide layer formed on the SIN layer) is formed on the second temporary layer 212a. Similarly, the first bump located in the bump area A3 31 (e.g., a logic contact) and second bump 32 (e.g., an SRAM contact) each have a laminate structure similar to the first temporary structure 11 and the second temporary structure 21.

According to an application example, among the first temporary structure 11 and the second temporary structure 21 and the first bump 31 and the second bump 32, a thin oxide layer on the substrate 10 has a thickness of, for example, about 38 Å; The amorphous germanium layer on the oxide layer has a thickness of, for example, about 1100 Å. Therefore, the first temporary layer 112a and the second temporary layer 212a (and the temporary layers at the same positions in the first and second bumps 31 and 32) have the same height. However, in the first temporary structure 11, the second temporary structure 21, and the first bump 31 and the second bump 32, the hard mask layer may have different heights depending on the thickness of the oxide layer to which it belongs. For example, of the first and second temporary structures 11 and 21 and the first and second bumps 31 and 32, the SiN layer on the amorphous germanium layer has a thickness of, for example, about 100 Å. In the first region A1, the oxide layer of the first hard mask layer 112h has a thickness of, for example, about 400 Å. In the second region A2, the oxide layer of the second hard mask layer 212h has a thickness of, for example, about 450 Å. In the bump region A3 (third region), the oxide layers of the first bump 31 and the second bump 32 have a thickness of, for example, about 900 Å and 800 Å. It is to be noted that the foregoing numerical values are only one of the specifications that can be applied to the description, and are not intended to limit the scope of the disclosure.

Furthermore, in FIG. 1A, the semiconductor device further includes a contact etch stop layer (CESL) 16 formed on the substrate 10 and covering the substrate 10, the first temporary structure 11 and the second temporary structure 21 And the first bump 31 and the second bump 32 located in the bump area A3. In one of the application examples, flow chemical vapor deposition (flowable chemical vapor) Deposition, FCVD) process. A flow dielectric layer 41 is deposited on the device by a CVD process, and the flow dielectric layer 41 is ground by chemical mechanical polishing (CMP) to stop at the bump (eg, the first bump) 31), as shown in Figure 1A.

As shown in FIG. 1B, the semiconductor element is non-selectively etched to remove the top portions of the first and second temporary structures 11 and 21 and the first and second bumps 31 and 32 to produce a flat surface. . In FIG. 1B, the top surface of the contact etch stop layer 16, a portion of the spacers 114 and 214, and the oxidation of portions of the first and second hard mask layers 112h and 212h, the first and second bumps 31 and 32, The layer system was removed. In one application, the thickness of the remaining oxide layer after removal is, for example, about 200 Å.

As shown in FIG. 1C, part of the flow dielectric layer 41 is replaced with another dielectric layer, such as a high density plasma (HDP) dielectric layer 42 (ie, deposited by a high density plasma CVD process). One dielectric layer). In one embodiment, the flow dielectric layer 41 can be partially removed by SiCoNi etch back, and then a dielectric layer 42 is deposited by HDP CVD process, followed by CMP polishing to complete partial replacement of the dielectric layer.

As shown in FIG. 1D, the element is then polished to remove the first and second temporary structures 11 and 21 and the hard mask layer in the first and second bumps 31 and 32 (eg, the remaining oxidation in FIG. 1C) Layer and SiN layer). In FIG. 1D, a first temporary layer 112a (eg, comprising an amorphous germanium layer of about 1100 Å and a thin oxide layer of about 38 Å) and a second temporary layer 212a (and first and second bumps 31 and 32) The temporary layer) is substantially the same height. According to one of the application examples, the polysilicon or amorphous germanium in the temporary layer As a pseudo gate, it will be replaced by metal in the subsequent process to form a metal gate. For example, in the HKMG process disclosed in the high-k dielectric layer (High K last), a high-k dielectric layer is deposited in a trench formed by removing the dummy gate. The trench is then filled with a metal on the high-k dielectric layer to form a metal gate. Therefore, the profile of the spacer, including the shape and height, can have an inevitable effect on the gate. The spacer loss causes a loss in the height of the gate (such as a metal gate) formed by subsequent processes and an incomplete surface profile.

Structurally, the spacers (such as 114' and 214'), the contact etch stop layer 16', and the patterned inner dielectric layer (including the patterned dielectric layer 42' and the flow dielectric layer 41' As shown in Fig. 1D, it can be regarded as an insulation 51 as a whole. The gate of the first temporary structure 11' (the first gate, that is, the first temporary layer 112a), the gate of the second temporary structure 21' (the second gate, that is, the second temporary layer 212a), And the gates of the first and second bumps 31' and 32' are separated by an insulating layer 51.

In one embodiment, the spacers 114/114' and 214/214' and the contact etch stop layer 16/16' can be made from the same material (or different materials). The material of the hard mask layer may be different from the material of the spacers 114/114', 214/214' and the contact etch stop layer 16/16'. In one embodiment, the spacer and the material contacting the etch stop layer are, for example, atomic layer deposition (ALD) of carbonitride (SiCN). In one embodiment, the material of the HDP dielectric layer is, for example and without limitation, an oxide.

However, at this point in the process, there are usually structural defects, such as The recesses 61 formed at the upper surface of the insulating layer 51 shown in Fig. 1D. In one embodiment, the recesses 61 on the upper surface of the insulating layer 51 correspondingly span the top of the spacers 114', 214' and the contact etch stop layer 16'. The recess 61 located on the upper surface of the insulating layer 51 causes a problem of gate height loss and incomplete gate surface profile, resulting in failure of the component.

According to an embodiment, a capping layer 70 is formed on the insulating layer, the gate of the first temporary structure 11' (the first gate, that is, the first temporary layer 112a), and the second temporary structure 21' The gate (the second gate, that is, the second temporary layer 212a) and the gates of the first and second bumps 31' and 32' are as shown in FIG. 1E. The material of the cover layer 70 is filled and filled with the recesses 61. Thereafter, the cover layer 70 is removed by, for example, CMP until reaching the upper surface of the insulating layer 51, thereby forming insulating depositions 70' as shown in Fig. 1F.

In one embodiment, the thickness h of the cover layer 70 is about 1.5 to 2.5 times the depth d of one of the recesses 61. In one embodiment, the cover layer 70 has a thickness h of about 250 Å. In one embodiment, the cap layer 70 comprises an oxide, tantalum nitride or tantalum carbonitride (SiCN) and can be deposited in an ALD manner. The spacers 114/214 and the contact etch stop layer 16 may be formed of the same material. In one embodiment, the cover layer 70 is comprised of the same material as at least one of the spacers 114/214 and the contact etch stop layer 16. Alternatively, the cover layer 70 is comprised of at least one of the spacers 114/214 and the contact etch stop layer 16 comprising a different material.

Please refer to Figures 2A and 2B. 2A is a magnified view of the gate (first gate, ie, the first temporary layer 112a) of the first temporary structure in FIG. 1D and the insulating layer schematic diagram. Fig. 2B is an enlarged schematic view showing the gate and the insulating layer of the first temporary structure in Fig. 1F. In one embodiment, the recess 61 on the upper surface of the insulating layer 51 correspondingly spans the top of the spacer 114' and the contact etch stop layer 16' as shown in Fig. 2A.

2A and 2B show the gate height H0 of the insulating deposit 70' and the gate height H1 after the insulating deposit 70' is formed, respectively; H0 < H1 due to the loss of the spacer. According to an embodiment, the insulating deposit 70' fills the recesses 61, and the upper surface 711 of the insulating deposit 70' is substantially flush with the upper surface of the insulating layer 51, such as a dielectric layer (HDP dielectric layer) The upper surface 421 of 42' is flush. After the formation of the insulating deposit 70', the subsequently formed gate will have a sufficient gate height (e.g., H1). In one embodiment, the spacer and the insulating deposit 70' contact the sidewall of the first gate of the first temporary structure 11' of the first region A1 and the second temporary structure 21' of the second region A2. The sidewall of the second gate.

Although FIG. 2B is a view showing that the insulating deposit 70' is located at the first gate of the first temporary structure (ie, the first temporary layer 112a) and the insulating layer, the second gate of the second temporary structure ( That is, the first temporary layer 212a) and the insulating layer having the insulating deposit 70' are also similar to the structure of FIG. 2B to obtain a sufficient gate height.

According to the above, the semiconductor device produced by the manufacturing method disclosed in the embodiment can effectively solve the problem of gate height loss. According to an embodiment, the resulting semiconductor device has a gate with sufficient gate height and a complete surface profile to provide excellent electrical performance. Furthermore, the manufacturing method disclosed in the embodiment that can solve the problem of gate height loss simplifies the process, and not only improves the product yield but also controls the manufacturing cost.

Furthermore, other embodiments of different gate structures can also be applied to the present disclosure, and can be appropriately changed and modified according to the needs of practical applications. Therefore, the drawings 1A-1F and 2A and 2B are only for the purpose of describing the embodiments, and are not intended to limit the scope of protection. Thus, it will be apparent to those skilled in the art that the shapes or relative positions of the various components in the structure may be adjusted accordingly depending on the structure and/or process steps employed.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (20)

A method of fabricating a semiconductor device, comprising: providing a substrate having at least a first region including a plurality of first gates and a second region including a plurality of second gates, and The adjacent first gates and the adjacent second gates are separated by an insulation, wherein an upper surface of the insulating layer has a plurality of recesses, and the The insulating layer includes a plurality of spacers formed on sidewalls of the first gates and the second gates, and a contact etch stop layer is formed on the outer side of the spacers, wherein the upper surface of the insulating layer is located The recesses correspondingly span the top of the spacers and the contact etch stop layer; forming a capping layer on the first gates, the second gates, and the insulating layer, And filling the recesses; and removing the cover layer to reach the upper surface of the insulating layer. The manufacturing method of claim 1, wherein one of the thicknesses of the cover layer is about 1.5 to 2.5 times the depth of one of the depressions. The manufacturing method of claim 1, wherein one of the cover layers has a thickness of about 250 Å. The manufacturing method of claim 1, wherein the cover layer comprises an oxide, tantalum nitride or tantalum carbonitride (SiCN). The manufacturing method of claim 1, wherein the insulating layer further comprises: A patterned interlayer dielectric (ILD) is formed in each of the spaces adjacent to the contact etch stop layer. The manufacturing method of claim 5, wherein the spacers and the contact etch stop layer are formed of the same material. The manufacturing method of claim 5, wherein the cover layer comprises at least one of the spacers and the contact etch stop layer of the same material. The manufacturing method of claim 5, wherein the patterned interlayer dielectric layer is a single layer or a composite layer. The manufacturing method of claim 1, wherein the covering layer is removed by chemical mechanical polishing (CMP). The manufacturing method of claim 1, wherein the first gates and the second gates are respectively a first silicon-containing gate and a second germanium-containing gate, The manufacturing method includes: replacing the first germanium-containing gates and the second germanium-containing gates with metal to form a plurality of first metal gates and a plurality of second metal gates, respectively. The manufacturing method of claim 10, further comprising: removing the first germanium-containing gates and the second germanium-containing germanium-containing germanium portions to form a plurality of first trenches and a plurality of a second trench; forming a high-k dielectric layer in the first trench and the second trench; and in the first trench and the The metal is formed in the trenches on the high-k dielectric layer. The manufacturing method of claim 1, wherein the first region comprises a plurality of first fin field effect transistors (first FinFETs), and the second region comprises a plurality of second fin field effect transistors ( Second FinFETs). A semiconductor device structure comprising: a substrate having at least a first region and a second region, the first region comprising a plurality of first gates, the second region comprising a plurality of second gates, adjacent The first gates and the adjacent second gates are separated by an insulation, wherein an upper surface of the insulating layer has a plurality of recesses, and the insulating layer The method includes a plurality of spacers formed on sidewalls of the first gates and the second gates, and a contact etch stop layer formed on the outer sides of the spacers; and a plurality of insulating depositions Filling the recesses, wherein the insulating deposits of the recesses correspondingly span the top of the spacers and the contact etch stop layer; wherein the upper surfaces of the insulating deposits are substantially flush with The upper surface of the insulating layer. The structure of claim 13, wherein the insulating deposits comprise an oxide, tantalum nitride or tantalum carbonitride (SiCN). The structure of claim 13, wherein the insulating layer further comprises: a patterned interlayer dielectric layer formed in each of the spaces adjacent to the contact etch stop layer. The structure of claim 15, wherein the spacers and the contact etch stop layer are formed of the same material. The structure of claim 15, wherein the cover layer comprises at least one of the spacers and the contact etch stop layer of the same material. The structure of claim 15, wherein the patterned interlayer dielectric layer is a single layer or a composite layer. The structure of claim 15, wherein the spacers and the insulating deposits contact sidewalls of the first gates and the second gates. The structure of claim 13, wherein the first region comprises a plurality of first fin field effect transistors (first FinFETs), and the second region comprises a plurality of second fin field effect transistors (second FinFETs).