TW201543685A - Method for manufacturing semiconductor device and device manufactured by the same - Google Patents
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Description
本發明是有關於一種半導體元件之製造方法及應用其製得之元件,且特別是有關於一種包括具有足夠高度閘極的半導體元件之製造方法,進而改善製得之半導體元件的電子特性。 The present invention relates to a method of fabricating a semiconductor device and an element using the same, and more particularly to a method of fabricating a semiconductor device including a gate electrode having a sufficient height to improve the electronic characteristics of the fabricated semiconductor device.
近年來半導體元件尺寸日益減小。對半導體科技來說,持續縮小半導體結構的尺寸之外,改善速率、增進效能、提高密度及降低成本,都是重要的發展目標。隨著半導體元件尺寸的縮小,元件的電子特性也必須維持甚至是加以改善,以達到市場產品之要求。例如,半導體結構的各層與所屬元件如有缺陷或損傷,會對結構的電子特性造成無法忽視之影響,是製造半導體元件需注意的重要問題的之一。一般而言,擁有優異電性表現的半導體元件,其閘極必須具 有良好性質,例如完整的輪廓和足夠的閘極高度。一般現有的閘極形成製程會產生間隙物損失(spacer loss)進而影響閘極高度的問題。而閘極高度不足會影響到製得半導體元件之電性表現。 In recent years, the size of semiconductor components has been decreasing. For semiconductor technology, increasing the size of semiconductor structures, improving speed, improving performance, increasing density, and reducing costs are all important development goals. As the size of semiconductor components shrinks, the electronic characteristics of the components must be maintained or even improved to meet market product requirements. For example, if the layers of the semiconductor structure and the associated components are defective or damaged, the electronic characteristics of the structure may be neglected, which is one of the important issues to be paid attention to in manufacturing the semiconductor component. In general, a semiconductor component with excellent electrical performance must have a gate Good properties such as full profile and sufficient gate height. In general, the existing gate forming process causes a spacer loss which affects the gate height. Insufficient gate height can affect the electrical performance of the fabricated semiconductor components.
因此,如何於半導體製程中製得具充足高度的閘極,解決閘極高度損失的問題,是相關業者注意的課題之一。 Therefore, how to produce a gate with sufficient height in the semiconductor process to solve the problem of gate height loss is one of the topics that the relevant industry pays attention to.
本發明係有關於一種半導體元件之製造方法及應用其製得之元件,係以絕緣沈積物來獲得足夠高度的閘極,進而改善製得之半導體元件的電子特性。 SUMMARY OF THE INVENTION The present invention relates to a method of fabricating a semiconductor device and an element for use thereof, which is obtained by using an insulating deposit to obtain a gate of a sufficient height to improve the electronic characteristics of the fabricated semiconductor device.
根據實施例,提出一種半導體元件之製造方法。提供具有至少一第一區域和一第二區域之一基板,第一區域包括複數個第一閘極(first gates),第二區域包括複數個第二閘極(second gates),且相鄰的第一閘極和相鄰的第二閘極係以一絕緣層(insulation)分隔開來,其中絕緣層之上表面具有複數個凹陷(recesses)。之後,形成一覆蓋層(capping layer)於第一閘極、第二閘極和絕緣層上,並填入該些凹陷。 接著,移除覆蓋層至到達絕緣層之上表面。 According to an embodiment, a method of fabricating a semiconductor device is proposed. Providing a substrate having at least one first region and a second region, the first region comprising a plurality of first gates, the second region comprising a plurality of second gates, and adjacent The first gate and the adjacent second gate are separated by an insulation, wherein the upper surface of the insulating layer has a plurality of recesses. Thereafter, a capping layer is formed on the first gate, the second gate, and the insulating layer, and the recesses are filled. Next, the cover layer is removed to reach the upper surface of the insulating layer.
根據實施例,提出一種半導體結構,包括具有至少一第一區域和一第二區域之一基板,其中第一區域包括複數個第一閘極,第二區域包括複數個第二閘極,且相鄰的第一閘極和相鄰的第二閘極係以一絕緣層分隔開來,其中絕緣層之上表面具有複數個凹陷。半導體結構更包括複數個絕緣沈積物(insulating depositions)填滿該些凹陷,其中絕緣沈積物的上表面係實質上齊平於絕緣層之上表面。 According to an embodiment, a semiconductor structure is provided, including a substrate having at least a first region and a second region, wherein the first region includes a plurality of first gates, and the second region includes a plurality of second gates, and The adjacent first gate and the adjacent second gate are separated by an insulating layer, wherein the upper surface of the insulating layer has a plurality of recesses. The semiconductor structure further includes a plurality of insulating depositions filling the recesses, wherein the upper surface of the insulating deposit is substantially flush with the upper surface of the insulating layer.
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉較佳實施例,並配合所附圖式,作詳細說明如下: In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:
10‧‧‧基板 10‧‧‧Substrate
11、11’‧‧‧第一暫置結構 11, 11' ‧ ‧ first temporary structure
112‧‧‧第一擬閘極結構 112‧‧‧First pseudo gate structure
112a‧‧‧第一暫置層 112a‧‧‧First temporary layer
112h‧‧‧第一硬質遮罩層 112h‧‧‧First hard mask layer
114、214、114’、214’‧‧‧間隙壁 114, 214, 114’, 214’ ‧ ‧ spacers
16、16’‧‧‧接觸蝕刻停止層 16, 16'‧‧‧Contact etch stop layer
21、21’‧‧‧第二暫置結構 21, 21’ ‧ ‧ second temporary structure
212‧‧‧第二擬閘極結構 212‧‧‧Second pseudo gate structure
212a‧‧‧第二暫置層 212a‧‧‧Second temporary layer
212h‧‧‧第二硬質遮罩層 212h‧‧‧Second hard mask layer
31、31’‧‧‧第一凸點 31, 31'‧‧‧ first bump
32、32’‧‧‧第二凸點 32, 32’‧‧‧second bump
41、41’‧‧‧流動式介電層 41, 41'‧‧‧Mobile dielectric layer
42、42’‧‧‧高密度電漿(HDP)介電層 42. 42'‧‧‧ High Density Plasma (HDP) Dielectric Layer
421‧‧‧HDP介電層的上表面 421‧‧‧The upper surface of the HDP dielectric layer
51‧‧‧絕緣層 51‧‧‧Insulation
61‧‧‧凹陷 61‧‧‧ dent
70‧‧‧覆蓋層 70‧‧‧ Coverage
70’‧‧‧絕緣沈積物 70'‧‧‧Insulating sediments
711‧‧‧絕緣沈積物的上表面 711‧‧‧ Upper surface of insulating deposits
A1‧‧‧第一區域 A1‧‧‧ first area
A2‧‧‧第二區域 A2‧‧‧Second area
A3‧‧‧凸點區域 A3‧‧‧Bump area
H0、H1‧‧‧閘極高度 H0, H1‧‧‧ gate height
h‧‧‧覆蓋層之厚度 h‧‧‧Thickness of the cover layer
d‧‧‧凹陷之深度 D‧‧‧ Depth of depression
第1A~1F圖係為本揭露一實施例之半導體元件製造方法之示意圖。 1A to 1F are schematic views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
第2A圖是第1D圖中第一暫置結構的閘極和絕緣層之放大示意圖。 Fig. 2A is an enlarged schematic view showing the gate and the insulating layer of the first temporary structure in Fig. 1D.
第2B圖是第1F圖中第一暫置結構的閘極和絕緣層之放大示意圖。 Fig. 2B is an enlarged schematic view showing the gate and the insulating layer of the first temporary structure in Fig. 1F.
實施例係提出一種半導體元件之製造方法。根據實施例所製得之半導體元件之閘極係具有足夠的最終閘極高度和完整的表面廓形,進而具有優異的電性表現。本揭露實施例之製造方法解決以傳統製程製作傳統半導體元件製程中常發生的閘極高度損失之問題。 The embodiment proposes a method of manufacturing a semiconductor element. The gate of the semiconductor device fabricated in accordance with the embodiments has sufficient final gate height and a complete surface profile to provide excellent electrical performance. The manufacturing method of the disclosed embodiment solves the problem of the gate height loss that often occurs in the conventional process for fabricating a conventional semiconductor device.
以下係提出實施例,配合圖示以詳細說明相關的製造方法及應用其製得之元件結構。然而本揭露並不僅限於此。本揭露並非顯示出所有可能的實施例。可在不脫離本揭露之精神和範圍內對結構和製程加以變化與修飾,以符合實際應用之需要。因此,未於本揭露提出的其他實施態樣也可能可以應用。再者,圖式上的尺寸比例並非按照實際產品等比例繪製。因此,說明書和圖示內容僅作敘述實施例之用,而非作為限縮本揭露保護範圍之用。 The following embodiments are presented in conjunction with the drawings to explain in detail the related manufacturing methods and the component structures obtained using the same. However, the disclosure is not limited to this. This disclosure does not show all possible embodiments. The structure and process may be modified and modified to meet the needs of the actual application without departing from the spirit and scope of the disclosure. Therefore, other implementations not presented in the present disclosure may also be applicable. Furthermore, the dimensional ratios on the drawings are not drawn in proportion to the actual product. Therefore, the description and illustration are for illustrative purposes only and are not intended to be limiting.
實施例中,係利用沉積一覆蓋層之後搭配平坦化步驟以形成絕緣沈積物(insulating depositions)填滿因先前步驟產生的凹陷,使絕緣沈積物的上表面係實質上與閘極之上表面齊平。因此,根據實施例所製得之半導體元件係具 有足夠閘極高度和完整表面廓形的閘極。實施例之製造方法可應用於許多不同製造方法所製得的半導體元件,例如以高介電常數介電層-金屬閘極(high K metal gates,HKMG)製程製作之半導體元件,但本揭露並不侷限於某種特定態樣。細部製造步驟亦不僅限於實施例之敘述與圖示,可依實際應用態樣和製程需求的不同而加以變化與修飾實施方法。以下是以應用本揭露於一高介電常數介電層後製(High K last)之HKMG製程為實施例之說明,但不揭露並不以此為限。 In an embodiment, the deposition of a cover layer is followed by a planarization step to form insulating depositions to fill the depressions generated by the previous steps, so that the upper surface of the insulating deposit is substantially flush with the upper surface of the gate. level. Therefore, the semiconductor component harness produced according to the embodiment A gate with sufficient gate height and full surface profile. The manufacturing method of the embodiment can be applied to semiconductor components produced by many different manufacturing methods, such as semiconductor devices fabricated by high-k metal gate-metal (GMG) processes, but the disclosure Not limited to a particular aspect. The detailed manufacturing steps are not limited to the description and illustration of the embodiments, and may be modified and modified according to actual application conditions and process requirements. The following is a description of the embodiment of the HKMG process disclosed in the high-k dielectric layer (High K last), but it is not limited thereto.
第1A~1F圖係為本揭露一實施例之半導體元件製造方法之示意圖。實施例中,一基板10具有至少一第一區域A1和一第二區域A2。圖示中基板10可能更包括一凸點區域(bump area)A3。一實施例中,第一區域A1和第二區域A2例如分別是一NMOS區域和一PMOS區域。一實施例中,凸點區域A3可包括至少一第一凸點31例如一邏輯觸點(logic bump),和一第二凸點32例如一靜態隨機存取記憶體觸點(SRAM bump)。實施例提出之製造方法可廣泛地應用在不同態樣的半導體元件中。在其中一種應用態樣中,第一區域A1例如是包括複數個第一鰭狀場效電晶體(first FinFETs),第二區域A2例如是包括複數個第二鰭狀場效電晶 體(second FinFETs)。 1A to 1F are schematic views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. In an embodiment, a substrate 10 has at least a first area A1 and a second area A2. The substrate 10 in the illustration may further include a bump area A3. In one embodiment, the first area A1 and the second area A2 are, for example, an NMOS area and a PMOS area, respectively. In one embodiment, the bump region A3 may include at least one first bump 31 such as a logic bump, and a second bump 32 such as a SRAM bump. The manufacturing method proposed in the embodiment can be widely applied to semiconductor elements of different aspects. In one of the application aspects, the first region A1 includes, for example, a plurality of first fin field effect transistors (first FinFETs), and the second region A2 includes, for example, a plurality of second fin field effect transistors (second FinFETs). ).
如第1A圖所示,基板10的第一區域A1和第二區域A2分別包括至少一第一暫置結構(first dummy structure)11和一第二暫置結構21。第一暫置結構11包括一第一擬閘極結構(first dummy gate structure)112於基板10上,以及間隙壁(spacers)114位於第一擬閘極結構112之兩側。相似的,第二暫置結構21包括一第二擬閘極結構(second dummy gate structure)212於基板10上,以及間隙壁214位於第二擬閘極結構212之兩側。 As shown in FIG. 1A, the first area A1 and the second area A2 of the substrate 10 respectively include at least a first dummy structure 11 and a second temporary structure 21. The first temporary structure 11 includes a first dummy gate structure 112 on the substrate 10, and spacers 114 are located on both sides of the first dummy gate structure 112. Similarly, the second temporary structure 21 includes a second dummy gate structure 212 on the substrate 10, and the spacers 214 are located on opposite sides of the second dummy gate structure 212.
一實施例中,第一擬閘極結構112包括一第一暫置層112a形成於基板10上和一第一硬質遮罩層112h形成於第一暫置層112a上。第一暫置層112a例如是包括一多晶矽層或一非晶矽層形成於一薄氧化層上。一實施例中,第一硬質遮罩層112h例如是(但不限制地)一氮化層、一氧化層、或兩者皆具;例如:第一硬質遮罩層112h係包括形成於非晶矽層上之一氮化矽層以及形成於氮化矽層上之一氧化層。間隙壁114可以是多層間隙壁或如第1A圖中所示之單層間隙壁。相似的,第二擬閘極結構212包括一第二暫置層212a(例如一多晶矽層或一非晶矽層形成於一薄氧化層上) 形成於基板10上,和一第二硬質遮罩層212h(例如形成於非晶矽層上之一SIN層以及形成於SIN層上之一氧化層)形成於第二暫置層212a上。相似的,位於凸點區域A3之第一凸點31(例如一邏輯觸點)和第二凸點32(例如一SRAM觸點)各具有與第一暫置結構11和第二暫置結構21相似之疊層結構。 In one embodiment, the first pseudo gate structure 112 includes a first temporary layer 112a formed on the substrate 10 and a first hard mask layer 112h formed on the first temporary layer 112a. The first temporary layer 112a includes, for example, a polysilicon layer or an amorphous germanium layer formed on a thin oxide layer. In one embodiment, the first hard mask layer 112h is, for example, but not limited to, a nitride layer, an oxide layer, or both; for example, the first hard mask layer 112h includes an amorphous layer. One layer of tantalum nitride on the tantalum layer and one oxide layer formed on the tantalum nitride layer. The spacers 114 may be a plurality of spacers or a single layer spacer as shown in FIG. 1A. Similarly, the second pseudo gate structure 212 includes a second temporary layer 212a (eg, a polysilicon layer or an amorphous layer is formed on a thin oxide layer) Formed on the substrate 10, and a second hard mask layer 212h (for example, one SIN layer formed on the amorphous germanium layer and one oxide layer formed on the SIN layer) is formed on the second temporary layer 212a. Similarly, the first bump 31 (eg, a logic contact) and the second bump 32 (eg, an SRAM contact) located in the bump region A3 have a first temporary structure 11 and a second temporary structure 21, respectively. A similar laminate structure.
根據一應用例,第一暫置結構11和第二暫置結構21以及第一凸點31和第二凸點32中,位於基板10上之一薄氧化層其厚度例如約38Å;形成於薄氧化層上之非晶矽層其厚度例如約1100Å。因此,第一暫置層112a和第二暫置層212a(以及第一、第二凸點31和32中相同位置之暫置層)係具有相同高度。然而,第一暫置結構11、第二暫置結構21以及第一凸點31和第二凸點32中,硬質遮罩層可能因所屬氧化層厚度的不同而產生不同高度。舉例來說,第一、第二暫置結構11和21以及第一、第二凸點31和32中,位於非晶矽層上的SiN層其厚度例如約100Å。在第一區域A1中,第一硬質遮罩層112h的氧化層其厚度例如約400Å。在第二區域A2中,第二硬質遮罩層212h的氧化層其厚度例如約450Å。在凸點區域A3(第三區域)中,第一凸點31和第二凸點32的氧化層其厚度例如約900Å和800Å。 值得注意的是,前述之數值僅為例示說明可應用之其中一種規格,並非用以限制本揭露之權利保護範圍。 According to an application example, among the first temporary structure 11 and the second temporary structure 21 and the first bump 31 and the second bump 32, a thin oxide layer on the substrate 10 has a thickness of, for example, about 38 Å; The amorphous germanium layer on the oxide layer has a thickness of, for example, about 1100 Å. Therefore, the first temporary layer 112a and the second temporary layer 212a (and the temporary layers at the same positions in the first and second bumps 31 and 32) have the same height. However, in the first temporary structure 11, the second temporary structure 21, and the first bump 31 and the second bump 32, the hard mask layer may have different heights depending on the thickness of the oxide layer to which it belongs. For example, of the first and second temporary structures 11 and 21 and the first and second bumps 31 and 32, the SiN layer on the amorphous germanium layer has a thickness of, for example, about 100 Å. In the first region A1, the oxide layer of the first hard mask layer 112h has a thickness of, for example, about 400 Å. In the second region A2, the oxide layer of the second hard mask layer 212h has a thickness of, for example, about 450 Å. In the bump region A3 (third region), the oxide layers of the first bump 31 and the second bump 32 have a thickness of, for example, about 900 Å and 800 Å. It is to be noted that the foregoing numerical values are only one of the specifications that can be applied to the description, and are not intended to limit the scope of the disclosure.
再者,第1A圖中,半導體元件更包括一接觸蝕刻停止層(contact etch stop layer,CESL)16形成於基板10上,並覆蓋基板10、第一暫置結構11和第二暫置結構21,以及位於凸點區域A3之第一凸點31和第二凸點32。在應用實施例之一應用例中,係可採用流動式化學氣相沈積(flowable chemical vapor deposition,FCVD)製程。一流動式介電層41係以CVD製程沈積於元件上,且利用化學機械研磨(chemical mechanical polishing,CMP)對流動式介電層41進行研磨,使其停在凸點(如第一凸點31)上,如第1A圖所示。 Furthermore, in FIG. 1A, the semiconductor device further includes a contact etch stop layer (CESL) 16 formed on the substrate 10 and covering the substrate 10, the first temporary structure 11 and the second temporary structure 21 And the first bump 31 and the second bump 32 located in the bump area A3. In one of the application examples, a flowable chemical vapor deposition (FCVD) process may be employed. A flow dielectric layer 41 is deposited on the device by a CVD process, and the flow dielectric layer 41 is ground by chemical mechanical polishing (CMP) to stop at the bump (eg, the first bump) 31), as shown in Figure 1A.
如第1B圖所示,係對半導體元件進行非選擇性蝕刻,以移除第一、第二暫置結構11和21以及第一、第二凸點31和32之頂部,以產生一平坦表面。第1B圖中,接觸蝕刻停止層16的頂表面、部分的間隙壁114和214、以及第一、第二硬質遮罩層112h和212h、第一、第二凸點31和32中部分的氧化層係被移除。一應用例中,移除後剩餘的氧化層厚度例如約200Å。 As shown in FIG. 1B, the semiconductor element is non-selectively etched to remove the top portions of the first and second temporary structures 11 and 21 and the first and second bumps 31 and 32 to produce a flat surface. . In FIG. 1B, the top surface of the contact etch stop layer 16, a portion of the spacers 114 and 214, and the oxidation of portions of the first and second hard mask layers 112h and 212h, the first and second bumps 31 and 32, The layer system was removed. In one application, the thickness of the remaining oxide layer after removal is, for example, about 200 Å.
如第1C圖所示,部分的流動式介電層41係置換成另一種介電層,例如高密度電漿(high density plasma,HDP)介電層42(即以高密度電漿CVD製程沈積之一介電層)。一實施例中,流動式介電層41可利用SiCoNi回蝕方式部份地移除,之後以HDP CVD製程沈積之一介電層42,再以CMP研磨,完成介電層部份置換。 As shown in FIG. 1C, part of the flow dielectric layer 41 is replaced with another dielectric layer, such as a high density plasma (HDP) dielectric layer 42 (ie, deposited by a high density plasma CVD process). One dielectric layer). In one embodiment, the flow dielectric layer 41 can be partially removed by SiCoNi etch back, and then a dielectric layer 42 is deposited by HDP CVD process, followed by CMP polishing to complete partial replacement of the dielectric layer.
如第1D圖所示,接著研磨元件以移除第一、第二暫置結構11和21以及第一、第二凸點31和32中之硬質遮罩層(如第1C圖中剩餘的氧化層和SiN層)。第1D圖中,第一暫置層112a(例如是包括約1100Å之非晶矽層和約38Å之薄氧化層)和第二暫置層212a(和第一、第二凸點31和32的暫置層)實質上係具有相同高度。根據其中一應用例,暫置層中之多晶矽或非晶矽(做為一擬閘極)在後續製程中會被金屬取代而形成金屬閘極。以應用本揭露於高介電常數介電層後製(High K last)之HKMG製程為例,一高介電常數介電層係沈積於因移除擬閘極所形成之一溝槽中,之後在溝槽中填充金屬於高介電常數介電層上以形成金屬閘極。因此,間隙壁的廓形,包括形狀和高度,都會對閘極造成無法忽視之影響。間隙壁損失(spacer loss)會造成後續製程所形成的閘 極(如金屬閘極)高度有所損失以及表面廓形的不完整。 As shown in FIG. 1D, the element is then polished to remove the first and second temporary structures 11 and 21 and the hard mask layer in the first and second bumps 31 and 32 (eg, the remaining oxidation in FIG. 1C) Layer and SiN layer). In FIG. 1D, a first temporary layer 112a (eg, comprising an amorphous germanium layer of about 1100 Å and a thin oxide layer of about 38 Å) and a second temporary layer 212a (and first and second bumps 31 and 32) The temporary layer) is substantially the same height. According to one application example, the polysilicon or amorphous germanium (as a pseudo gate) in the temporary layer is replaced by a metal in a subsequent process to form a metal gate. For example, in the HKMG process disclosed in the high-k dielectric layer (High K last), a high-k dielectric layer is deposited in a trench formed by removing the dummy gate. The trench is then filled with a metal on the high-k dielectric layer to form a metal gate. Therefore, the profile of the spacer, including the shape and height, can have an inevitable effect on the gate. The spacer loss will cause the gate formed by the subsequent process The pole (such as the metal gate) has a loss of height and an incomplete surface profile.
結構上來說,間隙壁(如114’和214’)、接觸蝕刻停止層16’和圖案化內層介電層(patterned ILD,即包括圖案化介電層42’和流動式介電層41’),如第1D圖所示,可整體被視為一絕緣層(insulation)51。第一暫置結構11’之閘極(第一閘極,即第一暫置層112a)、第二暫置結構21’之閘極(第二閘極,即第二暫置層212a)、以及第一、第二凸點31’和32’之閘極係以絕緣層51分隔開來。 Structurally, the spacers (such as 114' and 214'), the contact etch stop layer 16', and the patterned inner dielectric layer (including the patterned dielectric layer 42' and the flow dielectric layer 41' As shown in Fig. 1D, it can be regarded as an insulation 51 as a whole. The gate of the first temporary structure 11' (the first gate, that is, the first temporary layer 112a), the gate of the second temporary structure 21' (the second gate, that is, the second temporary layer 212a), And the gates of the first and second bumps 31' and 32' are separated by an insulating layer 51.
一實施例中,間隙壁114/114’和214/214’和接觸蝕刻停止層16/16’可利用相同材料(或不同材料)製得。而硬質遮罩層的材料可不同於間隙壁114/114’、214/214’和接觸蝕刻停止層16/16’之材料。一實施例中,間隙壁和接觸蝕刻停止層之材料例如是以原子層沉積(atomic layer deposition,ALD)之碳氮化矽(SiCN)。一實施例中,HDP介電層之材料例如(但不限制地)是氧化物。 In one embodiment, the spacers 114/114' and 214/214' and the contact etch stop layer 16/16' can be made from the same material (or different materials). The material of the hard mask layer may be different from the material of the spacers 114/114', 214/214' and the contact etch stop layer 16/16'. In one embodiment, the spacer and the material contacting the etch stop layer are, for example, atomic layer deposition (ALD) of carbonitride (SiCN). In one embodiment, the material of the HDP dielectric layer is, for example and without limitation, an oxide.
然而,製程至此,通常會有結構上的缺陷產生,如第1D圖所示之形成於絕緣層51之上表面處的凹陷(recesses)61。一實施例中,位於絕緣層51上表面的該些凹陷61係對應地橫跨間隙壁114’,214’和接觸蝕刻停止層 16’之頂部。位於絕緣層51上表面的凹陷61會造成閘極高度損失和閘極表面廓形不完整的問題,而導致元件的失效(failure)。 However, at this point in the process, there are usually structural defects such as recesses 61 formed at the upper surface of the insulating layer 51 as shown in Fig. 1D. In one embodiment, the recesses 61 on the upper surface of the insulating layer 51 correspondingly span the spacers 114', 214' and the contact etch stop layer. The top of the 16'. The recess 61 located on the upper surface of the insulating layer 51 causes a problem of gate height loss and incomplete gate surface profile, resulting in failure of the component.
根據實施例,係形成一覆蓋層(capping layer)70於絕緣層、第一暫置結構11’之閘極(第一閘極,即第一暫置層112a)、第二暫置結構21’之閘極(第二閘極,即第二暫置層212a)、以及第一、第二凸點31’和32’之閘極上,如第1E圖所示。覆蓋層70的材料並填滿該些凹陷61。之後,例如利用CMP移除覆蓋層70,直至到達絕緣層51之上表面為止,因而形成絕緣沈積物(insulating depositions)70’,如第1F圖所示。 According to an embodiment, a capping layer 70 is formed on the insulating layer, the gate of the first temporary structure 11' (the first gate, that is, the first temporary layer 112a), and the second temporary structure 21' The gate (the second gate, that is, the second temporary layer 212a) and the gates of the first and second bumps 31' and 32' are as shown in FIG. 1E. The material of the cover layer 70 is filled and filled with the recesses 61. Thereafter, the cover layer 70 is removed by, for example, CMP until reaching the upper surface of the insulating layer 51, thereby forming insulating depositions 70' as shown in Fig. 1F.
一實施例中,覆蓋層70之厚度h為該些凹陷61之一深度d的約1.5~2.5倍。一實施例中,覆蓋層70之厚度h約為250Å。一實施例中,覆蓋層70包括氧化物、氮化矽或碳氮化矽(SiCN),且可以ALD方式沉積。間隙壁114/214和接觸蝕刻停止層16可以相同材料形成。一實施例中,覆蓋層70係與間隙壁114/214和接觸蝕刻停止層16至少其中一者包括相同材料。或者是,覆蓋層70係與間隙壁114/214和接觸蝕刻停止層16至少其中一者包括不同材 料。 In one embodiment, the thickness h of the cover layer 70 is about 1.5 to 2.5 times the depth d of one of the recesses 61. In one embodiment, the cover layer 70 has a thickness h of about 250 Å. In one embodiment, the cap layer 70 comprises an oxide, tantalum nitride or tantalum carbonitride (SiCN) and can be deposited in an ALD manner. The spacers 114/214 and the contact etch stop layer 16 may be formed of the same material. In one embodiment, the cover layer 70 is comprised of the same material as at least one of the spacers 114/214 and the contact etch stop layer 16. Alternatively, the cover layer 70 is comprised of at least one of the spacers 114/214 and the contact etch stop layer 16 comprising a different material.
請參照第2A和2B圖。第2A圖是第1D圖中第一暫置結構的閘極(第一閘極,即第一暫置層112a)和絕緣層之放大示意圖。第2B圖是第1F圖中第一暫置結構的閘極和絕緣層之放大示意圖。一實施例中,位於絕緣層51上表面的凹陷61係對應地橫跨間隙壁114’和接觸蝕刻停止層16’之頂部,如第2A圖所示。 Please refer to Figures 2A and 2B. Fig. 2A is an enlarged schematic view showing the gate (first gate, i.e., the first temporary layer 112a) and the insulating layer of the first temporary structure in Fig. 1D. Fig. 2B is an enlarged schematic view showing the gate and the insulating layer of the first temporary structure in Fig. 1F. In one embodiment, the recess 61 on the upper surface of the insulating layer 51 correspondingly spans the top of the spacer 114' and the contact etch stop layer 16' as shown in Fig. 2A.
其中,第2A圖和第2B圖係分別繪示未形成絕緣沈積物70’之閘極高度H0以及形成絕緣沈積物70’後之閘極高度H1;由於間隙壁的損失,H0<H1。根據實施例,絕緣沈積物70’填滿該些凹陷61,且絕緣沈積物70’的上表面711係實質上齊平於絕緣層51之上表面,例如是與介電層(HDP介電層)42’的上表面421齊平。在形成絕緣沈積物70’後,後續形成的閘極將具有足夠的閘極高度(如H1)。一實施例中,間隙壁和絕緣沈積物70’係接觸位於第一區域A1之第一暫置結構11’的第一閘極之側壁和位於第二區域A2之第二暫置結構21’的第二閘極之側壁。 2A and 2B show the gate height H0 of the insulating deposit 70' and the gate height H1 after the insulating deposit 70' is formed, respectively; H0 < H1 due to the loss of the spacer. According to an embodiment, the insulating deposit 70' fills the recesses 61, and the upper surface 711 of the insulating deposit 70' is substantially flush with the upper surface of the insulating layer 51, such as a dielectric layer (HDP dielectric layer) The upper surface 421 of 42' is flush. After the formation of the insulating deposit 70', the subsequently formed gate will have a sufficient gate height (e.g., H1). In one embodiment, the spacer and the insulating deposit 70' contact the sidewall of the first gate of the first temporary structure 11' of the first region A1 and the second temporary structure 21' of the second region A2. The sidewall of the second gate.
雖然第2B圖是繪示絕緣沈積物70’位於第一暫置結構的第一閘極(即第一暫置層112a)和絕緣層做說明,但 第二暫置結構的第二閘極(即第一暫置層212a)和具有絕緣沈積物70’之絕緣層也是類似第2B圖的結構,以得到足夠的閘極高度。 Although FIG. 2B is a view showing that the insulating deposit 70' is located at the first gate of the first temporary structure (ie, the first temporary layer 112a) and the insulating layer, The second gate of the second temporary structure (i.e., the first temporary layer 212a) and the insulating layer having the insulating deposit 70' are also similar to the structure of Figure 2B to obtain a sufficient gate height.
根據上述,實施例所揭露之製造方法所製得之半導體元件係可有效地解決閘極高度損失之問題。根據實施例,所製得之半導體元件其閘極係具有足夠的閘極高度和完整的表面廓形,進而具有優異的電性表現。再者,實施例所揭露之可解決閘極高度損失問題的製造方法,係簡化了製程,不但提高了產品良率更控制了製造成本。 According to the above, the semiconductor device produced by the manufacturing method disclosed in the embodiment can effectively solve the problem of gate height loss. According to an embodiment, the resulting semiconductor device has a gate with sufficient gate height and a complete surface profile to provide excellent electrical performance. Furthermore, the manufacturing method disclosed in the embodiment that can solve the problem of gate height loss simplifies the process, and not only improves the product yield but also controls the manufacturing cost.
再者,不同閘極結構之其他實施例也可應用本揭露,可根據實際應用之需求而做適當的變化與修飾。因此如第1A~1F圖和第2A圖、第2B圖是僅繪示作為敘述實施例之用,而非作為限縮本揭露保護範圍之用。因此具通常知識者可知,結構中各組成元件之形狀或相對位置可能根據實際應用的結構和/或製程步驟的不同而作相應調整。 Furthermore, other embodiments of different gate structures can also be applied to the present disclosure, and can be appropriately changed and modified according to the needs of practical applications. Therefore, as shown in FIGS. 1A to 1F and FIGS. 2A and 2B, only the embodiments are described, and the scope of protection is not limited. Thus, it will be apparent to those skilled in the art that the shapes or relative positions of the various components in the structure may be adjusted accordingly depending on the structure and/or process steps employed.
綜上所述,雖然本發明已以實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範 圍所界定者為準。 In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention is to be attached to the patent application. The definition of the enclosure shall prevail.
10‧‧‧基板 10‧‧‧Substrate
11’‧‧‧第一凸點 11’‧‧‧First bump
112a‧‧‧第一暫置層 112a‧‧‧First temporary layer
114’、214’‧‧‧間隙壁 114’, 214’‧‧‧
16’‧‧‧接觸蝕刻停止層 16'‧‧‧Contact etch stop layer
21’‧‧‧第二凸點 21’‧‧‧second bump
212a‧‧‧第二暫置層 212a‧‧‧Second temporary layer
31’‧‧‧第一凸點 31’‧‧‧First bump
32’‧‧‧第二凸點 32’‧‧‧second bump
41’‧‧‧流動式介電層 41'‧‧‧Mobile dielectric layer
42’‧‧‧高密度電漿介電層 42'‧‧‧High Density Plasma Dielectric Layer
61‧‧‧凹陷 61‧‧‧ dent
70’‧‧‧絕緣沈積物 70'‧‧‧Insulating sediments
A1‧‧‧第一區域 A1‧‧‧ first area
A2‧‧‧第二區域 A2‧‧‧Second area
A3‧‧‧凸點區域 A3‧‧‧Bump area
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