TWI534871B - Replacement gate process and device manufactured using the same - Google Patents

Description

Replace the gate process and apply the components it produces

SUMMARY OF THE INVENTION The present invention is directed to a device for replacing a gate process and for the use thereof, and more particularly to a replacement gate process for controlling gate height and for fabricating the same.

In recent years, the size of semiconductor components has been decreasing. For the semiconductor industry, continuing to reduce the size of semiconductor structures, while simultaneously improving speed, performance, density, and cost reduction, has been an important development goal. As the size of semiconductor components shrinks, the electronic characteristics of the components must be maintained or even improved to meet market product requirements. In recent years, high dielectric constant dielectric-metal gate (HKMG) technology has become the mainstream of high performance and low standby power logic components.

The high-k dielectric layer-metal gate process can be further divided into a gate first process and a gate last process. For example, in the post-gate process (also referred to as a replacement gate process), a dummy gate is formed by a material such as polysilicon or amorphous germanium, and then the dummy gate is removed and replaced with a metal gate. High dielectric constant (High K) thin films are an important component in memory applications in the semiconductor industry. High dielectric constant materials can be used to enhance memory in memory. Recall the capacitance value in the body. In the HKMG process, the high-k dielectric layer can be formed before the dummy gate is formed. This is called the high-k dielectric layer (High K first) HKMG process; it can also be fabricated in the virtual gate. And formed after removal, this is called the high-k dielectric layer post-production (High K last) HKMG process. Regardless of the HKMG process, extreme precision control is required for the final gate height and topography, resulting in superior electrical performance of the fabricated semiconductor components.

1A~1D is a traditional high dielectric constant dielectric layer-metal Schematic diagram of the manufacturing method of the gate (HKMG). As shown in FIG. 1A, a dummy gate 12 is formed on one of the substrates 10, and includes a polysilicon layer 121 and a hard mask layer 122. Both sides of the dummy gate 12 are provided. Spacers 14 are formed (which may be single or multiple spacers, first spacer 141 and second spacer 142 as shown). A contact etch stop layer 16 is formed on the substrate 10 to cover the spacers 14, and an interlayer dielectric (ILD) 17 is formed on the contact etch stop layer 16. An epitaxy layer 101 can be selectively grown on the substrate 10. As shown in FIG. 1B, the interlayer dielectric layer 17 is first planarized to contact the etch stop layer 16 by, for example, a chemical mechanical polishing (CMP) method to expose the upper surface of the contact etch stop layer 16. Next, as shown in FIG. 1C, a portion of the interlayer dielectric layer 17, the spacers 14, and the dummy gates 12 are removed, for example, by dry etching, wherein the hard mask layer 122 is completely removed, and the polysilicon layer 121 is removed. Then part of it was removed. Thereafter, as shown in Fig. 1D, the remaining polysilicon layer 121' is removed by wet etching to form trenches 18. Subsequent refilling of the metal in the trench 18 (not shown in Graphic).

In the current process, the spacers 14 (such as the first spacer 141 and the second spacer 142) and the material contacting the etch stop layer 16 are different, for example, oxide, hollow cathode discharge (HCD). The grown nitride, and nitride, which have low corrosion resistance to the dummy gate 12 by dry etching or wet etching. In order to maintain the final gate height H _G at a certain height value, a high false gate 12 height is required in the process. Taking the current 20nm HKMG process and applying the above 1A~1D drawing method as an example, if the final gate height H _G required to be obtained is 1000 Å, the polysilicon layer 121 and the hard mask layer 122 in FIG. 1A are required to be formed. The height is 1000Å. However, too high a false gate height can affect the electrical performance of the fabricated component, such as the doping ability of a lightly doped drain.

The present invention relates to an element obtained by replacing a gate process and a replacement gate process, which not only can precisely control the final gate height and maintain the surface topography of each layer structure, but also has excellent electrical properties. Sexual performance.

According to the present invention, a replacement gate process is provided, comprising: providing a substrate and forming a dummy gate structure on the substrate, wherein the dummy gate structure comprises a temporary layer on the substrate, and a hard mask layer is temporarily On the layer, the spacer is located on both sides of the temporary layer and the hard mask layer, and a contact etch stop The stop layer covers the substrate, the spacer and the hard mask layer, and the spacer and the contact etch stop layer are the same material; removing the top of one of the contact etch stop layers to expose the hard mask layer; removing the hard mask layer And removing the temporary layer to form a trench.

According to the present invention, a semiconductor structure is provided, comprising: a substrate; the spacers are oppositely formed on the substrate and separated by a trench; a patterned contact etch stop layer (patterned CESL) is formed on the outside of the spacer and covers the substrate; The wall and contact etch stop layers are of the same material.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

10, 20, 40‧‧‧ substrates

101, 201‧‧‧ epitaxial layer

12, 22‧‧‧false gate

121, 121'‧‧‧ polycrystalline layer

221‧‧‧ temporary layer

122, 222‧‧‧ hard mask layer

222a‧‧‧The surface of the hard mask layer

14, 24, 44‧ ‧ spacers

141, 241‧‧‧ first gap

142, 242‧‧‧ second gap

16, 16', 26, 26', 46‧‧‧ contact etch stop layer

26a‧‧‧Contact etch stop layer upper surface

17, 17', 27, 27', 27", 47‧ ‧ interlayer dielectric layers

18, 28, 48‧‧‧ trench

31‧‧‧ gate dielectric layer

41‧‧‧Shallow trench isolation

49‧‧‧Fin channel

491‧‧‧ dielectric layer

H _G ‧‧‧gate height

S‧‧‧ source

D‧‧‧汲

The 1A~1D diagram is a schematic diagram of a conventional high dielectric constant dielectric layer-metal gate (HKMG) manufacturing method.

2A-2E are schematic views showing a manufacturing method of a high-k dielectric gate process (HKMG) according to the first embodiment of the present disclosure.

FIG. 3 is a schematic view showing a semiconductor device in which a trench is formed after a dummy gate is removed in a high-k dielectric-metal gate (HKMG) process according to a second embodiment of the present disclosure.

FIG. 4 is a schematic view showing a semiconductor device in which a trench is formed after the dummy gate is removed in the fin field effect transistor process of the third embodiment of the present disclosure.

The embodiment proposes a replacement gate process and the components obtained by the same, which not only can precisely control the final gate height and surface topography, but also make the fabricated semiconductor component have excellent electrical properties. which performed. According to the manufacturing method of the present disclosure, the high selectivity of the material etching is matched with the special process, so that the false gate height of the desired fabrication is reduced, and the conventional process can be achieved (higher false gate height is required). And get the same final gate height.

Related embodiments of the disclosed application are described below with reference to the accompanying drawings. The present disclosure can be applied to a high-k dielectric layer-metal gate process to fabricate components such as a general transistor or a fin field effect transistor. The same or similar reference numerals are used to designate the same or similar parts. It should be noted that the drawings have been simplified to clearly illustrate the contents of the embodiments, and the dimensional ratios in the drawings are not drawn to the scale of the actual products, and therefore are not intended to limit the scope of protection; It is not limited to the description and illustration of the embodiments, and can be changed and modified depending on the actual application process. Furthermore, other implementations not presented in this disclosure may also be applicable.

2A-2E are schematic views showing a manufacturing method of a high-k dielectric gate process (HKMG) according to the first embodiment of the present disclosure. In the first embodiment, the application is disclosed in a high-k dielectric layer The HKK process of High K last is taken as an example.

As shown in FIG. 2A, a substrate 20 is provided and a dummy gate is formed A dummy gate structure is disposed on the substrate 20, wherein the dummy gate structure includes a dummy layer 221 on the substrate 20, and a hard mask layer 222 is disposed on the temporary layer 221, Spacers 24 are located on both sides of the temporary layer 221 and the hard mask layer 222, and a contact etch stop layer (CESL) 26 covers the substrate 20, the spacers 24, and the hard mask layer 222. . The temporary layer 221 and the hard mask layer 222 constitute one of the dummy gates 22 of the components. An epitaxial layer 201 is selectively grown on the substrate 20; as shown in FIG. 2A, a contact etch stop layer 26 is also formed on the epitaxial layer 201.

In this embodiment, the dummy gate structure further includes an interlayer dielectric layer An interlayer dielectric (ILD) 27 is overlaid on the contact etch stop layer 26. In the embodiment, the temporary layer 221 is, for example, a polysilicon layer or an amorphous germanium layer; and the spacers 24 may be a single layer or a plurality of spacers, as shown in the first spacer 241 and the second spacer 242. .

Furthermore, in the first embodiment, the spacers 24 and the contact etch stop layer The 26 is the same material, and the material of the hard mask layer 222 is different from the material of the spacer 24 and the contact etch stop layer 26. In one embodiment, the spacers 24 (including the first spacers 241 and the second spacers 242) and the material contacting the etch stop layer 26 are, for example, atomic layer deposition (ALD) carbonitride (SiCN). ). In one embodiment, the material of the hard mask layer 222 is, for example but not limited to, It is a nitride or an oxide; in one embodiment, the material of the hard mask layer 222 is tantalum nitride.

As shown in FIG. 2B, the interlayer dielectric layer 27 is planarized to expose the contacts One of the upper surfaces 26a of the etch stop layer 26 is etched. In one embodiment, the material of the interlayer dielectric layer 27 is, for example, an oxide, and the interlayer dielectric layer 27 is a step of planarization by chemical mechanical planarization or polishing (CMP).

Next, as shown in FIG. 2C, for example, by dry etching, The top portion of the contact etch stop layer 26 is removed to expose the surface 222a of the hard mask layer 222.

Then, as shown in FIG. 2D, for example, by wet etching, The hard mask layer 222 is removed. In one embodiment, if the material of the spacer 24 and the contact etch stop layer 26 is atomic layer deposited carbonitride (SiCN), and the material of the hard mask layer 222 is nitride, the hard mask layer 222 can be Wet etching is performed using a phosphate-based solution. Due to the high selectivity of the etchant to the hard mask layer 222 and the spacers 24/contact etch stop layer 26, the barrier layer 24 and the contact etch stop layer 26 are not damaged during the wet etch of the hard mask layer 222.

Thereafter, as shown in FIG. 2E, the temporary layer 221 is removed to form a Trench 28. In one embodiment, the temporary layer 221 is removed, for example, by dry etching or wet etching.

The application is disclosed in a high dielectric constant dielectric layer (High K last) In the HKMG process, a high-k dielectric layer can be formed in the trench in a subsequent step. In 28, a metal gate is formed in the trench 28. In an application example, an interfacial layer (IL) may be selectively formed on the substrate 20 in the trench 28 to insulate the contact between the high-k dielectric layer and the substrate 20, and the high-k dielectric is high. A layer may be formed on the sidewalls of the sidewalls and the bottom of the trenches 28; then, a metal layer is formed to fill the trenches 28, and the metal layer is planarized, for example, by CMP to form metal gates in the trenches 28 At the place, complete the replacement of the false gate.

In one embodiment, the material of the interface layer is, for example, an oxide (oxide). The material of the high-k dielectric layer is, for example, afnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide. ), tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, cerium oxide Ttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or other suitable materials. Metal layer/metal gate materials are suitable, for example. A work function metal that adjusts the work function of an N-type transistor or a P-type transistor, such as titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), tantalum carbide (TaC) ), tungsten carbide (WC), or aluminum titanium nitride (TiAlN), titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (tungsten aluminide) , WAl), tantalum aluminide (TaAl), or hafnium aluminide (hafnium aluminide, HfAl), and low resistivity metals such as aluminum, copper, or other suitable metallic materials.

The disclosure can also be applied to a high dielectric constant dielectric layer (High The KMG process of K first) has a method flow similar to that of FIGS. 2A-2E except that a gate dielectric layer is formed between the substrate 20 and the temporary layer 221 in the dummy gate structure. FIG. 3 is a schematic view showing a semiconductor device in which a trench is formed after a dummy gate is removed in a high-k dielectric-metal gate (HKMG) process according to a second embodiment of the present disclosure. Please also refer to Figures 2A~2E and Figure 3. In the second embodiment, the gate dielectric layer 31 is formed on the substrate 20 and the dummy gate is formed on the gate dielectric layer 31 (ie, the high-k dielectric layer is formed first), and then the second layer is as follows. The method described in FIG. 2E removes the dummy gate to form a trench 28 having a gate dielectric layer 31 therein. According to the practical application process, the gate dielectric layer 31 may be a single layer or a multilayer structure, such as a single high-k dielectric layer, or an interface layer (such as an oxide layer, or The foregoing material) and the high-k dielectric layer are formed on a multi-layer structure on the interface layer, and the disclosure is not limited thereto. Subsequent steps further form a metal layer to fill the trenches 28, and planarize the metal layer to form a metal gate at the trench 28 to complete the replacement of the dummy gate.

The disclosure can also be applied to a fin field effect transistor (FinFET) system. Cheng. The method flow is similar to the 2A~2E diagram. Please also refer to Figures 2A~2E and Figure 4. FIG. 4 is a schematic view showing a semiconductor device in which a trench is formed after the dummy gate is removed in the fin field effect transistor process of the third embodiment of the present disclosure. In the third embodiment, a fin-shaped channel 49 (for example, a fin fin) is formed on the substrate, and the substrate has, for example, a shallow trench isolation (STI) 41. The extending direction of the fin passages 49 (e.g., the parallel X direction) is perpendicular to the extending direction of the grooves 48 (e.g., parallel to the Y direction). And a dielectric layer 491 overlies the fin channel 49 and the exposed substrate surface. A dummy gate structure (i.e., a location where the trench 48 and the metal gate are subsequently formed) is formed on the fin via 49 and the substrate and exposes a portion of the fin via 49. Furthermore, a source S and a drain D are formed on opposite sides of the exposed portion of the fin channel 49, respectively, and are located on the outer side of the spacer 44 and adjacent to the spacer 44. As in the method of FIGS. 2A-2E, a dummy gate structure (including, for example, a temporary layer, a hard mask layer, a spacer 44, a contact etch stop layer 46, and an interlayer dielectric) is formed on a substrate having a fin channel 49. Layer 47), through the high selection, removes the dummy gates by dry/wet etching to form trenches 48. Subsequent steps further form a metal layer to fill the trenches 48, and planarize the metal layer to form a metal gate at the trench 48 to complete the replacement of the dummy gate. The resulting metal gates span the finned passages 49 to form a three-dimensional (3D) fin structure that surrounds the gates that control the flow of current.

According to the manufacturing method disclosed in the above embodiments, the pseudo gate height to be fabricated can be reduced, and the same final gate height obtained by the conventional process (which requires a higher false gate height) can be achieved. The false gate height reduces the effect of the ion implantation process on the electrical performance of the component, such as reducing the shadow effect of lightly doped drain doping. Please compare 1A and 2A, and compare 1D and 2E, assuming that the final gate height H _G is 1000 Å, and a polysilicon layer 121 of about 1000 Å height is required to be formed by conventional methods. That is, the temporary layer) and the hard mask layer 122, but the manufacturing method of the application embodiment only needs to form the temporary layer 221 and the hard mask layer 222 which respectively form a height of about 500 Å. In one embodiment, the thickness (/height) of the temporary layer 221 is, for example, in the range of 400 Å to 1200 Å (provided by the inventor), but the disclosure is not limited to the thickness (/height) range, and the temporary layer 221 The thickness (/height) is suitably selected from the final gate height required for practical use. Furthermore, the manufacturing method disclosed in the embodiment does not affect the spacer 24 and the contact etch stop layer 26 when the hard mask layer 222 is etched by using the high selectivity ratio of the dry/wet etching. The surface topography of each layer gives the resulting semiconductor component excellent electrical performance.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

20‧‧‧Substrate

201‧‧‧Elevation layer

22‧‧‧false gate

221‧‧‧ temporary layer

222‧‧‧hard mask layer

222a‧‧‧The surface of the hard mask layer

24‧‧‧ spacer

241‧‧‧First gap

242‧‧‧Second gap

26'‧‧‧Contact etch stop layer

27"‧‧‧Interlayer dielectric layer

Claims (19)

A replacement gate process includes: providing a substrate and forming a dummy gate structure on the substrate, wherein the dummy gate structure includes a dummy layer Located on the substrate, a hard mask layer is located on the temporary layer, spacers are located on both sides of the temporary layer and the hard mask layer, and a contact etch stop layer (contact An etch stop layer (CESL) covers the substrate, the spacers and the hard mask layer, and an interlayer dielectric layer overlying the contact etch stop layer, and the spacers and the contact etch stop layer are the same Materialing: planarizing the interlayer dielectric layer to expose an upper surface of the contact etch stop layer and forming a patterned interlayer dielectric layer, wherein the upper surface of the contact etch stop layer covering the hard mask layer And aligning the contact etch stop layer to remove a top portion of the contact etch stop layer, and the etching step is stopped at the hard mask One of the layers Surface, to expose the hard mask layer; removing the hard mask layer; and removing the temporary layer to form a trench counter (trench). The process of claim 1, wherein the material of the hard mask layer is different from the material of the spacers and the contact etch stop layer. The process of claim 1, wherein the temporary layer is a polysilicon layer or an amorphous layer. The process of claim 1, wherein the spacers and the material of the contact etch stop layer are tantalum carbonitrides (atomic layer deposition (ALD)). The process of claim 1, wherein the material of the hard mask layer is a nitride or an oxide. The process of claim 5, wherein the material of the hard mask layer is tantalum nitride. The process of claim 1, wherein the top of the contact etch stop layer is removed by dry etching to expose the hard mask layer. The process of claim 1, wherein the hard mask layer is removed by wet etching. The process of claim 1, wherein the dummy gate structure further comprises a gate dielectric layer between the substrate and the temporary layer. The process of claim 9, wherein the gate dielectric layer is a single high-k dielectric layer, or includes an oxide layer and the high-k dielectric. A layer is formed on the oxide layer in a multilayer structure. The process of claim 1, further comprising forming a high-k dielectric layer in the trench. The process of claim 1, further comprising forming a metal gate to the trench. For example, the process described in claim 1 of the patent scope, wherein a fin-shaped channel Formed on the substrate, the dummy gate structure is formed on the fin channel and the substrate and exposes a portion of the fin channel, and a source and a drain are respectively formed on the fin channel. The opposite sides of the exposed portion are adjacent to the dummy gate structure. The process of claim 1, wherein one of the temporary layers has a thickness ranging from 400 Å to 1200 Å. A semiconductor structure includes: a substrate; spacers are oppositely formed on the substrate and separated by a trench; and a patterned contact etch stop layer (patterned CESL) is formed on the outside of the spacer And covering the substrate; wherein the spacers and the contact etch stop layer are the same material; a fin channel is formed on the substrate, the fin channel extending in a direction perpendicular to the extending direction of the trench; A metal layer fills the trench and covers a portion of the finned channel. The semiconductor structure of claim 15, wherein the spacers and the material of the contact etch stop layer are tantalum carbonitrides (atomic layer deposition (ALD)). The semiconductor structure of claim 15, wherein the metal layer formed in the trench is a metal gate. The semiconductor structure of claim 17, further comprising a high-k dielectric layer formed in the trench and located at the substrate and the metal gate between. The semiconductor structure of claim 15 further comprising a source and a drain, the source and the drain being respectively formed on opposite sides of the fin channel and located outside the spacer And adjacent to the spacers.