TWI623927B - Display panel and method for driving pixel thereof - Google Patents

Abstract

Display panel and driving method of pixels thereof. The display panel includes a pixel array, and the pixel array has a plurality of pixels. Each pixel includes a light emitting diode, a certain current source and a time control unit. The light emitting diode receives a first system voltage. A constant current source provides a certain current. The time control unit is coupled in series with the light emitting diode and the constant current source, and has a first capacitor to store a voltage difference between a reference voltage and a data voltage. The time control unit determines a supply time of providing a constant current to the light emitting diode according to the voltage difference.

Description

Display panel and pixel driving method thereof

The present invention relates to a driving technology, and in particular, to a display panel and a driving method of pixels thereof.

Due to the advantages of self-luminescence, wide viewing angle, high contrast, and fast response speed, light-emitting diode LEDs have become one of the main display technologies for large-scale displays. Among them, if a light-emitting diode is used in combination with an active-matrix driving method, it can be applied to small and medium-sized display products. The driving method will control the light-emitting diode's light-emitting brightness through the strength of the driving current, and thus produce the Required grayscale. However, with the development of the process, the light-emitting diode is gradually miniaturized to a micron level to become a micro-LED, but the result of the miniaturization not only causes the brightness of the micro-light-emitting diode to change with the driving current. The intensity changes, and its hue also changes with the intensity of the driving current, which causes the problem of color shift of the display. Therefore, a new pixel driving technology is needed to drive micro-light emitting diodes.

The invention provides a display panel and a pixel driving method thereof, which can avoid the problem of color shift of the pixels of the display panel.

The display panel of the present invention includes a pixel array and has a plurality of pixels. Each pixel includes a light emitting diode, a certain current source and a time control unit. The light emitting diode receives a first system voltage. A constant current source provides a certain current. The time control unit is coupled in series with the light emitting diode and the constant current source, and has a first capacitor to store a voltage difference between a reference voltage and a data voltage. The time control unit determines a supply time of providing a constant current to the light emitting diode according to the voltage difference.

The pixel driving method of the present invention has a light emitting diode. The driving method includes the following steps. During a data writing period, a voltage difference between a data voltage and a reference voltage is determined. And, during a light emitting period, a providing time for providing a certain current to the light emitting diode is determined according to the voltage difference.

Based on the foregoing, the display panel and the pixel driving method of the embodiment of the present invention, since the light-emitting diode determines the overall light-emitting brightness of the light-emitting diode through the supply time of the constant current, and the supply time of the constant current is based on the reference The voltage difference between the voltage and the data voltage can avoid the color shift caused by the current change after the light-emitting diode is miniaturized.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

In the following embodiments, for the sake of concise description, the same or similar elements or items are labeled with the same or similar as much as possible, but the same or similar can only be regarded as similar situations, instead of being used to indicate the same. The content of the embodiments is described, and the embodiments of the present invention are not limited thereto.

FIG. 1 is a system schematic diagram of a display panel according to an embodiment of the present invention. Please refer to FIG. 1. In this embodiment, the display panel 100 includes a plurality of control lines 110, a plurality of data lines 120, and a pixel array PXA. The pixel array PXA has a plurality of pixels PX arranged in an array. The control line 110 is used to couple a control circuit (such as a gate driver or similar circuit) to receive a control signal (such as a gate driving signal). A data line 120 is coupled to a voltage supply circuit (such as a source driver, a power supply, or a similar circuit) to receive a voltage (such as a data voltage VDATA, a reference voltage VREF, a system voltage OVDD, and OVSS) required for the pixel PX operation.

Each pixel PX is coupled to a corresponding control line 110 and a corresponding data line 120 to receive a corresponding voltage according to a corresponding control signal. Each pixel PX includes a light emitting diode OLD1, a time control unit TCX, and a constant current source SRI. In this embodiment, the light-emitting diode OLD1, the time control unit TCX, and the constant current source SRI are serially coupled in series between the system voltage OVDD and the system voltage OVSS, that is, the anode of the light-emitting diode OLD1 receives the system voltage OVDD. The constant current source SRI receives the system voltage OVSS, but the embodiment of the present invention is not limited thereto, that is, the positions of the light emitting diode OLD1, the time control unit TCX, and the constant current source Sri can be determined according to the circuit design. In the period during which the light emitting diode OLD1 is driven, the system voltage OVDD is greater than the system voltage OVSS, and the constant current source SRI provides a constant current iFX.

The time control unit CTX has a capacitor C1 (corresponding to the first capacitor) to store the voltage difference VDF between the reference voltage VREF and the data voltage VDATA, so as to determine the time for providing a constant current iFX to the light-emitting diode OLD1 according to the voltage difference VDF. The voltage VDATA corresponds to the brightness (that is, the grayscale value) of the pixel PX. For example, when the brightness of the data voltage VDATA corresponding to the pixel PX is lower, through the change of the voltage difference VDF, the provision time of the constant current iFX will be shorter; when the data voltage VDATA corresponds to the higher brightness of the pixel PX, the transmission The change of the voltage difference VDF, the longer the constant current iFX will be provided.

According to the above, since the light emitting diode OLD1 determines the overall light emitting brightness of the light emitting diode OLD1 through the supply time of the constant current iFX, the supply time of the constant current iFX is based on the voltage difference between the reference voltage VREF and the data voltage VDATA VDF, thus avoiding the color shift caused by the current change after the light-emitting diode OLD1 is miniaturized.

FIG. 2A is a schematic circuit diagram of pixels of the display panel of FIG. 1 according to the first embodiment of the present invention. Please refer to FIG. 1 and FIG. 2A. In this embodiment, the pixel PXa includes a transistor T11 (corresponding to the first transistor), a light emitting diode OLD1, a time control unit TCXa, and a constant current source SRia. The time control unit TCXa includes a transistor T12 (corresponding to a second transistor) and a capacitor C1. The constant current source SRia includes a transistor T13 (corresponding to a third transistor). Among them, the transistors T11 to T13 are examples of n-type transistors.

The drain (corresponding to the first terminal) of the transistor T11 receives the data voltage VDATA, the gate (corresponding to the control terminal) of the transistor T11 receives the write control signal SWTn, and the source (corresponding to the second terminal) of the transistor T11 is coupled to the capacitor One end of C1. One end of the capacitor C1 is coupled to the source of the transistor T11, and the other end of the capacitor C1 receives the ramp signal Vran. The drain (corresponding to the first terminal) of the transistor T12 is coupled to the cathode of the light emitting diode OLD1, the gate (corresponding to the control terminal) of the transistor T12 is coupled to one end of the capacitor C1, and the source of the transistor T12 (corresponding to the second Terminal) is coupled to a constant current source SRia.

The anode of the light-emitting diode OLD1 receives a system voltage OVDD (corresponding to the first system voltage). The drain (corresponding to the first terminal) of the transistor T13 is coupled to the source of the transistor T12, the gate (corresponding to the control terminal) of the transistor T13 receives the bias voltage VBa, and the source (corresponding to the second terminal) of the transistor T13 receives A system voltage OVSS (corresponding to the second system voltage) different from the system voltage OVDD.

FIG. 2B is a driving schematic diagram of the pixel of FIG. 2A according to the first embodiment of the present invention. Please refer to FIG. 2A and FIG. 2B. During the data writing period PDW, the writing control signal SWTn forms a positive writing pulse PWT1 to turn on the crystal T11; the bias voltage VBa is set to a disabled level (such as system voltage OVSS or ground). Voltage) to cut off the transistor T13; and the ramp signal Vran is set to the reference voltage VREF, and the capacitor C1 stores the voltage difference VDF. At this time, since the transistor T13 is not turned on, the driving current ida flowing through the light-emitting diode OLD1 is 0.

During the reset period PRT, the bias voltage VBa and the write control signal SWTn are set to the disabled level, that is, the transistors T11 and T13 are not turned on; and the ramp signal Vran is a voltage between the reference voltage VREF and the system voltage OVSS. The voltage VRTn is set, and the gate voltage VGa of the transistor T12 is VRTn + VDF.

During the light-emitting period PLT, the bias VBa is set to the bias level, that is, any voltage greater than the threshold voltage of the transistor T13 and located in the saturation region; the write control signal SWTn is set to the disabled level to cut off the transistor T11 ; And the ramp signal Vran forms at least one sawtooth wave between the reset voltage VRTn and the peak voltage VTn (here, one is taken as an example), wherein the peak voltage VTn is located between the reference voltage VREF and the system voltage OVDD, and the gate The highest point of the pole voltage VGa is VTn + VDF.

According to the above, the ramp signal Vran is clamped by the capacitor C1, so it is shifted by a voltage difference VDF. In addition, when the voltage level of the shifted ramp signal Vran is less than the threshold voltage Vth1 of the transistor T12, the transistor T12 will not conduct, so that the driving current ida flowing through the light emitting diode OLD1 during the PLT period is 0; Conversely, when the voltage level of the shifted ramp signal Vran is greater than or equal to the threshold voltage Vth1 of the transistor T12, the transistor T12 will be turned on, so that the driving current ida flowing through the light emitting diode OLD1 during the PLT period is a constant current. iFX. With this, the degree of displacement of the ramp signal Vran determines the supply time TPR of the constant current iFX. Among them, the bias level of the bias VBa determines the magnitude of the constant current iFX.

In this embodiment, when the voltage level of the ramp signal Vran shifted during the light-emitting period PLT is less than the threshold voltage Vth1 of the transistor T12, that is, VTn + VDF is less than the threshold voltage Vth1, it means that the transistor T12 emits light throughout The PLT will not be turned on during the period, so the brightness (that is, the grayscale value) of the pixel PX will be 0.

3A is a schematic circuit diagram of a pixel of the display panel of FIG. 1 according to a second embodiment of the present invention. Please refer to FIG. 1 and FIG. 3A. In this embodiment, the pixel PXb includes a transistor T21 (corresponding to the first transistor), a light emitting diode OLD1, a time control unit TCXb, and a constant current source SRib. The time control unit TCXb includes a transistor T22 (corresponding to a second transistor) and a capacitor C1. The constant current source SRib includes a transistor T23 (corresponding to a third transistor). Among them, the transistors T21 to T23 are based on a p-type transistor as an example.

The source (corresponding to the first terminal) of the transistor T21 receives the data voltage VDATA, the gate (corresponding to the control terminal) of the transistor T21 receives the write control signal SWTp, and the drain (corresponding to the second terminal) of the transistor T21 is coupled to the capacitor One end of C1. One end of the capacitor C1 is coupled to the drain of the transistor T21, and the other end of the capacitor C1 receives a ramp signal Vrap. The drain (corresponding to the first terminal) of the transistor T22 is coupled to the anode of the light-emitting diode OLD1, the gate (corresponding to the control terminal) of the transistor T22 is coupled to one end of the capacitor C1, and the source of the transistor T22 (corresponding to the second Terminal) is coupled to a constant current source SRib.

The cathode of the light-emitting diode OLD1 receives a system voltage OVSS (corresponding to the first system voltage). The drain of transistor T23 (corresponding to the first terminal) is coupled to the source of transistor T22. The gate of transistor T23 (corresponding to the control terminal) receives the bias voltage VBb, and the source of transistor T23 (corresponding to the second terminal) receives System voltage OVDD (corresponding to the second system voltage).

FIG. 3B is a driving schematic diagram of the pixel of FIG. 3A according to the second embodiment of the present invention. Please refer to FIG. 3A and FIG. 3B. During the data writing period PDW, the writing control signal SWTp forms a negative writing pulse PWT2 to turn on the crystal T21. The bias voltage VBb is set to a disabled level (such as the system voltage OVDD or the power supply). Voltage) to cut off the transistor T23; and the ramp signal Vrap is set to the reference voltage VREF, and the capacitor C1 stores the voltage difference VDF. At this time, since the transistor T23 is not turned on, the driving current idb flowing through the light-emitting diode OLD1 is 0.

During the reset period PRT, the bias voltage VBb and the write control signal SWTp are set to the disabled level, that is, the transistors T21 and T23 are not turned on; and the ramp signal Vrap is set to be between the reference voltage VREF and the system voltage OVDD. The reset voltage VRTp, and the gate voltage VGb of the transistor T22 is VRTn + VDF.

During the light-emitting period PLT, the bias voltage VBb is set to the bias level, that is, any voltage lower than the threshold voltage of the transistor T23 and located in the saturation region; the write control signal SWTp is set to the disabled level to cut off the transistor T21; In addition, the ramp signal Vrap forms at least one sawtooth wave between the reset voltage VRTp and the peak voltage VTp (here, one is taken as an example), where the peak voltage VTp is between the reference voltage VREF and the system voltage OVSS, and the gate The lowest point of the voltage VGb is VTp + VDF.

According to the above, the ramp signal Vrap is clamped by the capacitor C1, so it is shifted by a voltage difference VDF. In addition, when the voltage level of the displaced ramp signal Vrap is greater than the threshold voltage Vth2 of the transistor T22, the transistor T22 will not be turned on, so that the driving current idb of the PLT flowing through the light emitting diode OLD1 during the light emitting period is 0; Conversely, when the voltage level of the shifted ramp signal Vrap is less than or equal to the threshold voltage Vth2 of the transistor T22, the transistor T22 will be turned on, so that the driving current idB of the PLT flowing through the light emitting diode OLD1 during the light emission period is a constant current. iFX. With this, the degree of displacement of the ramp signal Vrap also determines the supply time TPR of the constant current iFX. Among them, the bias level of the bias VBb determines the magnitude of the constant current iFX.

In this embodiment, when the voltage level of the ramp signal Vrap shifted during the light-emitting period PLT is greater than the threshold voltage Vth2 of the transistor T22, that is, VTp + VDF is greater than the threshold voltage Vth2, which indicates that the transistor T22 is in the light-emitting period. The PLT will not be turned on, so the brightness (that is, the grayscale value) of the pixel PX will be 0.

4A is a schematic circuit diagram of a pixel of the display panel of FIG. 1 according to a third embodiment of the present invention. Please refer to FIG. 1 and FIG. 4A. In this embodiment, the pixel PXc includes a transistor T31 (corresponding to a first transistor), a transistor T34 (corresponding to a fourth transistor), a light emitting diode OLD1, and a time control unit TCXc. And constant current source SRic. The time control unit TCXc includes a transistor T32 (corresponding to a second transistor) and a capacitor C1. The constant current source SRic includes a transistor T33 (corresponding to a third transistor). Among them, the transistors T31 to T34 are taken as examples of n-type transistors.

The drain (corresponding to the first terminal) of the transistor T31 receives the data voltage VDATA, the gate (corresponding to the control terminal) of the transistor T31 receives the write control signal SWTn, and the source (corresponding to the second terminal) of the transistor T31 is coupled to the capacitor One end of C1. One end of the capacitor C1 is coupled to the source of the transistor T31, and the other end of the capacitor C1 receives the ramp signal Vran. The gate (corresponding to the control terminal) of the transistor T32 is coupled to one end of the capacitor C1, and the source (corresponding to the second terminal) of the transistor T32 is coupled to a constant current source SRic.

The drain (corresponding to the first terminal) of the transistor T33 is coupled to the source of the transistor T32. The gate (corresponding to the control terminal) of the transistor T33 receives the bias voltage VBc, and the source (corresponding to the second terminal) of the transistor T33 receives System voltage OVSS (corresponding to the second system voltage). Among them, the bias voltage VBc is any voltage greater than the threshold voltage of the transistor T33 and located in the saturation region.

The drain (corresponding to the first terminal) of the transistor T34 is coupled to the cathode of the light emitting diode OLD1, the gate (corresponding to the control terminal) of the transistor T34 receives the light-emitting control signal SLTn, and the source (corresponding to the second terminal) of the transistor T34 ) Is coupled to the drain (corresponding to the first end) of the transistor T32, that is, the transistor T32 of the time control unit TCXc is coupled to the constant current source SRic. The anode of the light-emitting diode OLD1 receives a system voltage OVDD (corresponding to the first system voltage).

FIG. 4B is a driving schematic diagram of the pixel of FIG. 4A according to the third embodiment of the present invention. Please refer to FIG. 4A and FIG. 4B. During the data writing period PDW, the writing control signal SWTn forms a positive writing pulse PWT1 to turn on the crystal T31. The light emission control signal SLTn is set to a disable level to turn off the transistor T34. ; And the ramp signal Vran is set to the reference voltage VREF, and the capacitor C1 stores a voltage difference VDF. At this time, since the transistor T34 is not conducting, the driving current idc flowing through the light-emitting diode OLD1 is 0.

During the reset period PRT, the write control signal SWTn and the light emission control signal SLTn are set to the disabled level, that is, the transistors T31 and T34 are not turned on; and the ramp signal Vran is between the reference voltage VREF and the system voltage OVSS. The reset voltage VRTn, and the gate voltage VGc of the transistor T32 is VRTn + VDF.

During the light-emitting period PLT, the write control signal SWTn is set to the disable level to turn off the transistor T31; the light-emitting control signal SLTn is set to the enable level to turn on the transistor T34; and the ramp signal Vran is formed at the reset voltage At least one sawtooth wave between VRTn and the peak voltage VTn (here, one is taken as an example), wherein the peak voltage VTn is located between the reference voltage VREF and the system voltage OVDD, and the highest point of the gate voltage VGc is VTn + VDF.

According to the above, the ramp signal Vran is clamped by the capacitor C1, so it is shifted by a voltage difference VDF. In addition, when the voltage level of the displaced ramp signal Vran is less than the threshold voltage Vth3 of the transistor T32, the transistor T32 will not be turned on, so that the driving current idc of the PLT flowing through the light emitting diode OLD1 during the light emitting period is 0; Conversely, when the voltage level of the shifted ramp signal Vran is greater than or equal to the threshold voltage Vth3 of the transistor T32, the transistor T32 is turned on, so that the driving current idc of the PLT flowing through the light emitting diode OLD1 during the light emission period is a constant current. iFX. With this, the degree of displacement of the ramp signal Vran determines the supply time TPR of the constant current iFX. Among them, the bias voltage VBc determines the magnitude of the constant current iFX.

In this embodiment, when the voltage level of the ramp signal Vran shifted during the light-emitting period PLT is less than the threshold voltage Vth3 of the transistor T32, that is, VTn + VDF is less than the threshold voltage Vth3, it means that the transistor T32 is in the light-emitting period. The PLT will not be turned on, so the brightness (that is, the grayscale value) of the pixel PX will be 0.

5A is a schematic circuit diagram of a pixel of the display panel of FIG. 1 according to a fourth embodiment of the present invention. Please refer to FIG. 1 and FIG. 5A. In this embodiment, the pixel PXd includes a transistor T41 (corresponding to a first transistor), a transistor T44 (corresponding to a fourth transistor), a light emitting diode OLD1, and a time control unit TCXd. And constant current source SRid. The time control unit TCXd includes a transistor T42 (corresponding to a second transistor) and a capacitor C1. The constant current source SRid includes a transistor T43 (corresponding to a third transistor). Among them, the transistors T41 to T44 use p-type transistors as an example.

The source (corresponding to the first terminal) of the transistor T41 receives the data voltage VDATA, the gate (corresponding to the control terminal) of the transistor T41 receives the write control signal SWTp, and the drain (corresponding to the second terminal) of the transistor T41 is coupled to the capacitor One end of C1. One end of the capacitor C1 is coupled to the drain of the transistor T41, and the other end of the capacitor C1 receives a ramp signal Vrap. The gate (corresponding to the control end) of the transistor T42 is coupled to one end of the capacitor C1, and the drain (corresponding to the first end) of the transistor T42 is coupled to the anode of the light emitting diode OLD1. The cathode of the light-emitting diode OLD1 receives a system voltage OVSS (corresponding to the first system voltage).

The gate (corresponding to the control terminal) of the transistor T43 receives the bias voltage VBd, and the source (corresponding to the second terminal) of the transistor T43 receives the system voltage OVDD (corresponding to the second system voltage). Wherein, the bias voltage VBd is an arbitrary voltage which is smaller than the threshold voltage of the transistor T43 and is located in the saturation region.

The drain (corresponding to the first terminal) of the transistor T44 is coupled to the source (corresponding to the second terminal) of the transistor T42, that is, the transistor T42 is coupled to the anode of the light-emitting diode OLD1, and the gate of the transistor T44 ( The corresponding control terminal) receives the light-emitting control signal SLTp, and the source (corresponding to the second terminal) of the transistor T44 is coupled to the drain (corresponding to the first terminal) of the transistor T43 of the constant current source SRid.

FIG. 5B is a driving schematic diagram of the pixel of FIG. 5A according to the fourth embodiment of the present invention. Please refer to FIG. 5A and FIG. 5B. During the data writing period PDW, the write control signal SWTp forms a negative write pulse PWT2 to turn on the crystal T41; the light emission control signal SLTp is set to the disable level to cut off the transistor T44. ; And the ramp signal Vrap is set to the reference voltage VREF, and the capacitor C1 stores a voltage difference VDF. At this time, since the transistor T44 is not turned on, the driving current idd flowing through the light-emitting diode OLD1 is 0.

During the PRT reset period, the write control signal SWTp and the light emission control signal SLTp are set to the disabled level, that is, the transistors T41 and T44 are not turned on; and the ramp signal Vrap is between the reference voltage VREF and the system voltage OVDD. The reset voltage VRTp, and the gate voltage VGd of the transistor T42 is VRTp + VDF.

During the light-emitting period PLT, the write control signal SWTp is set to the disable level to cut off the transistor T41; the light-emitting control signal SLTp is set to the enable level to turn on the transistor T44; and the ramp signal Vrap is formed at the reset voltage VRTp At least one sawtooth wave between the peak voltage VTp (here, one is taken as an example), where the peak voltage VTp is between the reference voltage VREF and the system voltage OVSS, and the lowest point of the gate voltage VGd is VTp + VDF.

According to the above, the ramp signal Vrap is clamped by the capacitor C1, so it is shifted by a voltage difference VDF. In addition, when the voltage level of the displaced ramp signal Vrap is greater than the threshold voltage Vth4 of the transistor T42, the transistor T42 will not be turned on, so that the driving current idd of the PLT flowing through the light emitting diode OLD1 during the light emitting period is 0; Conversely, when the voltage level of the displaced ramp signal Vrap is less than or equal to the threshold voltage Vth4 of the transistor T42, the transistor T42 will be turned on, so that the driving current idd flowing through the light-emitting diode OLD1 during the light-emitting period is a constant current. iFX. With this, the degree of displacement of the ramp signal Vrap determines the supply time TPR of the constant current iFX. Among them, the bias voltage VBd determines the magnitude of the constant current iFX.

In this embodiment, when the voltage level of the ramp signal Vrap shifted during the light-emitting period PLT is greater than the threshold voltage Vth4 of the transistor T42, that is, VTn + VDF is greater than the threshold voltage Vth3, it means that the transistor T42 is in the light-emitting period. The PLT will not be turned on, so the brightness (that is, the grayscale value) of the pixel PX will be 0.

6A is a schematic circuit diagram of a pixel of the display panel of FIG. 1 according to a fifth embodiment of the present invention. Please refer to FIG. 1 and FIG. 6A. In this embodiment, the pixel PXe includes a transistor T51 (corresponding to the first transistor), a light emitting diode OLD1, a time control unit TCXe, and a constant current source Srie. The time control unit TCXe includes a transistor T52 (corresponding to a second transistor) and a capacitor C1. The constant current source SRie includes transistors T53 to T55 (corresponding to the fifth to seventh transistors) and a capacitor C2 (corresponding to the second capacitor). Among them, the transistors T51 to T55 are examples of n-type transistors.

The drain (corresponding to the first terminal) of the transistor T51 receives the data voltage VDATA, the gate (corresponding to the control terminal) of the transistor T51 receives the write control signal SWTn, and the source (corresponding to the second terminal) of the transistor T51 is coupled to the capacitor. One end of C1. One end of the capacitor C1 is coupled to the source of the transistor T51, and the other end of the capacitor C1 receives the ramp signal Vran. The drain (corresponding to the first terminal) of the transistor T52 is coupled to the constant current source SRie to couple the cathode of the light emitting diode OLD1 through the constant current source SRie, and the gate (corresponding to the control terminal) of the transistor T52 is coupled to the capacitor C1 At one end, the source (corresponding to the second end) of the transistor T52 receives the system voltage OVSS (corresponding to the second system voltage).

The anode of the light-emitting diode OLD1 receives a system voltage OVDDx (corresponding to the first system voltage). The drain (corresponding to the first end) of the transistor T53 is coupled to the cathode of the light emitting diode OLD1, and the source (corresponding to the second end) of the transistor T53 is coupled to the drain of the transistor T52. The capacitor C2 is coupled between the gate (corresponding to the control terminal) and the source of the transistor T53. The drain (corresponding to the first terminal) of the transistor T54 receives the high voltage VDDH, the gate (corresponding to the control terminal) of the transistor T54 receives the switching control signal SSCn, and the source (corresponding to the second terminal) of the transistor T54 is coupled to the capacitor C2 The end. The drain (corresponding to the first terminal) of the transistor T55 receives the low voltage VDDL, the gate (corresponding to the control terminal) of the transistor T55 receives the switching control signal SSCn, and the source (corresponding to the second terminal) of the transistor T55 is coupled to the transistor The drain of T53.

FIG. 6B is a driving schematic diagram of the pixel of FIG. 6A according to a fifth embodiment of the present invention. 6A and 6B, during the data writing period PDW, the writing control signal SWTn forms a positive writing pulse PWT1 to turn on the crystal T51; the switch control signal SSCn is set to the enable level to turn on the crystal T54 And T55; the system voltage OVDDx is set to a low voltage VDDL, the ramp signal Vran is set to a reference voltage VREF, and the capacitor C1 stores a voltage difference VDF.

At this time, since the voltage across the light emitting diode OLD1 is at the same voltage level, the driving current ide flowing through the light emitting diode OLD1 is 0. In addition, the turned-on transistor T53 transmitted through the source of the transistor T55 is coupled to the other end of the capacitor C2, so that the capacitor C2 stores a voltage difference between the high voltage VDDH and the low voltage VDDL.

During the PRT reset, the write control signal SWTn is set to the disabled level to cut off the transistor T51; the switch control signal SSCn is set to the enabled level, the system voltage OVDDx is set to the high voltage VDDH, and the ramp signal Vran is located at The reset voltage VRTn between the reference voltage VREF and the system voltage OVSS, and the gate voltage VGe of the transistor T52 is VRTn + VDF.

During the light-emitting period PLT, the system voltage OVDDx is set to a high voltage VDDH; the write control signal SWTn and the switch control signal SSCn are set to disable levels to cut off the transistors T51, T54, and T55; and the ramp signal Vran is formed at reset At least one sawtooth wave between the voltage VRTn and the peak voltage VTn (here, one is taken as an example), where the peak voltage VTn is between the reference voltage VREF and the system voltage OVDD, and the highest point of the gate voltage VGe is VTn + VDF .

According to the above, the ramp signal Vran is clamped by the capacitor C1, so it is shifted by a voltage difference VDF. In addition, when the voltage level of the shifted ramp signal Vran is less than the threshold voltage Vth5 of the transistor T52, the transistor T52 will not be turned on, so that the driving current ide flowing through the light emitting diode OLD1 during the PLT period is 0; Conversely, when the voltage level of the shifted ramp signal Vran is greater than or equal to the threshold voltage Vth5 of the transistor T52, the transistor T52 will be turned on, so that the driving current ide flowing through the light emitting diode OLD1 during the PLT period is a constant current. iFX. With this, the degree of displacement of the ramp signal Vran determines the supply time TPR of the constant current iFX. Among them, the voltage difference between the high voltage VDDH and the low voltage VDDL determines the magnitude of the constant current iFX.

In this embodiment, when the voltage level of the ramp signal Vran shifted in the light-emitting period PLT is less than the threshold voltage Vth5 of the transistor T52, that is, VTn + VDF is less than the threshold voltage Vth5, it means that the transistor T52 is in the light-emitting period. The PLT will not be turned on, so the brightness (that is, the grayscale value) of the pixel PX will be 0.

FIG. 7A is a schematic circuit diagram of pixels of the display panel of FIG. 1 according to a sixth embodiment of the present invention. Please refer to FIG. 1 and FIG. 7A. In this embodiment, the pixel PXf includes a transistor T61 (corresponding to the first transistor), a light emitting diode OLD1, a time control unit TCXf, and a constant current source SRif. The time control unit TCXf includes a transistor T62 (corresponding to a second transistor) and a capacitor C1. The constant current source SRif includes transistors T63 to T65 (corresponding to the fifth to seventh transistors) and a capacitor C3 (corresponding to the second capacitor). Among them, the transistors T61 to T65 are p-type transistors as an example.

The source (corresponding to the first terminal) of the transistor T61 receives the data voltage VDATA, the gate (corresponding to the control terminal) of the transistor T61 receives the write control signal SWTp, and the drain (corresponding to the second terminal) of the transistor T61 is coupled to the capacitor One end of C1. The other end of the capacitor C1 receives the ramp signal Vrap. The drain (corresponding to the first terminal) of the transistor T62 is coupled to the constant current source SRif to couple the anode of the light-emitting diode OLD1 through the constant current source SRif. The gate (corresponding to the control terminal) of the transistor T62 is coupled to the capacitor C1 At one end, the source (corresponding to the second end) of the transistor T62 receives the system voltage OVDDx (corresponding to the second system voltage).

The cathode of the light-emitting diode OLD1 receives a system voltage OVSS (corresponding to the first system voltage). The drain (corresponding to the first terminal) of the transistor T63 is coupled to the anode of the light emitting diode OLD1, and the source (corresponding to the second terminal) of the transistor T63 is coupled to the drain of the transistor T62. The capacitor C3 is coupled between the gate (corresponding to the control terminal) and the source of the transistor T63. The drain (corresponding to the first terminal) of the transistor T64 receives the low voltage VDDL, the gate (corresponding to the control terminal) of the transistor T64 receives the switching control signal SSCp, and the source (corresponding to the second terminal) of the transistor T64 is coupled to the capacitor C3 The end. The drain (corresponding to the first terminal) of the transistor T65 receives the high voltage VDDH, the gate (corresponding to the control terminal) of the transistor T65 receives the switching control signal SSCp, and the source (corresponding to the second terminal) of the transistor T65 is coupled to the capacitor C3 The other end.

FIG. 7B is a driving schematic diagram of the pixel of FIG. 2A according to a sixth embodiment of the present invention. Please refer to FIG. 7A and FIG. 7B. During the data writing period PDW, the write control signal SWTp forms a negative write pulse PWT2 to turn on the crystal T61. The switch control signal SSCp is set to the enable level to turn on the crystal T64. And T65; the system voltage OVDDx is set to a low voltage VDDL, the ramp signal Vrap is set to a reference voltage VREF, and the capacitor C1 stores a voltage difference VDF.

At this time, since the system voltage OVDDx is a low voltage VDDL, the driving current idf flowing through the light-emitting diode OLD1 is 0. Also, the capacitor C3 stores a voltage difference between the high voltage VDDH and the low voltage VDDL.

During the PRT reset, the write control signal SWTp is set to the disable level to cut off the transistor T61; the switch control signal SSCp is set to the enable level, the system voltage OVDDx is set to the low voltage VDDL, and the ramp signal Vrap is located at The reset voltage VRTp between the reference voltage VREF and the system voltage OVSS, and the gate voltage VGf of the transistor T62 is VRTp + VDF.

During the light-emitting period PLT, the system voltage OVDDx is a high voltage VDDH; the write control signal SWTp and the switch control signal SSCp are disabled levels to cut off the transistors T61, T64, and T65; and the ramp signal Vrap is formed between the reset voltage VRTp and At least one sawtooth wave between the peak voltages VTp (here, one is taken as an example), where the peak voltage VTp is between the reference voltage VREF and the system voltage OVSS, and the lowest point of the gate voltage VGf is VTp + VDF.

According to the above, the ramp signal Vrap is clamped by the capacitor C1, so it is shifted by a voltage difference VDF. In addition, when the voltage level of the displaced ramp signal Vrap is greater than the threshold voltage Vth6 of the transistor T62, the transistor T62 will not be turned on, so that the driving current idf of the PLT flowing through the light emitting diode OLD1 during the light emitting period is 0; Conversely, when the voltage level of the displaced ramp signal Vrap is less than or equal to the threshold voltage Vth6 of the transistor T62, the transistor T62 will be turned on, so that the driving current idf of the PLT flowing through the light-emitting diode OLD1 during the light-emitting period is a constant current. iFX. With this, the degree of displacement of the ramp signal Vrap determines the supply time TPR of the constant current iFX. Among them, the voltage difference between the high voltage VDDH and the low voltage VDDL determines the magnitude of the constant current iFX.

In this embodiment, when the voltage level of the ramp signal Vrap shifted during the light-emitting period PLT is greater than the threshold voltage Vth6 of the transistor T62, that is, VTn + VDF is greater than the threshold voltage Vth6, it indicates that the transistor T62 is in the light-emitting period. The PLT will not be turned on, so the brightness (that is, the grayscale value) of the pixel PX will be 0.

Please refer to FIGS. 1, 2A, 2B, 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A, and 7B. In an embodiment of the invention, all pixels (such as PX, PXa ~ PXf) will receive the corresponding data voltage VDATA during the data writing period PDW, and the same ramp signal (such as Vran, Vrap). In this way, the driving method of the pixels of the display panel (such as 100) can be simplified, and the image sticking caused by sequential lighting can be avoided.

In another embodiment of the present invention, all pixels (such as PX, PXa ~ PXf) can be divided into multiple pixel groups, and the corresponding data voltages VDATA are sequentially written and lighted sequentially, in which pixels A group is a unit of a row, that is, each pixel group includes at least one row of pixels (such as PX, PXa ~ PXf). The pixels in each pixel group (such as PX, PXa ~ PXf) will receive the corresponding data voltage VDATA during the data writing period PDW, and the same ramp signal (such as Vran, Vrap) will be received during the light-emitting period PLT That is, pixels of different pixel groups (such as PX, PXa ~ PXf) receive different slope signals (such as Vran, Vrap) during the light-emitting period PLT. Thereby, the time required for PDW in the data writing period can be shortened, and the PLT time in the light-emitting period can be extended, and each pixel (such as PX, PXa ~ PXf) can have a longer light-emitting time.

FIG. 8 is a flowchart of a pixel driving method according to an embodiment of the present invention. Referring to FIG. 8, in this embodiment, the pixel has a light emitting diode, and the driving method of the pixel includes the following steps. In step S810, during the data writing period, a voltage difference between the data voltage and the reference voltage is determined. In step S820, during the light emission period, the supply time of providing a constant current to the light emitting diode is determined according to the voltage difference. The sequence of steps S810 and S820 is for illustration, and the embodiment of the present invention is not limited thereto. And, for details of steps S810 and S820, please refer to FIGS. 1, 2A, 2B, 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A and 7B. As shown in the embodiment, it will not be repeated here.

For example, in some embodiments, the pixel driving method further includes: forming at least one sawtooth wave between the reset voltage and the peak voltage during the light emission period; and shifting at least one sawtooth according to the voltage difference during the light emission period. And, during the light emission period, comparing the shifted at least one sawtooth wave with the threshold voltage of the transistor to determine the supply time of the constant current to the light emitting diode. The reference voltage is between the reset voltage and the peak voltage. In some embodiments, the pixel driving method further includes: blocking a constant current from being supplied to the light emitting diode during a data writing period and a reset period.

In summary, in the display panel and the pixel driving method of the embodiment of the present invention, since the light-emitting diode determines the overall light-emitting brightness of the light-emitting diode through the supply time of the constant current, the supply time of the constant current is According to the voltage difference between the reference voltage and the data voltage, the color shift caused by the current change after miniaturizing the light emitting diode can be avoided. In addition, all the pixels in the display panel receive the same ramp signal, thereby simplifying the driving method of the pixels of the display panel and avoiding the image sticking caused by sequential lighting. Alternatively, all pixels in the display panel can be divided into multiple pixel groups. The pixels in each pixel group receive the same ramp signal, and the pixels of different pixel groups receive different ramp signals. Each pixel may have a longer lighting time.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

100‧‧‧ display panel

110‧‧‧Control line

120‧‧‧ Data Line

C1 ~ C3‧‧‧Capacitor

ida ~ idf‧‧‧Drive current

iFX‧‧‧Constant current

OLD1‧‧‧light-emitting diode

OVDD, OVSS, OVDDx‧‧‧ system voltage

PDW‧‧‧Data writing period

PLT‧‧‧lighting period

PRT‧‧‧ Reset period

PWT1‧‧‧ is writing pulse

PWT2‧‧‧Negative write pulse

PX, PXa ~ PXf‧‧‧ pixels

PXA‧‧‧Pixel Array

SLTn, SLTp ‧‧‧light control signal

SRi, SRia ~ SRif‧‧‧Constant current source

SSCn, SSCp‧‧‧ Switch control signal

SWTn, SWTp‧‧‧ write control signal

T11 ~ T13, T21 ~ T23, T31 ~ T34, T41 ~ T44, T51 ~ T55, T61 ~ T65‧‧‧Transistors

TCX, TCXa ~ TCXf‧‧‧ Time Control Unit

TPR‧‧‧ provides time

VBa ~ VBf‧‧‧ bias

VDATA‧‧‧Data voltage

VDDH‧‧‧High voltage

VDDL‧‧‧Low voltage

VDF‧‧‧Voltage difference

VGa ~ VGf‧‧‧Gate voltage

Vran, Vrap ‧‧‧ Ramp signal

VREF‧‧‧Reference voltage

VRTn, VRTp‧‧‧ reset voltage

Vth1 ~ Vth6‧‧‧ critical voltage

VTn, VTp‧‧‧ peak voltage

S810, S820‧‧‧step

FIG. 1 is a system schematic diagram of a display panel according to an embodiment of the present invention. FIG. 2A is a schematic circuit diagram of pixels of the display panel of FIG. 1 according to the first embodiment of the present invention. FIG. 2B is a driving schematic diagram of the pixel of FIG. 2A according to the first embodiment of the present invention. 3A is a schematic circuit diagram of a pixel of the display panel of FIG. 1 according to a second embodiment of the present invention. FIG. 3B is a driving schematic diagram of the pixel of FIG. 3A according to the second embodiment of the present invention. 4A is a schematic circuit diagram of a pixel of the display panel of FIG. 1 according to a third embodiment of the present invention. FIG. 4B is a driving schematic diagram of the pixel of FIG. 4A according to the third embodiment of the present invention. 5A is a schematic circuit diagram of a pixel of the display panel of FIG. 1 according to a fourth embodiment of the present invention. FIG. 5B is a driving schematic diagram of the pixel of FIG. 5A according to the fourth embodiment of the present invention. 6A is a schematic circuit diagram of a pixel of the display panel of FIG. 1 according to a fifth embodiment of the present invention. FIG. 6B is a driving schematic diagram of the pixel of FIG. 6A according to a fifth embodiment of the present invention. FIG. 7A is a schematic circuit diagram of pixels of the display panel of FIG. 1 according to a sixth embodiment of the present invention. FIG. 7B is a driving schematic diagram of the pixel of FIG. 2A according to a sixth embodiment of the present invention. FIG. 8 is a flowchart of a pixel driving method according to an embodiment of the present invention.

Claims (13)

A display panel includes: a pixel array having a plurality of pixels, each of which includes: a light-emitting diode that receives a first system voltage; a certain current source that provides a certain current; a time control unit Is coupled in series with the light emitting diode and the constant current source, and has a first capacitor to store a voltage difference between a reference voltage and a data voltage, wherein the time control unit determines to provide the constant current according to the voltage difference A supply time to the light-emitting diode; and a first transistor having a first terminal receiving the data voltage, a control terminal receiving a write control signal, and a second terminal coupled to one end of the first capacitor Terminal, wherein the time control unit includes: the first capacitor having the one terminal and the other terminal receiving a ramp signal; and a second transistor having a first terminal coupled to the light emitting diode and coupled to the first terminal. A control terminal of the one end of a capacitor and a second terminal coupled to the constant current source. The display panel according to item 1 of the patent application scope, wherein the current source includes a third transistor, a first terminal coupled to the second terminal of the second transistor, a control terminal receiving a bias voltage, and a receiving terminal. A second terminal of a second system voltage, wherein the second system voltage is different from the first system voltage. The display panel according to item 2 of the scope of patent application, wherein during a data writing period, the writing control signal forms a writing pulse, the bias voltage is a disabled level, and the ramp signal is the reference Voltage, during a reset period, the bias voltage and the write control signal are the disabled level, and the ramp signal is a reset voltage between the reference voltage and the second system voltage, and a light emitting During this period, the bias voltage is a bias level, the write control signal is the disable level, and the ramp signal forms at least one sawtooth wave between the reset voltage and a peak voltage, wherein the peak voltage Between the reference voltage and the first system voltage. The display panel according to item 2 of the scope of patent application, further comprising a fourth transistor having a first terminal coupled to the light-emitting diode, a control terminal receiving a light-emitting control signal, and a constant current source. The second end. The display panel according to item 4 of the scope of patent application, wherein in a data writing period, the writing control signal forms a writing pulse, the light emitting control signal is a disabled level, and the ramp signal is the The reference voltage. During a reset period, the write control signal and the light emission control signal are the disabled level, and the ramp signal is a reset voltage between the reference voltage and the second system voltage. During a light emission period, the write control signal is the disable level, the light emission control signal is the uniform level, and the ramp signal forms at least one sawtooth wave between the reset voltage and a peak voltage, wherein the The peak voltage is between the reference voltage and the first system voltage. The display panel according to item 1 of the patent application scope, wherein the current source includes a fifth transistor having a first terminal coupled to the light emitting diode and a first terminal coupled to the second transistor. A second capacitor, coupled between the control terminal of the fifth transistor and the second terminal of the fifth transistor; a sixth transistor, having a first terminal receiving a high voltage, A control terminal receiving a switch control signal and a second terminal coupled to one end of the second capacitor; and a seventh transistor having a first terminal receiving a low voltage, a control terminal receiving the switch control signal, and A second end coupled to the other end of the second capacitor. The display panel according to item 6 of the scope of patent application, wherein during a data writing period, the writing control signal forms a writing pulse, the switching control signal is a uniform energy level, and the second system voltage is the Low voltage, and the ramp signal is the reference voltage, during a reset period, the switch control signal is the enable level, the write control signal is a disable level, and the ramp signal is at the reference voltage A reset voltage between the second system voltage and the second system voltage during the light emission period, the second system voltage is the high voltage, the write control signal and the switch control signal are the disable level, and the ramp signal Forming at least one sawtooth wave between the reset voltage and a peak voltage, wherein the peak voltage is between the reference voltage and the first system voltage. The display panel according to item 1 of the scope of patent application, wherein the pixels are divided into multiple pixel groups, and each of the pixel groups receives the same slope signal, and different pixel groups receive different Ramp signal. The display panel according to item 8 of the scope of patent application, wherein each of the pixel groups includes a row of the pixels. The display panel according to item 1 of the scope of patent application, wherein the pixels receive the same ramp signal. A pixel driving method. The pixel has a light-emitting diode, which includes: determining a voltage difference between a data voltage and a reference voltage during a data writing period; and providing a light-emitting period based on the voltage difference. A certain current to a supply time of the light emitting diode; and blocking the constant current from being supplied to the light emitting diode during the data writing period and a reset period. The pixel driving method according to item 11 of the scope of patent application, further comprising: during the light emission period, forming at least one sawtooth wave between a reset voltage and a peak voltage; during the light emission period, according to the voltage Differentially shifting the at least one sawtooth wave; and during the light emission period, comparing the shifted at least one sawtooth wave with a threshold voltage of a transistor to determine the supply time of the constant current to the light emitting diode. The pixel driving method according to item 12 of the application, wherein the reference voltage is between the reset voltage and the peak voltage.