TWI621239B - Transient voltage suppressor (tvs) with reduced breakdown voltage - Google Patents

Transient voltage suppressor (tvs) with reduced breakdown voltage Download PDF

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TWI621239B
TWI621239B TW105142485A TW105142485A TWI621239B TW I621239 B TWI621239 B TW I621239B TW 105142485 A TW105142485 A TW 105142485A TW 105142485 A TW105142485 A TW 105142485A TW I621239 B TWI621239 B TW I621239B
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epitaxial layer
implant
trench
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TW201724459A (en
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史寧
管靈鵬
博多 馬督兒
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萬國半導體股份有限公司
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Abstract

一個帶有突返控制和低電壓穿通擊穿模式的低電容暫態電壓抑制器，包括一個n+型基板、一個在基板上的第一外延層、一個形成在第一外延層中的掩埋層、一個在第一外延層上的第二外延層，以及一個形成在掩埋層下方第一外延層中的注入層。注入層在掩埋層上方延伸。第一溝槽位於掩埋層的一邊和注入層的一邊。第二溝槽位於掩埋層的另一邊，並在注入層中延伸。第三溝槽位於注入層的另一邊。一組源極區形成在第二外延層的頂面中。注入區形成在第二外延層中，第一注入區位於第一源極區下方。 A low capacitance transient voltage suppressor with a flashback control and a low voltage punch-through breakdown mode, comprising an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed in the first epitaxial layer, a second epitaxial layer on the first epitaxial layer and an implant layer formed in the first epitaxial layer below the buried layer. The implant layer extends over the buried layer. The first trench is located on one side of the buried layer and on one side of the implanted layer. The second trench is located on the other side of the buried layer and extends in the implanted layer. The third trench is located on the other side of the implant layer. A set of source regions are formed in the top surface of the second epitaxial layer. The implantation region is formed in the second epitaxial layer, and the first implantation region is located below the first source region.

Description

暫態電壓抑制器元件及製備方法 Transient voltage suppressor component and preparation method

本發明主要涉及積體電路，更確切地說是暫態電壓抑制器。 The present invention relates generally to integrated circuits, and more particularly to transient voltage suppressors.

暫態電壓抑制器(TVS)是用於保護積體電路不受過電壓損壞的元件。積體電路設計在正常範圍內的電壓下工作。然而，靜電放電(ESD)、電力快速瞬變和閃電、意外的、不可控的高電壓等情況可能會對電路造成意外損壞。需要TVS元件提供保護，避免發生這種過電壓情況時，可能會對積體電路造成的損壞。隨著越來越多的元件配有這種易受過電壓損壞的積體電路，對TVS保護的需求也與日俱增。TVS的典型應用可以用於USB電源和資料線保護、數位視訊介面、高速乙太網、筆記型電腦、顯示器和平板顯示器。 A transient voltage suppressor (TVS) is an element used to protect an integrated circuit from overvoltage damage. The integrated circuit is designed to operate at voltages within the normal range. However, electrostatic discharge (ESD), rapid power transients and lightning, unexpected, uncontrollable high voltage conditions can cause accidental damage to the circuit. TVS components are required to provide protection against damage to the integrated circuit when such overvoltage conditions occur. As more and more components are equipped with such integrated circuits that are susceptible to overvoltage damage, the need for TVS protection is increasing. Typical applications for TVS can be used for USB power and data line protection, digital video interface, high speed Ethernet, notebook computers, displays and flat panel displays.

如圖1所示，配有二極體陣列的傳統TVS電路，用於高頻寬資料匯流排的靜電放電(ESD)保護。TVS電路100包括一個主穩壓二極體101，配有兩套導向二極體，也就是高端導向二極體103和低端導向二極體105。高端導向二極體103連接到電壓源Vcc，低端導向二極體105連接到接地端Gnd，輸入/輸出埠I/O連接在高端和低端導向二極體之間。穩壓二極體101具有大尺寸，用作雪崩二極體，從高壓端(即Vcc端)到接地電壓端(即Gnd端)。當I/O(輸入/輸出)端連接正電壓時，高端二極體提供正向偏壓，被大型穩壓二極體鉗位。 As shown in Figure 1, a conventional TVS circuit with a diode array is used for electrostatic discharge (ESD) protection of high-frequency wide data busses. The TVS circuit 100 includes a main regulated diode 101 with two sets of guiding diodes, namely a high-end guiding diode 103 and a low-end guiding diode 105. The high side steering diode 103 is connected to the voltage source Vcc, the low side guiding diode 105 is connected to the ground terminal Gnd, and the input/output 埠 I/O is connected between the high side and the low side guiding diode. The voltage stabilizing diode 101 has a large size and is used as an avalanche diode from the high voltage terminal (ie, the Vcc terminal) to the ground voltage terminal (ie, the Gnd terminal). When the I/O (input/output) is connected to a positive voltage, the high-side diode provides forward bias and is clamped by a large regulator.

這種TVS需要多種元件性能。為了更好地保護連接到TVS上的積體電路，需要很低的TVS鉗位元電壓。低鉗位元電壓確保任何靜電放電(ESD) 都不會影響積體電路。元件鉗位元電壓在很大程度上依賴於穩壓/雪崩二極體的擊穿電壓。因此，為了增大鉗位元電壓，還需要維持穩壓/雪崩二極體處很低的擊穿電壓。“穩壓”和“雪崩”一詞可以互換使用，以描述具有雪崩擊穿性能的二極體。為了具有很低的鉗位元電壓和很低的雪崩二極體擊穿電壓，還必須具有極其低的整體元件電容。低元件電容意味著元件運行時較高的可允許頻寬以及插損的降低。為了減少成本並維持與小尺寸積體電路的相容性，也需要減小這種TVS元件的晶片封裝尺寸。 This TVS requires a variety of component performance. In order to better protect the integrated circuit connected to the TVS, a very low TVS clamp voltage is required. Low clamp voltage ensures any electrostatic discharge (ESD) Will not affect the integrated circuit. The component clamp voltage is largely dependent on the breakdown voltage of the regulated/avalanche diode. Therefore, in order to increase the clamp voltage, it is also necessary to maintain a very low breakdown voltage at the voltage regulator/avalanche diode. The terms "regulated" and "avalanche" are used interchangeably to describe a diode having avalanche breakdown properties. In order to have a very low clamp voltage and a very low avalanche diode breakdown voltage, it is also necessary to have an extremely low overall component capacitance. Low component capacitance means a higher allowable bandwidth and a reduction in insertion loss when the component is operating. In order to reduce costs and maintain compatibility with small-sized integrated circuits, it is also necessary to reduce the chip package size of such TVS components.

利用目前的TVS元件，仍然需要進一步減小晶片尺寸，降低元件電容，改進擊穿電壓和鉗位元電壓等性能。因此，必須提出新型的、改良元件結構，藉由新型結構佈局和製備方法，來達成這些目標。 With current TVS components, there is still a need to further reduce wafer size, reduce component capacitance, and improve breakdown voltage and clamp voltage. Therefore, new and improved component structures must be proposed to achieve these goals through new structural layouts and fabrication methods.

正是在這樣的背景下，提出了本發明的實施例。 It is against this background that embodiments of the invention have been proposed.

本發明提供一種具有低擊穿電壓的暫態電壓抑制器，減小晶片尺寸，降低元件電容，改進擊穿電壓和鉗位元電壓性能。 The present invention provides a transient voltage suppressor having a low breakdown voltage, which reduces wafer size, reduces component capacitance, and improves breakdown voltage and clamp voltage performance.

為實現上述目的，本發明提供一種暫態電壓抑制器元件，其特點是，包含：a)一個第一導電類型的半導體基板；b)在基板上，一個第一導電類型的半導體材料的第一外延層；c)一個第一導電類型的半導體材料的掩埋層，位於第一外延層中；d)一個第二導電類型的半導體材料的注入層，位於掩埋層下方的第一外延層中，注入層在水平方向延伸超出掩埋層，NPN結構由掩埋層、注入層、第一外延層和基板構成； e)一個第一導電類型的半導體材料的第二外延層，位於第一外延層上方；f)一對第二導電類型的半導體材料的注入區，在第二外延層的頂面中；g)一個第二導電類型的半導體材料的穿通注入區，在外延層的頂面中；h)一組形成在第二外延層和第一外延層中的溝槽，組中的每個溝槽都至少內襯電介質材料，這組溝槽包括一個第一溝槽，靠近掩埋層一邊緣和注入層一邊緣以及在穿通注入區和第一注入區之間，一個第二溝槽，靠近掩埋層另一邊緣，延伸到注入層中，一個第三溝槽，靠近注入層另一邊緣，其中第二溝槽在第一溝槽和第三溝槽之間；以及i)一組第一導電類型的半導體材料的源極區，在第二外延層的頂面中，這組源極區包括一個第一源極區，位於穿通注入區上方，一個第二源極區，位於第一溝槽和第二溝槽之間，一個第三源極區，位於第二溝槽和第三溝槽之間，以及一個第四源極區，使得第三溝槽位於第三源極區和第四源極區之間，其中第一注入區位於第二源極區和第三源極區之間，第二注入區位於第三溝槽和第三溝槽側壁附近的第三源極區之間，由第一源極區、穿通注入區和第二外延層構成一個垂直PN結，由第二源極區、第二外延層和第一注入區構成一個水平PN結，以及由第三源極區、第二外延層和第二注入區構成一個水平PN結。 To achieve the above object, the present invention provides a transient voltage suppressor element characterized by comprising: a) a semiconductor substrate of a first conductivity type; b) a first semiconductor material of a first conductivity type on the substrate An epitaxial layer; c) a buried layer of a first conductivity type semiconductor material, located in the first epitaxial layer; d) an implant layer of a second conductivity type semiconductor material, located in the first epitaxial layer below the buried layer, implanted The layer extends in a horizontal direction beyond the buried layer, and the NPN structure is composed of a buried layer, an implanted layer, a first epitaxial layer, and a substrate; e) a second epitaxial layer of a first conductivity type semiconductor material over the first epitaxial layer; f) a pair of implant regions of a second conductivity type semiconductor material in the top surface of the second epitaxial layer; g) a through-injection region of a second conductivity type semiconductor material in a top surface of the epitaxial layer; h) a set of trenches formed in the second epitaxial layer and the first epitaxial layer, each trench in the group being at least Lined with a dielectric material, the set of trenches includes a first trench adjacent an edge of the buried layer and an edge of the implant layer and between the feedthrough implant region and the first implant region, a second trench adjacent to the buried layer and another An edge extending into the implant layer, a third trench adjacent the other edge of the implant layer, wherein the second trench is between the first trench and the third trench; and i) a set of semiconductors of the first conductivity type a source region of the material, in the top surface of the second epitaxial layer, the set of source regions includes a first source region, above the through implant region, and a second source region at the first trench and the second region Between the trenches, a third source region, located in the second trench and Between the third trenches and a fourth source region, such that the third trench is between the third source region and the fourth source region, wherein the first implant region is located in the second source region and the third source Between the polar regions, the second implant region is located between the third trench and the third source region near the sidewall of the third trench, and the first source region, the punch-through implant region and the second epitaxial layer form a vertical PN junction Forming a horizontal PN junction from the second source region, the second epitaxial layer, and the first implant region, and forming a horizontal PN junction from the third source region, the second epitaxial layer, and the second implant region.

上述第一導電類型為N，第二導電類型為P。 The first conductivity type is N and the second conductivity type is P.

上述基板為重摻雜n-型半導體基板。 The substrate is a heavily doped n-type semiconductor substrate.

上述第一外延層的半導體材料為n-型材料，其n-型摻雜濃度低於基板。 The semiconductor material of the first epitaxial layer is an n-type material having an n-type doping concentration lower than that of the substrate.

上述第一溝槽、第二溝槽和第三溝槽中的每一個都用電介質材料填充。 Each of the first trench, the second trench, and the third trench is filled with a dielectric material.

h)中的每個溝槽都用多晶矽填充。 Each trench in h) is filled with polysilicon.

上述元件還包括一個p-型半導體材料的沉降區，形成在第二外延層中，沉降區位於穿通注入區下方，在第一源極區和第二源極區之間。 The element further includes a settling region of a p-type semiconductor material formed in the second epitaxial layer, the settling region being located below the through implant region, between the first source region and the second source region.

上述元件還包括一個p-型半導體材料的沉降區，形成在第二外延層中，沉降區位於第三溝槽的右側壁附近。 The element further includes a settling region of a p-type semiconductor material formed in the second epitaxial layer, the settling region being located adjacent the right side wall of the third trench.

上述元件還包括一個n-型半導體材料的沉降區，形成在第二外延層中，沉降區位於第四源極區下方。 The above component further includes a sink region of an n-type semiconductor material formed in the second epitaxial layer, the sink region being located below the fourth source region.

一種暫態電壓抑制器元件的製備方法，其特點是，包括：a)在第一導電類型的半導體基板上方，製備一個第一導電類型的第一外延層；b)在第一外延層的頂面中，製備一個第一導電類型的半導體材料的掩埋層；c)在第一外延層中，製備一個第二導電類型的半導體材料的注入層，其中注入層位於掩埋層下方，注入層的長度延伸超出掩埋層的長度；d)在第一外延層上方，製備一個第一導電類型的半導體材料的第二外延層；e)在第二外延層的頂面中，製備一個第二導電類型的半導體材料的一對注入區；f)在第二外延層的頂面中，製備一個第二導電類型的半導體材料的穿通注入區；g)在第二外延層和第一外延層中，製備一組溝槽，這組溝槽包括一個第一溝槽，在掩埋層的一邊和注入層的一邊，以及穿通注入區和第一注 入區之間，一個第二溝槽，在掩埋層的另一邊，在注入層中延伸，以及一個第三溝槽，在注入層的另一邊；h)至少用一個電介質材料內襯每個溝槽；i)在第二外延層的頂面中，製備一組第一導電類型的半導體材料的源極區，這組源極區包括一個第一源極區，位於穿通注入區上方，一個第二源極區，位於第一溝槽和第二溝槽之間，一個第三源極區，位於第二溝槽和第三溝槽之間，以及一個第四源極區，使得第三溝槽位於第三源極區和第四源極區之間，其中第一注入區位於第二源極區和第三源極區之間，第二注入區位於第三溝槽和第三溝槽側壁附近的第三源極區之間，一個垂直PN結由第一源極區、穿通注入區和第二外延層構成，一個水平PN結由第二源極區、第二外延層和第一注入區構成，一個垂直PN結由掩埋層、第二外延層和第一注入區構成，以及一個水平PN結由第三源極區、第二外延層和第二注入區構成。 A method for fabricating a transient voltage suppressor element, comprising: a) preparing a first epitaxial layer of a first conductivity type over a semiconductor substrate of a first conductivity type; b) at the top of the first epitaxial layer Preparing a buried layer of a semiconductor material of a first conductivity type; c) preparing an implant layer of a semiconductor material of a second conductivity type in the first epitaxial layer, wherein the implant layer is below the buried layer, and the length of the implant layer Extending beyond the length of the buried layer; d) preparing a second epitaxial layer of a first conductivity type semiconductor material over the first epitaxial layer; e) preparing a second conductivity type in the top surface of the second epitaxial layer a pair of implant regions of semiconductor material; f) preparing a through implant region of a second conductivity type semiconductor material in a top surface of the second epitaxial layer; g) preparing a second epitaxial layer and the first epitaxial layer a group of trenches including a first trench, one side of the buried layer and one side of the implant layer, and a punch-through implant region and a first shot Between the entries, a second trench, on the other side of the buried layer, extending in the implant layer, and a third trench on the other side of the implant layer; h) at least one dielectric material lining each trench a trench; i) in the top surface of the second epitaxial layer, a source region of a set of first conductivity type semiconductor materials, the set of source regions including a first source region, above the through implant region, a first a second source region between the first trench and the second trench, a third source region between the second trench and the third trench, and a fourth source region such that the third trench The trench is located between the third source region and the fourth source region, wherein the first implant region is between the second source region and the third source region, and the second implant region is located at the third trench and the third trench Between the third source regions near the sidewalls, a vertical PN junction is formed by the first source region, the punch-through implant region, and the second epitaxial layer, and a horizontal PN junction is formed by the second source region, the second epitaxial layer, and the first The injection region is formed by a vertical PN junction composed of a buried layer, a second epitaxial layer and a first implantation region, and a water The flat PN junction is composed of a third source region, a second epitaxial layer, and a second implant region.

本發明具有低擊穿電壓的暫態電壓抑制器和現有技術相比，其優點在於，本發明減小了晶片尺寸，降低了元件電容，改進了擊穿電壓和鉗位元電壓性能。 The transient voltage suppressor of the present invention having a low breakdown voltage has an advantage over the prior art in that the present invention reduces wafer size, reduces component capacitance, and improves breakdown voltage and clamp voltage performance.

105、LSD‧‧‧低端導向二極體 105, LSD‧‧‧ low-end guiding diode

103、HSD、HSD2‧‧‧高端導向二極體 103, HSD, HSD2‧‧‧ high-end guiding diode

100、200、200’、300‧‧‧TVS元件 100, 200, 200', 300‧‧‧ TVS components

101‧‧‧穩壓二極體 101‧‧‧Regulators

201、301、401、501‧‧‧基板 201, 301, 401, 501‧‧‧ substrates

203、303、403、503‧‧‧第一外延層 203, 303, 403, 503‧‧‧ first epitaxial layer

205、305、405、505‧‧‧掩埋層 205, 305, 405, 505‧‧ ‧ buried layer

207、307、407、507‧‧‧注入層 207, 307, 407, 507‧‧ ‧ injection layer

209、309、409、509‧‧‧第二外延層 209, 309, 409, 509‧‧‧ second epitaxial layer

211、211'、211”、311、311’、311”、415、415’、415”、515、515’、515”、525‧‧‧絕緣溝槽 211, 211', 211", 311, 311', 311", 415, 415', 415", 515, 515', 515", 525 ‧ ‧ insulated trench

217、317、421、421’、423、521、521’、523‧‧‧沉降區 217, 317, 421, 421', 423, 521, 521', 523 ‧ ‧ settlement area

219、219’、219”、319、319’、319”、319'''、424、424’、424”、424'''、524、524’、524”、524'''‧‧‧源極區 219, 219', 219", 319, 319', 319", 319''', 424, 424', 424", 424''', 524, 524', 524", 524''' ‧ ‧ source Polar zone

221、321、321’、411、411’、413、511、511’、513‧‧‧注入區 221, 321, 321', 411, 411', 413, 511, 511', 513‧‧ ‧ injection area

300’‧‧‧暫態電壓抑制器 300'‧‧‧ Transient Voltage Suppressor

417‧‧‧電介質材料 417‧‧‧Dielectric materials

419‧‧‧多晶矽 419‧‧‧ Polysilicon

429、429’、529、529’‧‧‧接觸區 429, 429’, 529, 529’ ‧ ‧ contact areas

430、530、525、527‧‧‧絕緣層 430, 530, 525, 527‧‧‧ insulation

517‧‧‧氧化層 517‧‧‧Oxide layer

523A、523B、523C‧‧‧區 523A, 523B, 523C‧‧‧

530‧‧‧絕緣層 530‧‧‧Insulation

532‧‧‧金屬層 532‧‧‧metal layer

閱讀以下詳細說明並參照圖式之後，本發明的各個方面及優勢將顯而易見：圖1為傳統的暫態電壓抑制器(TVS)電路的電路圖，其中二極體陣列與雪崩二極體並聯。 The various aspects and advantages of the present invention will be apparent from the following detailed description and reference to the drawings. FIG. 1 is a circuit diagram of a conventional transient voltage suppressor (TVS) circuit in which a diode array is connected in parallel with an avalanche diode.

圖2A為依據原有技術，傳統暫態電壓抑制器(TVS)元件的剖面示意圖。 2A is a schematic cross-sectional view of a conventional transient voltage suppressor (TVS) component in accordance with the prior art.

圖2B為依據原有技術，一種可選暫態電壓抑制器(TVS)元件的剖面示意圖。 2B is a cross-sectional view of an optional transient voltage suppressor (TVS) component in accordance with the prior art.

圖3A為依據本發明的一個可選實施例，一種暫態電壓抑制器(TVS)元件的剖面示意圖。 3A is a cross-sectional view of a transient voltage suppressor (TVS) component in accordance with an alternative embodiment of the present invention.

圖3B為依據本發明的一個可選實施例，一種暫態電壓抑制器(TVS)元件的剖面示意圖。 3B is a cross-sectional view of a transient voltage suppressor (TVS) component in accordance with an alternative embodiment of the present invention.

圖3C為依據本發明的一個可選實施例，一種暫態電壓抑制器(TVS)元件的剖面示意圖。 3C is a cross-sectional view of a transient voltage suppressor (TVS) component in accordance with an alternative embodiment of the present invention.

圖3D為依據本發明的一個實施例，圖3C所示的暫態電壓抑制器增加了頂面絕緣層和相應的金屬墊，以形成電連接的剖面示意圖。 3D is a cross-sectional view of the transient voltage suppressor of FIG. 3C with the top insulating layer and the corresponding metal pad added to form an electrical connection, in accordance with an embodiment of the present invention.

圖4A-P為依據本發明的一個實施例，圖3D所示的TVS元件的製備方法。 4A-P are diagrams showing a method of fabricating the TVS element shown in Fig. 3D in accordance with an embodiment of the present invention.

以下結合附圖，進一步說明本發明的具體實施例。 Specific embodiments of the present invention are further described below in conjunction with the accompanying drawings.

引言 introduction

如圖2A所示，依據原有技術，一種傳統暫態電壓抑制器(TVS)元件200的剖面示意圖。這種傳統的TVS 200與圖1所示TVS 100的電路圖類似。 As shown in FIG. 2A, a schematic cross-sectional view of a conventional transient voltage suppressor (TVS) component 200 is provided in accordance with the prior art. This conventional TVS 200 is similar to the circuit diagram of the TVS 100 shown in FIG.

TVS 200形成在重摻雜p+半導體基板201上，p+半導體基板201承載輕p-摻雜第一外延層203以及更加輕p-摻雜的第二外延層209。由於第二外延層209的摻雜濃度對於高端導向二極體HSD和低端導向二極體LSD的電容有顯著作用，因此必須設置該層209的摻雜濃度盡可能的低(電容與摻雜濃度成正比)。由於導向二極體HSD、LSD與穩壓二極體並聯，因此導向二極體HSD、LSD的電容將對TVS 200的整體電容有很大的影響。無論穩壓二極體的電容大 或小，都可以使用導向二極體HSD、LSD的電容，將整體TVS電容有效地降低到所需值。 The TVS 200 is formed on a heavily doped p+ semiconductor substrate 201 carrying a light p-doped first epitaxial layer 203 and a lighter p-doped second epitaxial layer 209. Since the doping concentration of the second epitaxial layer 209 has a significant effect on the capacitance of the high-side guiding diode HSD and the low-side guiding diode LSD, it is necessary to set the doping concentration of the layer 209 as low as possible (capacitance and doping). The concentration is proportional to). Since the guiding diodes HSD and LSD are connected in parallel with the voltage stabilizing diode, the capacitance of the guiding diodes HSD and LSD will have a great influence on the overall capacitance of the TVS 200. No matter the capacitance of the regulator diode Or small, you can use the capacitance of the guiding diode HSD, LSD, effectively reduce the overall TVS capacitor to the required value.

形成在第一外延層203中的n+掩埋層205，用作高端導向二極體HSD的陰極。第一外延層203中n+掩埋層205下方的p+注入層207，被分成兩部分，在高端導向二極體HSD下方有一個縫隙，以避免高端導向二極體HSD下方的重摻雜層。穩壓二極體由n+掩埋層205、p+注入層207、第一外延層203以及p+基板201構成。N+掩埋層205構成穩壓二極體的陰極，p+注入層207、第一外延層203以及p+基板201共同構成穩壓二極體的陽極。製備一組絕緣溝槽211、211’、211”，使低端導向二極體LSD和集成穩壓二極體的高端導向二極體HSD絕緣。 The n+ buried layer 205 formed in the first epitaxial layer 203 serves as a cathode of the high side guiding diode HSD. The p+ implant layer 207 under the n+ buried layer 205 in the first epitaxial layer 203 is divided into two parts, and there is a gap under the high side guiding diode HSD to avoid the heavily doped layer under the high side guiding diode HSD. The voltage stabilizing diode is composed of an n+ buried layer 205, a p+ implanted layer 207, a first epitaxial layer 203, and a p+ substrate 201. The N+ buried layer 205 constitutes a cathode of the voltage stabilizing diode, and the p+ implant layer 207, the first epitaxial layer 203, and the p+ substrate 201 together constitute an anode of the voltage stabilizing diode. A set of insulating trenches 211, 211', 211" is prepared to insulate the low-side guiding diode LSD from the high-side guiding diode HSD of the integrated voltage stabilizing diode.

在第二外延層209中形成第一、第二和第三n+源極區219、219’、219”。如圖所示，第一和第二源極區219、219’分別位於第一絕緣溝槽211的右側壁和第二絕緣溝槽211’的左側壁附近。第三源極區219”位於第三絕緣溝槽211”的右側壁附近。垂直低端導向二極體LSD由第三源極區219”、第二外延層209、第一外延層203和基板201形成。第二外延層209、第一外延層203和基板201共同構成低端導向二極體LSD的陽極，第三源極區219”構成低端導向二極體LSD的陰極。低端導向二極體LSD的陽極藉由基板，電連接到穩壓二極體的陽極。 First, second, and third n+ source regions 219, 219', 219" are formed in the second epitaxial layer 209. As shown, the first and second source regions 219, 219' are respectively located in the first insulation The right side wall of the trench 211 and the left side wall of the second insulating trench 211'. The third source region 219" is located near the right side wall of the third insulating trench 211". The vertical low-end guiding diode LSD is third The source region 219", the second epitaxial layer 209, the first epitaxial layer 203, and the substrate 201 are formed. The second epitaxial layer 209, the first epitaxial layer 203 and the substrate 201 together form the anode of the low-end guiding diode LSD, and the third source region 219" constitutes the cathode of the low-end guiding diode LSD. The low-end guiding diode The anode of the LSD is electrically connected to the anode of the voltage stabilizing diode by a substrate.

形成在第二外延層209的頂層中，在第一和第二源極區219、219’之間的P+注入區221、第二外延層209以及n+掩埋層205構成高端導向二極體HSD。P+注入區221和第二外延層209共同構成高端導向HSD二極體的陽極，n+掩埋層205構成高端導向二極體HSD的陰極。高端導向二極體HSD的陰極藉由n+掩埋層205，電連接到穩壓二極體的陰極。 Formed in the top layer of the second epitaxial layer 209, the P+ implant region 221, the second epitaxial layer 209, and the n+ buried layer 205 between the first and second source regions 219, 219' constitute a high side via diode HSD. The P+ implant region 221 and the second epitaxial layer 209 together form the anode of the high-side guided HSD diode, and the n+ buried layer 205 constitutes the cathode of the high-side conductive diode HSD. The cathode of the high-side steering diode HSD is electrically connected to the cathode of the voltage stabilizing diode by an n+ buried layer 205.

此外，絕緣層(圖中沒有表示出)可以形成在第二外延層209上方，並在其中形成用於金屬接觸的開口。Vcc墊(圖中沒有表示出)可以藉由 絕緣層中的一個開口，連接到穩壓二極體上方的第二源極區219’。N-型沉降區217可以形成在第二源極區219’和n+掩埋層205之間，使穩壓二極體在元件200的頂面上形成連接。在反向模式下，n-型沉降區217作為PN結的一部分，可以用於改善正、負模式下N+源極到基板201的鉗位元性能。I/O墊(圖中沒有表示出)可以藉由絕緣層中的另一個開口，連接到p+注入區221(即高端導向二極體的陽極)。此外，第二I/O墊(圖中沒有表示出)可以藉由絕緣層中的另一個開口，連接到第三源極區219”(即低端導向二極體的陰極)。 Further, an insulating layer (not shown) may be formed over the second epitaxial layer 209 and an opening for metal contact is formed therein. Vcc pad (not shown) can be used An opening in the insulating layer is connected to the second source region 219' above the stabilizing diode. An N-type sinker region 217 may be formed between the second source region 219' and the n+ buried layer 205 such that the voltage stabilizing diode forms a connection on the top surface of the element 200. In the reverse mode, the n-type sinker region 217, as part of the PN junction, can be used to improve the clamper performance of the N+ source to the substrate 201 in the positive and negative modes. An I/O pad (not shown) can be connected to the p+ implant region 221 (i.e., the anode of the high side steering diode) by another opening in the insulating layer. In addition, a second I/O pad (not shown) may be connected to the third source region 219" (i.e., the cathode of the low-side guiding diode) by another opening in the insulating layer.

如圖所示，根據圖1所示的電路圖，傳統TVS 200的運行方式和功能如上所述。這種傳統的TVS 200具有多種必要的元件性能。其一，傳統的TVS 200位於p-型基板201上，允許基板作為接地端，有利於較為簡便地集成導向二極體HSD、LSD和穩壓二極體。此外，由於第二外延層209的輕摻雜以及導向二極體和穩壓二極體的垂直集成造成的小元件封裝尺寸，使得傳統的TVS 200具有低電容。 As shown, according to the circuit diagram shown in Fig. 1, the operation mode and function of the conventional TVS 200 are as described above. This conventional TVS 200 has a variety of necessary component capabilities. First, the conventional TVS 200 is located on the p-type substrate 201, allowing the substrate to serve as a grounding terminal, which facilitates the simple integration of the guiding diodes HSD, LSD, and voltage stabilizing diode. In addition, the conventional TVS 200 has a low capacitance due to the light doping of the second epitaxial layer 209 and the small component package size caused by the vertical integration of the guiding diode and the voltage stabilizing diode.

儘管傳統的TVS 200具有許多必須的元件性能，但是它仍然受到許多不良的元件性能影響，使其不盡理想。對於所有的TVS元件來說，為了給所連接的積體電路提供更好的保護，鉗位元電壓必須很低。TVS的鉗位元電壓與穩壓二極體的擊穿電壓成正比，因此受到穩壓二極體擊穿特性的局限。 Although the conventional TVS 200 has many necessary component performances, it is still affected by many poor component performance, making it less than ideal. For all TVS components, the clamp voltage must be low in order to provide better protection for the connected integrated circuit. The clamp voltage of the TVS is proportional to the breakdown voltage of the Zener diode and is therefore limited by the breakdown characteristics of the regulated diode.

穩壓二極體結處p+注入層207的摻雜濃度決定了穩壓二極體的擊穿電壓。雖然增大p+注入層的摻雜濃度會降低穩壓二極體的擊穿電壓，然而存在一個特定的閾值，進一步增大摻雜濃度將產生很大的反向漏電流，有可能對元件造成損壞。因此，在傳統的TVS 200中，很難配置擊穿電壓低於6V的穩壓二極體。對於許多要求Vcc為3V或更低的現有應用來說，這種TVS 200並不理想。因此，必須製備一種改進擊穿電壓和鉗位元電壓性能的TVS元件，同時保持傳統TVS 200的低電容和小元件封裝尺寸。 The doping concentration of the p+ implant layer 207 at the junction of the Zener diode determines the breakdown voltage of the Zener diode. Although increasing the doping concentration of the p+ implant layer lowers the breakdown voltage of the Zener diode, there is a specific threshold. Further increasing the doping concentration will generate a large reverse leakage current, which may cause components. damage. Therefore, in the conventional TVS 200, it is difficult to configure a voltage stabilizing diode having a breakdown voltage lower than 6V. For many existing applications requiring a Vcc of 3V or less, this TVS 200 is not ideal. Therefore, it is necessary to prepare a TVS component that improves the breakdown voltage and the clamp voltage performance while maintaining the low capacitance and small component package size of the conventional TVS 200.

可選TVS元件 Optional TVS components

在Lingpeng Guan等人共同指定的美國專利號8,698,196中，提出了具有改進擊穿電壓以及鉗位元電壓性能的TVS元件，特此引用其全文以作參考。所引的原有技術參考文獻所述的元件，藉由配置N-P-N結構，而非穩壓二極體，用作雪崩二極體，已經實現了改進擊穿電壓性能。圖2B表示這種TVS元件200’的示例。TVS元件200’形成在n+基板301上，而不是p+基板上，有利於N-P-N雪崩二極體的集成。形成在第一外延層303中的n+掩埋層305構成高端導向二極體HSD的陰極。第一外延層303中n+掩埋層305下方的p+注入層307，在n+掩埋層305上方水平延伸。雪崩二極體由n+掩埋層305、p+注入層307、第一外延層303和n+基板301構成。掩埋層305構成雪崩二極體的發射極，p+注入層307構成雪崩二極體的基極，第一外延層303和n+基板301共同構成雪崩二極體的集電極。 A TVS component having improved breakdown voltage and clamp voltage performance is set forth in U.S. Patent No. 8,698,196, the entire disclosure of which is incorporated herein by reference. The elements described in the prior art references have been improved in breakdown voltage performance by configuring an N-P-N structure instead of a voltage stabilizing diode for use as an avalanche diode. Figure 2B shows an example of such a TVS element 200'. The TVS element 200' is formed on the n+ substrate 301 instead of the p+ substrate, facilitating the integration of the N-P-N avalanche diode. The n+ buried layer 305 formed in the first epitaxial layer 303 constitutes the cathode of the high-end guiding diode HSD. The p+ implant layer 307 under the n+ buried layer 305 in the first epitaxial layer 303 extends horizontally above the n+ buried layer 305. The avalanche diode is composed of an n+ buried layer 305, a p+ implanted layer 307, a first epitaxial layer 303, and an n+ substrate 301. The buried layer 305 constitutes the emitter of the avalanche diode, and the p+ implant layer 307 constitutes the base of the avalanche diode. The first epitaxial layer 303 and the n+ substrate 301 together constitute the collector of the avalanche diode.

形成在第二外延層309和第一外延層303中的絕緣溝槽311、311’、311”，使低端導向二極體LSD與高端導向二極體HSD絕緣，高端導向二極體HSD與雪崩二極體集成在一起。第一、第二、第三和第四n+源極區319、319’、319”、319'''形成在第二外延層309中，如圖所示。可選n-型沉降區317可以形成在第二源極區319’和n+掩埋層305之間，使雪崩二極體在元件300的頂面上形成連接，在元件運行的正和負偏置模式下都能提高N+源極對基板301的鉗位。 在第二外延層309的頂部，形成一對p+注入區321、321’。高端二極體HSD由第一p+注入區321、第二外延層309和n+掩埋層305形成。第一p+注入區321和第二外延層309共同構成高端導向HSD二極體的陽極，n+掩埋層305構成高端導向二極體HSD的陰極。高端導向二極體HSD的陰極藉由n+掩埋層305，電連接到雪崩二極體的發射極。 The insulating trenches 311, 311', 311" formed in the second epitaxial layer 309 and the first epitaxial layer 303 insulate the low-side guiding diode LSD from the high-end guiding diode HSD, and the high-end guiding diode HSD and The avalanche diodes are integrated. The first, second, third and fourth n+ source regions 319, 319', 319", 319"' are formed in the second epitaxial layer 309 as shown. An optional n-type sinker region 317 can be formed between the second source region 319' and the n+ buried layer 305 such that the avalanche diode forms a connection on the top surface of the component 300, and the positive and negative bias modes of operation of the component The clamping of the N+ source to the substrate 301 can be improved. On top of the second epitaxial layer 309, a pair of p+ implant regions 321, 321' are formed. The high side diode HSD is formed by a first p+ implant region 321, a second epitaxial layer 309, and an n+ buried layer 305. The first p+ implant region 321 and the second epitaxial layer 309 together form the anode of the high side guided HSD diode, and the n+ buried layer 305 constitutes the cathode of the high side conductive diode HSD. The cathode of the high-side steering diode HSD is electrically connected to the emitter of the avalanche diode by an n+ buried layer 305.

低端導向二極體LSD由第三源極區319”、第二外延層309和第二p+注入區321’構成。第二p+注入區321’和第二外延層309共同構成低端導向二極體LSD的陽極，第三源極區319”構成低端導向二極體LSD的陰極。與圖 2A所示的原有技術中的低端導向二極體不同，該低端導向二極體LSD為水平集成，而不是垂直集成。然而，低端導向二極體LSD的水平集成並不會顯著增大元件的封裝尺寸，因此所發明的TVS 300仍然可以保持所需的小元件封裝尺寸。 The low-side guiding diode LSD is composed of a third source region 319", a second epitaxial layer 309 and a second p+ implant region 321'. The second p+ implant region 321' and the second epitaxial layer 309 together form a low-end guide two The anode of the polar body LSD, the third source region 319" constitutes the cathode of the low-end guiding diode LSD. And figure Unlike the low-end steering diodes of the prior art shown in FIG. 2A, the low-end guiding diode LSD is horizontally integrated rather than vertically integrated. However, the horizontal integration of the low-side guiding diode LSD does not significantly increase the package size of the component, so the inventive TVS 300 can still maintain the required small component package size.

雪崩二極體(例如N-P-N結構)的運行方式與傳統TVS 200中穩壓二極體的運行方式不同。傳統TVS 200中穩壓二極體的擊穿，取決於p+注入區的摻雜濃度，並且受到反向漏電流等問題的局限。TVS 200’中雪崩二極體的擊穿電壓取決於P-N結(也就是P+注入層307和N+掩埋層305之間的結)的擊穿電壓以及N-P-N結構的增益。雪崩二極體的擊穿電壓與P-N結的擊穿電壓成正比，與N-P-N結構的增益成反比。因此，p+注入層307的摻雜濃度保持在防止反向漏電流所需的水平上，同時調節N-P-N結構的增益，以獲得所需的TVS擊穿電壓。N-P-N結構的增益取決於基極的厚度，在這種情況下，基極為p+注入層307。藉由增大該p+注入層307的厚度和摻雜濃度，還可以有效降低TVS的擊穿電壓。因此，藉由減小p+注入層307的厚度，TVS的擊穿電壓可以降至6V一下，以便實現廣泛應用。由於TVS的鉗位元電壓與擊穿電壓關係密切，因此調節雪崩二極體的增益(即減小p+注入層307的厚度)，還可以有效降低TVS的鉗位元電壓。 Avalanche diodes (such as N-P-N structures) operate differently than conventional regulators in TVS 200. The breakdown of the Zener diode in the conventional TVS 200 depends on the doping concentration of the p+ implant region and is limited by problems such as reverse leakage current. The breakdown voltage of the avalanche diode in the TVS 200' depends on the breakdown voltage of the P-N junction (i.e., the junction between the P+ implant layer 307 and the N+ buried layer 305) and the gain of the N-P-N structure. The breakdown voltage of the avalanche diode is proportional to the breakdown voltage of the P-N junction and inversely proportional to the gain of the N-P-N structure. Therefore, the doping concentration of the p+ implant layer 307 is maintained at a level required to prevent reverse leakage current while adjusting the gain of the N-P-N structure to obtain a desired TVS breakdown voltage. The gain of the N-P-N structure depends on the thickness of the base, in which case the base is extremely p+ implanted in layer 307. By increasing the thickness and doping concentration of the p+ implant layer 307, the breakdown voltage of the TVS can also be effectively reduced. Therefore, by reducing the thickness of the p+ implant layer 307, the breakdown voltage of the TVS can be lowered to 6V for a wide range of applications. Since the clamp voltage of the TVS is closely related to the breakdown voltage, adjusting the gain of the avalanche diode (ie, reducing the thickness of the p+ implant layer 307) can also effectively lower the clamp voltage of the TVS.

TVS元件200’保留了上一代產品的低電容和小元件封裝。藉由將N-P-N結構代替穩壓二極體集成在TVS中，可以將TVS的擊穿電壓降至6V。 從而使鉗位元電壓降至所需水平，而不會產生不良的反向漏電流。此外，利用上述技術，這樣的TVS保留了原有技術元件200的低電容和小元件封裝。美國專利8,698,196提出的集成N-P-N雪崩二極體的TVS儘管如上所述改善了性能特徵，但是仍然繼續按照圖1所示的電路圖運行和工作。 The TVS component 200' retains the low capacitance and small component packages of the previous generation. By integrating the N-P-N structure in place of the regulated diode in the TVS, the breakdown voltage of the TVS can be reduced to 6V. Thereby the clamp voltage is reduced to the desired level without causing undesirable reverse leakage current. Moreover, with the above techniques, such TVS retains the low capacitance and small component packages of the prior art component 200. The TVS integrated with the N-P-N avalanche diode proposed by U.S. Patent No. 8,698,196, while improving the performance characteristics as described above, continues to operate and operate in accordance with the circuit diagram shown in FIG.

然而美國專利8,698,196提出的TVS元件的暫態電壓抑制器類型，仍然局限於雪崩擊穿機制。原有技術元件的擊穿電壓無法降至6V以下。此外，這種元件無法控制突返，其中擊穿提供了充足的基極電流，可接通電晶體。而 且，原有技術的TVS元件的製備方法很難控制擊穿機制結構所使用的摻雜結構層。因此，有必要設計一種擊穿電壓較低的元件，而且其中突返現象可以單獨控制。 However, the type of transient voltage suppressor for TVS components proposed in U.S. Patent No. 8,698,196 is still limited to the avalanche breakdown mechanism. The breakdown voltage of the original technology components cannot be reduced to below 6V. In addition, such components are unable to control the flashback, where the breakdown provides sufficient base current to turn the transistor on. and Moreover, the preparation method of the prior art TVS device is difficult to control the doped structural layer used in the breakdown mechanism structure. Therefore, it is necessary to design a component with a low breakdown voltage, and the phenomenon of the reentry can be controlled separately.

正是在這樣的背景下，提出了本發明的各個方面。 It is against this background that various aspects of the invention have been presented.

小擊穿電壓的TVS元件 Small breakdown voltage TVS components

為了設計一種擊穿電壓較低的元件，而且其中突返現象可以單獨控制，在本發明的實施例中使用了一種擊穿的穿通模式。這種擊穿模式可以使用非常低的摻雜濃度和非常窄的摻雜結構實現。 In order to design an element having a lower breakdown voltage, and in which the reentry phenomenon can be controlled separately, a punch-through mode is used in the embodiment of the present invention. This breakdown mode can be achieved using very low doping concentrations and very narrow doping structures.

圖3A所示的TVS 300具有比美國專利8.698,196中所述的TVS更優的元件性能特徵。除了初始的N-P-N雪崩二極體結構之外，還集成了穿通N-P-N結構，利用上述技術，TVS 300的擊穿電壓可以降至3-5V之間。從而將鉗位元電壓降至所需水平，而不會產生不良的反向漏電流。此外，TVS 300保留了上述原有技術元件的低電容和小元件封裝。TVS 300儘管如上所述改善了性能特徵，但是仍然繼續按照圖1所示的電路圖運行和工作。 The TVS 300 shown in Figure 3A has better component performance characteristics than the TVS described in U.S. Patent No. 8.698,196. In addition to the initial N-P-N avalanche diode structure, a punch-through N-P-N structure is integrated, and with the above technique, the breakdown voltage of the TVS 300 can be reduced to between 3-5V. This reduces the clamp voltage to the desired level without producing a bad reverse leakage current. In addition, the TVS 300 retains the low capacitance and small component packages of the prior art components described above. Although the TVS 300 improves performance characteristics as described above, it continues to operate and operate in accordance with the circuit diagram shown in FIG.

圖3A-3D表示依據本發明的各個方面，暫態電壓抑制器(TVS)元件的剖面示意圖。配置這些TVS元件，提供低電容和小元件封裝尺寸，利用穿通模式、以及突返控制之外，還進一步改進擊穿電壓。在圖3A-3D所示類型的元件中，發生穿通的電壓比藉由正向偏置二極體HSD2的HSD建立的雪崩二極體更低。當電壓升至雪崩擊穿以上時，雪崩二極體接通並控制突返。穿通模式在旁邊運行，雖然圖3A-3D所示的TVS元件基本按照圖1所示的上述TVS 100工作，但是還額外提供了穿通模式，用於較低電壓的擊穿。穿通NPN提供較低的TVS擊穿電壓(3-5V)，初始的NPN雪崩二極體控制突返，因此TVS 300元件的設計允許獨立控制擊穿電壓和突返，這是一項很大的優勢，TVS結構200和200’無法實現。 3A-3D are cross-sectional views of a transient voltage suppressor (TVS) component in accordance with various aspects of the present invention. These TVS components are configured to provide low capacitance and small component package sizes, using punch-through mode and flashback control to further improve breakdown voltage. In the components of the type shown in Figures 3A-3D, the punch-through voltage is lower than the avalanche diode established by the HSD of the forward biased diode HSD2. When the voltage rises above the avalanche breakdown, the avalanche diode turns on and controls the sudden return. The feedthrough mode operates sideways, although the TVS components shown in Figures 3A-3D operate substantially in accordance with the aforementioned TVS 100 shown in Figure 1, but additionally provide a feedthrough mode for lower voltage breakdown. Through-pass NPN provides a lower TVS breakdown voltage (3-5V), and the initial NPN avalanche diode controls the sudden return, so the design of the TVS 300 component allows independent control of breakdown voltage and reciprocation, which is a large Advantages, TVS structures 200 and 200' are not possible.

在圖3A中，TVS元件300形成在第一導電類型的重摻雜半導體基板401上，重摻雜半導體基板承載第一外延層403和第二外延層409。在本說明中，半導體基板401可以是n+基板；然而本發明的各個方面並不局限於這種配置。為了集成雪崩二極體作為N-P-N結構，而不是P-N二極體，可以使用n+基板401，而不是p+基板。N-P-N結構具有特定的性能特徵，用在TVS中比P-N二極體更佔優勢。這些優勢將在下文中詳細介紹。此後，N-P-N結構將被稱為雪崩二極體。 In FIG. 3A, the TVS element 300 is formed on a heavily doped semiconductor substrate 401 of a first conductivity type, and the heavily doped semiconductor substrate carries a first epitaxial layer 403 and a second epitaxial layer 409. In the present description, the semiconductor substrate 401 may be an n+ substrate; however, aspects of the present invention are not limited to this configuration. In order to integrate the avalanche diode as an N-P-N structure instead of a P-N diode, an n+ substrate 401 may be used instead of a p+ substrate. The N-P-N structure has specific performance characteristics and is more dominant in TVS than P-N diodes. These advantages will be described in detail below. Thereafter, the N-P-N structure will be referred to as an avalanche diode.

第一外延層403為輕摻雜n-層。該第一外延層403可以摻雜濃度為2×1016/cm3數量級的磷。第二外延層409為極輕摻雜n-層。該第二外延層409可以摻雜硼，其最小摻雜濃度為1014/cm3數量級或更低。由於第二外延層409的摻雜濃度對高端導向二極體HSD和低端導向二極體LSD的電容有顯著影響，因此必須使該層409的摻雜濃度盡可能地低。由於導向二極體HSD、LSD並聯到雪崩二極體上，因此導向二極體HSD、LSD的電容將顯著影響TVS 300的整體電容。無論雪崩二極體的電容大或小，都可以使用導向二極體HSD、LSD的電容，將整體TVS 300的電容有效地降低到所需值。 The first epitaxial layer 403 is a lightly doped n-layer. The first epitaxial layer 403 may be doped with phosphorus having a concentration of the order of 2 × 10 16 /cm 3 . The second epitaxial layer 409 is an extremely lightly doped n-layer. The second epitaxial layer 409 may be doped with boron having a minimum doping concentration of the order of 10 14 /cm 3 or less. Since the doping concentration of the second epitaxial layer 409 has a significant influence on the capacitance of the high side guiding diode HSD and the low side guiding diode LSD, the doping concentration of the layer 409 must be made as low as possible. Since the guiding diodes HSD and LSD are connected in parallel to the avalanche diode, the capacitance of the guiding diodes HSD and LSD will significantly affect the overall capacitance of the TVS 300. Regardless of whether the capacitance of the avalanche diode is large or small, the capacitance of the diodes HSD and LSD can be used to effectively reduce the capacitance of the overall TVS 300 to a desired value.

在圖3A所示的示例中，n+掩埋層405形成在第一外延層403中。 該n+掩埋層405構成高端導向二極體HSD的陰極，這將在下文中詳細介紹。此外，在圖3A所示的TVS示例中，在第一外延層403中n+掩埋層405下方，注入p+注入層407。P+注入層407在n+掩埋層405上方水平延伸。雪崩二極體由n+掩埋層405、p+注入層407、第一外延層403和n+基板401構成。掩埋層405構成雪崩二極體的發射極，p+注入層407構成雪崩二極體的基極，第一外延層403和n+基板401共同構成雪崩二極體的集電極。 In the example shown in FIG. 3A, an n+ buried layer 405 is formed in the first epitaxial layer 403. The n+ buried layer 405 constitutes the cathode of the high side steering diode HSD, which will be described in detail below. Further, in the TVS example shown in FIG. 3A, a p+ implant layer 407 is implanted under the n+ buried layer 405 in the first epitaxial layer 403. The P+ implant layer 407 extends horizontally above the n+ buried layer 405. The avalanche diode is composed of an n+ buried layer 405, a p+ implanted layer 407, a first epitaxial layer 403, and an n+ substrate 401. The buried layer 405 constitutes the emitter of the avalanche diode, and the p+ implant layer 407 constitutes the base of the avalanche diode. The first epitaxial layer 403 and the n+ substrate 401 together constitute the collector of the avalanche diode.

TVS 300中的雪崩二極體(即N-P-N結構)的工作方式不同于傳統TVS 200中的穩壓二極體。然而，傳統TVS 200中穩壓二極體的擊穿電壓行為僅僅取決於p+注入區的摻雜濃度，並且受到反向漏電流問題的局限，所發明 的TVS 300中雪崩二極體的擊穿電壓使自己更加靈活。雪崩二極體的擊穿電壓取決於兩個不同的因數：P-N結(即P+注入層407和N+掩埋層405之間的結)的擊穿電壓以及N-P-N結構的增益。雪崩二極體的擊穿電壓與P-N結的擊穿電壓成正比，與N-P-N結構的增益成反比。因此，p+注入層407的摻雜濃度保持在防止反向漏電流所需的水平，同時調節N-P-N的增益，以獲得所需的TVS擊穿電壓。N-P-N的增益取決於基極的厚度，在這種情況下基極為p+注入層407。 藉由減小p+注入層407的厚度，也可以有效降低TVS的擊穿電壓。因此，藉由減小p+注入層407的厚度，TVS的擊穿電壓可以降至6V，以便廣泛應用。由於TVS的鉗位元電壓與擊穿電壓關係密切，因此調節雪崩二極體的增益(即減小p+注入層407的厚度)，還可以有效降低TVS的鉗位元電壓。 The avalanche diode (ie, the N-P-N structure) in the TVS 300 operates differently than the regulated diode in the conventional TVS 200. However, the breakdown voltage behavior of the regulator diode in the conventional TVS 200 depends only on the doping concentration of the p+ implant region, and is limited by the problem of reverse leakage current. The breakdown voltage of the avalanche diode in the TVS 300 makes it more flexible. The breakdown voltage of the avalanche diode depends on two different factors: the breakdown voltage of the P-N junction (ie, the junction between the P+ implant layer 407 and the N+ buried layer 405) and the gain of the N-P-N structure. The breakdown voltage of the avalanche diode is proportional to the breakdown voltage of the P-N junction and inversely proportional to the gain of the N-P-N structure. Therefore, the doping concentration of the p+ implant layer 407 is maintained at a level required to prevent reverse leakage current while adjusting the gain of N-P-N to obtain a desired TVS breakdown voltage. The gain of N-P-N depends on the thickness of the base, in which case the base is extremely p+ implanted 407. By reducing the thickness of the p+ implant layer 407, the breakdown voltage of the TVS can also be effectively reduced. Therefore, by reducing the thickness of the p+ implant layer 407, the breakdown voltage of the TVS can be lowered to 6V for wide application. Since the clamp voltage of the TVS is closely related to the breakdown voltage, adjusting the gain of the avalanche diode (ie, reducing the thickness of the p+ implant layer 407) can also effectively lower the clamp voltage of the TVS.

在第二外延層409和第一外延層403中製備一組絕緣溝槽415、415’、415”，並用電介質材料417(例如氧化矽)填充。配置絕緣溝槽415、415’、415”，使低端導向二極體LSD和高端導向二極體HSD絕緣，高端導向二極體HSD與雪崩二極體集成在一起。第一絕緣溝槽415靠近位於N+掩埋層405的邊緣和p+注入層407的邊緣。第二絕緣溝槽415’位於靠近N+掩埋層405的另一邊緣，並且延伸到p+注入層407中。第三絕緣溝槽415”位於靠近p+注入層407的另一邊緣。 A set of insulating trenches 415, 415', 415" are prepared in the second epitaxial layer 409 and the first epitaxial layer 403 and filled with a dielectric material 417 (eg, hafnium oxide). The insulating trenches 415, 415', 415" are disposed, The low-side guiding diode LSD and the high-end guiding diode HSD are insulated, and the high-end guiding diode HSD is integrated with the avalanche diode. The first insulating trench 415 is adjacent to the edge of the N+ buried layer 405 and the edge of the p+ implant layer 407. The second insulating trench 415' is located adjacent the other edge of the N+ buried layer 405 and extends into the p+ implant layer 407. The third insulating trench 415" is located near the other edge of the p+ implant layer 407.

在第二外延層409中製備一組n+源極區424、424’、424”、424'''。 如上所述，第一源極區424位於第一絕緣溝槽415左側。第二源極區424’位於第一絕緣溝槽415和第二絕緣溝槽415’之間。第三源極區424”位於第二絕緣溝槽415’和第三絕緣溝槽415”之間。第四源極區424'''位於第三絕緣溝槽311”的右側壁附近。 A set of n+ source regions 424, 424', 424", 424"' are prepared in the second epitaxial layer 409. As described above, the first source region 424 is located on the left side of the first insulating trench 415. The second source region 424' is located between the first insulating trench 415 and the second insulating trench 415'. The third source region 424" is located between the second insulating trench 415' and the third insulating trench 415". The fourth source region 424"" is located near the right side wall of the third insulating trench 311".

在第二外延層409的頂層中製備一對p+注入區411、411’。第一p+注入區411位於第二和第三源極區424’、424”之間。第二p+注入區411’位於第三絕緣溝槽415”的左側壁附近。 A pair of p+ implant regions 411, 411' are prepared in the top layer of the second epitaxial layer 409. The first p+ implant region 411 is located between the second and third source regions 424', 424". The second p+ implant region 411' is located adjacent the left side wall of the third insulating trench 415".

穿通p注入區413形成在第二外延層409的頂層中。穿通p注入區413位於第一絕緣溝槽415的左側壁附近以及第一源極區424下方。隨著穿通p-區413的摻雜分佈減小，耗盡區增大。如果穿通p-區413的摻雜濃度足夠低，並且在垂直方向上足夠窄，那麼由於電場可以輕鬆穿通N-第二外延層409和N+源極區424之間的穿通p-區，就可以很輕鬆地應用穿通模式。因此，藉由減小p+注入層413的厚度和摻雜濃度，TVS的擊穿電壓可以降至5V，以實現廣泛應用。 A punch-through p implantation region 413 is formed in the top layer of the second epitaxial layer 409. The through p implantation region 413 is located near the left side wall of the first insulating trench 415 and below the first source region 424. As the doping profile of the punch-through p-region 413 decreases, the depletion region increases. If the doping concentration of the through-p-region 413 is sufficiently low and sufficiently narrow in the vertical direction, since the electric field can easily pass through the through-p-region between the N-second epitaxial layer 409 and the N+ source region 424, It is easy to apply the punch through mode. Therefore, by reducing the thickness and doping concentration of the p+ implant layer 413, the breakdown voltage of the TVS can be lowered to 5V for a wide range of applications.

高端二極體HSD由第一p+注入區411、第二外延層409和n+掩埋層405構成。第一p+注入區411和第二外延層409共同構成高端導向二極體HSD的陽極，n+掩埋層405構成高端導向二極體HSD的陰極。高端導向二極體HSD的陰極藉由n+掩埋層405，電連接到雪崩二極體的發射極。 The high side diode HSD is composed of a first p+ implant region 411, a second epitaxial layer 409, and an n+ buried layer 405. The first p+ implant region 411 and the second epitaxial layer 409 together form the anode of the high side steering diode HSD, and the n+ buried layer 405 constitutes the cathode of the high side steering diode HSD. The cathode of the high-side steering diode HSD is electrically connected to the emitter of the avalanche diode by an n+ buried layer 405.

低端導向二極體LSD由第三源極區424”、第二外延層409和第二p+注入區411’構成。第二p+注入區411’和第二外延層409共同構成低端導向二極體LSD的陽極，第三源極區424”構成低端導向二極體LSD的陰極。與圖2A所示的原有技術中的低端導向二極體不同，該低端導向二極體LSD水平集成，而不是垂直集成。然而，低端導向二極體LSD的水平集成並不會顯著影響元件的封裝尺寸，因此所發明的TVS 300仍然可以保持所需的小元件封裝尺寸。 The low-side guiding diode LSD is composed of a third source region 424", a second epitaxial layer 409 and a second p+ implant region 411'. The second p+ implant region 411' and the second epitaxial layer 409 together form a low-end guide The anode of the polar body LSD, the third source region 424" constitutes the cathode of the low-end guiding diode LSD. Unlike the low-end steering diodes of the prior art shown in FIG. 2A, the low-end guiding diode LSD is horizontally integrated rather than vertically integrated. However, the horizontal integration of the low-side guiding diode LSD does not significantly affect the package size of the component, so the inventive TVS 300 can still maintain the required small component package size.

第二水平高端PN二極體(HSD 2)由第一注入區411、第二外延層409和第二源極區424’構成。第一注入區411和第二外延層409共同構成第二水平二極體HSD2的陽極，第二源極區424’構成水平高端二極體(HSD 2)的陰極。 The second horizontal high side PN diode (HSD 2) is composed of a first implantation region 411, a second epitaxial layer 409, and a second source region 424'. The first implantation region 411 and the second epitaxial layer 409 together constitute the anode of the second horizontal diode HSD2, and the second source region 424' constitutes the cathode of the horizontal high-end diode (HSD 2).

穿通結構由第一源極區424、穿通p注入區413和第二外延層409構成。一個N-沉降結構423形成在第三絕緣溝槽415”的右側壁附近，以便提供連接基板401和地電勢的電路。此外，p+接觸區429和429”分別由p+注入區411和411’構成。 The feedthrough structure is composed of a first source region 424, a through p implant region 413, and a second epitaxial layer 409. An N-sink structure 423 is formed adjacent the right side wall of the third insulating trench 415" to provide a circuit for connecting the substrate 401 and the ground potential. Further, the p+ contact regions 429 and 429" are composed of p+ implant regions 411 and 411', respectively. .

此外，絕緣層430形成在第二外延層409上方，開口形成在其中，提供到TVS元件300零部件的金屬接頭。絕緣層430包括，例如含有硼酸的矽玻璃(BPSG)，形成在低溫氧化物(LTO)上方。由導電層(圖中沒有表示出)形成在I/O墊，可藉由絕緣層中的一個開口，連接到p+接觸區429和p+注入區411(即高端導向二極體的陽極)。此外，構成I/O墊的導電層可藉由絕緣層中的另一個開口，連接到第三源極區424”(即低端導向二極體的陰極)。此外，由導電層(圖中沒有表示出)形成的GND墊，可藉由絕緣層430中的另一個開口，連接到第二注入區411’和第四源極區424'''。 Further, an insulating layer 430 is formed over the second epitaxial layer 409, and an opening is formed therein to provide a metal joint to the components of the TVS element 300. The insulating layer 430 includes, for example, bismuth glass (BPSG) containing boric acid, formed over the low temperature oxide (LTO). A conductive layer (not shown) is formed on the I/O pad and can be connected to the p+ contact region 429 and the p+ implant region 411 (i.e., the anode of the high side via diode) by an opening in the insulating layer. In addition, the conductive layer constituting the I/O pad may be connected to the third source region 424" (ie, the cathode of the low-end guiding diode) by another opening in the insulating layer. Further, the conductive layer (in the figure) The GND pad formed, not shown, may be connected to the second implant region 411' and the fourth source region 424'" by another opening in the insulating layer 430.

圖3B-3D表示按照圖3A上述暫態電壓抑制器(TVS)元件的可選實施例。為了簡化，圖3B-3D中沒有表示出絕緣層430。 Figures 3B-3D illustrate an alternate embodiment of the transient voltage suppressor (TVS) component described above in accordance with Figure 3A. For the sake of simplicity, the insulating layer 430 is not shown in FIGS. 3B-3D.

圖3B表示依據本發明的可選方法，暫態電壓抑制器(TVS)元件300’。TVS 300’除了在每個絕緣溝槽415、415’、415”中增加多晶矽填充物419之外，還保留了與圖3A所示的TVS 300相同的結構。首先，每個絕緣溝槽415、415’、415”都內襯一個電介質417(例如氧化物)薄層，剩餘部分基本用多晶矽419填充。用多晶矽419，而不是氧化物填充溝槽415、415’、415”的過程，極大地簡化了製備製程。用氧化物內襯溝槽，用多晶矽填充溝槽，比用氧化物填充溝槽更加簡單，並且避免了在最終結構中引入高應力的複雜製程。 Figure 3B shows an alternative method, a transient voltage suppressor (TVS) component 300', in accordance with the present invention. The TVS 300' retains the same structure as the TVS 300 shown in Fig. 3A except that the polysilicon fill 419 is added to each of the insulating trenches 415, 415', 415". First, each of the insulating trenches 415, Both 415', 415" are lined with a thin layer of dielectric 417 (e.g., oxide) and the remainder is substantially filled with polysilicon 419. The process of filling the trenches 415, 415', 415" with polysilicon 419 instead of oxide greatly simplifies the fabrication process. The trench is filled with oxide, and the trench is filled with polysilicon, which is more than filling the trench with oxide. It is simple and avoids the complicated process of introducing high stress into the final structure.

圖3C表示依據本發明的另一個可選方面，暫態電壓抑制器(TVS)元件300”的剖面示意圖。TVS300”除了增加p-沉降區421和421’從第二外延層409開始延伸穿過第一外延層403之外，還保留了與圖3A所示的TVS 300’相同的結構。P-沉降區421位於第二外延層409和第一外延層403中，在穿通p注入區413下方以及第一絕緣溝槽415的左側壁附近。P-沉降區421’位於第二外延層409和第一外延層403中，第三絕緣溝槽415”的右側壁附近。P-沉降區421和421’在p+注入層407中終止。這些沉降區421和421’用於將p+注入層連接到接 地端，以防洩露。該TVS 300”繼續按照圖1所示的電路圖工作和運行，但是還提供一個穿通模式，用於在較低電壓下擊穿。 3C shows a cross-sectional view of a transient voltage suppressor (TVS) device 300" in accordance with another alternative aspect of the present invention. The TVS 300" extends through the second epitaxial layer 409 except that the p-sink regions 421 and 421' are added. In addition to the first epitaxial layer 403, the same structure as the TVS 300' shown in Fig. 3A is retained. The P-sinking region 421 is located in the second epitaxial layer 409 and the first epitaxial layer 403, below the through-p implant region 413 and near the left side wall of the first insulating trench 415. The P-sinking zone 421' is located in the second epitaxial layer 409 and the first epitaxial layer 403, near the right side wall of the third insulating trench 415". The P-sinking regions 421 and 421' terminate in the p+ implanted layer 407. These sedimentation Zones 421 and 421' are used to connect the p+ injection layer to the Ground to prevent leakage. The TVS 300" continues to operate and operate in accordance with the circuit diagram shown in Figure 1, but also provides a feedthrough mode for breakdown at lower voltages.

圖3D表示依據本發明的另一方面，暫態電壓抑制器300'''的剖面示意圖。暫態電壓抑制器300'''與圖3B基本類似，具有填充的絕緣溝槽，但是增加了圖3C所示的p-沉降區421和421’。 3D shows a cross-sectional view of a transient voltage suppressor 300"" in accordance with another aspect of the present invention. Transient voltage suppressor 300"" is substantially similar to Figure 3B, with filled insulating trenches, but with the addition of p-sinking regions 421 and 421' shown in Figure 3C.

圖4A-4N表示上述圖3D所示TVS元件的製備方法。雖然，示意圖和說明僅針對圖3D所示的TVS元件，但是本領域的技術人員應理解該製備方法藉由額外的標準處理製程，就可輕鬆擴展至上述任意TVS元件。還應注意，雖然為了簡便僅表示出了一個單獨的元件，但是本領域的技術人員應理解圖4A-4N所示的製備製程也可用於元件晶胞中排布多個這種元件的積體電路。 此外，雖然以下示例中提供的是特定導電類型的材料，但是本領域的技術人員應理解導電類型可以互換，摻雜濃度可以與典型示例中的濃度不同。 4A-4N show the preparation method of the TVS element shown in Fig. 3D above. Although the schematic and illustration are directed only to the TVS component shown in FIG. 3D, those skilled in the art will appreciate that the fabrication method can be easily extended to any of the above TVS components by an additional standard processing process. It should also be noted that although only a single component has been shown for simplicity, those skilled in the art will appreciate that the fabrication process illustrated in Figures 4A-4N can also be used to arrange a plurality of such components in a unit cell. Circuit. Further, although materials of a specific conductivity type are provided in the following examples, those skilled in the art will appreciate that the conductivity types may be interchanged, and the doping concentration may be different from that in the typical example.

如圖4A所示，TVS元件從第一導電類型的基板501(例如矽晶圓)開始。在圖4A-4N所示的TVS元件中，所使用的基板為n+型基板。這是與大多數TVS元件所使用的p+型基板作對比。第一外延層503生長在n+型基板501上方，如圖4B所示。第一外延層503可以是輕摻雜n-型外延層。第一外延層503和n+基板503將共同構成N-P-N元件的集電極。 As shown in FIG. 4A, the TVS element begins with a substrate 501 of a first conductivity type, such as a germanium wafer. In the TVS element shown in FIGS. 4A-4N, the substrate used is an n+ type substrate. This is in contrast to the p+ type substrate used in most TVS components. The first epitaxial layer 503 is grown over the n+ type substrate 501 as shown in FIG. 4B. The first epitaxial layer 503 can be a lightly doped n-type epitaxial layer. The first epitaxial layer 503 and the n+ substrate 503 will collectively constitute the collector of the N-P-N device.

如圖4C所示，隨後進行帶掩膜的注入(掩膜沒有表示出)，形成一個n+掩埋層505。該n+掩埋層505之後將作為高端導向二極體HSD的陰極，以及N-P-N雪崩二極體的發射極。N+掩埋層505僅沿第一外延層的一部分長度延伸。 As shown in Fig. 4C, a masked implant is then performed (the mask is not shown) to form an n+ buried layer 505. The n+ buried layer 505 will then serve as the cathode for the high side steering diode HSD and the emitter of the N-P-N avalanche diode. The N+ buried layer 505 extends only along a portion of the length of the first epitaxial layer.

然後，進行另一次帶掩膜的注入(掩膜沒有表示出)，形成一個p+注入層507。該p+注入層507之後將作為N-P-N雪崩二極體的基極。該p+注入層507在n+掩埋層505的長度上方延伸，以便防止低端導向二極體LSD短路。 在n+注入之後進行p+注入，其原因在於需要使用較高能量的注入才能獲得想要的結果。 Then, another implantation with a mask (not shown) is performed to form a p+ implant layer 507. The p+ implant layer 507 will then serve as the base of the N-P-N avalanche diode. The p+ implant layer 507 extends over the length of the n+ buried layer 505 to prevent shorting of the low side lead diode LSD. The p+ implant is performed after the n+ implant because the higher energy injection is required to obtain the desired result.

在圖4E中，在第一外延層503上方生長一個第二外延層509。 第二外延層509可以是輕摻雜n-外延層。如上所述，第二外延層509的摻雜濃度顯然會控制導向二極體的電容，因此必須使摻雜濃度達到最小，才能獲得很低的元件電容。此外，該第二外延層之後將作為N-P-N穿通結構的發射極。 In FIG. 4E, a second epitaxial layer 509 is grown over the first epitaxial layer 503. The second epitaxial layer 509 can be a lightly doped n- epitaxial layer. As described above, the doping concentration of the second epitaxial layer 509 obviously controls the capacitance of the guiding diode, so the doping concentration must be minimized to obtain a very low component capacitance. In addition, the second epitaxial layer will then serve as the emitter of the N-P-N punch-through structure.

如圖4F所示，在第二外延層509的頂面中，利用掩膜(掩膜沒有表示出)注入一對p+注入區511、511’。第一p+注入區511和第二外延層509共同構成垂直高端導向二極體HSD的陽極和第二水平二極體HSD2的陽極，同時n+掩埋層505構成垂直高端導向二極體HSD的陰極。第二p+注入區511’和第二外延層509構成水平低端導向二極體LSD的陽極。 As shown in Fig. 4F, in the top surface of the second epitaxial layer 509, a pair of p+ implant regions 511, 511' are implanted by a mask (not shown). The first p+ implant region 511 and the second epitaxial layer 509 together form the anode of the vertical high side steering diode HSD and the anode of the second horizontal diode HSD2, while the n+ buried layer 505 constitutes the cathode of the vertical high side steering diode HSD. The second p+ implant region 511' and the second epitaxial layer 509 form the anode of the horizontal low end via diode LSD.

如圖4G所示，在第二外延層509的頂面中，利用掩膜(掩膜沒有表示出)注入一個穿通p注入區513。藉由控制穿通p-注入513的深度和摻雜濃度，可以控制穿通結構的擊穿電壓。注入深度可以藉由調節注入能量來控制。 注入能量越大，注入深度越深。摻雜濃度可以藉由控制注入離子的劑量來調節。 離子劑量越大，摻雜濃度就越大。降低摻雜濃度和/或減小穿通p-注入區的厚度，可降低穿通擊穿電壓，從而降低TVS擊穿電壓。分開完成的兩個p+注入511、511’可以在同一時間進行。作為示例，但不作為局限，兩個p+注入511、511’可以在600KeV左右的能量下，用3×1011/cm2的劑量完成。作為對比，穿通p-注入513可以在稍高的能量下，例如660KeV，根據所需的TVS擊穿電壓，用5×1011/cm2-8×1011/cm2的劑量完成。 As shown in FIG. 4G, in the top surface of the second epitaxial layer 509, a punch-through p-implantation region 513 is implanted using a mask (not shown). The breakdown voltage of the feedthrough structure can be controlled by controlling the depth and doping concentration of the through p-injection 513. The depth of implantation can be controlled by adjusting the implantation energy. The greater the injection energy, the deeper the injection depth. The doping concentration can be adjusted by controlling the dose of the implanted ions. The larger the ion dose, the greater the doping concentration. Reducing the doping concentration and/or reducing the thickness of the through-p- implanted region reduces the punch-through breakdown voltage, thereby reducing the TVS breakdown voltage. The two p+ injections 511, 511' that are completed separately can be performed at the same time. By way of example, but not by way of limitation, the two p+ implants 511, 511' can be completed with a dose of 3 x 10 11 /cm 2 at an energy of around 600 KeV. In contrast, the punch-through p-injection 513 can be performed at a slightly higher energy, such as 660 keV, depending on the desired TVS breakdown voltage, with a dose of 5 x 10 11 /cm 2 -8 x 10 11 /cm 2 .

如圖4H所示，在第一外延層503和第二外延層509中，形成一組三個絕緣溝槽515、515’和515”。絕緣溝槽515、515’和515”可以利用一個硬掩膜(掩膜沒有表示出)，刻蝕到大約7微米的深度，使溝槽底部正好位於基板501的上方。第一絕緣溝槽515位於N+掩埋層505的一邊和p+注入層507的 一邊，溝槽515的左側壁位於穿通p注入區513的附近。第二絕緣溝槽515’位於N+掩埋層505的另一邊，並延伸到p+注入層507中，溝槽515’的左側壁位於p+注入區511的附近。第三絕緣溝槽515”位於p+注入層507的另一邊，溝槽515”的左側壁位於p+注入區511’的附近。如圖4I所示，沿絕緣溝槽壁，可以選擇沉積或生長一個氧化層517，其厚度約為50nm。絕緣溝槽515的剩餘部分用多晶矽519填充。利用回刻製程，除去多餘的多晶矽。圖4I表示氧化物生長和多晶矽沉積之後的元件。 As shown in FIG. 4H, in the first epitaxial layer 503 and the second epitaxial layer 509, a set of three insulating trenches 515, 515' and 515" are formed. The insulating trenches 515, 515' and 515" can utilize a hard The mask (not shown) is etched to a depth of about 7 microns so that the bottom of the trench is just above the substrate 501. The first insulating trench 515 is located on one side of the N+ buried layer 505 and the p+ implanted layer 507 On the one side, the left side wall of the trench 515 is located in the vicinity of the through p injection region 513. The second insulating trench 515' is located on the other side of the N+ buried layer 505 and extends into the p+ implanted layer 507, and the left side wall of the trench 515' is located adjacent to the p+ implanted region 511. The third insulating trench 515" is located on the other side of the p+ implanted layer 507, and the left side wall of the trench 515" is located adjacent to the p+ implanted region 511'. As shown in FIG. 4I, along the walls of the insulating trench, an oxide layer 517 may be selectively deposited or grown having a thickness of about 50 nm. The remaining portion of the insulating trench 515 is filled with a polysilicon 519. The excess polysilicon is removed by a etch back process. Figure 4I shows the elements after oxide growth and polycrystalline germanium deposition.

如圖4J所示，在第二外延層509和第一外延層503中，利用掩膜(圖中沒有表示出)可以選擇注入P-沉降注入區521、521’。P-沉降區521位於第二外延層509和第一外延層503中，在穿通p注入區513下方以及第一絕緣溝槽515的左側壁附近。P-沉降區521’位於第二外延層509和第一外延層503中，在第三絕緣溝槽515”的右側壁附近。P-沉降區521和521’都在p+注入層507中終止。如圖4J所示，還可以注入一個N-沉降區523，以便提供連接基板501和地電勢的電路。N-沉降可以在一個單獨的注入製程中利用單獨的掩膜(圖中沒有表示出)注入。 As shown in Fig. 4J, in the second epitaxial layer 509 and the first epitaxial layer 503, the implantation of the P-sinking implantation regions 521, 521' can be selectively performed using a mask (not shown). The P-sinking region 521 is located in the second epitaxial layer 509 and the first epitaxial layer 503, below the through-p implant region 513 and near the left side wall of the first insulating trench 515. The P-sinking zone 521' is located in the second epitaxial layer 509 and the first epitaxial layer 503, near the right side wall of the third insulating trench 515". Both the P-sinking regions 521 and 521' terminate in the p+ implanted layer 507. As shown in Fig. 4J, an N-sinking region 523 can also be implanted to provide a circuit for connecting the substrate 501 to the ground potential. N-sedimentation can utilize a separate mask in a separate implantation process (not shown) injection.

如圖4K所示，利用另一個掩膜(圖中沒有表示出)，在第二外延層509的頂面中，注入一組四個源極區524、524’、524”、524'''。第一源極區524、穿通p注入區513以及第二外延層509的下層部分構成穿通結構。第二源極區524’成為水平二極體HSD的陰極，第一p+注入區511和第二外延層509共同構成水平二極體HSD的陽極。第三源極區524”成為水平低端導向二極體LSD的陰極。第四源極區524'''為n-沉降區523提供接頭。 As shown in FIG. 4K, a set of four source regions 524, 524', 524", 524"' are implanted into the top surface of the second epitaxial layer 509 using another mask (not shown). The first source region 524, the through-p implant region 513, and the lower portion of the second epitaxial layer 509 form a punch-through structure. The second source region 524' becomes the cathode of the horizontal diode HSD, the first p+ implant region 511 and the The two epitaxial layers 509 together form the anode of the horizontal diode HSD. The third source region 524" becomes the cathode of the horizontal low-end guiding diode LSD. The fourth source region 524"" provides a joint for the n-sinking region 523.

如圖4L-4M所示，在兩個階段形成一個絕緣層530。如圖4L所示，在第二外延層509上方，例如藉由低溫製程，可以選擇製備一個第一絕緣層525(例如二氧化矽)。然後，如圖4M所示，在第一絕緣層525上製備一層第二絕緣層527(例如含有硼酸的矽玻璃(BPSG))，以形成絕緣層530。 As shown in Figures 4L-4M, an insulating layer 530 is formed in two stages. As shown in FIG. 4L, a first insulating layer 525 (e.g., hafnium oxide) may be selectively formed over the second epitaxial layer 509, for example, by a low temperature process. Then, as shown in FIG. 4M, a second insulating layer 527 (for example, barium-containing bismuth glass (BPSG)) is formed on the first insulating layer 525 to form an insulating layer 530.

如圖4N所示，在絕緣層530中形成開口，例如藉由傳統的掩膜和刻蝕技術，提供到TVS元件的接觸點。這些開口包括在穿通注入區上方到第一源極區524的接頭開口。在第二源極區524’上方，形成第二開口，以便形成到突返二極體陽極的接頭。在第一p+注入區524”上方，形成第三開口，以便形成到低端二極體陰極的接頭。在第四源極區524'''上方，形成一個額外的開口，以便形成藉由n-沉降區523到基板501的接地接頭。在p+注入區511、511’上方，形成多個額外的開口，以便形成到水平低端導向二極體的陽極和雪崩二極體陽極的電連接。如圖4N所示，藉由絕緣層530中的開口，在p+注入層511和511’中嵌入p+接觸區529和529’，以便於電接觸。 As shown in FIG. 4N, openings are formed in the insulating layer 530, such as by conventional masking and etching techniques, to provide contact points to the TVS elements. These openings include a joint opening above the feedthrough region to the first source region 524. Above the second source region 524', a second opening is formed to form a joint to the anode of the protruding diode. Above the first p+ implant region 524", a third opening is formed to form a junction to the lower terminal diode cathode. Over the fourth source region 524"", an additional opening is formed to form by n - a grounding junction of the settling zone 523 to the substrate 501. Over the p+ implanted regions 511, 511 ', a plurality of additional openings are formed to form an electrical connection to the anode of the horizontal low-end guiding diode and the avalanche diode anode. As shown in FIG. 4N, p+ contact regions 529 and 529' are embedded in the p+ implant layers 511 and 511' by openings in the insulating layer 530 to facilitate electrical contact.

如圖4O所示，在絕緣層530上方，形成一個金屬層532，以提供到TVS零部件的電接觸/接頭。金屬層532可分為第一、第二和第三區523A、523B、523C，它們之間相互電絕緣。第一區523A允許突返二極體陰極和穿通結構之間的電接觸。第二區523B允許低端二極體陰極和高端二極體陽極的I/O電接觸。第三區523C藉由第四源極區524'''和N-沉降區523，提供到低端二極體陽極和基板501的電接地接頭。 As shown in FIG. 4O, over the insulating layer 530, a metal layer 532 is formed to provide electrical contacts/joints to the TVS components. The metal layer 532 can be divided into first, second, and third regions 523A, 523B, 523C that are electrically insulated from each other. The first zone 523A allows for electrical contact between the cathode of the diode and the feedthrough structure. The second zone 523B allows for I/O electrical contact of the low side diode cathode and the high side diode anode. The third region 523C provides an electrical ground connection to the low side diode anode and substrate 501 by a fourth source region 524"" and an N-sink region 523.

如上所述，圖4A-4P所示製備TVS的上述步驟，用於圖3D所示的TVS元件。在可選實施例中，可以利用不同的製程步驟、不同的掩膜或兩者的組合，藉由改變圖4A-4P的製程，製備TVS元件，例如圖3A-3C所示的那些TVS元件。例如，利用圖4A-4P所示製程，但是使用不同的溝槽掩膜製備絕緣溝槽415、不同的製程步驟進行電介質填充溝槽並且省去製備p-沉降區521、521’所用的掩膜和注入，也可以製備圖3A所示的元件。此外，利用圖4A-4P所示製程，但是省去製備p-沉降區521、521’所用的掩膜和注入，也可以製備圖3B所示的元件。此外，包括製備p-沉降區521、521’所用的掩膜和注入，但是利用不同的溝槽掩膜製備絕緣溝槽415和不同的製程步驟進行電介質填充溝槽，也可以製備圖3C所示的元件。 As described above, the above steps of preparing the TVS shown in Figs. 4A-4P are for the TVS element shown in Fig. 3D. In alternative embodiments, TVS components, such as those illustrated in Figures 3A-3C, may be fabricated by varying the process of Figures 4A-4P using different process steps, different masks, or a combination of both. For example, the process shown in FIGS. 4A-4P is used, but the trench trenches 415 are prepared using different trench masks, the different process steps are performed to dielectrically fill the trenches, and the mask used to prepare the p-sink regions 521, 521' is omitted. The components shown in Fig. 3A can also be prepared by injection. Further, the components shown in Fig. 3B can be prepared by using the processes shown in Figs. 4A-4P, but omitting the mask and implantation used to prepare the p-sinking regions 521, 521'. In addition, including the mask and implantation used to prepare the p-sinking regions 521, 521', but using different trench masks to prepare the insulating trenches 415 and different process steps for dielectric filling trenches, it is also possible to prepare as shown in FIG. 3C. Components.

儘管本發明關於某些較佳的版本已經做了詳細的敘述，但是仍可能存在各種不同的修正、變化和等效情況。因此，本發明的範圍不應由上述說明決定，與之相反，本發明的範圍應參照所附的申請專利範圍書及其全部等效內容。任何可選件(無論首選與否)，都可與其他任何可選件(無論首選與否)組合。在以下申請專利範圍中，除非特別聲明，否則不定冠詞“一個”或“一種”都指下文內容中的一個或多個專案的數量。除非用“意思是”明確指出限定功能，否則所附的申請專利範圍書並不應認為是意義-加-功能的局限。沒有明確指出“意思是”執行特定功能的申請專利範圍書中的任意內容，都不應認為是35 USC § 112,¶ 6中所述的“意思”或“步驟”。 Although the present invention has been described in detail with respect to certain preferred embodiments, various modifications, changes and equivalents are possible. Therefore, the scope of the invention should be construed as being limited by the scope of the appended claims. Any option (whether preferred or not) can be combined with any other option (whether preferred or not). In the following claims, the indefinite article "a" or "an" Unless the "function" is used to clearly indicate a defined function, the scope of the appended patent application should not be construed as a limitation of meaning-plus-function. Anything in the scope of the patent application that does not explicitly state "meaning" that a particular function is performed should not be considered as "meaning" or "step" as described in 35 USC § 112, ¶ 6.

儘管本發明的內容已經藉由上述較佳實施例作了詳細介紹，但應當認識到上述的描述不應被認為是對本發明的限制。在本領域技術人員閱讀了上述內容後，對於本發明的多種修改和替代都將是顯而易見的。因此，本發明的保護範圍應由所附的申請專利範圍來限定。 Although the present invention has been described in detail by the preferred embodiments thereof, it should be understood that the description Various modifications and alterations of the present invention will be apparent to those skilled in the art. Therefore, the scope of the invention should be limited by the scope of the appended claims.

Claims (10)

一種暫態電壓抑制器元件，其包含：a)一個第一導電類型的半導體基板；b)一個第一導電類型的半導體材料的第一外延層，在該半導體基板上；c)一個第一導電類型的半導體材料的掩埋層，位於該第一外延層中；d)一個第二導電類型的半導體材料的注入層，位於該掩埋層下方的該第一外延層中，該注入層在水平方向延伸超出該掩埋層，NPN結構由該掩埋層、該注入層、該第一外延層以及該半導體基板構成；e)一個第一導電類型的半導體材料的第二外延層，位於該第一外延層上方；f)一對第二導電類型的半導體材料的注入區，在該第二外延層的頂面中；該注入區包括一個第一注入區及一個第二注入區；g)一個第二導電類型的半導體材料的穿通注入區，在該第二外延層的頂面中；h)一組形成在第二外延層以及第一外延層中的溝槽，該組中的每個溝槽都至少內襯電介質材料，該組溝槽包括一個第一溝槽，靠近該掩埋層的一邊緣及該注入層的一邊緣、以及在該穿通注入區及該第一注入區之間；一個第二溝槽，靠近掩埋層的另一邊緣，延伸到該注入層中；一個第三溝槽，靠近 該注入層的另一邊緣，其中該第二溝槽在該第一溝槽以及該第三溝槽之間；以及i)一組第一導電類型的半導體材料的源極區，在該第二外延層的頂面中，該組源極區包括一個第一源極區，位於該穿通注入區上方；一個第二源極區，位於該第一溝槽以及該第二溝槽之間；一個第三源極區，位於該第二溝槽以及該第三溝槽之間；以及一個第四源極區，使得該第三溝槽位於該第三源極區以及第四源極區之間，其中該第一注入區位於該第二源極區以及該第三源極區之間，該第二注入區位於該第三溝槽以及該第三溝槽側壁附近的該第三源極區之間，由該第一源極區、該穿通注入區以及該第二外延層構成一個垂直PN結，由該第二源極區、該第二外延層以及該第一注入區構成一個水平PN結，以及由該第三源極區、該第二外延層以及該第二注入區構成一個水平PN結。 A transient voltage suppressor element comprising: a) a first conductivity type semiconductor substrate; b) a first epitaxial layer of a first conductivity type semiconductor material on the semiconductor substrate; c) a first conductive a buried layer of a type of semiconductor material, located in the first epitaxial layer; d) an implant layer of a second conductivity type semiconductor material, located in the first epitaxial layer below the buried layer, the implant layer extending in a horizontal direction Exceeding the buried layer, the NPN structure is composed of the buried layer, the implanted layer, the first epitaxial layer and the semiconductor substrate; e) a second epitaxial layer of a first conductivity type semiconductor material, above the first epitaxial layer f) a pair of implant regions of a second conductivity type semiconductor material in the top surface of the second epitaxial layer; the implant region includes a first implant region and a second implant region; g) a second conductivity type a punch-through implant region of the semiconductor material in the top surface of the second epitaxial layer; h) a set of trenches formed in the second epitaxial layer and the first epitaxial layer, each trench in the set being at least lining a dielectric material, the set of trenches including a first trench, adjacent an edge of the buried layer and an edge of the implant layer, and between the punch-through implant region and the first implant region; a second trench Adjacent to the other edge of the buried layer, extending into the injection layer; a third trench, close Another edge of the implant layer, wherein the second trench is between the first trench and the third trench; and i) a source region of a set of first conductivity type semiconductor material, in the second In the top surface of the epitaxial layer, the set of source regions includes a first source region above the punch-through implant region; and a second source region between the first trench and the second trench; a third source region between the second trench and the third trench; and a fourth source region such that the third trench is between the third source region and the fourth source region The first implantation region is located between the second source region and the third source region, and the second implantation region is located at the third source region of the third trench and the third trench sidewall Between the first source region, the through implant region and the second epitaxial layer, a vertical PN junction is formed, and the second source region, the second epitaxial layer and the first implant region form a horizontal PN And forming a horizontal PN junction from the third source region, the second epitaxial layer, and the second implant region. 如申請專利範圍第1項所述之暫態電壓抑制器元件，其中，該第一導電類型為N，第二導電類型為P。 The transient voltage suppressor element of claim 1, wherein the first conductivity type is N and the second conductivity type is P. 如申請專利範圍第1項所述之暫態電壓抑制器元件，其中，該半導體基板為重摻雜n-型半導體基板。 The transient voltage suppressor element of claim 1, wherein the semiconductor substrate is a heavily doped n-type semiconductor substrate. 如申請專利範圍第2項所述之暫態電壓抑制器元件，其中，該第一外延層的半導體材料為n-型材料，其n-型摻雜濃度低於基板。 The transient voltage suppressor element of claim 2, wherein the semiconductor material of the first epitaxial layer is an n-type material having an n-type doping concentration lower than the substrate. 如申請專利範圍第1項所述之暫態電壓抑制器元件，其中，該第一溝槽、該第二溝槽以及該第三溝槽中的每一個都用電介質材料填充。 The transient voltage suppressor component of claim 1, wherein each of the first trench, the second trench, and the third trench is filled with a dielectric material. 如申請專利範圍第1項所述之暫態電壓抑制器元件，其中，h)中的每個溝槽都用多晶矽填充。 The transient voltage suppressor element of claim 1, wherein each of the trenches in h) is filled with polysilicon. 如申請專利範圍第1項所述之暫態電壓抑制器元件，其中，該元件更包括一個p-型半導體材料的沉降區，形成在該第二外延層中，該沉降區位於該穿通注入區下方，在該第一源極區以及該第二源極區之間。 The transient voltage suppressor element of claim 1, wherein the element further comprises a settling region of a p-type semiconductor material formed in the second epitaxial layer, the settling region being located in the through implant region Below, between the first source region and the second source region. 如申請專利範圍第1項所述之暫態電壓抑制器元件，其中，該元件更包括一個p-型半導體材料的沉降區，形成在該第二外延層中，該沉降區位於該第三溝槽的右側壁附近。 The transient voltage suppressor element of claim 1, wherein the element further comprises a settling region of a p-type semiconductor material formed in the second epitaxial layer, the settling region being located in the third trench Near the right side wall of the tank. 如申請專利範圍第1項所述之暫態電壓抑制器元件，其中，該元件更包括一個n-型半導體材料的沉降區，形成在該第二外延層中，沉降區位於該第四源極區下方。 The transient voltage suppressor component of claim 1, wherein the component further comprises a sink region of an n-type semiconductor material formed in the second epitaxial layer, the settling region being located at the fourth source Below the area. 一種暫態電壓抑制器元件的製備方法，其包括：a)在第一導電類型的半導體基板上方，製備一個第一導電類型的第一外延層；b)在該第一外延層的頂面中，製備一個第一導電類型的半導體材料的掩埋層；c)在該第一外延層中，製備一個第二導電類型的半導體材料的注入層，其中該注入層位於該掩埋層下方，該注入層的長度延伸超出該掩埋層的長度；d)在該第一外延層上方，製備一個第一導電類型的半導體材料的第二外延層；e)在該第二外延層的頂面中，製備一個第二導電類型的半導體材料的一對注入區；該注入區包括一個第一注入區及一個第二注入區； f)在該第二外延層的頂面中，製備一個第二導電類型的半導體材料的穿通注入區；g)在該第二外延層以及該第一外延層中，製備一組溝槽，該組溝槽包括一個第一溝槽，在該掩埋層的一邊以及該注入層的一邊，以及該穿通注入區以及該第一注入區之間；一個第二溝槽，在該掩埋層的另一邊，在該注入層中延伸；以及一個第三溝槽，在該注入層的另一邊；h)至少用一個電介質材料內襯每個溝槽；i)在該第二外延層的頂面中，製備一組第一導電類型的半導體材料的源極區，該組源極區包括一個第一源極區，位於該穿通注入區上方；一個第二源極區，位於該第一溝槽以及該第二溝槽之間；一個第三源極區，位於該第二溝槽以及該第三溝槽之間；以及一個第四源極區，使得該第三溝槽位於該第三源極區以及該第四源極區之間，其中該第一注入區位於該第二源極區以及該第三源極區之間，該第二注入區位於該第三溝槽以及該第三溝槽側壁附近的該第三源極區之間，一個垂直PN結由該第一源極區、該穿通注入區以及該第二外延層構成，一個水平PN結由該第二源極區、該第二外延層以及該第一注入區構成，一個垂直PN結由該掩埋層、該第二外延層以及該第一注入區構成，以及一個水平PN結由該第三源極區、該第二外延層以及該第二注入區構成。 A method of fabricating a transient voltage suppressor element, comprising: a) preparing a first epitaxial layer of a first conductivity type over a semiconductor substrate of a first conductivity type; b) in a top surface of the first epitaxial layer Preparing a buried layer of a semiconductor material of a first conductivity type; c) preparing an implant layer of a semiconductor material of a second conductivity type in the first epitaxial layer, wherein the implant layer is under the buried layer, the implant layer a length extending beyond the length of the buried layer; d) preparing a second epitaxial layer of a first conductivity type semiconductor material over the first epitaxial layer; e) preparing a top surface of the second epitaxial layer a pair of implant regions of a second conductivity type semiconductor material; the implant region includes a first implant region and a second implant region; f) preparing a through-injection region of a semiconductor material of a second conductivity type in a top surface of the second epitaxial layer; g) preparing a set of trenches in the second epitaxial layer and the first epitaxial layer, The group trench includes a first trench on one side of the buried layer and one side of the implant layer, and between the punch-through implant region and the first implant region; and a second trench on the other side of the buried layer Extending in the injection layer; and a third trench on the other side of the implant layer; h) lining each trench with at least one dielectric material; i) in the top surface of the second epitaxial layer, Preparing a set of source regions of a first conductivity type semiconductor material, the set of source regions including a first source region above the through implant region; a second source region at the first trench and the Between the second trenches; a third source region between the second trench and the third trench; and a fourth source region such that the third trench is located in the third source region And the fourth source region, wherein the first implant region is located at the second source Between the region and the third source region, the second implant region is between the third trench and the third source region near the sidewall of the third trench, a vertical PN junction is formed by the first source a region, the punch-through implant region and the second epitaxial layer, a horizontal PN junction is formed by the second source region, the second epitaxial layer and the first implant region, and a vertical PN junction is formed by the buried layer The second epitaxial layer and the first implant region are formed, and a horizontal PN junction is formed by the third source region, the second epitaxial layer, and the second implant region.
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