TWI622155B - Esd protection circuit - Google Patents

Abstract

The invention discloses an electrostatic protection circuit comprising: a P-type diode, an N-type diode and a clamping circuit. The P-type diode includes: a P-type semiconductor substrate; an N-well; a first N+ diffusion region disposed in the N-well; and a P+ diffusion region disposed in the first N+ diffusion region. And a second N+ diffusion region disposed around the P+ diffusion region. The N-type diode includes: a P-type semiconductor substrate; a first P+ diffusion region disposed in the P-type semiconductor substrate of the N-type diode; and an N+ diffusion region disposed on the first P+ diffusion a periphery of the region; and a second P+ diffusion region disposed around the N+ diffusion region.

Description

Electrostatic protection circuit

The invention relates to an electrostatic protection circuit, in particular to an electrostatic protection circuit with an innovative diode structure, which can have better electrostatic protection function and relatively low parasitic capacitance without increasing the area.

FIG. 1 is a simplified schematic diagram of a conventional electrostatic protection circuit 100, and FIG. 2 is a plan view and a cross section of an N-type diode in an electrostatic protection circuit 100 of FIG. schematic diagram. As shown in FIG. 1 , the electrostatic protection circuit 100 includes a P-type diode 110 coupled to a power terminal Power and an input/output terminal I/O. An N-type diode 120 is coupled to the The ground terminal GND and an input/output terminal I/O; and a clamp circuit 130 are connected in parallel to the P-type diode 110 and the N-type diode 120. As shown in FIG. 2, the N-type diode 120 includes a P-type semiconductor substrate 122, an N+ diffusion region 124, and a P+ diffusion region 126. The N+ diffusion region 124 is disposed in the P-type semiconductor substrate 122 and coupled to the input and output terminals I/O. The P+ diffusion region 126 is disposed around the N+ diffusion region 124 and coupled to the ground GND. Therefore, the conventional electrostatic protection circuit 100 can only cause current to flow from the P+ diffusion region 126 to the N+ diffusion region 124, that is, there is only one path, so the conventional electrostatic protection circuit 100 must wait for a better electrostatic protection function. The proportion increases the overall area of the N-type diode 120, but after the area is increased, the parasitic capacitance will increase, which has a great influence on high-speed applications. Similarly, the P-type diode 110 has a similar structure to the N-type diode 120, and thus causes the same problem.

In view of this, one of the objects of the present invention is to provide an electrostatic protection circuit with an innovative diode structure, which can have better electrostatic protection function and relatively low parasitic capacitance without increasing the area, so as to solve the above problem. problem.

According to the patent application scope of the present invention, an electrostatic protection circuit includes: a P-type diode coupled to a power terminal and an input/output terminal; and an N-type diode coupled to the a ground terminal and an input/output terminal; and a clamp circuit connected in parallel to the P-type diode and the N-type diode. The P-type diode includes: a P-type semiconductor substrate; an N-well (N-well) disposed in the P-type semiconductor substrate; a first N+ diffusion region disposed in the N-well and coupled to the P-type semiconductor substrate a power supply terminal; a P+ diffusion region disposed around the first N+ diffusion region and coupled to the input/output terminal; and a second N+ diffusion region disposed around the P+ diffusion region and coupled to the power terminal The N-type diode includes: a P-type semiconductor substrate; a first P+ diffusion region disposed in the P-type semiconductor substrate of the N-type diode, coupled to the ground; an N+ diffusion region The second P+ diffusion region is disposed around the N+ diffusion region and coupled to the ground end.

In summary, the present invention provides an electrostatic protection circuit with an innovative diode structure, which can have better electrostatic protection function and lower parasitic capacitance without increasing the area, thereby facilitating high-speed applications.

Certain terms are used throughout this specification and the following claims to refer to particular elements, and those of ordinary skill in the art should understand that the hardware manufacturer may refer to the same element by a different noun. The scope of the specification and the subsequent patent application does not use the difference in name as the means of distinguishing the elements, but the difference in the function of the elements as the criterion for distinguishing, as mentioned in the entire specification and subsequent claims. "Includes" is an open-ended term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used in this context to include any direct and indirect electrical connection means. Depicting a first device coupled to a second device means that the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device through other devices or connection means.

Please refer to FIG. 3-5. FIG. 3 is a simplified schematic diagram of an electrostatic protection circuit 200 according to an embodiment of the present invention, and FIG. 4 is an electrostatic protection circuit of FIG. A top view and a cross-sectional view of one of the P-type diodes in FIG. 5, and a top view and a cross-sectional view of one of the N-type diodes in an electrostatic protection circuit 200 of FIG. As shown in FIG. 3, the electrostatic protection circuit 200 includes a P-type diode 210 coupled to a power terminal Power and an input/output terminal I/O. An N-type diode 220 is coupled to the The ground terminal GND and an input/output terminal I/O; and a clamp circuit 230 are connected in parallel to the P-type diode 210 and the N-type diode 220. As shown in FIG. 4, the P-type diode 210 includes a P-type semiconductor substrate 212, an N-well 214, a first N+ diffusion region 215, a P+ diffusion region 216, and a second. N+ diffusion region 217. The N well 214 is disposed in the P-type semiconductor substrate 212; the first N+ diffusion region 215 is disposed in the N well 214 and coupled to the power terminal Power. The P+ diffusion region 216 is disposed around the first N+ diffusion region 215 and coupled to the input/output terminal I/O. The second N+ diffusion region 217 is disposed around the P+ diffusion region 216 and coupled to the power supply terminal Power. In this manner, the present invention can diffuse current from the P+ diffusion region 216 to the first N+ diffusion region 215 and the second N+ diffusion, respectively. The region 217 flows, because the P-type diode 210 of the present invention can obtain a better electrostatic protection function, and the P+ diffusion region 216 has a larger area than the conventional P-type diode. The P+ diffusion region in the bulk structure is small, so the parasitic capacitance of the P-type diode 210 of the present invention is also relatively small.

As shown in FIG. 5, the N-type diode 220 includes a P-type semiconductor substrate 222, a first P+ diffusion region 225, an N+ diffusion region 226, and a second P+ diffusion region 227. The first P+ diffusion region 225 is disposed in the P-type semiconductor substrate 222 and coupled to the ground GND. The N+ diffusion region 226 is disposed around the first P+ diffusion region 225 and coupled to the input/output terminal I/O. The second P+ diffusion region 227 is disposed around the N+ diffusion region 226 and coupled to the ground GND. In this way, the present invention can cause current to flow from the first P+ diffusion region 225 and the second P+ diffusion region 227 to the N+ diffusion region 226, respectively. Since there is one more path than the conventional N-type diode structure, the N of the present invention. The type diode 220 can also obtain a better electrostatic protection function, and the area of the N+ diffusion region 226 is smaller than the N+ diffusion region in the conventional N-type diode structure, so the parasitic capacitance of the P-type diode 210 of the present invention. It will also be relatively small. In addition, it should be noted that the above-described embodiments are merely illustrative of the present invention, and are not limitations of the present invention, for example, the first N+ diffusion region 215, the P+ diffusion region 216 of the P-type diode 210, and The shape and number of the second N+ diffusion regions 217 may vary depending on different design requirements. Similarly, the shape and number of the first P+ diffusion region 225, the N+ diffusion region 226, and the second P+ diffusion region 227 of the N-type diode 220 may also vary according to different design requirements. In addition, in another embodiment of the present invention, the N well 214 of the P-type diode 210 of FIG. 4 may be disposed in a deep N-well 232, and the deep N well 232 is disposed in the P-type. The semiconductor substrate 212 is as shown in FIG. 6; and the N-type diode 220 of FIG. 5 may further include a P well 240 disposed in a deep N well 242, and a deep N well 242 disposed on the P-type semiconductor. In the substrate 222, as shown in Fig. 7.

In summary, the present invention provides an electrostatic protection circuit with an innovative diode structure, which can have better electrostatic protection function and lower parasitic capacitance without increasing the area, thereby facilitating high-speed applications. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧Electrostatic protection circuit
110‧‧‧P type diode
120‧‧‧N type diode
122‧‧‧P type semiconductor substrate
124‧‧‧N+ diffusion area
126‧‧‧P+ diffusion area
124‧‧‧N+ diffusion area
130‧‧‧Clamp circuit
200‧‧‧Electrostatic protection circuit
210‧‧‧P type diode
220‧‧‧N type diode
212‧‧‧P type semiconductor substrate
214‧‧‧N Well
215‧‧‧First N+ diffusion zone
216‧‧‧P+ diffusion area
217‧‧‧Second N+ diffusion area
222‧‧‧P type semiconductor substrate
225‧‧‧First P+ diffusion zone
226‧‧‧N+ diffusion area
227‧‧‧Second P+ diffusion zone
230‧‧‧Clamp circuit
232‧‧‧Deep N well
240‧‧‧P well
242‧‧‧Deep N well
Power‧‧‧Power terminal
I/O‧‧‧ input and output
GND‧‧‧ ground terminal

Figure 1 is a simplified schematic diagram of a conventional electrostatic protection circuit. FIG. 2 is a plan view and a cross-sectional view showing an N-type diode in an electrostatic protection circuit of FIG. 1 . Figure 3 is a simplified schematic diagram of an electrostatic protection circuit in accordance with an embodiment of the present invention. Fig. 4 is a plan view and a cross-sectional view showing a P-type diode in the electrostatic protection circuit of Fig. 3. Fig. 5 is a plan view and a cross-sectional view showing an N-type diode in an electrostatic protection circuit of Fig. 3. FIG. 6 is a plan view and a cross-sectional view showing another embodiment of the P-type diode of FIG. 4. FIG. 7 is a plan view and a cross-sectional view showing another embodiment of an N-type diode of FIG. 5.

Claims (5)

An electrostatic protection circuit includes: a P-type diode coupled to a power terminal and an input terminal, comprising: a P-type semiconductor substrate; an N-well (N-well) disposed on the P-type a first N+ diffusion region is disposed in the N-well and coupled to the power supply terminal; a P+ diffusion region is disposed around the first N+ diffusion region and coupled to the input and output terminals; a second N+ diffusion region is disposed around the P+ diffusion region and coupled to the power supply terminal. An N-type diode is coupled to a ground terminal and the input/output terminal, and includes: a P-type semiconductor substrate; a first P+ diffusion region is disposed in the P-type semiconductor substrate of the N-type diode and coupled to the ground; an N+ diffusion region is disposed around the first P+ diffusion region and coupled to the And a second P+ diffusion region disposed around the N+ diffusion region and coupled to the ground terminal; and a clamping circuit connected in parallel to the P-type diode and the N-type diode. The electrostatic protection circuit of claim 1, wherein the P-type diode causes current to flow from the P+ diffusion region to the first N+ diffusion region and the second N+ diffusion region, respectively. The electrostatic protection circuit of claim 1, wherein the N-type diode causes current to flow from the first P+ diffusion region and the second P+ diffusion region to the N+ diffusion region, respectively. The electrostatic protection circuit of claim 1, wherein the P-type diode further comprises: a deep N-well disposed in the P-type semiconductor substrate of the P-type diode, And the N well of the P-type diode is disposed in the deep N well. The electrostatic protection circuit of claim 1, wherein the N-type diode further comprises: a deep N well disposed in the P-type semiconductor substrate of the N-type diode; and a P-well, The first P+ diffusion region, the N+ diffusion region and the second P+ diffusion region of the N-type diode are disposed in the P well.