TWI619019B - Security chip, non-volatile memory control device and non-volatile memory control method - Google Patents

Abstract

The invention discloses a security chip and a non-volatile memory control device and method thereof. The non-volatile memory control device includes: a non-volatile memory including a first storage area and a check storage area; and a memory controller including: a first write unit; a check value write unit; and cyclic redundancy The verification unit is used to calculate the cyclic redundancy check value corresponding to the data; the register unit is used to register the cyclic redundancy check value corresponding to the read data; the comparison unit is used to compare the check storage area corresponding to the read data The cyclic redundancy check value in and the cyclic redundancy check value in the register unit corresponding to the read data; the first read unit is used when the cyclic redundancy check value and read data in the check storage area corresponding to the read data When the cyclic redundancy check value in the corresponding register unit is the same, the data is read back.

Description

Security chip, non-volatile memory control device and non-volatile memory control method

The present invention relates to the technical field of security chips, and in particular, to a security chip and a nonvolatile memory control device and method thereof.

Security chip refers to the integrated circuit chip with data encryption and anti-security attack technology. It is widely used in digital signing, identity authentication and other fields, such as common public transportation cards and social security cards, smart cards, and online banking Shield Examples of security chip applications.

Attacks on security chips are currently generally divided into three forms: non-invasive attacks, invasive attacks, and semi-invasive attacks. Among them, non-intrusive attacks do not require direct contact with the internal components of the chip, nor do they cause any damage to the chip, such as timing attacks and power analysis. Such invasive attacks require direct contact with internal components of the chip, such as chemical Corrosion and laser cutting belong to this category; semi-invasive attacks are somewhere between non-invasive and invasive attacks. It also needs to open the package of the wafer to access the surface of the wafer, but does not require electrical contact with the metal surface. In this way, there is no mechanical damage to silicon, such as common laser attacks.

Semi-intrusive attacks, including light injection, electromagnetic manipulation, radiation injection, etc., at specific physical locations at specific times during the operation of the security chip, artificially introduce instantaneously controllable interference signals to change the chip program flow and memory To obtain sensitive information such as sensitive permissions and keys, and laser injection is the most common. Due to the energy concentration of the laser, it is easy to cause the digital logic inside the chip to be mistakenly flipped, or to cause transient data errors in the memory unit, thereby jeopardizing the safety of the chip. At present, the common methods for the wafer to resist laser attacks mainly include the use of a passive mask layer (covering a large area of a metal layer on the surface of the wafer), a light sensor, and adding a data check bit. However, the method of the metal mask layer can only be applied to the front side of the wafer due to the current process and manufacturing conditions. If the laser attacks from the back of the wafer, the metal mask layer does not work; meanwhile, the method of the light sensor is limited to the wafer Due to the limitation of area, it always exists at a certain density and it is impossible to cover the whole wafer.

FIG. 1 is a schematic structural diagram of a security chip of the prior art. As shown in FIG. 1, the security chip mainly includes the following.

The security algorithm unit 101 is configured to implement a security algorithm. Generally, security algorithms include RSA (Rivest Shamir Adlemen) algorithms, AES (Advanced Encryption Standard) algorithms, HASH algorithms, and the like.

The analog oscillator 102 is used to provide a required clock signal for the entire chip system.

The power management unit 103 is configured to provide a stable and reliable power for the entire chip, and cooperate with the system's low power consumption strategy.

The security protection unit 104 generally includes a light sensor, a temperature sensor, a magnetic field sensor, and the like.

Microprocessor and bus matrix 105. The microprocessor is the core of the entire chip. It is connected with various peripherals through the bus matrix, so that Software running on the processor controls the operation of the entire system.

The clock and reset management unit 106 is configured to manage the clock and reset network of the entire chip.

The interface unit 107 usually includes a communication interface conforming to the ISO 7816 protocol or the ISO 14443 protocol.

The non-volatile memory and its controller 108 generally include ROM, EEPROM, or FLASH and the corresponding memory controller.

The dynamic random memory and its controller 109, that is, the memory and the memory controller required by the microprocessor for operation.

Generally, in security chips, non-volatile memory (mainly flash memory and EEPROM) always occupies a considerable area, so it is also the easiest target for semi-intrusive security attacks. Memory security has also been one of the key considerations in the design of security chips.

In order to solve the technical problems existing in the prior art, the embodiments of the present invention are expected to provide a security chip and a nonvolatile memory control device and method thereof, which can implement non-volatile data in the security chip with less hardware and system overhead. Protection of stored data.

The technical solution of the embodiment of the present invention is implemented as follows.

An embodiment of the present invention provides a non-volatile memory control device, including: a non-volatile memory and a memory controller.

The non-volatile memory includes: a first storage area and a check storage area.

The first storage area is used to store the first writing data.

Check storage area for storing cyclic redundancy calibration corresponding to the first write data Verification value.

The memory controller includes: a cyclic redundancy check unit, a check value write unit, a first write unit, a register unit, a comparison unit, and a first read unit.

Cyclic redundancy check unit, used to calculate the cyclic redundancy check value corresponding to the data.

The check value writing unit is configured to write a cyclic redundancy check value corresponding to the first write data into the check storage area.

The first writing unit is configured to write first write data into the first storage area.

The registering unit is used to register a cyclic redundancy check value corresponding to the read data.

The comparison unit is configured to compare the cyclic redundancy check value in the verification storage area corresponding to the read data with the cyclic redundancy check value in the registration unit corresponding to the read data.

The first reading unit is configured to return the read data when the cyclic redundancy check value in the check storage area corresponding to the read data is the same as the cyclic redundancy check value in the register unit corresponding to the read data.

In the above solution, the memory controller further includes: an alarm unit, configured to read the cyclic redundancy check value in the verification storage area corresponding to the read data and the cyclic redundancy check value in the registration unit corresponding to the read data. If they are not the same, the alarm information is returned.

In the above solution, the non-volatile memory further includes: a second storage area for storing the second write data.

The memory controller further includes: a second writing unit for directly writing the second write data into the second storage area; and a second reading unit for directly returning the data in the second storage area.

In the above solution, the first storage area of the non-volatile memory is not adjacent to the check storage area, or the first storage area is far from the first address of the check storage area.

In the above solution, in the nonvolatile memory, a unit of data in the first storage area corresponds to a cyclic redundancy check value in the check storage area.

An embodiment of the present invention further provides a security chip. The security chip includes any one of the foregoing nonvolatile memory control devices.

An embodiment of the present invention further provides a non-volatile storage control method. The method includes: when performing a write operation on a first storage area, a cyclic redundancy check unit calculates a cyclic redundancy check value corresponding to the first write data; The check value writing unit writes the cyclic redundancy check value corresponding to the first write data into the check storage area; the first write unit writes the first write data into the first storage area; When a read operation is performed in the storage area, the cyclic redundancy check unit calculates the cyclic redundancy check value corresponding to the read data; the register unit registers the cyclic redundancy check value corresponding to the read data; the comparison unit compares the school corresponding to the read data The cyclic redundancy check value in the check storage area and the cyclic redundancy check value in the register unit corresponding to the read data; when the cyclic redundancy check value in the check storage area corresponding to the read data corresponds to the read data When the cyclic redundancy check value in the registration unit is the same, the first reading unit returns the reading data.

In the above solution, the method further includes: when the cyclic redundancy check value in the verification storage area corresponding to the read data is different from the cyclic redundancy check value in the registration unit corresponding to the read data, the alarm unit returns an alarm Information.

In the above solution, the method further includes: when performing a write operation on the second storage area, the second writing unit directly writes the second write data into the second storage area. Area; when a read operation is performed on the second storage area, the second reading unit directly returns the data in the second storage area.

In the above solution, calculating the cyclic redundancy check value corresponding to the first write data includes: calculating a corresponding cyclic redundancy check value for each unit of data of the first write data one by one.

The security chip and the non-volatile memory control device and method provided by the embodiments of the present invention can use a dedicated cyclic redundancy check circuit to perform feature value calculation on important data in the non-volatile memory, and This characteristic value and important data are stored separately, so that when the non-volatile memory of the security chip is attacked, the system can detect whether the important data has been tampered with in time, and then can promptly report to the police or take other measures. The cyclic redundancy check circuit is used to calculate the eigenvalues. The hardware and software implementation complexity is low, and the system performance loss is small.

21‧‧‧Non-volatile memory

22‧‧‧Memory Controller

101‧‧‧Security Algorithm Unit

102‧‧‧analog oscillator

103‧‧‧Power Management Unit

104‧‧‧Security Protection Unit

105‧‧‧Microprocessor and Bus Matrix

106‧‧‧ Clock and Reset Management Unit

107‧‧‧ interface unit

108‧‧‧Non-volatile memory and its controller

109‧‧‧Dynamic random memory and its controller

211‧‧‧first storage area

212‧‧‧Check storage area

221‧‧‧cyclic redundancy check unit

222‧‧‧Check value writing unit

223‧‧‧First writing unit

224‧‧‧Storage Unit

225‧‧‧ Matching Unit

226‧‧‧First Reading Unit

301 ~ 307‧‧‧ steps

FIG. 1 is a schematic structural diagram of a security chip of the prior art.

FIG. 2 is a schematic structural diagram of a non-volatile memory control device according to an embodiment of the present invention.

FIG. 3 is a schematic flowchart of a non-volatile storage control method provided by an embodiment of the present invention.

In order to explain the embodiments and technical solutions of the present invention more clearly, the technical solutions of the present invention will be described in more detail with reference to the drawings and the embodiments. Obviously, the described embodiments are part of the present invention, but not all of them. Examples. Based on the embodiments of the present invention, ordinary techniques in the art All other embodiments obtained by a person without creative efforts belong to the protection scope of the present invention.

In the embodiment of the present invention, the non-volatile memory and its controller in the security chip are collectively referred to as a non-volatile memory control device. For example, the non-volatile memory and its controller 108 in FIG. 1 may be It is called a non-volatile memory control device.

FIG. 2 is a schematic structural diagram of a non-volatile memory control device according to an embodiment of the present invention. As shown in FIG. 2, the device includes a non-volatile memory 21 and a memory controller 22.

The non-volatile memory 21 includes: a first storage area 211 and a check storage area 212; wherein the first storage area 211 is used to store a first write data; the check storage area 212 is used to store a cycle corresponding to the first write data Redundancy check value.

The memory controller 22 includes a cyclic redundancy check unit 221, a check value write unit 222, a first write unit 223, a register unit 224, a comparison unit 225, and a first read unit 226.

The cyclic redundancy check unit 221 is configured to calculate a cyclic redundancy check value corresponding to the data.

The check value writing unit 222 is configured to write the cyclic redundancy check value corresponding to the first write data into the check storage area 212.

The first writing unit 223 is configured to write first write data into the first storage area 211.

The registering unit 224 is configured to register a cyclic redundancy check value corresponding to the read data.

The comparison unit 225 is configured to compare the cyclic redundancy check value in the verification storage area 212 corresponding to the read data with the cyclic redundancy check value in the registration unit 224 corresponding to the read data.

The first reading unit 226 is configured to return the read data when the cyclic redundancy check value in the check storage area 212 corresponding to the read data is the same as the cyclic redundancy check value in the register unit 224 corresponding to the read data. .

Specifically, the first write data is usually very important data. Once such data is tampered or lost, it will cause losses to the users of the security chip, such as user key, recharge card balance information, etc. Therefore, such information needs special protection. When the security chip writes such data (first write data) into the non-volatile memory 21, the first write data should be stored in the first storage area 211. In order to strengthen the protection of the first written data, in the embodiment of the present invention, the memory controller 22 includes a cyclic redundancy check unit 221, which can calculate the corresponding cyclic redundancy check value for the first written data, and The cyclic redundancy check value is written into the check storage area 212 by the check value writing unit 222. Accordingly, the first writing data is written into the first storage area 211 by the first writing unit 223.

Here, the selection of the polynomial used to calculate the cyclic redundancy check value may not be fixed, and the security chip may be selected according to application requirements. Common and standard cyclic redundancy check value generation polynomials are: X8 + X5 + X4 + 1, X16 + X15 + X2 + 1, X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + 1 and so on. But no matter what kind of polynomial is used, the advantages of cyclic redundancy check are that the hardware is less difficult to implement, takes up less logical resources, and requires less space to store the check value. This is sensitive to cost and power Security chips (such as smart cards) are extremely advantageous.

When the security chip reads the data in the first storage area 211 in the non-volatile memory 21, that is, the read address is in the first storage area 211, the data corresponding to the read address is called "read data" here. Then, the cyclic redundancy check unit 221 of the memory controller 22 calculates a cyclic redundancy check value corresponding to the read data, and the register unit 224 registers the cyclic redundancy check value corresponding to the read data; then, the comparison unit 225 compares the cyclic redundancy check value in the check storage area 212 corresponding to the read data with the cyclic redundancy check value in the register unit 224 corresponding to the read data; when the check storage area 212 corresponding to the read data When the cyclic redundancy check value of is the same as the cyclic redundancy check value in the register unit 224 corresponding to the read data, it means that the non-volatile memory 21 is not damaged, and the first read unit 226 returns the Reading materials.

Preferably, in the above control device, the memory controller 22 further includes: an alarm unit, configured to read the cyclic redundancy check value in the check storage area 212 corresponding to the read data and the register unit 224 corresponding to the read data. When the cyclic redundancy check values are different, an alarm message is returned to the security chip.

Further, the returning the alarm information to the security chip may include: the alarm unit sends an alarm signal to the internal chip of the security chip or the chip system control unit; the security signal may be protected and processed by the security chip firmware or hardware system, for example, Power off or reset inside the chip.

In some embodiments, the non-volatile memory 21 may also store some less important data. Such data does not need special protection. Therefore, in the above-mentioned non-volatile memory control device, as shown in FIG. 2 The non-volatile memory 21 may further include a second storage area for storing a second write data. Data; here, the second written information refers to the type of information that does not require special protection.

Correspondingly, the memory controller 22 may further include: a second writing unit for directly writing the second write data into the second storage area; and a second reading unit for directly returning the data in the second storage area. data.

In this way, the non-volatile memory control device can adopt different storage control strategies for the stored data according to different factors such as the security level and importance of the data, which improves flexibility.

Further, in order to reduce the chance of the first storage area 211 and the verification storage area 212 of the non-volatile memory 21 being attacked at the same time, in the above control device, the first storage area 211 of the non-volatile memory 21 and the school The verification storage area 212 is preferably not adjacent, for example, they are separated by a second storage area; or the first address of the first storage area 211 and the first address of the check storage area 212 are relatively far away.

Further, in the non-volatile memory 21, a unit of data in the first storage area 211 corresponds to a cyclic redundancy check value in the check storage area 212.

Specifically, an important piece of data may require multiple storage units to store. Here, the storage unit may be 1 byte or 1 page, which is determined according to the read / write bandwidth and application scenario of the non-volatile memory 21; In order to improve security, in some embodiments, a cyclic redundancy check value is calculated and stored for each unit of data of a first write data, so that an important piece of data will correspond to more than one cyclic redundancy Check value.

In practical applications, the above non-volatile memory 21 may be a one-time programmable read-only memory (OTP ROM), an electrically erasable programmable read-only memory Reading memory (EEPROM) or flash memory (Flash), the memory controller 22 may be implemented by a control circuit.

An embodiment of the present invention further provides a security chip. The security chip includes any one of the foregoing nonvolatile memory control devices.

An embodiment of the present invention further provides a non-volatile storage control method. As shown in FIG. 3, the method includes: when a write operation is performed on the first storage area, step 301, the cyclic redundancy check unit calculates the first write data. Corresponding cyclic redundancy check value.

Step 302: The check value writing unit writes the cyclic redundancy check value corresponding to the first write data into the check storage area.

Step 303: The first writing unit writes the first writing data into the first storage area.

When a read operation is performed on the first storage area, step 304, the cyclic redundancy check unit calculates a cyclic redundancy check value corresponding to the read data.

Step 305: The registration unit registers a cyclic redundancy check value corresponding to the read data.

Step 306: The comparison unit compares the cyclic redundancy check value in the verification storage area corresponding to the read data with the cyclic redundancy check value in the registration unit corresponding to the read data.

Step 307: When the cyclic redundancy check value in the check storage area corresponding to the read data is the same as the cyclic redundancy check value in the register unit corresponding to the read data, the first reading unit returns the read data.

Preferably, the above method further includes: when reading the cyclic redundancy check value and When the cyclic redundancy check values in the register units corresponding to the read data are different, the alarm unit returns alarm information.

Further, the method may further include: when performing a write operation on the second storage area, the second writing unit directly writes the second write data into the second storage area; when performing a read operation on the second storage area, the first The second reading unit directly returns the data in the second storage area.

Further, in the above method, calculating the cyclic redundancy check value corresponding to the first write data includes: calculating each cyclic redundancy check value corresponding to each unit of data of the first write data one by one.

Those skilled in the art should understand that the embodiments of the present invention may be provided as a method, a system, or a computer program product. Therefore, the present invention may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, magnetic disk memory, optical memory, etc.) containing computer-usable code.

The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, and a combination of the process and / or block in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to generate a machine for instructions executed by the processor of the computer or other programmable data processing device Generates a block or blocks specified in a flow chart or flow and / or block diagram Functional device.

These computer program instructions can also be stored in computer readable memory that can guide a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce a manufactured article including a command device The instruction device implements the functions specified in a flowchart or a plurality of processes and / or a block or a plurality of blocks in the block diagram.

These computer program instructions can also be loaded on a computer or other programmable data processing equipment, so that a series of operating steps can be performed on the computer or other programmable equipment to generate computer-implemented processing, and thus on the computer or other programmable equipment The instructions executed on the steps provide steps for implementing the functions specified in one or more of the flowcharts and / or one or more of the block diagrams.

The above description is only the preferred embodiments of the present invention, and is not intended to limit the protection scope of the present invention.

21‧‧‧Non-volatile memory

22‧‧‧Memory Controller

211‧‧‧first storage area

212‧‧‧Check storage area

221‧‧‧cyclic redundancy check unit

222‧‧‧Check value writing unit

223‧‧‧First writing unit

224‧‧‧Storage Unit

225‧‧‧ Matching Unit

226‧‧‧First Reading Unit

Claims (10)

A non-volatile memory control device includes: a non-volatile memory and a memory controller; the non-volatile memory includes: a first storage area for storing first write data; and a check storage area, It is used to store the cyclic redundancy check value corresponding to the first write data; the first storage area is independent of the check storage area; the memory controller includes: a cyclic redundancy check unit for calculating the corresponding data Cyclic redundancy check value; a check value writing unit for writing the cyclic redundancy check value corresponding to the first write data into the check storage area; a first writing unit for writing the first write data Into the first storage area; the register unit is used to register the cyclic redundancy check value corresponding to the read data; the comparison unit is used to compare the cyclic redundancy check value and The cyclic redundancy check value in the register unit corresponding to the read data; the first read unit is used when the cyclic redundancy check value in the check storage area corresponding to the read data and the register unit corresponding to the read data When the cyclic redundancy check value is the same, return the reading ; When the first write data is written into the non-volatile memory, the cyclic redundancy check unit executes to calculate a corresponding cyclic redundancy check value for the first write data, and the check value The writing unit writes the cyclic redundancy check value into the verification storage area, and the first writing unit stores the first write data in the first storage area. The non-volatile memory control device according to claim 1, wherein the memory controller further includes: an alarm unit, configured to read the cyclic redundancy check value and read in the check storage area corresponding to the read data. When the cyclic redundancy check values in the registration unit corresponding to the data are different, an alarm message is returned. The non-volatile memory control device according to claim 1, wherein the non-volatile memory further includes: a second storage area for storing the second write data; the memory controller further includes: a second write A unit for directly writing the second write data into the second storage area; and a second read unit for directly returning the data in the second storage area. The non-volatile memory control device according to claim 1, wherein the first storage area of the non-volatile memory is not adjacent to the check storage area, or the first storage area and the check storage The first addresses of the districts are far apart. The nonvolatile memory control device according to claim 1, wherein in the nonvolatile memory, a unit data of the first storage area A cyclic redundancy check value corresponding to the check memory area. A security chip includes the nonvolatile memory control device according to any one of claims 1 to 5. A non-volatile memory control method, which is used in a non-volatile memory control device as in claim 1, includes the following steps: when a write operation is performed on the first storage area, the cyclic redundancy check unit calculates The cyclic redundancy check value corresponding to the first write data; the cyclic redundancy check value and the first write data are stored separately; the check value writing unit corresponds to the cyclic redundancy check value corresponding to the first write data Write to the check storage area; the first write unit writes the first write data to the first storage area; when a read operation is performed on the first storage area, the cyclic redundancy check unit calculates a cycle corresponding to the read data Redundancy check value; the register unit registers the cyclic redundancy check value corresponding to the read data; the comparison unit compares the cyclic redundancy check value in the check storage area corresponding to the read data with the register unit corresponding to the read data The cyclic redundancy check value in the read; and when the cyclic redundancy check value in the check storage area corresponding to the read data is the same as the cyclic redundancy check value in the register unit corresponding to the read data, the first read The unit returns the reading. The non-volatile storage control method according to claim 7, wherein the non-volatile storage control method further includes: When the cyclic redundancy check value in the check storage area corresponding to the read data is different from the cyclic redundancy check value in the registration unit corresponding to the read data, the alarm unit returns alarm information. The non-volatile storage control method according to claim 7, wherein the non-volatile storage control method further includes: when a write operation is performed on the second storage area, the second write unit directly writes the second write data into the A second storage area; when a read operation is performed on the second storage area, the second reading unit directly returns the data in the second storage area. The non-volatile storage control method according to claim 7, wherein the calculating the cyclic redundancy check value corresponding to the first write data includes: calculating each cyclic redundancy corresponding to each unit of data of the first write data one by one. I check value.