TW201721442A - Secure chip, and nonvolatile storage control device and method for same - Google Patents

Abstract

Disclosed in the present invention are a secure chip, and a nonvolatile storage control device and method for the same. The device comprises a nonvolatile memory and a storage controller. The nonvolatile memory comprises a first storage region and a check storage region. The storage controller comprises a cyclic redundancy check unit, a first write unit, a check value write unit, a register unit, a comparison unit, and a first read unit. The cyclic redundancy check unit is used for calculating a cyclic redundancy check value corresponding to data. The register unit is used for registering the cyclic redundancy check value corresponding to read data. The comparison unit is used for making a comparison between a cyclic redundancy check value in the check storage region corresponding to read data and a cyclic redundancy check value in the register unit corresponding to the read data. The first read unit is used for returning the read data when the cyclic redundancy check value in the check storage region corresponding to the read data is the same as the cyclic redundancy check value in the register unit corresponding to the read data, and otherwise, giving out an alarm signal.

Description

Security chip, nonvolatile memory control device and nonvolatile storage control method

The present invention relates to the field of security wafer technology, and more particularly to a security chip and a nonvolatile memory control device and method thereof.

The security chip refers to the integrated circuit chip with data encryption and anti-security attack technology. It is widely used in digital signage, identity authentication and other fields, such as common public transportation cards and social security cards, such as smart cards and online banking. An example of a secure wafer application.

Attacks on security chips are currently divided into three types: non-intrusive attacks, intrusive attacks, and semi-intrusive attacks. Among them, non-intrusive attacks do not need to directly touch the internal components of the chip, nor do they cause any damage to the wafer. For example, timing attack and power analysis belong to this category; intrusive attacks require direct contact with internal components of the chip, such as chemistry. Corrosion and laser cutting are examples of this type; semi-invasive attacks are between non-intrusive and invasive attacks. They also require the opening of the wafer package to access the wafer surface, but do not require electrical contact with the metal surface. There is no mechanical damage to the cockroaches, such as the common laser attack.

Semi-invasive attacks including light injection, electromagnetic manipulation, radiation injection, etc., specific physical positions at specific moments of safe wafer operation, artificially introducing instantaneous controllable interference signals, changing wafer program flow, memory To obtain sensitive information such as sensitive permission operations and keys, and laser injection is the most common. Due to the concentrated energy of the laser, it is easy to cause the internal logic of the chip to be erroneously flipped, or the memory unit is subjected to transient data errors, thereby jeopardizing the safety of the wafer. At present, the commonly used methods for wafers against laser attacks mainly include the use of a passive mask layer (covering a large area of metal layer on the surface of the wafer), a photosensor, and an additional data check bit. However, the method of the metal mask layer can only be applied to the front side of the wafer due to the limitations of existing processes and manufacturing conditions. If the laser strikes from the back side of the wafer, the metal mask layer does not work; at the same time, the method of the photo sensor is limited to the wafer. The area is limited, so it always exists at a certain density and cannot spread the entire wafer.

1 is a schematic structural view of a prior art security wafer. As shown in FIG. 1, the security wafer mainly includes the following.

The security algorithm unit 101 is configured to implement a security algorithm. In general, security algorithms include RSA (Rivest Shamir Adlemen, a public key encryption) algorithm, AES (Advanced Encryption Standard) algorithm, hash (HASH) algorithm, and the like.

The analog oscillator 102 is used to provide the required clock signal for the entire wafer system.

The power management unit 103 is configured to provide a stable and reliable power supply for the entire wafer, and to cooperate with the system's low power consumption strategy.

The security protection unit 104 generally includes a light sensor, a temperature sensor, a magnetic field sensor, and the like.

Microprocessor and bus bar matrix 105, the microprocessor is the core of the entire chip, it is connected through the bus matrix and various peripherals, thereby passing Software running on the processor to control the operation of the entire system.

The clock and reconfiguration management unit 106 is configured to manage the clock and re-network of the entire wafer.

The interface unit 107 generally includes a communication interface conforming to the ISO 7816 protocol or the ISO 14443 protocol.

The non-volatile memory and its controller 108 typically include a ROM, EEPROM or FLASH, etc., and their corresponding memory controllers.

The dynamic random memory and its controller 109, that is, the memory and memory controller required for the microprocessor to operate.

Generally, in security chips, non-volatile memory (mainly flash memory and EEPROM) always occupies a considerable area, so it is also the easiest target for semi-intrusive security attacks, but for non-volatile Memory security has also been one of the key considerations for secure chip design.

In order to solve the technical problems existing in the prior art, embodiments of the present invention are expected to provide a security chip and a non-volatile memory control apparatus and method thereof, which can realize non-volatileness in a security chip with a small hardware and system overhead. Protection of stored data.

The technical solution of the embodiment of the present invention is implemented as follows.

Embodiments of the present invention provide a nonvolatile memory control device including: a nonvolatile memory and a memory controller.

The non-volatile memory includes: a first storage area and a verification storage area.

The first storage area is configured to store the first write data.

Verifying the storage area for storing the cyclic redundancy check corresponding to the first write data Test value.

The memory controller includes: a cyclic redundancy check unit, a check value write unit, a first write unit, a registration unit, a comparison unit, and a first read unit.

A cyclic redundancy check unit is used to calculate a cyclic redundancy check value corresponding to the data.

The check value writing unit is configured to write the cyclic redundancy check value corresponding to the first write data into the check storage area.

The first writing unit is configured to write the first write data into the first storage area.

The registration unit is configured to register a cyclic redundancy check value corresponding to the read data.

The comparison unit is configured to compare the cyclic redundancy check value in the check storage area corresponding to the read data and the cyclic redundancy check value in the registration unit corresponding to the read data.

The first reading unit is configured to return the read data when the cyclic redundancy check value in the check storage area corresponding to the read data is the same as the cyclic redundancy check value in the register unit corresponding to the read data.

In the above solution, the memory controller further includes: an alarm unit, configured to: when the read data corresponds to the cyclic redundancy check value in the check storage area and the cyclic redundancy check value in the register unit corresponding to the read data When not the same, the alarm information is returned.

In the above solution, the non-volatile memory further includes: a second storage area, configured to store the second write data.

The memory controller further includes: a second write unit for directly writing the second write data to the second storage area; and a second read unit for directly returning the data in the second storage area.

In the above solution, the first storage area of the non-volatile memory is not adjacent to the verification storage area, or the first storage area is far from the first address of the verification storage area.

In the above solution, in the non-volatile memory, one unit data of the first storage area corresponds to a cyclic redundancy check value of the verification storage area.

The embodiment of the invention further provides a security chip, which includes any of the above non-volatile memory control devices.

The embodiment of the present invention further provides a non-volatile storage control method, the method includes: when performing a write operation on the first storage area, the cyclic redundancy check unit calculates a cyclic redundancy check value corresponding to the first write data; The check value writing unit writes the cyclic redundancy check value corresponding to the first write data into the check storage area; the first write unit writes the first write data into the first storage area; When the storage area performs a read operation, the cyclic redundancy check unit calculates a cyclic redundancy check value corresponding to the read data; the registration unit registers the cyclic redundancy check value corresponding to the read data; and the comparison unit compares the read data corresponding to the school Verifying the cyclic redundancy check value in the storage area and the cyclic redundancy check value in the register unit corresponding to the read data; the cyclic redundancy check value and the read data corresponding to the check storage area corresponding to the read data When the cyclic redundancy check value in the registration unit is the same, the first read unit returns the read data.

In the above solution, the method further includes: when the cyclic redundancy check value in the check storage area corresponding to the read data is different from the cyclic redundancy check value in the register unit corresponding to the read data, the alarm unit returns an alarm. News.

In the above solution, the method further includes: when performing a write operation on the second storage area, the second write unit directly writes the second write data to the second storage When the read operation is performed on the second storage area, the second read unit directly returns the data in the second storage area.

In the above solution, the calculating the cyclic redundancy check value corresponding to the first write data comprises: calculating a cyclic redundancy check value corresponding to each unit data of the first write data one by one.

The security chip and the non-volatile memory control device and method provided by the embodiments of the present invention can perform eigenvalue calculation by using a dedicated cyclic redundancy check circuit for important data in the non-volatile memory, and The feature value is stored separately from the important data, so that when the non-volatile memory of the security chip is attacked, the system can timely discover whether the important data has been tampered with, and then can promptly alarm or take other countermeasures. The cyclic redundancy check circuit is used to calculate the eigenvalues, the hardware and software implementation complexity is low, and the system performance loss is small.

21‧‧‧ Non-volatile memory

22‧‧‧Memory Controller

101‧‧‧Security algorithm unit

102‧‧‧ Analog Oscillator

103‧‧‧Power Management Unit

104‧‧‧Safety protection unit

105‧‧‧Microprocessor and Bus Bar Matrix

106‧‧‧clock and re-management unit

107‧‧‧Interface unit

108‧‧‧ Non-volatile memory and its controller

109‧‧‧Dynamic random memory and its controller

211‧‧‧First storage area

212‧‧‧Check storage area

221‧‧‧Cyclic Redundancy Check Unit

222‧‧‧Check value writing unit

223‧‧‧first writing unit

224‧‧‧Registering unit

225‧‧‧ comparison unit

226‧‧‧ first reading unit

301~307‧‧‧Steps

1 is a schematic structural view of a prior art security wafer.

2 is a schematic structural diagram of a structure of a nonvolatile memory control device according to an embodiment of the present invention.

FIG. 3 is a schematic flowchart of an implementation process of a non-volatile storage control method according to an embodiment of the present invention.

In order to more clearly illustrate the embodiments and technical solutions of the present invention, the technical solutions of the present invention will be described in more detail below with reference to the drawings and embodiments. It is obvious that the described embodiments are a part of the embodiments of the present invention, and not all Example. General techniques in the art based on embodiments of the invention All other embodiments obtained by a person without creative efforts are within the scope of the present invention.

In the embodiment of the present invention, the non-volatile memory in the security chip and its controller are collectively referred to as a non-volatile memory control device, such as the non-volatile memory in FIG. 1 and its controller 108. It is called a non-volatile memory control device.

2 is a schematic structural diagram of a nonvolatile memory control device according to an embodiment of the present invention. As shown in FIG. 2, the device includes a nonvolatile memory 21 and a memory controller 22.

The non-volatile memory 21 includes: a first storage area 211 and a verification storage area 212; wherein the first storage area 211 is configured to store the first write data; and the verification storage area 212 is configured to store a cycle corresponding to the first write data. Redundancy check value.

The memory controller 22 includes a cyclic redundancy check unit 221, a check value write unit 222, a first write unit 223, a registration unit 224, a comparison unit 225, and a first read unit 226.

The cyclic redundancy check unit 221 is configured to calculate a cyclic redundancy check value corresponding to the data.

The check value writing unit 222 is configured to write the cyclic redundancy check value corresponding to the first write data into the check storage area 212.

The first writing unit 223 is configured to write the first write data into the first storage area 211.

The register unit 224 is configured to register a cyclic redundancy check value corresponding to the read data.

The comparing unit 225 is configured to compare the cyclic redundancy check value in the check storage area 212 corresponding to the read data with the cyclic redundancy check value in the register unit 224 corresponding to the read data.

The first reading unit 226 is configured to return the read data when the cyclic redundancy check value in the check storage area 212 corresponding to the read data is the same as the cyclic redundancy check value in the register unit 224 corresponding to the read data. .

Specifically, the first written data is usually very important information. Once such data is tampered with or lost, it will cause losses to users of the security chip, such as user keys, recharge card balance information, and the like. Therefore, such information needs to be specifically protected. When the security chip writes such material (first write data) into the nonvolatile memory 21, the first write data should be stored in the first storage area 211. In order to enhance the protection of the first write data, in the embodiment of the present invention, the memory controller 22 includes a cyclic redundancy check unit 221, and can calculate a corresponding cyclic redundancy check value for the first write data, and The cyclic redundancy check value is written to the check storage area 212 by the check value writing unit 222. Correspondingly, the first write data is written by the first write unit 223 to the first storage area 211.

Here, the selection of the polynomial used to calculate the cyclic redundancy check value may not be fixed, and the security chip may be selected according to the needs of the application. Commonly used and standard cyclic redundancy check value generator polynomials are: X8+X5+X4+1, X16+X15+X2+1, X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+ X5+X4+X2+1 and so on. However, no matter which polynomial is chosen, the advantage of cyclic redundancy check is that the implementation of the hardware is less difficult, the logic resources are less, and the space required for storing the check value is also small. This is sensitive to some cost and power consumption Security chips (such as smart cards) are extremely advantageous.

When the security chip reads the data of the first storage area 211 in the non-volatile memory 21, that is, when the read address is in the first storage area 211, the data corresponding to the read address is referred to as "read data". Then, the cyclic redundancy check unit 221 of the memory controller 22 calculates a cyclic redundancy check value corresponding to the read data, and registers the cyclic redundancy check value corresponding to the read data by the register unit 224; then, the comparison unit 225: the cyclic redundancy check value in the check storage area 212 corresponding to the read data and the cyclic redundancy check value in the register unit 224 corresponding to the read data; in the check storage area 212 corresponding to the read data When the cyclic redundancy check value is the same as the cyclic redundancy check value in the register unit 224 corresponding to the read data, the non-volatile memory 21 is not destroyed, and the first read unit 226 returns the security chip to the security chip. Read the materials.

Preferably, in the above control device, the memory controller 22 further includes: an alarm unit, and a registration unit 224 corresponding to the cyclic redundancy check value and the read data in the check storage area 212 corresponding to the read data. When the cyclic redundancy check values are different, the alarm information is returned to the security chip.

Further, the returning the alarm information to the security chip may include: the alarm unit sends an alarm signal to the internal microprocessor of the security chip or the chip system control unit; and the security signal may be securely protected and processed by the security chip firmware or the hardware system, for example, The inside of the chip is powered off or reset.

In some embodiments, some non-essential data may also be stored in the non-volatile memory 21, and such data does not need special protection. Therefore, in the above non-volatile memory control device, as shown in FIG. The non-volatile memory 21 may further include: a second storage area for storing the second write capital Here, the second written data refers to the type of information that does not require special protection.

Correspondingly, the memory controller 22 may further include: a second write unit for directly writing the second write data to the second storage area; and a second read unit for directly returning to the second storage area data.

In this way, the non-volatile memory control device uses different storage control strategies for the stored data according to different factors such as the data security level and importance, thereby improving flexibility.

Further, in order to reduce the probability that the first storage area 211 and the verification storage area 212 of the non-volatile memory 21 are simultaneously attacked, in the above control device, the first storage area 211 of the non-volatile memory 21 is calibrated. Preferably, the memory areas 212 are not adjacent, for example, such that they are separated by a second memory area; or the first address of the first memory area 211 is at a relatively long distance from the first address of the verification memory area 212.

Further, in the non-volatile memory 21, one unit data of the first storage area 211 corresponds to one cyclic redundancy check value of the verification storage area 212.

Specifically, an important data may need to be stored in multiple storage units. Here, the storage unit may be 1 byte or 1 page, which is determined according to the read/write bandwidth of the non-volatile memory 21 and the application scenario; In order to improve security, in some embodiments, a cyclic redundancy check value is separately calculated for each unit data of a first write data, so that an important data will correspond to more than one cyclic redundancy. Check value.

In practical applications, the non-volatile memory 21 may be a one-time programmable read-only memory (OTP ROM), electrically erasable and programmable. The read memory (EEPROM) or flash memory (Flash), the memory controller 22 can be implemented by a control circuit.

The embodiment of the invention further provides a security chip, which includes any of the above non-volatile memory control devices.

The embodiment of the present invention further provides a non-volatile storage control method. As shown in FIG. 3, the method includes: when performing a write operation on the first storage area, in step 301, the cyclic redundancy check unit calculates the first write data. Corresponding cyclic redundancy check value.

Step 302: The check value writing unit writes the cyclic redundancy check value corresponding to the first write data into the check storage area.

Step 303: The first write unit writes the first write data into the first storage area.

When a read operation is performed on the first storage area, in step 304, the cyclic redundancy check unit calculates a cyclic redundancy check value corresponding to the read data.

Step 305, the registration unit registers the cyclic redundancy check value corresponding to the read data.

Step 306: The comparison unit compares the cyclic redundancy check value in the check storage area corresponding to the read data with the cyclic redundancy check value in the register unit corresponding to the read data.

Step 307: When the cyclic redundancy check value in the check storage area corresponding to the read data is the same as the cyclic redundancy check value in the register unit corresponding to the read data, the first read unit returns the read data.

Preferably, the method further includes: when the read data corresponds to the cyclic redundancy check value in the check storage area and When the cyclic redundancy check value in the registration unit corresponding to the read data is different, the alarm unit returns the alarm information.

Further, the method may further include: when performing a write operation on the second storage area, the second write unit directly writes the second write data to the second storage area; when performing the read operation on the second storage area, The second reading unit directly returns the data in the second storage area.

Further, in the above method, the calculating the cyclic redundancy check value corresponding to the first write data comprises: calculating, according to each unit data of the first write data, a cyclic redundancy check value corresponding thereto.

Those skilled in the art will appreciate that embodiments of the present invention can be provided as a method, system, or computer program product. Thus, the invention may take the form of a hardware embodiment, a software embodiment, or an embodiment incorporating a software and a hardware. Moreover, the present invention can take the form of a computer program product embodied on one or more computer usable storage media (including but not limited to disk memory and optical memory, etc.) including computer usable code.

The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (system), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of flowcharts and/or block diagrams, and combinations of flows and/or blocks in the flowcharts and/or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, a special purpose computer, an embedded processor or other programmable data processing device to produce a machine for executing instructions by a processor of a computer or other programmable data processing device Generated for implementation in a flow or a flow or a block diagram in a block or blocks Functional device.

The computer program instructions can also be stored in a computer readable memory that can boot a computer or other programmable data processing device to operate in a particular manner, such that instructions stored in the computer readable memory produce an article of manufacture including the instruction device. The instruction device implements the functions specified in one or more flows of the flowchart or in a block or blocks of the flowchart.

These computer program instructions can also be loaded onto a computer or other programmable data processing device to perform a series of operational steps on a computer or other programmable device to produce computer-implemented processing on a computer or other programmable device. The instructions executed on the steps provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of the flowchart.

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention.

21‧‧‧ Non-volatile memory

22‧‧‧Memory Controller

211‧‧‧First storage area

212‧‧‧Check storage area

221‧‧‧Cyclic Redundancy Check Unit

222‧‧‧Check value writing unit

223‧‧‧first writing unit

224‧‧‧Registering unit

225‧‧‧ comparison unit

226‧‧‧ first reading unit

Claims (10)

A non-volatile memory control device includes: a non-volatile memory and a memory controller; the non-volatile memory includes: a first storage area for storing a first write data; a check storage area, And a cyclic redundancy check value corresponding to the first write data; the memory controller includes: a cyclic redundancy check unit, configured to calculate a cyclic redundancy check value corresponding to the data; and a check value write unit, Writing a cyclic redundancy check value corresponding to the first write data to the check storage area; a first write unit for writing the first write data to the first storage area; and a register unit for registering the read The cyclic redundancy check value corresponding to the data; the comparison unit is configured to compare the cyclic redundancy check value in the check storage area corresponding to the read data and the cyclic redundancy check in the register unit corresponding to the read data a first reading unit, configured to return the read data when the cyclic redundancy check value in the check storage area corresponding to the read data is the same as the cyclic redundancy check value in the register unit corresponding to the read data . A nonvolatile memory control device as recited in claim 1, wherein The memory controller further includes: an alarm unit, configured to: when the cyclic redundancy check value in the check storage area corresponding to the read data is different from the cyclic redundancy check value in the register unit corresponding to the read data , return to the alarm information. The non-volatile memory control device of claim 1, wherein the non-volatile memory further comprises: a second storage area for storing the second write data; the memory controller further comprising: the second write a unit for directly writing the second write data to the second storage area; and a second read unit for directly returning the data in the second storage area. The non-volatile memory control device of claim 1, wherein the first storage area of the non-volatile memory is not adjacent to the verification storage area, or the first storage area and the verification storage The first addresses of the district are far apart. The non-volatile memory control device of claim 1, wherein a unit data of the first storage area corresponds to a cyclic redundancy check value of the storage area in the non-volatile memory. A security chip comprising the nonvolatile memory control device according to any one of claims 1 to 5. A non-volatile storage control method includes the following steps: when performing a write operation on the first storage area, the cyclic redundancy check unit calculates a cyclic redundancy check value corresponding to the first write data; The check value writing unit writes the cyclic redundancy check value corresponding to the first write data into the check storage area; the first write unit writes the first write data into the first storage area; when the first storage is When the area performs a read operation, the cyclic redundancy check unit calculates a cyclic redundancy check value corresponding to the read data; the register unit registers the cyclic redundancy check value corresponding to the read data; and the comparison unit compares the read data corresponding to the school Verifying the cyclic redundancy check value in the storage area and the cyclic redundancy check value in the registration unit corresponding to the read data; and the cyclic redundancy check value and the read data in the check storage area corresponding to the read data When the corresponding cyclic redundancy check value in the register unit is the same, the first read unit returns the read data. The non-volatile storage control method as claimed in claim 7, wherein the non-volatile storage control method further comprises: the cyclic redundancy check value and the read data corresponding to the read storage area corresponding to the read data When the cyclic redundancy check values in the registration unit are different, the alarm unit returns an alarm message. The nonvolatile storage control method as claimed in claim 7, wherein the nonvolatile storage control method further comprises: when performing a write operation on the second storage area, the second write unit directly writes the second write data to the a second storage area; when performing a read operation on the second storage area, the second read unit directly returns the data in the second storage area. The non-volatile storage control method as claimed in claim 7, wherein the calculating the cyclic redundancy check value corresponding to the first write data comprises: calculating, by each unit of the first write data, a cyclic redundancy corresponding thereto The remaining check value.