TWI618240B - Semiconductor device - Google Patents

Abstract

A semiconductor device includes a plurality of first wires, a plurality of second wires, a first conductive layer, and a second conductive layer. Each of the first wires forms a closed polygon and surrounds a center. Each of the second wires forms the closed polygon and surrounds the center, wherein the first and second wires are arranged alternately with each other, and any one of the first and second wires are not connected. The first conductive layer is a full-surface structure, located above the first and second wires, and coupled to the first wire. The second conductive layer is a full-surface structure, is disposed on the first and second wires, and is coupled to the second wire, wherein the first conductive layer is located between the second conductive layer and the first and second wires, and 1. The second conductive layers are not connected.

Description

Semiconductor device

The present invention relates to a semiconductor device, and more particularly to a circuit layout for a diode.

In recent years, the development of semiconductor devices has been trending towards miniaturization, but the physical properties of some semiconductor devices are affected by this. For example, the driving current of a diode is proportional to the perimeter of the junction, so how effective is it. The use of an area to increase the junction perimeter of the diode to maintain the miniaturization of the device and to obtain a large drive current is an important issue for those skilled in the art.

In view of this, an embodiment of the present invention provides a semiconductor device including a plurality of first wires, a plurality of second wires, a first conductive layer, and a second conductive layer. Each of the first wires forms a closed polygon and surrounds a center. Each of the second wires forms the closed polygon and surrounds the center, wherein the first and second wires are arranged alternately with each other, and any one of the first and second wires are not connected. The first conductive layer is a full-surface structure, located above the first and second wires, and coupled to the first wire. The second conductive layer is a full-surface structure, is disposed on the first and second wires, and is coupled to the second wire, wherein the first conductive layer is located between the second conductive layer and the first and second wires, and 1. The second conductive layers are not connected.

According to an embodiment of the invention, the first conductive layer and the upper layer The second conductive layer is a single piece of complete copper foil.

According to an embodiment of the invention, the first conductive layer and the upper layer Any one of the second conductive layers covers all of the first wire and the second wire from above.

According to an embodiment of the invention, the semiconductor device further includes The plurality of first conductive columns and the plurality of second conductive columns. The first conductive pillar is coupled to the first conductive layer and the first conductive line. The plurality of second conductive pillars are coupled to the second conductive layer and the second conductive line.

According to an embodiment of the invention, the first conductive layer is formed with And a plurality of through holes, and the second conductive pillars are coupled to the second conductive layer and the second wires through the through holes.

According to an embodiment of the invention, the second conductive pillar and the upper The first conductive layers are not connected.

According to an embodiment of the invention, the through hole is along the seal The outlines of the closed polygons are arranged, and the through holes are spaced apart from each other by a distance.

According to an embodiment of the invention, the closed polygon is a Regular polygon, a circle or an ellipse.

According to an embodiment of the invention, the semiconductor device is a The diode further includes a plurality of P-type doped layers and a plurality of N-type doped layers, and the first wire is coupled to the P-type doped layer, and the second wire is coupled to the N-type doped layer.

According to an embodiment of the present invention, each of the first wires It is a diode positive terminal, and each of the second wires is a diode negative terminal.

The above described objects, features and advantages of the present invention will become more apparent from the aspects of the appended claims.

10‧‧‧ diode

11‧‧‧P type doped layer

12‧‧‧N-doped layer

21‧‧‧First wire

22‧‧‧second wire

23‧‧‧ Center

41‧‧‧First conductive layer

42‧‧‧First Conductive Column

43‧‧‧Second conductive layer

44‧‧‧Second conductive column

45‧‧‧through holes

1 is a partial cross-sectional view showing a diode according to an embodiment of the present invention.

Figure 2 is a top view showing a diode according to an embodiment of the present invention.

Figure 3 is a top view showing a diode according to another embodiment of the present invention.

Figure 4 is a partial cross-sectional view showing a diode according to still another embodiment of the present invention.

Figure 5A is a top view showing a first conductive layer in accordance with an embodiment of the present invention.

Figure 5B is a top view showing a second conductive layer in accordance with an embodiment of the present invention.

Figure 6A is a top view showing a first conductive layer in accordance with another embodiment of the present invention.

Figure 6B is a top view showing a second conductive layer in accordance with another embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described with reference to the related drawings. In the drawings, the shapes and dimensions of some of the elements of the embodiments are expanded to facilitate the identification and clarity. In addition, it is not shown in the drawings or is not described in the specification. The elements are in a form known to those of ordinary skill in the art.

Figure 1 is a diagram showing a diode according to an embodiment of the present invention. Partial section view. Figure 2 is a top view showing a diode according to an embodiment of the present invention. As shown in FIG. 1 and FIG. 2 , the diode 10 is, for example, a Schottky diode or a fast recovery diode, but is not limited thereto. a plurality of P-type doped layers 11, a plurality of N-type doped layers 12, a plurality of first conductive lines 21, and a plurality of second conductive lines 22, wherein the first conductive lines 21 are stacked on the P-type doped layer 11 and coupled to the P-type The doped layer 11 and the second wire 22 are stacked on the N-type doped layer 12 and coupled to the N-type doped layer 12 . However, according to another embodiment of the present invention, the first wire 21 is stacked on the N-type doped layer 12 and coupled to the N-type doped layer 12, and the second wire 22 is stacked on the P-type doped layer. 11 is coupled to the P-type doped layer 11. It should be understood that the P-type doped layer 11 and the N-type doped layer 12 under the first conductive line 21 and the second conductive line 22 are not shown in FIG.

As shown in FIG. 2, each of the first wire 21 and the second wire 22 The system forms a closed circle and surrounds a center 23. More specifically, the first wire 21 and the second wire 22 are formed in concentric circles arranged alternately with each other, and any one of the first and second wires 21 and 22 is not connected. According to an embodiment of the present invention (Fig. 2), a second wire 22 is disposed in the middle of each of the two first wires 21, and the outermost side of the first wire 21 and the second wire 22 is a first A wire 21. According to another embodiment of the present invention, the outermost side of the first wire 21 and the second wire 22 is a second wire 22, and a first wire 21 is disposed in the middle of each of the two second wires 22.

It should be understood that the first wire 21 and the second wire 22 are between Having a wire spacing, and the minimum spacing of the wires is based on the semiconductor process Determined by the design rule. Furthermore, when the first wire 21 is coupled to the P-type doped layer 11 and the second wire 22 is coupled to the N-type doped layer 12, the first wire 21 and the second wire 22 respectively represent the diode 20 Positive and negative ends. On the contrary, when the first wire 21 is coupled to the N-type doped layer 12 and the second wire 22 is coupled to the P-type doped layer 11, the second wire 22 and the first wire 21 respectively represent the positive of the diode 20 Extreme and negative side. Since neither of the first and second wires 21 and 22 are connected, it is possible to prevent a short circuit from occurring.

It should be specially noted that, in this embodiment, the first wire is located. 21 and the P-type doped layer 11 and the N-type doped layer 12 under the second wire 22 form a plurality of concentric circles having junctions arranged alternately. By repeating the stacked structure from the inside to the outside, the junction circumference of the diode 10 can be effectively increased to increase the driving current thereof, and the area of the diode 10 does not need to be increased (area efficiency can be improved). ), thereby facilitating miniaturization of the device. Further, compared with the existing diode, since the diode 10 of the embodiment can obtain the same magnitude of driving current with a small effective device area, the manufacturing cost of the device can be greatly reduced, and the product competitiveness can be improved. .

Figure 3 is a diagram showing a diode according to another embodiment of the present invention. Upper view. In order to explain the technical features of the present embodiment in detail, the following description will be made together with the first drawing. As shown in FIG. 1 and FIG. 3, the diode 10 is, for example, a Schottky diode or a fast recovery diode, but is not limited thereto. a plurality of P-type doped layers 11, a plurality of N-type doped layers 12, a plurality of first conductive lines 21, and a plurality of second conductive lines 22, wherein the first conductive lines 21 are stacked on the P-type doped layer 11 and coupled to the P-type The doped layer 11 and the second wire 22 are stacked on the N-type doped layer 12 and coupled to the N-type doped layer 12 . Of course According to another embodiment of the present invention, the first conductive line 21 is stacked on the N-type doped layer 12 and coupled to the N-type doped layer 12, and the second conductive line 22 is stacked on the P-type doped layer. 11 is coupled to the P-type doped layer 11. It should be understood that the P-type doped layer 11 and the N-type doped layer 12 under the first conductive line 21 and the second conductive line 22 are not shown in FIG.

As shown in FIG. 3, each of the first wire 21 and the second wire 22 The system forms a closed ellipse and surrounds a center 23. More specifically, the first wire 21 and the second wire 22 are formed as concentric ellipses arranged alternately with each other, and any of the first and second wires 21 and 22 are not connected. According to an embodiment of the present invention (Fig. 3), a second wire 22 is disposed in the middle of each of the two first wires 21, and the outermost side of the first wire 21 and the second wire 22 is a first A wire 21. According to another embodiment of the present invention, the outermost side of the first wire 21 and the second wire 22 is a second wire 22, and a first wire 21 is disposed in the middle of each of the two second wires 22.

It should be understood that the first wire 21 and the second wire 22 are between There is a wire spacing, and the minimum spacing of the wires is determined by the design rule of the semiconductor process. Furthermore, when the first wire 21 is coupled to the P-type doped layer 11 and the second wire 22 is coupled to the N-type doped layer 12, the first wire 21 and the second wire 22 respectively represent the diode 20 Positive and negative ends. On the contrary, when the first wire 21 is coupled to the N-type doped layer 12 and the second wire 22 is coupled to the P-type doped layer 11, the second wire 22 and the first wire 21 respectively represent the positive of the diode 20 Extreme and negative side. Since neither of the first and second wires 21 and 22 are connected, it is possible to prevent a short circuit from occurring.

It should be specially noted that, in this embodiment, the first wire is located. 21 and the P-type doped layer 11 and the N-type doped layer 12 under the second wire 22 form a plurality of concentric ellipses having junctions arranged in an alternating manner. By repeating the stacked structure from the inside to the outside, the junction perimeter of the diode 10 can be effectively increased to increase the driving current thereof, and the area of the diode 10 does not need to be increased (area efficiency can be improved) )), thereby facilitating miniaturization of the device. Further, compared with the existing diode, since the diode 10 of the embodiment can obtain the same magnitude of driving current with a small effective device area, the manufacturing cost of the device can be greatly reduced, and the product competitiveness can be improved. .

In addition, the first wire shown in Figure 2 and Figure 3 The first wire 21 and the second wire 22 are respectively coupled via a contact point. Connected to the P-type doped layer 11 and the N-type doped layer 12. According to another embodiment of the present invention, the first wire 21 and the second wire 22 are respectively coupled to the N-type doping layer 12 and the P-type doping layer 11 via contact points.

Although each of the first and second wires 21 and 22 of the above embodiment The system forms a closed circular or elliptical shape, but it can also form a closed regular quadrilateral, a regular hexagon, a regular octagon, or any other closed pattern.

Figure 4 is a diagram showing a dipole according to still another embodiment of the present invention. A partial cross-sectional view of the body. In order to explain the technical features of the present embodiment in detail, the following description will be made together with the second drawing. As shown in FIG. 2 and FIG. 4, the diode 10 is, for example, a Schottky diode or a fast recovery diode, but is not limited thereto. a plurality of P-type doped layers 11, a plurality of N-type doped layers 12, a plurality of first conductive lines 21, a plurality of second conductive lines 22, a first conductive layer 41, a plurality of first conductive vias 42, and a second The conductive layer 43 and the plurality of second conductive pillars 44. It should be understood that the circuit layouts of the P-type doped layer 11, the N-type doped layer 12, the first conductive line 21, and the second conductive line 22 of the present embodiment are referred to the alternating concentric arrangement shown in FIG. Therefore, we will not repeat them here. In the present embodiment, the first conductive layer 41 is disposed on the first conductive line 21 and the second conductive line 22, and is coupled to the first conductive line 21 (and the P-type doped layer 11) through the first conductive pillar 42. The second conductive layer 43 is disposed on the first conductive line 21 and the second conductive line 22, and is coupled to the second conductive line 22 (and the N-type doped layer 12) through the second conductive pillar 44. In addition, the first conductive layer 41 is located between the second conductive layer 43 and the first and second wires 21 and 22, and the first conductive layer 41 and the second conductive layer 43 are not connected.

It should be particularly noted that the first conductive layer 41 of the embodiment and The second conductive layers 43 are all a whole-area structure. Referring to FIG. 5A and FIG. 5B together, respectively, top views of the first conductive layer 41 and the second conductive layer 43 according to an embodiment of the present invention are shown. As shown in FIG. 5A and FIG. 5B , the first conductive layer 41 and the second conductive layer 43 are all a circular full-surface structure, and the first conductive layer 41 is formed with a plurality of through holes 45 , wherein the through holes 45 are along the edge. The closed circular contours formed by the second wires 22 as shown in FIG. 2 are arranged at a distance from each other, so that the second conductive pillars 44 as shown in FIG. 4 can be coupled through the through holes 45. Connected to the second conductive layer 43 and the second conductive line 22 (and the N-type doped layer 12). It is to be noted that the first conductive layer 41 and the second conductive layer 43 in this embodiment have substantially the same area, and any of the first conductive layer 41 and the second conductive layer 43 may cover all of the above. The first wire 21 and the second wire 22.

Thereby, a driving voltage can pass through the first guide The electric layer 41 and the second conductive layer 43 are uniformly applied between the P-type doped layer 11 and the N-type doped layer 12, and the P-type doped layer 11 and the N-type doping on the inside and outside of the diode 10 are made. The driving voltages supplied between the hybrid layers 12 can be uniform. As a result, the driving currents generated by the plurality of junctions between the P-doped layer 11 and the N-type doped layer 12 of the diode 10 can be ideally added to improve the overallity of the diode 10. Drive current.

On the contrary, if the narrow wire of the prior art is substituted for the embodiment The first conductive layer 41 and the second conductive layer 43 of the entire surface structure may have a high resistance value due to a narrow wire, which may result in the P-type doped layer 11 and the N-type doped layer 12 located inside and outside the diode. The driving voltages supplied are inconsistent (for example, the driving voltage on the outer side is greater than the driving voltage on the inner side), and thus the driving current generated by the plurality of junctions between the P-type doping layer 11 of the diode and the N-type doping layer 12 There will also be inconsistent sizes (even some junctions will not generate drive current), causing the overall drive current of the diode to drop.

It is worth mentioning that the first conductive layer 41 and the first embodiment of the present embodiment The two conductive layers 43 can cover all of the first wires 21 and the second wires 22 from above according to the number of turns of the first wires 21 and the second wires 22 and the area design. Therefore, when the number of turns and the area of the first wire 21 and the second wire 22 increase, the driving voltage supplied between the P-type doping layer 11 and the N-type doping layer 12 inside and outside the diode 10 is still It can be said that the driving currents generated by the plurality of junctions between the P-doped layer 11 of the diode 10 and the N-type doped layer 12 can still be ideally added to improve the overallity of the diode 10. Drive current. On the other hand, the diode of the narrow wire of the prior art may have an overall driving current which may not be ideally increased as the number of turns and the area of the first wire 21 and the second wire 22 increase. improve.

According to an embodiment of the present invention, the through hole 45 is shown in FIG. The hole wall is provided with an insulating material to prevent the second conductive post 44 from being connected to the first conductive layer 41 to cause a short circuit. In addition, a dielectric layer may be separately disposed between the first conductive layer 41 and the second conductive layer 43 and the first conductive layer 41, the P-type doped layer 11, and the N-type doped layer 12 (in FIG. 4) Not shown) to form insulation.

Although the first conductive layer 41 and the second conductive layer are shown in FIG. The 43 series are respectively coupled to the P-type doped layer 11 and the N-type doped layer 12, but may be coupled to the N-type doped layer 12 and the P-type doped layer 11, respectively.

According to another embodiment of the present invention, the first and second wires 21 and Each of 22 forms a closed ellipse (as shown in Figure 3). In this case, the first conductive layer 41 and the second conductive layer 43 may each have an elliptical full-surface structure (see FIGS. 6A and 6B), and the first conductive layer 41 is formed with a plurality of through holes 45, The through holes 45 are arranged along the contour of the closed ellipse formed by the second wires 22 as shown in FIG. 3, and are spaced apart from each other by a distance, so that the second conductive post 44 as shown in FIG. 4 can be worn. The second conductive layer 43 and the second conductive line 22 (and the N-type doped layer 12) are coupled to the through hole 45. Similarly, the first conductive layer 41 and the second conductive layer 43 may have substantially the same area, and any of the first conductive layer 41 and the second conductive layer 43 may cover all of the first wires 21 and the second wires from above. twenty two. In this way, the driving currents generated by the plurality of junctions between the P-doped layer 11 and the N-type doped layer 12 of the diode 10 of the present embodiment can also be ideally added to increase the polarity. The overall drive current of body 10.

Additionally, in accordance with some embodiments of the present invention, when the first and second Each of the wires 21 and 22 forms a regular quadrangle, a regular hexagon, and a positive octagon In the case of a shape or any other closed pattern, the shape of the first conductive layer 41 and the second conductive layer 43 and the circuit layout of the first conductive pillar 42, the second conductive pillar 44, and the through hole 45 only need to be correspondingly changed.

In the above embodiment, the first conductive layer 41 and the second conductive layer 43 can be a single piece of complete copper foil or other optional metal film.

According to some embodiments of the invention, the first conductive layer 41 or/and The number of the two conductive layers 43 may also be plural, but the first conductive layer 41 and the second conductive layer 43 may be disposed alternately and in a non-connecting manner.

It is added that although the first conductive layer 41 shown in FIG. 4 is And the second conductive layer 43 is respectively located in the second metal layer (metal-2 layer) and the third metal layer (metal-3 layer) in the semiconductor process, but may also be respectively located in the first metal layer (first, second Wires 21 and 22) are any of the different metal layers above.

Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. Those skilled in the art having the ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (9)

A semiconductor device comprising: a plurality of first wires, wherein each of the first wires forms a closed polygon and surrounds a center; and a plurality of second wires, wherein each of the second wires forms the closed polygon And surrounding the center, wherein the first and second wires are arranged alternately with each other, and any one of the first and second wires is not connected; a first conductive layer is a full-surface structure The first and second wires are coupled to the first wire; and the second conductive layer is a full-surface structure, located on the first and second wires, and coupled to the second a wire, wherein the first conductive layer is located between the second conductive layer and the first and second wires, and the first and second conductive layers are not connected; wherein one of the first wires passes through a plurality The first conductive pillars are coupled to the first conductive layer; and wherein one of the second conductive wires is coupled to the second conductive layer via a plurality of second conductive pillars. The semiconductor device according to claim 1, wherein the first conductive layer and the second conductive layer are each a single piece of complete copper foil. The semiconductor device according to claim 1, wherein any one of the first conductive layer and the second conductive layer covers all of the first conductive line and the second conductive line from above. The semiconductor device according to claim 1, wherein the first guide The electric layer is formed with a plurality of through holes, and the second conductive post is coupled to the second conductive layer and the second wire through the through hole. The semiconductor device according to claim 4, wherein the second conductive pillar and the first conductive layer are not connected. The semiconductor device according to claim 4, wherein the through holes are arranged along a contour of the closed polygon, and the through holes are spaced apart from each other by a distance. The semiconductor device according to claim 1, wherein the closed polygon is a regular polygon, a circle or an ellipse. The semiconductor device of claim 1, wherein the semiconductor device is a diode, further comprising a plurality of P-type doped layers and a plurality of N-type doped layers, and the first wire is coupled to the P The doped layer is coupled to the N-type doped layer. The semiconductor device of claim 8, wherein each of the first wires is a diode positive terminal, and each of the second wires is a diode negative terminal.