TW201838135A - Semiconductor structure - Google Patents

Abstract

A semiconductor structure is disclosed. The semiconductor structure includes an ESD protection device. The ESD protection device includes a first MOSFET, a ring well and a base grounding region. The first MOSFET includes a gate, a source, a drain and a first base well. The first base well has a first type conductivity. The ring well has a second type conductivity opposing to the first type conductivity. The semiconductor structure also includes a second MOSFET. The second MOSFET includes a second base well. The second base well has the second type conductivity. The base grounding region is in a portion of the first base well between the gate, the source and the drain of the first MOSFET and the second base well of the second MOSFET and is surrounded by the ring well.

Description

Semiconductor structure

This invention relates to a semiconductor structure and, more particularly, to a semiconductor structure having an electrostatic discharge protection device.

Electrostatic discharge is a phenomenon in which an electrostatic charge on a non-conductive surface migrates through a conductive material. Since the electrostatic voltage is usually quite high, electrostatic discharge can easily damage the substrate and other components of an integrated circuit. In order to protect the integrated circuit from electrostatic discharge damage, devices having a function of conducting electrostatic discharge current to the ground are integrated into the integrated circuit.

The present invention relates to a semiconductor structure having an electrostatic discharge protection device.

In accordance with one aspect of the present disclosure, a semiconductor structure is proposed that includes an electrostatic discharge protection device. The ESD protection device comprises a first gold oxide half field effect transistor, a ring well and a base connection region. The first MOS field effect transistor includes a gate, a source, a drain, and a first base well. The first base well has a first conductivity type. The annular well has a second conductivity type that is opposite to the first conductivity type. The semiconductor structure also includes a second gold oxide half field effect transistor. The second gold oxide half field effect transistor includes a second base well. The second base well has a second conductivity type. The base connection region is in the first base well between the gate, the source and the drain of the first MOS field transistor and the second base well of the second MOS field and is surrounded by the ring well around.

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

In an embodiment, the electrostatic discharge protection device increases the electrostatic discharge protection by providing a base connection region in a portion of the first base oxide well of the first metal oxide half field effect transistor adjacent to the second gold oxide half field effect transistor. The protective function of the device and avoiding the blocking effect of the semiconductor structure.

The following is explained by some embodiments. It should be noted that the disclosure does not show all possible embodiments, and other embodiments not disclosed in the disclosure may also be applied. Furthermore, the dimensional ratios on the drawings are not drawn in proportion to the actual product. Therefore, the description and illustration are for illustrative purposes only and are not intended to be limiting. In addition, the description in the embodiments, such as the detailed structure, the process steps, the material application, and the like, are for illustrative purposes only and are not intended to limit the scope of the disclosure. The details of the steps and the details of the embodiments may be varied and modified in accordance with the needs of the actual application process without departing from the spirit and scope of the disclosure. The same/similar symbols are used to describe the same/similar elements.

The semiconductor structure according to an embodiment can be explained with reference to FIGS. 1 to 3. FIG. 1 is a plan view showing a semiconductor structure. Fig. 2 is a cross-sectional view taken along line AA of Fig. 1. Fig. 3 is a cross-sectional view taken along line BB of Fig. 1. In this example, the first gold-oxygen half-field effect transistor and the second gold-oxygen half-field effect transistor system are exemplified by an N-type gold-oxygen half-field effect transistor NMOS and a P-type gold-oxygen half-field effect transistor PMOS, respectively.

Referring to FIGS. 1 to 3, the electrostatic discharge protection device of the semiconductor structure includes an N-type MOS field-effect transistor NMOS, an N-type ring well N-Well, and a P-type base connection region 102.

The N-type metal oxide half field effect transistor NMOS includes a P-type first base well (P-Well) 104, an N-type source 106, an N-type drain 108, and between the N-type source 106 and the N-type drain 108. The gate 110 above the P-type first base well 104. N-type source 106 and N-type drain 108 may include heavily doped (n+) regions. N-type source 106 and N-type drain 108 may also include a metal halide layer formed over the heavily doped (n+) region.

An N-type annular well N-Well can be formed in the P-type first base well 104 and surround the N-type gold-oxygen half-field effect transistor NMOS and P-type base connection region 102. An N-type heavily doped (n+) region can be formed in the N-type annular well N-Well. A metal telluride layer can be formed on the N-type heavily doped (n+) region.

The P-type base contact region 102 (Figs. 1 and 3) may include a P-type heavily doped (p+) region formed in the P-type first base well 104. The P-type base contact region 102 can also include a metal telluride layer on the heavily doped region.

The ESD protection device may further include a P-type base contact region 112 formed in the P-type first base well 104 and separated from the P-type base contact region 102. P-type base contact region 112 can include a P-type heavily doped (p+) region. The P-type base contact region 112 may also include a metal telluride layer formed on the P-type heavily doped region. The P-type base contact region 112 is electrically connected to the trigger node (N _trig ).

The ESD protection device may further include a P-type annular doping region 114 formed in the P-type first base well 104 and surrounding the N-type annular well N-Well. The P-type annular doped region 114 can include a heavily doped (p+) region. A metal telluride layer can be formed on the heavily doped region of the P-type annular doped region 114. The P-type annular doping region 114 is grounded.

The semiconductor structure includes a P-type MOS field-effect transistor PMOS including an N-type second base well (NW) 116, a first P-type source/drain 118, a second P-type source/drain 120, and at first A gate 122 above the N-type second base well 116 between the P-type source/drain 118 and the second P-type source/drain 120. The first P-type source/drain 118 can be one of a source and a drain, and the second P-type source/drain 120 can be the other of the source and the drain. The first P-type source/drain 118 and the second P-type source/drain 120 may include heavily doped (p+) regions. The first P-type source/drain 118 and the second P-type source/drain 120 may also include a metal telluride layer formed on the heavily doped (p+) region.

The semiconductor structure can include a dielectric structure 124 (shown only in FIGS. 2 and 3) buried in the P-type first base well 104. As shown, the range of the heavily doped regions of the embodiment and the N-type annular well N-Well can be defined by the dielectric structure 124 and the gates 110, 122. The bottom surface of the N-type annular well N-Well is lower than the bottom surface of the dielectric structure 124. Dielectric structure 124 is not limited to shallow trench isolation structures, but may include other suitable isolation structures, such as field oxide structures, combinations of the foregoing, and the like.

In an embodiment, the P-type base contact region 102 of the ESD protection device is disposed in a region of the P-type first base well 104 surrounded by the N-type annular well N-Well and adjacent to the P-type MOS field-effect transistor PMOS. Thereby, the protection function of the electrostatic discharge protection device is improved and the blocking effect of the semiconductor structure is avoided.

For example, in the top view shown in FIG. 1, the P-type base contact region 102 may be disposed on the upper side of the gate 110, the N-type source 106, and the N-type drain 108 of the N-type metal oxide half field effect transistor NMOS. And having an elongated shape extending substantially parallel to the direction from the N-type source 106 to the N-type drain 108.

Compared with the comparative example in which the semiconductor structure does not have the P-type base contact region, the electrostatic discharge protection device having the P-type base contact region 102 according to the embodiment of the present invention can withstand higher electrostatic discharge current/voltage while simultaneously It has an electrostatic discharge trigger rate comparable to that of the comparative example. In addition, the semiconductor structure having the P-type base contact region 102 according to the embodiment of the present invention is not susceptible to latch-up in a general state (in this case, the trigger node N _trig is electrically floating), so the N-type MOS half-field effect transistor NMOS and The area of the P-type MOS field-effect transistor PMOS can be designed to be closer to save space and increase component layout density.

For example, FIG. 4 illustrates a substrate triggered equivalent circuit of an electrostatic discharge protection device according to an embodiment. The electrostatic trigger circuit can include a resistor and a capacitor electrically connected in series, and can include an N-type MOS field-effect transistor NMOS whose gate is coupled to a node between the resistor and the capacitor. The trigger node N _trig is coupled between two N-type metal oxide half field effect transistors NMOS. In the embodiment, in the normal state, the trigger node N _trig is in an electrical floating state, and the coupled resistance (indicated by a broken line) is generated by the P-type base connection region 102 (Fig. 1 and Fig. 3). Parasitic BJT occurs. The electrostatic discharge protection device according to the embodiment grounds the P-type base connection region 102 in a general state to provide the ground terminal of the P-type first base well 104, and thus the P-type of the N-type gold-oxygen half-field effect transistor NMOS A base well 104 (Figs. 1 to 3) is not susceptible to electrical reversal due to the proximity of a P-type MOS half-effect transistor PMOS operation (PN junction, such as P-type first base well 104 and The electrical conduction of the junction between the N-type second base wells 116 has a latch-up effect. In the embodiment, the more the contact points (e.g., the number of contact pads) of the P-type base contact region 102, and the wider the distribution range, the more significant utility can be caused.

In other embodiments, the contour and position of the P-type base contact region 102 can be arbitrarily changed according to actual needs.

For example, in a top view of the semiconductor structure shown in FIG. 5, a plurality of P-type base regions 102 are provided in the gate 110, the N-type source 106, and the N-type NMOS of the N-type MOS field-effect transistor NMOS. The upper side of the pole 108 is spaced apart substantially parallel to the direction from the N-type source 106 to the N-type drain 108.

In other embodiments, the P-type MOS field-effect transistor PMOS is disposed on the right side of the N-type MOS field NMOS (the so-called right side can be referred to, for example, in the top view shown in FIG. 1 or FIG. At this time, the P-type base connection region 102 can be disposed in the region of the P-type first base well 104 on the right side of the N-type metal oxide half-field effect transistor NMOS, and can be designed to have a strip profile or a separate arrangement. Outline. This concept can also be extended to the case where the P-type MOS field-effect transistor PMOS system is disposed on the lower side and the left side of the N-type MOS field-effect transistor NMOS.

According to the above embodiment, the first base well of the first MOS field-effect transistor of the ESD protection device is disposed in the portion adjacent to the second MOS field-effect transistor, and is provided with a base connection which is grounded under normal conditions. In this way, the protection function of the ESD protection device can be improved and the blocking effect between the devices of different conductivity types can be avoided.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

102‧‧‧ base area

104. P-Well‧‧‧ first base well

106‧‧‧ source

108‧‧‧汲polar

110, 122‧‧‧ gate

112‧‧‧base contact area

114‧‧‧Circular doped area

116. NW‧‧‧Second base well

118, 120‧‧‧ source/bungee

124‧‧‧Dielectric structure

N _trig ‧‧‧trigger node

NMOS‧‧‧N type gold oxide half field effect transistor

PMOS‧‧‧P type gold oxide half field effect transistor

N-Well‧‧‧N type annular well

1 is a top plan view of a semiconductor structure in accordance with an embodiment. 2 is a cross-sectional view of a semiconductor structure in accordance with an embodiment. 3 is a cross-sectional view of a semiconductor structure in accordance with an embodiment. FIG. 4 illustrates an equivalent circuit of an electrostatic discharge protection device according to an embodiment. FIG. 5 is a top plan view of a semiconductor structure in accordance with another embodiment.

Claims (12)

A semiconductor structure comprising: an electrostatic discharge protection device comprising: a first gold oxide half field effect transistor comprising a gate, a source, a drain and a first base well, wherein the first base The well has a first conductivity type; a ring well having a second conductivity type opposite to the first conductivity type; and a base connection region; and a second gold oxide half field effect transistor including a second base a second well having the second conductivity type, wherein the base is in the gate of the first MOS field, the source and the drain and the second gold The first base well between the second base wells of the oxygen half field effect transistor is surrounded by the annular well. The semiconductor structure of claim 1, wherein the base region comprises a heavily doped region formed in the first base well. The semiconductor structure of claim 1, further comprising a dielectric structure buried in the first base well, wherein a range of the base contact region is defined by the dielectric structure. The semiconductor structure of claim 3, wherein the bottom surface of the annular well is lower than the bottom surface of the dielectric structure. The semiconductor structure of claim 1, wherein the ESD protection device further comprises a base contact region electrically connected to a trigger point and separated from the base. The semiconductor structure of claim 5, wherein the trigger point is connected to an electrostatic trigger circuit. The semiconductor structure of claim 6, wherein the electrostatic trigger circuit comprises at least a resistor and a capacitor electrically connected. The semiconductor structure of claim 1, wherein the plurality of base regions are separated from each other. The semiconductor structure of claim 1, wherein the base region has an elongated shape. The semiconductor structure of claim 1, further comprising an annular doped region formed in the first base well having the same conductivity type and surrounding the annular well. The semiconductor structure of claim 10, wherein the annular doped region is grounded. The semiconductor structure according to claim 1, wherein the first gold-oxygen half-field effect crystal system N-type gold-oxygen half-field effect transistor, the second gold-oxygen half-field effect electro-crystal system P-type gold-oxygen half-field effect Crystal.