TW538521B - Electrostatic discharge protection circuit - Google Patents

Abstract

This invention provides an electrostatic discharge (ESD) protection circuit formed on a P-type substrate. The ESD protection circuit is disposed between a bonding pad and an internal circuit formed on the P-type substrate, and has a P-type metal-oxide semiconductor (PMOS) and an N-type metal-oxide semiconductor (NMOS). The PMOS has a first doped region formed below a P<+> guard ring of the PMOS and a well pick-up of the PMOS, and the NMOS has a second doped region formed below an N<+> guard ring of the NMOS and a pick-up of the NMOS so that an equivalent Zener diode is formed on the P-type substrate. A breakdown of the equivalent Zener diode restricts the PMOS or the NMOS from producing a snapback breakdown.

Description

538521 V. Description of the invention (1) 'Field of the invention' The present invention provides a protection circuit, especially an electrostatic discharge protection circuit. [Background of the Invention] The electrostatic discharge (ESD) phenomenon is a common phenomenon in the semiconductor manufacturing process, and the excessive charge brought by it will pass through the I / 〇 pin of the integrated circuit in a very short time. Passed into the integrated circuit 'and destroys the internal circuit of the integrated circuit. In order to solve this problem, manufacturers usually set a protection circuit between the internal circuit and the I / 〇 pin. The protection circuit must be activated before the pulse of electrostatic discharge reaches the internal circuit to quickly eliminate the excessive Voltage to reduce damage caused by electrostatic discharge. In addition, the size of the semiconductor integrated circuit components has continued to shrink.

In the manufacturing technology of deep submicron complementary metal-oxide-semiconductor (CMOS), not only the channel length needs to be shortened, but also the gate oxide layer must be thinner. The depth of the junction becomes shallower, and the dopant concentration of the well (weH) must also be increased. However, the above processes often make integrated circuit products more vulnerable to electrostatic discharge (ESD) damage, so more effective ESP protection circuits must be added to the chip to release

Page 5 538521 V. Description of the invention (2)-ESD current 'protects the integrated circuit from esd damage, in other words, it increases the ESD withstand voltage of integrated circuit products. To make an effective ESD protection circuit, you must first design and make suitable ESD protection components in the ESD protection circuit. Secondly, it is also a direct and effective method to increase the area of the ESD current by increasing the area of the ESD protection element. However, when increasing the area of the ESD protection element, it is necessary to consider that it cannot occupy too much chip area, otherwise it will violate the principle of minimizing the chip size. A conventional method for preventing electrostatic breakdown caused by electrostatic pulses is to use a parasitic diode composed of a metal oxide semiconductor field effect transistor (MOSFET) as an electrostatic discharge protection circuit element. Please refer to FIG. 1. FIG. 1 is a schematic diagram of a conventional electrostatic discharge protection circuit 20 for protecting an internal circuit 10. The electrostatic discharge protection circuit 5 is electrically connected to the internal circuit 1 0 and a bonding pad 1 2 ′. The bonding pad 12 is used as an electronic signal transmission medium for the internal circuit 10 and the outside. When static electricity is introduced from the bonding pad 12, the electrostatic discharge protection circuit 20 can protect the internal circuit 12 from being burnt due to excessive static current. The electrostatic discharge protection circuit 20 includes a p-type metal-oxide semiconductor (PM0S) 22 and an N-type metal-oxide semiconductor (NM0S) 24, PMOS 2 2 and NMOS 24. The drains of the two transistors ((1 『31113) are connected to each other and are electrically connected to the internal circuit 10 and the bonding pad 12 ′ through a wire 14 and the source of the PM0S 2 2 is simultaneously connected to the PM0S 2 2 Gate

Page 6 538521 V. Description of the invention (4) [Objective and summary of the invention] Therefore, the object of the present invention is to provide an ESD protection circuit that does not take advantage of the snapback collapse phenomenon, and uses a simpler ion implantation method to An equivalent Zener diode is formed to provide a path for electrostatic discharge. The electrostatic discharge protection circuit of the present invention is formed on a P-type substrate, and is disposed between a bonding pad and an internal circuit. The internal circuit is also formed on the P-type substrate. on. The ESD protection circuit is electrically connected to the bonding pad, a first voltage terminal (VDD), a second voltage terminal (V ss), and the internal circuit at the same time, and includes a PM0S and a NM0S. The PMOS includes a p-guard ring, a first N + diffusion region, a first N-well, and a first ion doped region. Wherein the P guard ring is formed on the P plastic substrate, the first N diffusion region is formed on the P-type substrate and is surrounded by the P guard ring, and does not contact the p guard ring with each other 'the first N well Also formed on the P-type substrate and in contact with the first N diffusion region. The first ion-doped region is formed under the p-guard ring and the first N-diffusion region, and is in contact with the p-guard ring and the first N-diffusion region to form a first equivalent Zener II. Polar body (Zener diode). The NMOS comprises an N guard ring, a first P diffusion region, a second N well, and a second ion doped region. The N guard ring is formed on the p-type substrate, and a first p-diffusion region is formed.

538521 V. Description of the invention (5). On the P-type substrate and surrounded by the N guard ring, and not in contact with the N guard ring, the second N well is formed under the N guard ring, and The N guard rings are in contact. The second ion-doped region is formed under the N guard ring and the first p diffusion region, and is in contact with the N guard ring and the first p diffusion region to form a first-equivalent Zener Diode. [Detailed description of the invention] Please refer to FIG. 2 and FIG. 2. FIG. 2 is a schematic diagram of an electrostatic discharge (ESD) P-side protection circuit ι 〇 00 electrically connected to an internal circuit 90 according to the first embodiment of the present invention. FIG. 3 is a top view of the electrostatic discharge protection circuit 100 of FIG. 2. The electrostatic discharge protection circuit 100 is formed on a p-type substrate 10 2 and is disposed between a bonding pad (bon (jing pad) 9 2 and an internal circuit 90) to be bonded. The pad 92 is used as an electronic signal transmission medium for the internal circuit 90 and the outside world. The related electronic signals can be input to or output from the internal circuit 90 through the bonding pad 92, and the internal circuit 90 also It is formed on the P-type substrate 102. The electrostatic discharge protection circuit is electrically connected to the bonding pad 92, a first voltage terminal Vdd, a second voltage terminal, and the internal circuit 90, wherein the first voltage terminal VD # is used for electricity Connected to a positive% voltage to supply power to the internal circuit 90, and the second voltage terminal Vs ^ is used to ground to provide a zero potential reference for each electronic component, so when the potential of the first S voltage terminal is higher than the second When the voltage terminal Vs is equal to the potential, the internal circuit 90 can be supplied with power and operate normally.

Page 9 538521 V. Description of the invention (6) The electrostatic discharge protection circuit 100 includes a P-type metal-oxide semiconductor (PMOS) 110 and an N-type metal-oxide semiconductor (N-type metal- oxide semiconductor (NMOS) 140, PMOS 110 and NMOS 140 are formed on the P-type substrate 102. Among them, a first parasitic diode 114 is formed at the PMOS 110, and a second parasitic diode 144 is also formed at the NMOS 140. Similar to the conventional technology, the two parasitic diodes 114 and 14 are also used as the main electrostatic discharge protection elements. Please refer to FIG. 3 and FIG. 4. FIG. 4 is a cross-sectional view of the electrostatic discharge protection circuit 100 of FIG. 3 along all lines 4-4. PMOS 110 includes a P-guard ring 116, a first N + diffusion region 118, a first N-well 120, and a first P-type ion doped region. (P-type doped region) 122, a gate 112G, a source 112S, and a drain 112D. Among them, a p-ring 16 is formed on the P-type substrate 102 and is electrically connected to the second voltage terminal v ss to prevent the PMOS 110 from latching up. The first N diffusion region 118 is formed on the P-type substrate 1 02 and is surrounded by the P guard ring 1 16 and is not in contact with the P guard ring 116. The first N diffusion region 118 is electrically connected to the first A voltage terminal VDD 'is used as a well pick-up, so that the first N well 1 2 0 will not be in a floating state after a positive voltage is applied to the first voltage terminal v D . The first N well 120 is also formed on the P-type substrate 102 and is in contact with the first N diffusion region 118, and the first p-type ion doped region 1 2 2 is formed on the P-ring 1 16 and the first N diffusion area 1 1 8 and P guard ring 1 1 6

Page 10 538521 V. Description of the invention (7) &quot; and the first N diffusion region 11 8 are in contact with each other, so a first equivalent Zener will be formed between the p-ring η 6 and the first N diffusion region 11 8 Diode (Zener diode) 132. The first P-type ion doped region 12 2 is implanted by implanting erbium ions. As shown in FIG. 3, between the dotted lines 1 22A and 1 22B, implanted P ions are implanted to form the first P A region of the type ion doped region 12 2. The source 11 2 S and the drain 11 2 D of PMOS 11 0 are composed of two P diffusion regions (P + diffusion regions) located in the first n well 1 2 0 and formed on two of its gate 11 2 G. Side, and the surface of the first N well 1 2 0 is formed with a dioxide dioxide layer as a gate oxide layer (gate oxide layer) of the gate 11 2G, the source 112S and the gate of the PMOS 110 1 12G phase is connected and all are electrically connected to the first voltage terminal VDD. Relative to PMOS 110, NMOS 140 includes a guard ring (N + gUard ring) 146, a first p diffusion region 148, a second N well 150, a second p-type ion doped region 152, a The gate electrode 142G, a source electrode 142S, and a drain electrode 142D. Among them, the n guard ring 1 4 6 is formed on the P-type substrate 102 and is electrically connected to the first voltage terminal v⑽ to prevent the NMOS 140 from generating a latch-up phenomenon. The first p-diffusion region ι48 is formed on the P-type substrate 102 and is surrounded by the N guard ring 1 4 6 and communicates with the N guard ring! 4 6 are not in contact with each other, and the first P diffusion region 14 8 is electrically connected to the second voltage terminal Vss, so that NM0S 14 0 does not generate a floating body% effect. A second N-well 150 is also formed on the p-type substrate 102 and is in contact with the N guard ring 146. A second P-type ion doped region 152 is formed under the n guard ring ία and the first P diffusion region 148. With N guard ring 14 6 and the first p diffusion zone page 11 1 538521

The domains 148 are in contact with each other, and a second equivalent Zener diode 162 is formed between the N guard ring 146 and the first p diffusion region. The second p-type ion 1 5 2 is also formed by implanting p-ion implants. As shown in FIG. 3, between the dotted lines 152A and 152B, p-ion implants are implanted to form a second erbium ion doping Area of area 152. In addition, the source 142 level N142 of the NMOS 140 is composed of two N diffusion regions located in the p-type substrate 102 and formed on both sides of its gate 142G. The source 142S and the intermediate electrode of the NMOS 140 And 142G are connected and all are electrically connected to the second voltage terminal Vss, while the PM 112s 110D and the NMOS 14 0 drain 142D are connected and electrically connected to the bonding pad 92 and the internal circuit through a wire 94 90. In addition, the sum of the forward bias voltage when the first parasitic diode 114 is turned on and the first equivalent Zener diode 132's breakdown voltage (br € akdwn voltage) will be less than the sum of the PMOS 110 voltage. The snapback voltage, therefore, before the PM0S 110 snaps back to the collapse phenomenon, the first parasitic diode 11 4 and the first equivalent Zener diode i 3 2 are both turned on. Similarly, the sum of the forward bias voltage when the second parasitic diode 144 is turned on plus the breakdown voltage of the second equivalent Zener diode 162 will be less than the sudden breakdown voltage of NM0su〇, so when NMOS 140 Prior to the sudden collapse, the second parasitic "polar body 1 4 4" and the first equivalent Zener-polar body 16 2 would both be turned on. In addition, the p terminals of the two equivalent Zener diodes 132 and 162 are both electrically connected to the first voltage terminal V DD ′ and the N terminals thereof are electrically connected to the second voltage terminal v ss. When the diodes 1 3 2, 1 6 2 have equal or similar breakdown voltages, two equivalent Zener diodes 132, 16 2 can be replaced by another equivalent Zener diode ι8〇.

538521 V. Description of the invention (9)-to show 'as shown in Figure 2. In order to make the electrostatic protection mechanism of the ESD protection circuit 100 easier to understand, the following description is to replace the two equivalent Zener diodes 132 and 162 with the equivalent Zener diodes 18 0 to illustrate. When static electricity is introduced into the ESD protection circuit 100 through the bonding pad 92, it can be generally divided into the following four situations: 1. The potential of the bonding pad 92 is higher than the potential of the first voltage terminal Vdj ^; 2. The bonding pad The potential of 9 2 is lower than the potential of the first voltage terminal; 3. The potential of bonding 塾 92 is higher than the potential of the second voltage terminal; 4 • The potential of bonding 塾 92 is lower than the potential of the second voltage terminal v㈤. In the first case, the electrostatic current will flow from the bonding pad 92 through the first parasitic diode 114 to the first voltage terminal Vdd; in the second case, the electrostatic current will sequentially flow through the first voltage terminal VD, etc. After the Zener diode 180 and the second parasitic diode 144 flow to the bonding pad 92, in the third case, the electrostatic current will sequentially pass from the bonding pad 92 through the first parasitic diode 14 and so on. The Zener diode 180 flows to the second voltage terminal Vss; in the fourth case, the electrostatic current flows from the second voltage terminal Vs to the bonding pad 92 through the second parasitic diode 144. As mentioned above, the sum of the forward voltage when the first parasitic diode 114 is turned on plus the collapse voltage of the first equivalent Zener diode i 32 will be less than the sudden collapse voltage of pM0s 110. The sum of the forward bias when the second parasitic diode i 44 is turned on plus the second equivalent Zener diode i 6 2 breakdown voltage will be less than the snapback breakdown voltage of NMOS 14 0, and the Zener diode The 18 ° system is equivalent to two equivalent Zener diodes 132 and 162. Therefore, the conduction of two parasitic diodes 114 and 144 and two equivalent Zener diodes 132 and 162 can prevent pM0s.

538521 V. Description of the Invention (一) 1-10 and NMOS 14 0 have a sudden collapse, and at the same time, the electrostatic discharge protection circuit 1 0 0 also has the function of protecting the internal circuit 9 0 from damage caused by electrostatic discharge . Please refer to FIG. 5 and FIG. 6. FIG. 5 is a schematic diagram of the electrostatic discharge protection circuit 200 according to the second embodiment of the present invention when it is electrically connected to an internal circuit 190. FIG. 6 is a top view of the electrostatic discharge protection circuit 200 of FIG. The electrostatic discharge protection circuit 200 is formed on a P-type substrate 202, and is disposed between a bonding 塾 i 9 2 and an internal circuit 190, and the bonding pad 192 is used as an internal circuit! 〇 and its external electronic signal transmission medium, the electronic signal can be input to the internal circuit 190 or output from the internal circuit 190 by bonding 塾 192, and the internal circuit 190 is also formed on the P-type substrate 202. The electrostatic discharge protection circuit 2000 is electrically connected to the bonding pad 192, a first voltage terminal VDD, a second voltage terminal Vs and the internal circuit 190, wherein the first voltage terminal VD &lt; is used to be electrically connected to a positive voltage to connect Power is supplied to the internal circuit 190, and the second voltage terminal vs. thorn is used to ground to provide a zero potential reference for each electronic component. Therefore, when the potential of the first voltage terminal V DD is higher than the second voltage terminal V s -type potential, The internal circuit 190 can be supplied with power and operates normally. The ESD protection circuit 200 includes a P-type metal oxide semiconductor (PMOS) 210 and an N-type metal oxide semiconductor (NMOS) 240. The PMOS 210 and NMOS 240 are formed on the P-type substrate 202. Among them, a first parasitic diode 214 is formed at the PMOS 210, and a second parasitic diode 244 is also formed at the NMOS 2400. Same as the conventional technology, two parasitic two

Page 14 538521 V. Description of the invention (π) The polar bodies 214, 24 4 are also used as the main electrostatic discharge protection elements. Please refer to Figure 6 and Figure 7. Figure 7 is a cross-sectional view of the electrostatic discharge protection circuit 200 of Figure 6 along all lines 7-7. PMOS 2 10 includes a p-ring 216, a first N diffusion region 218, a first N well 2 2 0, a first N-type doped region 222, a gate 212G, A source 2 1 2 S and a drain 2 1 2 D. Among them, the P guard ring 2 1 6 is formed on the P-type substrate 20 2 ′ and is electrically connected to the second voltage terminal vss, which is used to prevent the pM0 210 from generating a blocking phenomenon. The first N diffusion region 2 1 8 is formed on the p-type substrate 2 0 2 and is surrounded by the P guard ring 2 1 6, but is not in contact with the p guard ring 2 1 6. The first n + diffusion region 218 is electrically connected. At the first voltage terminal Vdd, it is used as a well contact: so that the first N well 220 is operated at the first voltage terminal v D; it will not be in the state of foreign connection after a positive voltage is applied. The first N well 2 2 0 is also formed on the p-type substrate, and is in contact with the first N 1 scattered region 2 1 8 on the 002, and the first N-type ion doped region 2 2 2 is formed on the p 濩% 2 16 and the first N diffusion region 2 1 8 and are in contact with the p-ring 2 16 and the first N diffusion region 21 8 and partially overlap with the first ^ well 22 and thus are in the P-ring 21 A first equivalent Zener-polar body 232 will be formed between 6 and the first 1 ^ scattered region 218. The first n-type ion doped region 22 2 is formed by implanting N implantation, and as shown in FIG. 6, an N ion implantation is performed between the dotted line 222A and the dotted line 22 2b to form a first N-type ion doping. Area of area 222. The source electrode 212S and the drain electrode 212D of ρΓ〇 are composed of two located in the first field 220-1 9 and scattered and formed on both sides of its gate 2 1 2G. The silicon dioxide dielectric layer is used as the gate-gate oxide layer. The source 212S and the gate 212G phase of PM0S 210 are 538521. 5. Description of the invention (12) It is all connected to the first voltage terminal V DD. Relative to? Discuss 03210, Li 03 24 0 includes a ring 24 24, a first P diffusion region 248, a second N well 250, a second N-type ion doped region 252, a gate electrode 242G, a source electrode 242S, and One drain electrode 242D. Among them, the N guard ring 246 is formed on the P-type base 202 and is electrically connected to the first voltage end 71) 1) to prevent the Li 03 240 from generating a latch-up phenomenon. the first? The diffusion region 248 is formed on the P-type substrate 2 0 2 and is surrounded by the N guard ring 246 and is not in contact with the N + guard ring 21 6. The first P diffusion region 2 4 8 is electrically connected to the voltage terminal V ss 'So that NMOS 2 4 0 does not produce a floating body effect. A second n well 2 5 0 is also formed on the P-type substrate 2 02 and is in contact with the N guard ring 2 4 6, and a second n-type ion doped region 2 5 2 is formed on the N guard ring 2 4 6 and the first Below a P diffusion region 2 4 8 and in contact with the N guard ring 246 and the first P diffusion region 248 and partially overlapping with the second N well 2 50, the N guard ring 246 and the first P diffusion region 248 A second equivalent Zener diode 262 will be formed therebetween. The second N-type ion doped region 2 5 2 is also formed by implanting N-ion implants. As shown in FIG. 6, between the dotted lines 2 5 2 A and 2 5 2 B are implanted N-ion implants. To form a region of the second n-type ion doped region 252. In addition, the source 242S and the non-electrode 242D of the NMOS 240 are composed of two N diffusion regions located in the P-type substrate 202 and formed on both sides of the gate 242G of the NMOS 240. 242G is connected and all are electrically connected to the second voltage terminal vss, and the drain 21D of pM0f21〇 and the drain 242D of NMOS 2 40 are connected and electrically connected to the bonding pad 19 2 and the internal circuit through a wire 194 190.

538521 V. Explanation of the invention (13) In addition, the sum of the forward bias voltage when the first parasitic diode 2 1 4 is turned on plus the breakdown voltage of the first equivalent Zener diode 23 2 will be less than the PMOS The snap-back breakdown voltage of 210, so before the snap-down breakdown of PMOS 210 occurs, both the first parasitic diode 21 4 and the first equivalent Zener diode 23 2 will be turned on. Similarly, the sum of the forward bias voltage of the second parasitic diode 244 when it is turned on and the second equivalent Zener diode 262 2 breakdown voltage will be less than the snapback breakdown voltage of NMOS 240, so when NMOS 240 Prior to the sudden collapse, the second parasitic diode 24 4 and the second equivalent Zener diode 262 are both turned on. In addition, the P terminals of the two equivalent Zener diodes 2 3 2 and 2 6 2 are both electrically connected to the second voltage terminal V ss, and the N terminals thereof are electrically connected to the first voltage terminal v DD. When the effective Zener diodes 232, 2 62 have equal or similar breakdown voltages, the two equivalent Zener diodes 232, 26 2 can be represented by another equivalent Zener diode 28 0, As shown in Figure 5. Similar to the ESD protection circuit 100, the ESD protection circuit 2000 prevents PMOS by the synergistic effect of two parasitic diodes 214 and 244 and two equivalent Zener diodes 232 and 2 62. The 210 and NMOS 2 40 have a sudden crash, and they also have the function of protecting the internal circuit 190 from damage caused by electrostatic discharge. Compared with the conventional electrostatic discharge protection circuit, its components are not easy to manufacture due to the sudden collapse phenomenon. The electrostatic discharge protection circuit of the present invention uses ion implantation to form a p-plastic under its guard ring and its well contact. Or the surface ion-doped region forms an equivalent Zener diode on the P-type substrate, which is used to guide the input static electricity away.

Page 17 538521

Page 18 538521 Schematic description [Schematic description] Figure 1 is a schematic diagram of a conventional electrostatic discharge protection circuit used to protect internal circuits. FIG. 2 is a schematic diagram when the electrostatic discharge protection circuit according to the first embodiment of the present invention is electrically connected to an internal circuit. FIG. 3 is a top view of the electrostatic discharge protection circuit of FIG. 2. Fig. 4 is a cross-sectional view of the ESD protection circuit of Fig. 3 along a tangent line 4-4. FIG. 5 is a schematic diagram when the electrostatic discharge protection circuit according to the second embodiment of the present invention is electrically connected to an internal circuit. Figure 6 is a top view of the electrostatic discharge protection circuit of Figure 5. Figure 7 is a cross-sectional view of the electrostatic discharge protection circuit of Figure 6 along all lines 7-7. [Illustrated Symbols]

90 ^ 190 92 &gt; 192 94 &gt; 194 100 ^ 200 102, 202 110, 210 112D, 212D internal circuit bonding pad wire protection circuit P-type substrate P-type metal oxide semiconductor drain

Page 538521 Brief description of the diagram 11 2 G, 2 1 2 G Gate 112S, 212S Source 114, 214 116, 216 118, 218 120, 220 122, 222 122A, 222A 122B, 222B 132, 232 140, 240 The first parasitic diode P guard ring, the first N diffusion region, the first N-well P-type ion doped region, the dashed line, the dashed line, and the dashed line. Gate 142S, 242S Source 144, 244 146 '246 148, 248 150, 250 152, 252 152A, 252A 152B, 252B 162, 262 180, 280 Second parasitic diode N guard ring First P diffusion region Second N-line second P-type ion doped region defines a dotted line defining a dotted line second equivalent Zener diode equivalent Zener diode

Page 20

Claims (1)

538521 6. Application patent scope 1. An electrostatic discharge (ESD) protection circuit is formed on a P-type substrate, and is provided on a bonding pad and a P-type substrate. Between internal circuits on a type substrate, the ESD protection circuit is electrically connected to the bonding pad, a first voltage terminal (VDD), a second voltage terminal (V ss), and the internal circuit, which includes: a P P-type metal-oxide semiconductor (PM0S), which includes a P-guard ring (P + guard ring) formed on the P-type substrate and is electrically connected to the second voltage terminal; A first N diffusion region is formed on the P-type substrate, is surrounded by the P guard ring, is not in contact with the P guard ring, and is electrically connected to the first voltage terminal; A first N-well (N-we 11) is formed on the P-type substrate and is in contact with the first N-diffusion region; and a first doped region is formed at the? Huo Duo Ai is under the first N diffusion region, and is in contact with the P guard ring and the first N scatter region to form a first equivalent Zener diode (Zener di ode); and An N-type metal-oxide semiconductor (NMOS), the NMOS includes: an N-guard ring (N + guard ring) formed on the P-type substrate and electrically connected to the first voltage terminal A first P diffusion region (P + diffusion region) formed on the first P diffusion region 538521 6. The scope of patent application is on the P-type substrate, which is surrounded by the N guard ring and is not in contact with the N guard ring, and is electrically connected to the second voltage terminal; and a second N well formed in the The N guard ring is in contact with the N guard ring. 2. The electrostatic discharge protection circuit according to item 1 of the application scope, wherein the NMOS includes a second ion doped region formed under the N guard ring and the first P diffusion region, and connected with the N guard ring and the The first P diffusion regions are in contact with each other to form a second equivalent Zener diode. 1 3. If the electrostatic discharge protection circuit of item 2 of the application scope, wherein when the first equivalent Zener diode or the second equivalent Zener diode produces a breakdown phenomenon, the PMOS can be prevented And talk about NMOS produces snapback breakdown phenomenon. 4. The electrostatic discharge protection circuit according to item 2 of the application scope, wherein the first ion-doped region and the second ion-doped region are respectively a P-type ion-doped region. 5. The electrostatic discharge protection circuit according to item 2 of the application, wherein the first ion-doped region and the second ion-doped region are N-type ion-doped regions, respectively. 6. The electrostatic discharge protection circuit according to item 5 of the application, wherein the first Page 538521 The ion-doped region partially overlaps the first N-well, and the second ion-doped region partially overlaps the second N-well. • The electrostatic discharge protection circuit according to item 1 of the application scope, wherein when the first equivalent Zener diode has a breakdown phenomenon, the pM〇s and the NMOS can be prevented from causing a snapback breakdown. phenomenon. 8. The electrostatic discharge protection circuit according to item 1 of the application scope, wherein when the potential of the first voltage terminal is higher than the potential of the second voltage terminal, the internal circuit can be supplied with power to operate normally. 9. If the electrostatic discharge protection circuit of item 1 of the application scope, wherein the gate of the PM0S is connected to the source of the PM0S, the gate of the NM0S is connected to the source of the NM0S, and The drain of the PMOSi and the drain of the NMOS are electrically connected to the bonding pad and the internal circuit through a wire. 10. The electrostatic discharge protection circuit according to item 9 of the application scope, wherein the source of the PM0S is electrically connected to the first voltage terminal, and the source of the NMOS is electrically connected to the second voltage terminal. 11. · An electrostatic discharge (ESD) protection circuit is formed on a P-type substrate, and is provided on a bonding pad and an internal electrical circuit formed on the P-type substrate. Page 23 538521 6. Between patent application roads, the ESD protection circuit is electrically connected to the bonding pad, a first voltage terminal (V DD), a second voltage terminal (V ss), and the internal circuit. It includes: a P-type metal-oxide semiconductor (PM0S), the PM0S includes: a P-guard ring (P + guard ring) formed on the P-type substrate and electrically connected to the first Two voltage terminals A first N diffusion region is formed on the P-type substrate, is surrounded by the P guard ring, is not in contact with the P guard ring, and is electrically connected to the first voltage terminal; and A first N-well is formed on the P-type substrate and is in contact with the first N-diffusion region; and an N-type metal-oxide semiconductor (NM0S), the NM0S includes: an N guard ring (N + guard ring) formed on the type substrate and electrically connected to the first voltage terminal; A first P diffusion region is formed on the P-type substrate, is surrounded by the N guard ring, is not in contact with the N guard ring, and is electrically connected to the second voltage terminal; A second N well formed under the N guard ring and in contact with the N guard ring; and a second ion doped region formed in the N guard ring and the first P diffusion Under the region and in contact with the N guard ring and the first P diffusion region to form a second equivalent Zener diode (Zener Page 24, 538521 VI. Patent application scope (diode) 0 12. The electrostatic discharge protection circuit according to item 11 of the application scope, wherein the PM0S includes a first ion doped region 'formed on the P guard ring and the first N diffusion Under the region and in contact with the P guard ring and the first N diffusion region to form a first equivalent Zener diode. 13. If the electrostatic discharge protection circuit of item 12 of the application scope, wherein when the first equivalent Zener diode or the second equivalent Zener diode produces a breakdown phenomenon, the PM0S and The NMOS has a snapback breakdown phenomenon. 14. The electrostatic discharge protection circuit according to item 12 of the application, wherein the first ion-doped region and the second ion-doped region are respectively a P-type ion doped region. 15. The electrostatic discharge protection circuit according to item 12 of the application, wherein the ion-doped region and the second ion-doped region are N-type ion doped regions, respectively. 16. The electrostatic discharge protection circuit according to item 15 of the application, wherein the ion-doped region partially overlaps the first N-well, and the second ion pusher partially overlaps the second N-well. ’’, Pin ^ 38521 6. Scope of patent application '^ 7. If the electrostatic discharge protection circuit of item 11 of the scope of application, wherein when the first equivalent Zener diode produces a collapse phenomenon, the PM0S and the NMOS can be prevented from being generated. SnaPback breakdown. 18. The electrostatic discharge protection circuit according to item 11 of the application scope, wherein the internal circuit can be supplied with electric power to operate normally when the potential of the first voltage terminal is higher than the potential of the second voltage terminal. 19. The electrostatic discharge protection circuit according to item 11 of the application scope, wherein the gate of the PM0S is connected to the source of the PM0S, the gate of the NMOS is connected to the source of the NMOS, and The pMOSi drain and the NMOS drain are electrically connected to the bonding pad and the internal circuit through a wire. 20. The electrostatic discharge protection circuit according to item 19 of the application scope, wherein the source of ρ μ qs is electrically connected to the first voltage terminal, and the source of the NMOS is electrically connected to the second voltage terminal. Page 26