TW437047B - Low-voltage triggering electrostatic discharge protection - Google Patents

Abstract

The present invention provides a low-voltage triggering electrostatic discharge (ESD) protection system and method in the field of integrated circuit. The low-voltage triggering ESD protection circuit comprises a path with low triggering voltage and a low resistance that can be rapidly opened. The protection circuit can be applied to power bus, input, and input/output ESD protection device. The protection circuit is compatible with the compensated metal oxide semiconductor (CMOS) processing and achieving high ESD performance even for the device made in the advanced CMOS processing.

Description

Bu 4370 4 7-Case No. 87111857—M · " Yuekou __ V. Description of the Invention (1) Background of the Invention 1 · Field of the Invention The present invention generally refers to the electrostatic discharge (ESD) protection of semiconductor circuits. In an example, the present invention more particularly refers to a low voltage excited (LT) N_ channel metal oxide semiconductor (NMOS), which can be quickly turned on during an esd event, and provides a relatively uniform current density path for an ESD current. The resistor 'therefore effectively diverts all ESD pulses. 2 Discussion of related technologies

The conventional technology of electrostatic discharge protection devices is well known to those familiar with this technology. For example, a conventional method capable of providing electrostatic discharge protection is to provide a circuit in a device to guide a potentially dangerous electrostatic discharge to a ground terminal and to keep working components away from the circuit during an electrostatic discharge event. One way to provide ESD protection is to use a thick field device. For example, referring to the first figure, as shown in the figure, in a traditional thick field device (TFD), the N + doped source electrode 10 and the n + doped drain electrode 120 are located in a p-doped well 3 Inside. At the top of the p-dopant 丼 130, the insulating oxide layer 140 is located at the position 2 immediately next to the μ + dopant source 110 and the n + dopant; As shown in the first figure, there is no gate in TFD, and this TF0 is simply turned on by avalanche breakdown across the drain / channel junction. (TFJ shown in the first figure) is a traditional method to provide / Vss ESD protection. 2. Another method to provide ESD protection is to use a thin oxide layer of the grounding gate. NM0S is an example.

Μ Page 4 ί 437047 __Case No. 87111857_ Difficulty month month article _ V. Description of the invention (2) 'N + doped source 11 and N + doped drain 120 in chemical layer NMOS (GGNM0S) It is located in a P doped Y 130. The gate 210 is located at the top end of the P-doped well 130, and is located between the N + doped source 110 and the N + doped drain 1220. Two n-doped regions 220 are located below the gate 210, and the first is located adjacent to the N + dopant source 110 'and the second is located adjacent to the N + dopant 120. Two spacers 230 are located immediately next to the gate electrode 21o. At the top of the P-doped well 130, the insulating oxide layer 140 is located immediately next to the N + doped source 110 and the N + doped tear electrode 120. The device ′ shown in the second figure is a conventional LDD NMOS method with η-implantation to provide vdd / Vss ESD protection. Unfortunately, even the excitation voltage of the ldd NMOS device as shown in the second figure is not low enough to protect many types of circuits from damage. Therefore, Vdd to Vss power bus protection is provided, that is, two methods, such as a thick field device (TFD) as shown in the first figure and a thin gate oxide NMOS (GGNM0S) as shown in the second figure. Both of these protection devices play the role of NPN dual carrier devices in the esd event. The current-voltage characteristics of such an NPN dual-carrier device is shown in the third figure. More specifically, the trace in the third graph shows the current-voltage characteristics of the GGNM0S in the second graph, which has a snapback phenomenon. Referring to the third figure, when an excitation voltage (Vt r i) is reached, the 'NPN device is turned on and enters a low-impedance (Vsp) abrupt turnaround region to allow a large amount of ESD energy to dissipate out.

ES.D protection devices with lower Vtri (such as power bus protection devices) can be opened more effectively and quickly (first) to protect internal circuits from damage. An ESD protection device with a lower sudden swing voltage (Vsp) can further swell the relatively current and obtain a higher e s D

) '4370 4 7 __ Case No. 87111857_I./ Month ... Day_Amendment V. Description of the invention (3) Threshold (thresho 1 d). A good ESD protection circuit must have: i) a lower excitation voltage (V t r i) and a lower sudden swing voltage (vsp). However, the ES1) protection performance of these conventional techniques and methods cannot meet the requirements of advanced processes. For example, such as lightly doped electrode (L d D) devices, the use of thinner oxide layers, and automatic alignment stones Xi chemical process. In this or other advanced advanced processes, although the TFD and GGNM0S methods are used, during the ESD pulse stress, more and more ESD damage is occurring in the sub-micron integrated circuit. In the context of advanced processes such as the aforementioned slightly doped drain (LDD) devices, the use of thinner oxide layers, and automatic alignment with silicide processes, the traditional TFD and GGNM0S methods are not a way to provide ESd protection for power buses. Good way. Especially in the traditional TFD and GGNM0S methods, the inherent and higher excitation voltage level 'cannot protect weaker circuits from ESD damage. Using the conventional LDD device as shown in the second figure, there is a special disadvantage ', that such a device is quite fragile during the occurrence of ESD stress. In more detail, the LDD η-zone will cause uneven current distribution and local hot spot. When the size of the device is reduced to the sub-micron region or smaller, the local hot spot phenomenon becomes more and more difficult. Therefore, the LDD NMOS device as shown in the second figure cannot itself be a good ESD protection circuit. In order to solve the problem of the uneven current distribution just described, in an unsatisfactory method, a non-slightly doped drain (non-LDD) device must be used, that is, a non-LDD NMOS device as shown in the fourth figure. Referring to the fourth figure, the same

f 4370 4 7 _ case number 87111857_ year I / month ~ day you do not _ V. Description of the invention (4) Ground, N + doped source 110 and N + doped lutetium and pole 120 are located in ρ doped well Within 130. The gate 210 is also located at the top of the P-doped well 130, and is located between the ν + doped source 11 0 and the N + doped drain 1 2 0 'the two spacers 2 3 0 are located immediately next to the gate. 21 0 position. At the top of the P-doped well 130, the insulating oxide layer 140 is also located immediately next to the N + doped source 110 and the N + doped drain 1220. The difference between the structures of the second and fourth figures is that the device of the fourth figure does not have an n-doped region. As long as any n-doped region is absent, the hot spots inherent in the device shown in the second figure can be avoided. The purpose of using such non-LDD (non-LDD) devices is to improve the current distribution (compared to the device in the second figure) so as to promote a more uniform current distribution. In the absence of an? -Doped region, this limited purpose can be accomplished by the apparatus of Figure 4. Unfortunately, the excitation voltage of non-LDD devices in the fourth figure is not low enough to protect many types of circuits from damage. The device shown in Figure 4 is often used because the excitation voltage (Vtri) is too high, which causes ESD stress damage, especially when applied to the advanced process circuits, such as a lightly doped drain (LDD) device. , The use of thinner oxide layers, and automatic alignment with silicide processes. Therefore, there is a need for this technology to enable ESD protection methods to be switched very quickly to protect the balance of integrated circuits. Therefore, the required solution is to use a low excitation voltage (Vtr i) to achieve the purpose of fast response time. Another requirement of this technology is that the ESD protection method can indeed conduct all ESD pulses. Therefore, the solution is to use-low sudden swing voltage (Vsp) to show the ability to make all the ESD pulses sure. Another requirement of this technology is that ESD protection methods

437U 4 7 < Year 丨 Month W _ Amendment No. 87111857 V. The E S D pulse of Part (5) of the invention description, without any hot spot effect. Therefore, the solution is to use a uniform current distribution to show the ability to reliably divert all ESD pulses. Another requirement of this technology is that it must be economically effective in practical implementation. One of the major disadvantages of the previous methods shown in Figures 1 to 4 is the relatively high cost. Therefore, the solution is to meet the aforementioned needs in a more cost-effective manner. Therefore, in view of the foregoing, in order to improve the protection performance of ESD, a low voltage excitation protection method must be used, which combines a low excitation voltage (V tri) with a low sudden swing voltage (V sp) and a uniform current distribution, and is automatically aligned. There are economic benefits in the manufacture of silicide integrated circuits. So far, the aforementioned requirements for low excitation voltage (V tri), low sudden swing voltage (V sp), uniform current distribution, and low cost have not been fully met. The required solution is to satisfy all the requirements at the same time. . SUMMARY OF THE INVENTION The main object of the present invention is to provide an electrostatic discharge protection device. Another main object is to provide a method for manufacturing an electrostatic discharge device, and to provide a method for operating an electrostatic discharge protection device. According to these purposes, there is a need for a low-voltage excited (LT) N-channel metal oxide semiconductor (NMOS), a method of manufacturing the same, and a method of operating the same. Therefore, it is quite feasible to meet the requirements of the aforementioned low excitation voltage (V tri), low sudden swing voltage (Vsp), uniform f; current distribution, and low cost. These are often in conflict with each other in the conventional technology. And cannot be satisfied at the same time. The first aspect of the invention implemented in an example is an integrated circuit

Bu 437047 Case No. 87111857 Poverty year fl month U day Amendment

i 437 u 4 7 case number 87111857 gf year 丨 丨 month / (/ day amended five, description of the invention (7)-first.-one static electrode; then the discharge power will be transmitted to all lines, cycle area, first place, last three All these or must be described in the spirit of the invention. The drawing number is 110 130 210 230 1020 1040 1060 1045. The conductive state and a discharge pulse are switched after the electrostatic current is switched. After one, non-conductive discharge resistance is added along the line, and the pulse is pulsed. The electric discharge is doped with thick conductive static electricity. From the point of view, the following description is only a diagram and amendment, including for other purposes. It is understood that the changes within the range, and the N + doped source electrode P doped well gate spacer N + doped drain electrode P + the second P-massive conductor region mass concentration level of the present invention, The method includes: the draining device of the electrostatic discharge protection device in the conductive state to the conductive state to provide a path of fairly uniform current density of static electricity, thereby realizing the shunting, wherein the switching includes passing through the second guide The first region of the state, then the pulse, passes the second-degree level of the first conductive state, which is higher than the first dopant concentration. The quasi-electrical discharge pulse passes the second conductive state and the accompanying description and accompanying drawings. A better comment and understanding will be obtained. However, it is a way of indicating the preferred examples and special details of the present invention, rather than a limitation. Any copy is possible without losing all such modifications of the present invention. 120 N + Doped drain 140 Insulating oxide layer 22 0 η-doped region 1 0 1 0 Ν + doped source 1 0 3 0 P doped well 1 0 50 first ρ-doped region 1 0 7 0 gate electrode 1 08 0 spacer

Page 10 43 7 0 No. 7 87I11857__year / (month γ a_ V. Description of the invention (8) 1090 Insulating oxide layer 505 LDD NMOS gate 510 LTNMOS gate 515 P push substrate 520 Insulating oxide layer 525 η-Implanted photoresist mask 530 η-Region 535 ρ _Implanted photoresist mask 540 ρ-Region 545 Separator region 550 N + region 555 N + region 560 Detailed description of a preferred example of a diode The drawings and the following non-limiting examples, the present invention and various features and details with advantages, will be further fully explained. As for the description of known components and process technology, will be deleted 'to avoid the present invention Unnecessary confusion arises. The content of the present invention is an electrostatic discharge (ESD) protection within a integrated circuit, and can be used particularly in an integrated circuit including an N-channel metal oxide semiconductor. The inventor of the technology has found that In the development of advanced processes, such as' lightly doped drain (LDD) devices, the use of thinner oxide layers, and self-aligned silicide processes, there are more and more during the ESD pulse stress. ESD damage is occurring in sub-micron integrated circuits. More importantly, after detailed damage analysis, the inventor of the technology unexpectedly found that the location of the damage is usually in the internal circuit. For example, in the aforementioned advanced I In the circuit of the circuit, the conventional device shown in the fourth figure is used continuously, which will cause standby (bystand_by current or functional damage) after the ESD pulse stress. Protection device

Page 11 ϊ '437 0 4 7 _Case No. 87111857__ Di Nian f / Month Sun Zheng _ V. Description of the invention (9) Referring to the drawings, the fifth to fourteenth drawings provide details of the preferred embodiment of the present invention Instructions. Next, referring to the tenth figure, a low-voltage excited N-channel metal oxide semiconductor with an enhanced drain-gate field is shown, in which N + doped source 1 0 1 0 and N + doped drain 1 0 2 0 is located in a P-doped well 1030. The P + doped region 1040 is also located in the P-doped well 1030. A first p ~ doped region 1 0 50 is located adjacent to the source dopant source 1 0 1 0, and a second p-doped region 1 0 6 0 is located adjacent to the N + dopant drain 1 0 2 0 Its location. A gate 1070 is located at the top of the P doped well 1030 and is located between the N + doped source 1010 and the N + doped drain 1020. Therefore, the 'two p-doped regions 1050-1060 are located below the gate 1070. The gate electrode 1 0 0 is electrically connected to the P + doped region 1 0 4 0 by a conductor 1 0 4 5. The two spacers 1 0 0 0 are located immediately next to the gate 1 0 70, and the insulating oxide layer 〇 9 0 is located immediately adjacent to the N + doped source and the drain, and is located between the N + doped source. Between 1040 and 1040 p + doped regions. In the tenth figure, the 'P + doped region 1 0 4 0 is a pick-up diffusion region of the p doped well 3 0 3 0' is connected to vss (ground) by a circuit. The p doped well 103 0 can be abbreviated as PW 1030. The voltage level of PW 1030 is established via a P + diffusion region connected to the Vss metal line 1045. In the tenth figure, the P + mass region 1 040 clearly shows the parasitic NPN bipolar element formed in the final LTNm0S device structure. The tenth figure of the LTNM0S gate is connected to Vss (that is, connected to ground). Of course, compared to the case where there is no p ~ doped region, the presence of p_ doped region 1 50 0-1 0 6 0 will reduce the excitation voltage. As a result, a smaller excitation voltage is obtained than the device in the fourth figure. , P ~ doping degree can be adjusted to affect the excitation voltage. However, if the p ~ doping level is extremely low, it will cause excitation.

Page 12 ί 437047 _ Case No. 87111857_____ year of trespass " month day correction __: >: V. Description of the invention (10) The voltage is too high, so that the last device cannot be excited quickly enough. On the other hand, if the degree of P-doping is excessively high, the excitation voltage will be too low, and the device will not be excited properly, or even in an excited state. It must be noted that the functional resistance of the p-doped well in the tenth figure is represented by a simple resistor symbol and labeled Rsub. Similarly, the diode function of the channel in the tenth figure is represented by a series diode symbol. It must be understood that the low voltage of the tenth figure excites the rugged metal oxide semiconductor, even without the enhanced drain-gate field, that is, without the conductor i 0 4 5. The tenth figure shows an LTNM0S, which uses a grounding gate as a Vdd / Vss protection device. During the ESD pulse period, 'LTNM0S is used as a double-carrier NPN T1 device' and therefore better ESD performance than a low reverse breakdown diode can be obtained. The excitation voltage of LTNM0S is determined by the ρ-concentration, N + concentration, and the electric field between the drain electrode 〇 02 〇 and the gate electrode 〇 γ 〇. LTNM0s with enhanced drain-gate field can further reduce the breakdown breakdown voltage to less than the voltage of diode M. As shown in the fourth and second figures separately, 'LTNM0S with enhanced drain-gate field can be lower than non-LDD and LDD devices "and Vsp. For example, non-LDD varies with 03 and LTNM 〇k excitation voltages are u.7 volts and 9.4 volts respectively. The Vsp of LTNM0S is about 6, 0 volts, which is lower than the non-LDD of about 7.0 volts Vs ρ. Therefore, LTNM0S can be turned on first to prevent damage to the internal circuit 'And therefore get better Es. She can. As mentioned above, internal circuit damage is often found when non-LDD devices are used as wafer ESD protection. Although the preferred example shown in the tenth figure is ρ doped well, N + doped The mass source electrode is based on the p-doped channel region, but after reading the content of the present invention, it can be found that the application of the present invention to an i '4 3 7 0 4 7 case No. 87111857__ Di Nian " Month / (// Revision__ V. Explanation of the invention (11) N doped wells with P + doped source and P + doped drain are also within the general technical scope of the present invention Similar corrections are the same. After the NPN is turned on, 'the protection device with parasitic NPN double carriers will operate in the sudden turning zone' and However, the turning voltage Vsp will be lower than the sudden turning voltages of TFD and GGNM0S discussed previously. As a result, the present invention can achieve high ESD performance. Another preferred embodiment of the present invention can be used with non-volatile memory (NV M) The enhanced p_ channel implantation (cell implantation) of the process phase valley is used instead of the LDD ρ ~ implantation in Fig. 10 to reduce the excitation voltage. Referring to Fig. 13 again, another example of the LTMMOS device includes an enhancement ρ-channel (enhanced p-channel implant) implant 1 085, compatible with the memory p-cell implant (p-ce 1 1 i ιηρ 1 an t) of the non-volatile memory (NVM) process, replacing p -Quasi-LDD implantation to reduce the excitation voltage (V tri). Assuming that the p- dopant is boron, and enhanced p_channel implantation is formed before the gate oxide layer grows, no additional thermal cycling is required. (Thermal cycle) 'then strengthen p-channel implantation ι〇85, the preferred boron p-channel implantation dose is about 1 (1 0) 1 3 to 2 (1 0) 1 3 ions / cm 2. Method 'Enhanced p-channel implantation 1085 can become a low-voltage excited N-channel metal oxide semiconductor (LT NM0S) protection device Part of the method of manufacturing a Boda device Next, a method of simultaneously manufacturing a low-voltage excited ESD device and a normal slightly doped drain (LDD) NMOS device will be discussed. According to an example of the present invention, the fifth to ninth figures Represents a series of manufacturing steps of a low voltage excited NMOS (LTNMOS) adjacent to an LDD NM0s. It must be understood from the description of the following manufacturing steps that the LTNM0S system and the protection provided are not only substantially compatible with the CMOS process, but also specifically with Lj) j) NM0S since

Page 14 '4 3 7 U 4 7 ———__ Case No. 87111857 Ice Year " Month of the Day Chromium | 1 、 、 5. Description of the Invention (12) The process of dynamic alignment silicide is compatible. The fifth figure shows the completion of the first step of manufacturing an LDD NMOS adjacent to the LTNMOS protection device after silver engraving of the polycrystalline stone gate (ρ 〇 1 y g a t e). LDD NM0S will be completed on the left and LTNM0S will be completed on the right. The gate 505 of the LDD NM0S and the gate 510 of the LTNM0S are located at the top of a p # substrate 515, and a series of insulating oxide layers 520 are also located at the top of the substrate 515. The minimum design specification of polycrystalline slab gate length can be used for L T N M 0 S. Figure 6 shows the second step in which the unmasked surface area is exposed to an LDD N-implantation procedure. In the sixth figure, the LDD η-ions are indicated by arrows pointing downward. A η-implanted photoresist mask 525 is located at the top of the gates 5 1 0 and some insulating oxide layers (5 2 0) of the LTNM0S. If the η_ dopant is phosphorus, the LDD NJ10S device requires an LDD ^ η-implantation dose, approximately I (10) 1 3 to 3 (1 0) 13 ions / cm 2; in this way, two η -Zone 5 30 becomes part of the LDD NM0S device. However, as shown in the sixth figure, because it is covered by the η-implanted photoresist mask 525, the LTNM0S on the right protects the split_. There will be no η-implantation. This provides an abrupt junction. ). Therefore, the sixth figure illustrates NMOS—slightly doped n-implantation, but the LTNMOS protection device has no n-implantation. Figure 7 shows the third step in which the unmasked surface area is exposed to an LDD p-implantation procedure. In the seventh figure, the LDD ρ-ions are indicated by arrows pointing downward. A P-implanted photoresist mask 535 is located on top of the gate 505 of some LDD NM0S and some insulating oxide layer 520. Two p-regions 540 become part of the LTNM0S protection device. Therefore, the seventh figure shows the quasi-LDD ρ-implantation of the LTMMOS protection device, but the LDD NM0S has no ρ-implantation. If the ρ-dopant is boron, in the CMOS process, such as forming the ρ ~ region of LDD PM0S.

Page 15 '437U 4 7 __m 87111857 Shirt V month κ / _Η Revision 5, invention description (13) " domain, boron ρ required by LTNMOS device ~ implantation dose, the process of large LTNMOS protection device will be formed The process of ldd PMOS device is fully compatible. At the same time, it is possible to choose whether to form an LDD PM0s device. The ldd p_70 implant is also formed in the LTNM0S protection device. The ultimate purpose is to obtain a lower excitation voltage (Vtri) from the protection device. The main difference between LTNM0S and LDD NM0S is that normal LDD NMO S does not perform any lJ)]) p-implantation. The eighth figure shows the completion of the fourth step, in which the spacer region 545 has been formed on both sides of the adjacent gate electrodes 5 05 and 5 10. The definition of the spacer area is well understood in the LDD process. Therefore, the eighth figure illustrates the LDD NMOS and LTNMOS after spacer etching. The ninth figure shows the fifth step 'where the surface is exposed to the implantation procedure', which is commonly found on both sides of the LDD NM0S and LTNM0S subcomponents :: and the source and the source. In the ninth figure, the ions are represented by arrows pointing down. The two N + zones 550 become part of the LDD NM0S protection device. Similarly, the two N + regions 5 5 5 become part of the LTMMOS protection device. Therefore, the ninth figure illustrates the implantation of the N + source / and pole (S / D) of both of the LDD NM0S and LTNM0S devices. In general, the better N + implant is Asicic, with a dose of approximately 1 (10) 15 to 4 (10) 15 ions / cm 2. The LDD P-zone of the LTNM0S protection device can be automatically aligned by the compound silicon gate and the spacer. The protection device has a new diode D1 with a low breakdown voltage, which is formed by a steep N + junction and automatic alignment of the P- region. Still referring to the ninth figure, the final result of LTNM0S provides a low voltage

Page 16 I 437047 __Case No. 87Π1857_W f / Month K Days Amendment __ 二 'V. Description of the invention (14) Excitation protection to improve the performance of ESD. This ESW intensive protection device is advantageous as a Vdd / Vss power bus protection device to avoid damage to the internal circuit. The excitation voltage Vtri of the present invention is sufficiently low and can be turned on first (i; uril to overflow the ESD current and prevent the internal circuit from crashing. The ESD protection circuit is compatible with the existing CMOS process, and is made of non-LDD NMOS devices and slightly The mass P-region is formed (in the CMOS process, the PMOS device uses LDD P-planting). A diode 560 with a low breakdown voltage can be obtained by the junction of Ozaki and the LDD P-region. In this protection device, the electric field between the drain and the gate will further reduce the excitation voltage. Therefore, the protection device of the present invention has a lower excitation voltage and does not have the problem of uneven current in the LDD device. The invention can It is applied to input, output and input / output protection to obtain high ESD protection performance and improve ESD performance to avoid ESD degradation caused by advanced processes. The invention is particularly suitable for VDD / Vss power bus ESD protection. Threshold, low voltage excitation protection can be turned on first to spill ESD current and prevent internal circuit from breakdown. Figures 15 to 16 predict some NPN power of non-LDD NM0S devices and LTNM0S protection devices. Voltage characteristics. All four current-voltage curves are 'measured by Hewlett-Packard's HP4156 semiconductor parameter analyzer' and are DC characteristics. The main focus is on the excitation voltage and sudden turning voltage region, which is between Vtri and The area between Vsp is an unstable state. Figures 15 and 16 show the NPN excitation voltage and sudden turning voltage of a non-LDD NM0S device. Figure 15 shows the non-LDD NM0s device. Parasitic NPN double-carrier current vs. voltage characteristics with focus on the excitation region

f '437U 4 7 ___ 87111857_ " Month / f / _Revision_ 5. Explanation of the invention (15) Point ′ Vtri is about 12. 1 volt. The sixteenth figure also shows the parasitic NPN bipolar current vs. voltage characteristics of non-LDD NMOS devices, with the sudden turning region as the focal point 'V s p is about 7.2 volts. Figures 15 through 16 measure the same impact LDD NMOS device. _

Figures 17 and 18 show the NPN excitation voltage and sudden turning voltage of an LTNMOS device, which individually represent an example of the present invention. The seventeenth figure shows the parasitic NPN double-carrier current-to-voltage characteristics of the LTNMOS protection device, with the excitation region as the focus, and Vtri is about 8.6 volts. The eighteenth figure focuses on the sudden turning area, and Vsp is about 6.0 volts. Figures 17 and 18 measure the same LTNMOS device. These results are similar to the data obtained by the device of the tenth picture "LTNMOS 'Vtri of the seventeenth picture is 8.6 volts' is lower than the 9.4 volts obtained by the device of the tenth picture Injected dose, and because the data is measured from different wafer states. It must be understood that the comparison of the seventeenth and eighteenth figures with the fifteenth and sixteenth figures shows the significant improvement performance of the present invention. Examples Specific examples of the present invention will be further described by the following non-limiting examples, which can provide some more meaningful and detailed various characteristics.13 These examples are merely to make the present invention easier to understand in practice and to further familiarize it with Those skilled in the art can apply the invention. Accordingly, these examples should not be considered as a limitation of the scope of the present invention. Example 1 Referring to the eleventh figure, the first example of an LTNMOS coupled gate circuit is illustrated. In this example, if Vdd exceeds Vtr i of LTNMOS, Vdd will be divided

Page 18 '437047 _ case number 87111857_gf year " month / V day _ ^ ___ 5. Description of the invention (16) to the ground. The circuit in Figure 11 will further reduce the threshold value of the excitation voltage (Vtri) by combining the gate coupling resistor Rg and the LTNM0S protection device, and the closed pole of the LTNM0S protection device is connected to the ground terminal via the coupling resistor Rg . In this example, the coupling resistor Rg is a passive element and has an impedance of about 1 to 1 Ok ohms. At the same time, it can increase the gate voltage of the LTNM0S protection device and reduce the Vtr coupling resistor R g during the ESD pulse. Is an n-well, an n-diffusion path or any other type of resistor. Example 2

Referring to the twelfth figure, a second example of a LTNM0S surface closing circuit is illustrated. In this example, if Vdd ^ passes Vtri of LTNM0S, Vdd will also be shunted to the ground terminal. The circuit of Fig. 12 combines the M0S device Mg with the LTNM0S protection device, and the gate of the LTNMOS protection device is connected to the ground through the M0S device Mg. The circuit of Fig. 12 will further reduce the voltage of excitation (Vtri). Limit. In this example, the coupling resistor jjg is an active element. Although in Figures 11 and 12, the gate of LTNM0S is not directly connected to Vss, but during normal chip operation (meaning no ESD event, LTNM0S is in the off state 'and no additional leakage current), the gate The pole voltage level is still equal to V ss (meaning ground). In many integrated circuits [PW (P-substrate) 1030 is connected to Vss. However, in some integrated circuits, such as DRAM, the PW is connected to Vbb (from a built-in substrate bias generator). The Vbb voltage is approximately -1.5 volts to -3.0 volts. Vbb is negatively biased. Therefore, PW103〇 may not be equal to V s s (meaning ground).

Page 19 43 7U 4 7 __ 案 号 87111857 # 年 " Monthly Day Amendment V. Invention Details (Π) 'equals Vss. However, in the eleventh or twelfth figure, during the ESD pulse, the gate voltage of the LTNMOS is coupled to a voltage level, and this voltage depends on the interrogator / dead capacitance Cgd, the gate / source capacitance Cgs, Gate / whole (pw / capacitance Cgb and gate coupling resistor Rg are equivalent. For example, when a positive voltage ESD pulse is applied to the drain of an LTNMOS, the source and substrate (pw) are grounded; LTNMOS The gate voltage level can be induced to a positive voltage by the combination of the Esj) voltage. This RC depletion is defined by Rg, Cgd, Cgs, and Cgb above. A positive pole voltage reduces the parasitic NPN bipolar house. In order to achieve this, the LTNM0S in the eleventh and twelfth pictures is excited. Example 3 Refer to the fourteenth picture ′ to illustrate a third example of the LTNMOS switching gate circuit. In this example, the LTNMOS protection device is connected in parallel with an output buffer and provides an additional current discharge path to avoid leakage of the output device. During an ESD event, LTNMOS is very effective in protecting the output buffered LDD NMOS. In contrast, non-LDD off 0S (Figure 4) cannot provide sufficient protection for the output buffer. In addition, series resistors and thick-field devices (thick figure) used in conventional techniques to protect the output buffered NMOS (first picture) have been found to cause leakage of the output buffered nMOS. The LTNMOS of the present invention can obtain better ESD performance without the need for additional series resistors or reducing the output NMOS characteristics. Including published examples of the above three examples, the display—conductor (Figure 10 and Figures 13 and 14), a resistor (Figure 11), and an active MOS resistor (Figure 12) ' Acts as a structure that performs light-gate to diode functions. However, the structure of the closing gate to the diode may be other structures sufficient to perform this function ’, such as a diffusion line, a wire, a capacitor,

ί '4370 4 7 _ Case No. 87111857 V. Description of the invention (18) W years 丨 (Month U / Year correction or even inductance, etc. Practical application of the present invention In the technical field, the practical application of the present invention has considerable value. Combined with the Vdd / Vss power bus to protect the internal circuit from ESim damage. The invention is further used at the input, output or input / output terminals to prevent damage to the gate oxide layer and damage to the output device Etc. In fact, the present invention has countless uses, but it need not be repeated here. Advantages of the present invention

The low-voltage excited ESD protection method, which represents an example of the present invention, can effectively reduce the cost, and has at least the following advantages. Β Low-voltage excited ESD protection device includes a steep junction, and has a low excitation voltage (Vtri) and low sudden rotation. Voltage (Vsp), meanwhile, it has higher ESD performance than LDD NM0S device. Low voltage excitation of the ESD protection device during an ESD pulse 'will not cause any current non-uniformity problems (meaning hot spots). The method of manufacturing a low-voltage excited ESD protection device is compatible with the CMOS process, and the high ESD protection performance provided by the present invention can also be achieved based on examples manufactured by the advanced CMOS process. For example, the method of manufacturing the present invention is fully compatible with the slightly doped LDD) NM0S process steps produced by the saIC process. The best known examples are all published examples of the present invention, without the need for additional, and application. Although the actual mode has been described in the inventor's thought, the actual application of the invention should be controlled. Therefore, for those familiar with this technology, it must be clear that it can be applied to areas other than those specifically mentioned above. Individual components of material H do not need to form the published child

Page 21 Γ, 4370 4 7 _Case No. Di N / F / C / Day_Amended V. Description of the invention (] 9) (shapes) or New York Post, can be provided as the structure of any-shaped U (C 〇niigUrati〇n) 'Actual' does not require any structure from published materials. And 'individual components are made. In addition, although magically, it can be made of any suitable material, but the electrical device is obviously described in detail. Going one step further, except that 5 discharge devices can be added to their associated devices, each published element and each element and feature conflict with each other,… the element "::: Different from other special features, U :: Send: positive j reconfiguration of the present invention is covered by the following patent applications :: 2 Gods, Fan Yuan. Additions, amendments and reconfiguration of the invention. R, & quot The equivalent will also cover the limitation of all interpretation institutions plus functions. The scope of the patent application below is not solvable. Obviously, it is used to ... 'this—, system. The scope of application for patent scope is distinguished by subsidiary items.的 之 词 'and the present invention has

Page 22

4 3 7 0 4 7 Amendment ___ Case No. 87111857 The advantages and characteristics of the invention, the clear reference to the operation of the components and system modes, common and non-limiting, and the examples illustrated in the accompanying drawings and parts, the present invention will be easier to understand Among them, dedication and text represent the same workpiece (if it is presented in multiple styles, it must be understood that the characteristics illustrated in the drawings do not need to consider its illustration-a schematic diagram traditionally applied to Vdd / Vss electrostatic discharge protection, which appropriately represents the known technology . Schematic diagram of a conventional N-channel metal oxide semiconductor device applied to Vdd / Vss electrostatic discharge protection, suitable technology. Shown in the device of the second diagram, the current versus voltage relationship suddenly reverses. Diagram of a conventional application to Vdd / Vss static electricity. Discharge-Protected Drain N-Channel Metal Oxide Semiconductor Device (No η-Implantation, Appropriately Represents Conventional Technology. The diagram illustrates the fabrication of an adjacent low-voltage excited N-channel metal oxide with a slightly doped drain N-channel metal oxide semiconductor device. The schematic diagram of the first stage represents an example of the present invention. The diagram briefly explains the concept of this concept, and The grid is the same as the current thick-field reference. The size is the same. The second picture of the first picture of the device is slightly doped, which does not locally represent the characteristics of Xi third picture. At the time, the sixth diagram illustrates a second-order schematic diagram when manufacturing a lightly doped drain N-channel metal oxide semiconductor device adjacent to a low-voltage excited N-channel metal oxide semiconductor, which represents an example of the present invention. The figure illustrates a third-stage schematic diagram when manufacturing a slightly doped drain N-channel metal oxide semiconductor device connected to a low-voltage excited N-channel metal oxide semiconductor, and represents an example of the present invention.

Page 23 4370 4 7 years 丨 / month / ty date amendment _ case number 871] 1857 diagram briefly illustrates an eighth diagram illustrating the manufacture of a slightly doped drain N channel adjacent to a low voltage excited N channel metal oxide semiconductor In the case of a metal oxide semiconductor device, a fourth-order schematic diagram represents an example of the present invention. " The ninth figure illustrates the fifth stage schematic diagram of manufacturing—a lightly doped drain n-channel metal oxide semiconductor adjacent to the low voltage excited channel metal oxide semiconductor, which represents an example of the present invention. Fig. 10 illustrates a schematic diagram of a low-voltage excited n-channel oxide semiconductor with an enhanced drain-gate field to represent an example of the present invention. Figure 11 illustrates a schematic block diagram of a low-voltage excitation Nit-type semiconductor protection circuit combined with a coupling resistor. The above shows the tenth figure—illustration and an active metal oxide semiconductor resistor company II = low-voltage excitation N The block diagram of the channel metal oxide semiconductor protection circuit represents an example of the present invention. ^ Dao Jinying ί ΐ Ϊ f Ϊ A low-voltage excitation with enhanced P-channel implantation »'Intent of layer semiconductors' represents an example of the present invention. The fourteen-circle diagram is a low block applied to the input / output (1/0) protection = a schematic block diagram that excites an N-channel metal oxide semiconductor, an example of an early thin low invention. π Clothing Figure 15 illustrates the NPN excitation voltage of a non-LDD NMOS device. Pressure. The sixteenth figure illustrates a non-LDD NMOS device's NρN sudden turning electricity. The seventeenth figure illustrates a NPN excitation electric explosion applied to a LTMMOS device, which represents an example of the present invention. $ The eighteenth round solution is applied to the PNNM sudden rotation of the LTNM0S earthquake.

Page 24 ί * 4 3 7 ϋ 4 7 Autumn in January _ correction _tlfe 87111857 Simple illustration of the house, which represents an example of the present invention i ^ n Page 25

Claims (1)

: 437047 _ Case No. 87111857_% year f / month / (/ day amendment__ VI. Patent application scope 1. An electrostatic discharge protection circuit for a protected end in a integrated circuit substrate, the integrated circuit substrate has A first conductive state, and the electrostatic discharge protection circuit includes: a source electrode in the integrated circuit substrate and has a second conductive state; a drain electrode in the integrated circuit substrate and has the second conductive state A channel between the source and the drain; a first lightly doped region located in the channel between the source and the drain; and the first lightly doped region has a first conductive state; A first electrical contact in the electrode; and a second electrical contact in the drain, wherein the first electrical contact and the second electrical contact are coupled to the protected end in the integrated circuit substrate. The electrostatic discharge protection circuit of item 1, wherein the first slightly doped region and the drain electrode are adjacent to each other, and define a first diode. 3. The electrostatic discharge protection circuit of item 1 in the scope of patent application, further comprising a gate Pole structure, located in the channel with the first slight doping Areas above both. 4. For the electrostatic discharge protection circuit of item 3 of the patent application, where the gate structure is electrically coupled to ground to define a parasitic bipolar transistor. 5. For item 4 of the patent application scope The electrostatic discharge protection circuit further includes a region in the integrated circuit substrate, which has a first conductive state, and wherein the gate structure is electrically coupled to the ground. 6. The electrostatic discharge protection circuit according to item 5 of the patent application scope, wherein The gate structure uses a passive resistor to be electrically coupled to the ground. 7. The electrostatic discharge protection circuit of item 5 of the patent application, where the gate is Page 26! '437047 ^ _ Case No. 87111857_ ^ f7th of the month of amendment __ VI. Scope of patent application The structure uses an active resistor, which is electrically coupled to ground. 8. The electrostatic discharge protection circuit according to item 1 of the patent application scope, wherein the source is electrically coupled to the ground. 9. The electrostatic discharge protection circuit according to item 1 of the patent application, wherein the drain is electrically coupled to an input bus. 10. The electrostatic discharge protection circuit according to item 1 of the patent application scope, wherein the drain is electrically coupled to an output bus. 1 1. The electrostatic discharge protection circuit according to item 1 of the patent application, wherein the drain is electrically coupled to an input / output bus. 1 2. The electrostatic discharge protection circuit according to item 1 of the patent application, wherein the drain is connected to a power rail. 1 3. The electrostatic discharge protection circuit according to item 1 of the patent application scope, wherein the protection terminal is composed of a power supply input terminal. 14. The electrostatic discharge protection circuit according to item 1 of the scope of patent application, wherein the protected terminal is composed of a data signal input terminal. 15. The electrostatic discharge protection circuit according to item 2 of the patent application scope, further comprising a second slightly doped region, located in the channel, between the first slightly doped region and the source, and the second slightly doped The region has a first conductive state. 16. The electrostatic discharge protection circuit according to item 15 of the scope of patent application, wherein the second slightly doped region and the source are adjacent to each other, and a second diode is defined. 1 7. The electrostatic discharge protection circuit according to item 1 of the patent application scope, wherein the first slight #mass region defines an implantation channel. i 8. The electrostatic discharge protection circuit according to item 1 of the scope of patent application, wherein the first conductive state is a p-type and the second conductive state is an n-type. Page 27 437047 _ Case No. 87111857 Amendment 6. Scope of patent application 19. For the electrostatic discharge protection circuit of the first scope of patent application, the first electrical contact and the second electrical contact both include silicide. 20. —A integrated circuit in a substrate, having a first conductive state and a plurality of terminals (a plurality of circuits, coupled to a plurality of terminals; and nals). The body circuit includes: cuits), which includes the M0S electrostatic discharge protection circuit in the substrate, which is coupled to a group of protected terminals. The electrostatic discharge protection circuit includes: a source electrode in the substrate of the integrated circuit, A drain electrode located in the substrate of the integrated circuit, a channel between the source and the drain electrode, a first lightly doped region located in the channel and the first lightly doped region having a first conductive-gate structure, The channel and the first light structure are electrically coupled to the substrate to define a first electrical contact located in the source; and a second electrical contact located in the drain, wherein the first electrical contact and the second electrical contact 2 1. If the area of product 20 in the integrated circuit substrate of the scope of application for patents has a pole structure, it is electrically cut to ground. 22. If the product of item 21 of the patent application scope uses a passive resistor electrically coupled to ground 23. If the product of item 21 of the patent application scope has a second conductive state; and has a second conductive state; and Between the source and the drain, the state; the 5-closed bipolar transistor on top of the micro-mass region; coupled to the protected terminal group. The body circuit further includes a bit of the first conductive state, and wherein the gate body circuit has a gate structure, and the gate structure has a favorable structure. Page 28!., 437U 4 7 _Case No. 87111857_ Di Nian January / January ... Day Amendment _-VI. Patent Application Scope Use an active resistor electrically coupled to ground. 2 4. The integrated circuit of item 20 in the scope of patent application, wherein the source is electrically coupled to ground. 25. The integrated circuit of item 20 in the scope of patent application, wherein the drain is electrically coupled to an input bus. 2 6. The integrated circuit of item 20 in the scope of patent application, wherein the drain is electrically coupled to an output bus. 2 7. The integrated circuit of item 20 in the scope of patent application, whose _drain is electrically coupled to an input / output bus. 2 8. The integrated circuit of claim 20, wherein the drain is electrically coupled to a power source. 29. The integrated circuit of item 20 in the scope of patent application, wherein the protected terminal is composed of a power supply input terminal. 30. The integrated circuit of item 20 in the scope of patent application, wherein the protected terminal is composed of a data signal input terminal. 3 1. The integrated circuit of item 20 in the scope of patent application, wherein the first slightly doped region and the drain are adjacent to each other and define a first diode. 32. For example, the integrated circuit of item 31 of the patent application scope further includes a second slightly doped region located in the channel _, between the first slightly doped region and the source, and the second slightly doped region has First conductive state. 33. For the integrated circuit of item 32 in the scope of patent application, wherein the second slightly doped region and the source are adjacent to each other, and a second diode is defined. 34. The integrated circuit of claim 20, wherein the first lightly doped region defines an implantation channel. Page 29 ^ '437U 4 7 _Case No. 87111857_ Di Nian 丨 f / C / Day_ VI. Application for patent scope 35. For the integrated circuit of the 20th patent scope, the first conductive state is P And the second conductive state is n-type. 36. For the integrated circuit of item 20 in the scope of patent application, wherein the first electrical contact and the second electrical contact both include silicide. 37. A method for manufacturing an integrated circuit electrostatic discharge protection circuit, the integrated circuit electrostatic discharge protection circuit is located in a semiconductor substrate having a first conductive state and a first dopant concentration level, and the method includes : Forming a pole in the semiconductor substrate; forming a first doped region and a second doped region in a first conductive state in the semiconductor substrate, the first doped region and the second doped region are located Immediately next to the gate electrode, and because of a channel region in the semiconductor substrate, a certain space is separated from each other, the channel region is located below the gate electrode; and in the first doped region, a third conductive state is formed. A dopant region, and a fourth dopant region of a second conductive state is formed in the second dopant region; the third dopant region and the fourth dopant region are separated from each other by a distance greater than the first dopant region The distance from the second dopant interval, wherein the dopant concentration level of the first dopant region and the second dopant region is greater than the dopant concentration level of the semiconductor substrate. 38. The method of claim 37, further comprising: after forming the first and second dopant regions, and before forming the third and fourth dopant regions, forming i ) A first spacer adjacent to the first side of a gate and located on the first doped region, and ii) a second spacer adjacent to the second side of a gate and located on the second doped region on. 39. The method of claim 38, further comprising: Page 30 ί '437ϋ 4 7 _ Case No. 87111857_W ((pain date amendment _ 26, after the patent application scope of the third and fourth dopant regions, contact was made on the third and fourth regions 〇. The method of claim 39, wherein forming contact includes: forming a silicide on the third dopant region and the fourth dopant region; the silicide is formed by the pair of first and second spacers. 41. The method according to item 37 of the scope of patent application, further comprising: after forming the gate electrode and before forming the first doped region and the second doped region, masking the first portion of a substrate, The first doped region and the second doped region will be formed, and the carrier of the second conductive state will be implanted in the second part of a substrate to form a part of the MOS transistor in the second part of the substrate. 4 2. The method according to item 37 of the scope of patent application, wherein forming the first and second doped regions comprises: after implanting the second portion of the substrate, covering the second portion of the curtain substrate; and The carrier of the first conductive state is implanted in the first part of the substrate. 4 3. As in item 37 of the scope of patent application The method further comprises: after forming the third dopant region and the fourth dopant region, coupling the gate to a diode formed by a junction between the first dopant region and the third dopant region. 44. For example, the method of applying the scope of the patent item 43, wherein the coupling includes: forming a region having a first conductive state in the semiconductor substrate, and connecting the region to the gate. 45. The method of the scope of the patent application, 44 The connection region to the gate includes: using a passive resistor to connect the gate to the ground. 46. The method according to item 44 of the scope of patent application, wherein the connection region to the gate Page 31 Γ '4370 4 7 Case No. 87111857 Amendment W / li. 6. The scope of the patent application includes: using an active resistor 47. For example, the scope of patent application is 37, and the second conductive state is connected to the gate To ground. The method of the item, where the first guide 'Supplement II: 48. Orientation of the circuit, this side conducts a static protection device switching electrostatic current a lower electrostatic discharge switching circuit transmission and then, through the second zone, the first in- Bottom: Material, 1: Pulse pulse, to method / This method includes the power source of the electric discharge; The discharge protection resistor, the electric pulse includes: _ The conductive line is passed to the two-zone protective device to and is quite uniform and the shunt current state is P者 # Ψ.% F Provides electrostatic discharge protection to the first conductive state of the substrate in the substrate and a first dopant concentration quasi IF 1 '/ one in a non-conductive state. Electrostatic discharge protection in a conductive state ^ $ # 所' 立 提A conductive state to provide a path of uniform current density for electrostatic discharge, thereby opening up all, discharge pulses, conducting electrostatic discharge pulses through a first region of a second conductive state, and a dopant through a first lead The concentration level is higher than the first mass concentration level of the first doped state, and then, an electrostatic discharge pulse is conducted through the line through the second region of the second conductive state. Conducting static pulses through the line 49. The method according to item 48 of the patent application, further comprising: conducting static discharge pulses through the second area through the conductive static discharge pulse, and conducting static discharges through the line before the electrical discharge pulse through the third area passes through the circuit. Pass a fourth region of a first conductive state. 50. The method of claim 48, wherein the first region includes a drain electrode, and the electrostatic discharge protection device includes a gate electrode, and the gate electrode is located in the second region and Page 32 437 ϋ 4 7 Case number 87111857 and year g / month 6. Scope of Patent Application The third area is above and between the two areas, and further includes applying an electric field between the drain and gate. 51. The method according to item 50 of the scope of patent application, wherein an electrostatic field is obtained in a parasitic manner when conducting an electrostatic discharge pulse along a line through a junction defined by an interface between a first zone and a second zone. I Page 33